ps3vram.c 22 KB

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  1. /*
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright 2009 Sony Corporation
  5. *
  6. * Based on the MTD ps3vram driver, which is
  7. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  8. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  9. */
  10. #include <linux/blkdev.h>
  11. #include <linux/delay.h>
  12. #include <linux/proc_fs.h>
  13. #include <linux/seq_file.h>
  14. #include <asm/cell-regs.h>
  15. #include <asm/firmware.h>
  16. #include <asm/lv1call.h>
  17. #include <asm/ps3.h>
  18. #include <asm/ps3gpu.h>
  19. #define DEVICE_NAME "ps3vram"
  20. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  21. #define XDR_IOIF 0x0c000000
  22. #define FIFO_BASE XDR_IOIF
  23. #define FIFO_SIZE (64 * 1024)
  24. #define DMA_PAGE_SIZE (4 * 1024)
  25. #define CACHE_PAGE_SIZE (256 * 1024)
  26. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  27. #define CACHE_OFFSET CACHE_PAGE_SIZE
  28. #define FIFO_OFFSET 0
  29. #define CTRL_PUT 0x10
  30. #define CTRL_GET 0x11
  31. #define CTRL_TOP 0x15
  32. #define UPLOAD_SUBCH 1
  33. #define DOWNLOAD_SUBCH 2
  34. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  35. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  36. #define CACHE_PAGE_PRESENT 1
  37. #define CACHE_PAGE_DIRTY 2
  38. struct ps3vram_tag {
  39. unsigned int address;
  40. unsigned int flags;
  41. };
  42. struct ps3vram_cache {
  43. unsigned int page_count;
  44. unsigned int page_size;
  45. struct ps3vram_tag *tags;
  46. unsigned int hit;
  47. unsigned int miss;
  48. };
  49. struct ps3vram_priv {
  50. struct request_queue *queue;
  51. struct gendisk *gendisk;
  52. u64 size;
  53. u64 memory_handle;
  54. u64 context_handle;
  55. u32 *ctrl;
  56. void *reports;
  57. u8 *xdr_buf;
  58. u32 *fifo_base;
  59. u32 *fifo_ptr;
  60. struct ps3vram_cache cache;
  61. spinlock_t lock; /* protecting list of bios */
  62. struct bio_list list;
  63. };
  64. static int ps3vram_major;
  65. static const struct block_device_operations ps3vram_fops = {
  66. .owner = THIS_MODULE,
  67. };
  68. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  69. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  70. #define DMA_NOTIFIER_SIZE 0x40
  71. #define NOTIFIER 7 /* notifier used for completion report */
  72. static char *size = "256M";
  73. module_param(size, charp, 0);
  74. MODULE_PARM_DESC(size, "memory size");
  75. static u32 *ps3vram_get_notifier(void *reports, int notifier)
  76. {
  77. return reports + DMA_NOTIFIER_OFFSET_BASE +
  78. DMA_NOTIFIER_SIZE * notifier;
  79. }
  80. static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
  81. {
  82. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  83. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  84. int i;
  85. for (i = 0; i < 4; i++)
  86. notify[i] = 0xffffffff;
  87. }
  88. static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
  89. unsigned int timeout_ms)
  90. {
  91. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  92. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  93. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  94. do {
  95. if (!notify[3])
  96. return 0;
  97. msleep(1);
  98. } while (time_before(jiffies, timeout));
  99. return -ETIMEDOUT;
  100. }
  101. static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
  102. {
  103. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  104. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  105. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  106. }
  107. static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
  108. unsigned int timeout_ms)
  109. {
  110. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  111. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  112. do {
  113. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  114. return 0;
  115. msleep(1);
  116. } while (time_before(jiffies, timeout));
  117. dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
  118. priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
  119. priv->ctrl[CTRL_TOP]);
  120. return -ETIMEDOUT;
  121. }
  122. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  123. {
  124. *(priv->fifo_ptr)++ = data;
  125. }
  126. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
  127. u32 size)
  128. {
  129. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  130. }
  131. static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
  132. {
  133. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  134. int status;
  135. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  136. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  137. /* asking the HV for a blit will kick the FIFO */
  138. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  139. if (status)
  140. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  141. __func__, status);
  142. priv->fifo_ptr = priv->fifo_base;
  143. }
  144. static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
  145. {
  146. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  147. int status;
  148. mutex_lock(&ps3_gpu_mutex);
  149. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  150. (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
  151. /* asking the HV for a blit will kick the FIFO */
  152. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  153. if (status)
  154. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  155. __func__, status);
  156. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  157. FIFO_SIZE - 1024) {
  158. dev_dbg(&dev->core, "FIFO full, rewinding\n");
  159. ps3vram_wait_ring(dev, 200);
  160. ps3vram_rewind_ring(dev);
  161. }
  162. mutex_unlock(&ps3_gpu_mutex);
  163. }
  164. static void ps3vram_bind(struct ps3_system_bus_device *dev)
  165. {
  166. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  167. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  168. ps3vram_out_ring(priv, 0x31337303);
  169. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  170. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  171. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  172. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  173. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  174. ps3vram_out_ring(priv, 0x3137c0de);
  175. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  176. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  177. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  178. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  179. ps3vram_fire_ring(dev);
  180. }
  181. static int ps3vram_upload(struct ps3_system_bus_device *dev,
  182. unsigned int src_offset, unsigned int dst_offset,
  183. int len, int count)
  184. {
  185. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  186. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  187. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  188. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  189. ps3vram_out_ring(priv, dst_offset);
  190. ps3vram_out_ring(priv, len);
  191. ps3vram_out_ring(priv, len);
  192. ps3vram_out_ring(priv, len);
  193. ps3vram_out_ring(priv, count);
  194. ps3vram_out_ring(priv, (1 << 8) | 1);
  195. ps3vram_out_ring(priv, 0);
  196. ps3vram_notifier_reset(dev);
  197. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  198. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  199. ps3vram_out_ring(priv, 0);
  200. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  201. ps3vram_out_ring(priv, 0);
  202. ps3vram_fire_ring(dev);
  203. if (ps3vram_notifier_wait(dev, 200) < 0) {
  204. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  205. return -1;
  206. }
  207. return 0;
  208. }
  209. static int ps3vram_download(struct ps3_system_bus_device *dev,
  210. unsigned int src_offset, unsigned int dst_offset,
  211. int len, int count)
  212. {
  213. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  214. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  215. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  216. ps3vram_out_ring(priv, src_offset);
  217. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  218. ps3vram_out_ring(priv, len);
  219. ps3vram_out_ring(priv, len);
  220. ps3vram_out_ring(priv, len);
  221. ps3vram_out_ring(priv, count);
  222. ps3vram_out_ring(priv, (1 << 8) | 1);
  223. ps3vram_out_ring(priv, 0);
  224. ps3vram_notifier_reset(dev);
  225. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  226. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  227. ps3vram_out_ring(priv, 0);
  228. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  229. ps3vram_out_ring(priv, 0);
  230. ps3vram_fire_ring(dev);
  231. if (ps3vram_notifier_wait(dev, 200) < 0) {
  232. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  233. return -1;
  234. }
  235. return 0;
  236. }
  237. static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
  238. {
  239. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  240. struct ps3vram_cache *cache = &priv->cache;
  241. if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
  242. return;
  243. dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
  244. cache->tags[entry].address);
  245. if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
  246. cache->tags[entry].address, DMA_PAGE_SIZE,
  247. cache->page_size / DMA_PAGE_SIZE) < 0) {
  248. dev_err(&dev->core,
  249. "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
  250. entry * cache->page_size, cache->tags[entry].address,
  251. cache->page_size);
  252. }
  253. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  254. }
  255. static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
  256. unsigned int address)
  257. {
  258. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  259. struct ps3vram_cache *cache = &priv->cache;
  260. dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
  261. if (ps3vram_download(dev, address,
  262. CACHE_OFFSET + entry * cache->page_size,
  263. DMA_PAGE_SIZE,
  264. cache->page_size / DMA_PAGE_SIZE) < 0) {
  265. dev_err(&dev->core,
  266. "Failed to download from 0x%x to 0x%x size 0x%x\n",
  267. address, entry * cache->page_size, cache->page_size);
  268. }
  269. cache->tags[entry].address = address;
  270. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  271. }
  272. static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
  273. {
  274. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  275. struct ps3vram_cache *cache = &priv->cache;
  276. int i;
  277. dev_dbg(&dev->core, "FLUSH\n");
  278. for (i = 0; i < cache->page_count; i++) {
  279. ps3vram_cache_evict(dev, i);
  280. cache->tags[i].flags = 0;
  281. }
  282. }
  283. static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
  284. loff_t address)
  285. {
  286. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  287. struct ps3vram_cache *cache = &priv->cache;
  288. unsigned int base;
  289. unsigned int offset;
  290. int i;
  291. static int counter;
  292. offset = (unsigned int) (address & (cache->page_size - 1));
  293. base = (unsigned int) (address - offset);
  294. /* fully associative check */
  295. for (i = 0; i < cache->page_count; i++) {
  296. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  297. cache->tags[i].address == base) {
  298. cache->hit++;
  299. dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
  300. cache->tags[i].address);
  301. return i;
  302. }
  303. }
  304. /* choose a random entry */
  305. i = (jiffies + (counter++)) % cache->page_count;
  306. dev_dbg(&dev->core, "Using entry %d\n", i);
  307. ps3vram_cache_evict(dev, i);
  308. ps3vram_cache_load(dev, i, base);
  309. cache->miss++;
  310. return i;
  311. }
  312. static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
  313. {
  314. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  315. priv->cache.page_count = CACHE_PAGE_COUNT;
  316. priv->cache.page_size = CACHE_PAGE_SIZE;
  317. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  318. CACHE_PAGE_COUNT, GFP_KERNEL);
  319. if (priv->cache.tags == NULL) {
  320. dev_err(&dev->core, "Could not allocate cache tags\n");
  321. return -ENOMEM;
  322. }
  323. dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
  324. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  325. return 0;
  326. }
  327. static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
  328. {
  329. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  330. ps3vram_cache_flush(dev);
  331. kfree(priv->cache.tags);
  332. }
  333. static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
  334. size_t len, size_t *retlen, u_char *buf)
  335. {
  336. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  337. unsigned int cached, count;
  338. dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
  339. (unsigned int)from, len);
  340. if (from >= priv->size)
  341. return -EIO;
  342. if (len > priv->size - from)
  343. len = priv->size - from;
  344. /* Copy from vram to buf */
  345. count = len;
  346. while (count) {
  347. unsigned int offset, avail;
  348. unsigned int entry;
  349. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  350. avail = priv->cache.page_size - offset;
  351. entry = ps3vram_cache_match(dev, from);
  352. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  353. dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
  354. "avail=%08x count=%08x\n", __func__,
  355. (unsigned int)from, cached, offset, avail, count);
  356. if (avail > count)
  357. avail = count;
  358. memcpy(buf, priv->xdr_buf + cached, avail);
  359. buf += avail;
  360. count -= avail;
  361. from += avail;
  362. }
  363. *retlen = len;
  364. return 0;
  365. }
  366. static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
  367. size_t len, size_t *retlen, const u_char *buf)
  368. {
  369. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  370. unsigned int cached, count;
  371. if (to >= priv->size)
  372. return -EIO;
  373. if (len > priv->size - to)
  374. len = priv->size - to;
  375. /* Copy from buf to vram */
  376. count = len;
  377. while (count) {
  378. unsigned int offset, avail;
  379. unsigned int entry;
  380. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  381. avail = priv->cache.page_size - offset;
  382. entry = ps3vram_cache_match(dev, to);
  383. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  384. dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
  385. "avail=%08x count=%08x\n", __func__, (unsigned int)to,
  386. cached, offset, avail, count);
  387. if (avail > count)
  388. avail = count;
  389. memcpy(priv->xdr_buf + cached, buf, avail);
  390. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  391. buf += avail;
  392. count -= avail;
  393. to += avail;
  394. }
  395. *retlen = len;
  396. return 0;
  397. }
  398. static int ps3vram_proc_show(struct seq_file *m, void *v)
  399. {
  400. struct ps3vram_priv *priv = m->private;
  401. seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
  402. return 0;
  403. }
  404. static int ps3vram_proc_open(struct inode *inode, struct file *file)
  405. {
  406. return single_open(file, ps3vram_proc_show, PDE(inode)->data);
  407. }
  408. static const struct file_operations ps3vram_proc_fops = {
  409. .owner = THIS_MODULE,
  410. .open = ps3vram_proc_open,
  411. .read = seq_read,
  412. .llseek = seq_lseek,
  413. .release = single_release,
  414. };
  415. static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev)
  416. {
  417. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  418. struct proc_dir_entry *pde;
  419. pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops,
  420. priv);
  421. if (!pde)
  422. dev_warn(&dev->core, "failed to create /proc entry\n");
  423. }
  424. static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
  425. struct bio *bio)
  426. {
  427. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  428. int write = bio_data_dir(bio) == WRITE;
  429. const char *op = write ? "write" : "read";
  430. loff_t offset = bio->bi_sector << 9;
  431. int error = 0;
  432. struct bio_vec *bvec;
  433. unsigned int i;
  434. struct bio *next;
  435. bio_for_each_segment(bvec, bio, i) {
  436. /* PS3 is ppc64, so we don't handle highmem */
  437. char *ptr = page_address(bvec->bv_page) + bvec->bv_offset;
  438. size_t len = bvec->bv_len, retlen;
  439. dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
  440. len, offset);
  441. if (write)
  442. error = ps3vram_write(dev, offset, len, &retlen, ptr);
  443. else
  444. error = ps3vram_read(dev, offset, len, &retlen, ptr);
  445. if (error) {
  446. dev_err(&dev->core, "%s failed\n", op);
  447. goto out;
  448. }
  449. if (retlen != len) {
  450. dev_err(&dev->core, "Short %s\n", op);
  451. error = -EIO;
  452. goto out;
  453. }
  454. offset += len;
  455. }
  456. dev_dbg(&dev->core, "%s completed\n", op);
  457. out:
  458. spin_lock_irq(&priv->lock);
  459. bio_list_pop(&priv->list);
  460. next = bio_list_peek(&priv->list);
  461. spin_unlock_irq(&priv->lock);
  462. bio_endio(bio, error);
  463. return next;
  464. }
  465. static int ps3vram_make_request(struct request_queue *q, struct bio *bio)
  466. {
  467. struct ps3_system_bus_device *dev = q->queuedata;
  468. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  469. int busy;
  470. dev_dbg(&dev->core, "%s\n", __func__);
  471. spin_lock_irq(&priv->lock);
  472. busy = !bio_list_empty(&priv->list);
  473. bio_list_add(&priv->list, bio);
  474. spin_unlock_irq(&priv->lock);
  475. if (busy)
  476. return 0;
  477. do {
  478. bio = ps3vram_do_bio(dev, bio);
  479. } while (bio);
  480. return 0;
  481. }
  482. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  483. {
  484. struct ps3vram_priv *priv;
  485. int error, status;
  486. struct request_queue *queue;
  487. struct gendisk *gendisk;
  488. u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
  489. reports_size, xdr_lpar;
  490. char *rest;
  491. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  492. if (!priv) {
  493. error = -ENOMEM;
  494. goto fail;
  495. }
  496. spin_lock_init(&priv->lock);
  497. bio_list_init(&priv->list);
  498. ps3_system_bus_set_drvdata(dev, priv);
  499. /* Allocate XDR buffer (1MiB aligned) */
  500. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  501. get_order(XDR_BUF_SIZE));
  502. if (priv->xdr_buf == NULL) {
  503. dev_err(&dev->core, "Could not allocate XDR buffer\n");
  504. error = -ENOMEM;
  505. goto fail_free_priv;
  506. }
  507. /* Put FIFO at begginning of XDR buffer */
  508. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  509. priv->fifo_ptr = priv->fifo_base;
  510. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  511. if (ps3_open_hv_device(dev)) {
  512. dev_err(&dev->core, "ps3_open_hv_device failed\n");
  513. error = -EAGAIN;
  514. goto out_free_xdr_buf;
  515. }
  516. /* Request memory */
  517. status = -1;
  518. ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
  519. if (!ddr_size) {
  520. dev_err(&dev->core, "Specified size is too small\n");
  521. error = -EINVAL;
  522. goto out_close_gpu;
  523. }
  524. while (ddr_size > 0) {
  525. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  526. &priv->memory_handle,
  527. &ddr_lpar);
  528. if (!status)
  529. break;
  530. ddr_size -= 1024*1024;
  531. }
  532. if (status) {
  533. dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
  534. status);
  535. error = -ENOMEM;
  536. goto out_close_gpu;
  537. }
  538. /* Request context */
  539. status = lv1_gpu_context_allocate(priv->memory_handle, 0,
  540. &priv->context_handle, &ctrl_lpar,
  541. &info_lpar, &reports_lpar,
  542. &reports_size);
  543. if (status) {
  544. dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
  545. status);
  546. error = -ENOMEM;
  547. goto out_free_memory;
  548. }
  549. /* Map XDR buffer to RSX */
  550. xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
  551. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  552. xdr_lpar, XDR_BUF_SIZE,
  553. CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
  554. CBE_IOPTE_M);
  555. if (status) {
  556. dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
  557. status);
  558. error = -ENOMEM;
  559. goto out_free_context;
  560. }
  561. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  562. if (!priv->ctrl) {
  563. dev_err(&dev->core, "ioremap CTRL failed\n");
  564. error = -ENOMEM;
  565. goto out_unmap_context;
  566. }
  567. priv->reports = ioremap(reports_lpar, reports_size);
  568. if (!priv->reports) {
  569. dev_err(&dev->core, "ioremap REPORTS failed\n");
  570. error = -ENOMEM;
  571. goto out_unmap_ctrl;
  572. }
  573. mutex_lock(&ps3_gpu_mutex);
  574. ps3vram_init_ring(dev);
  575. mutex_unlock(&ps3_gpu_mutex);
  576. priv->size = ddr_size;
  577. ps3vram_bind(dev);
  578. mutex_lock(&ps3_gpu_mutex);
  579. error = ps3vram_wait_ring(dev, 100);
  580. mutex_unlock(&ps3_gpu_mutex);
  581. if (error < 0) {
  582. dev_err(&dev->core, "Failed to initialize channels\n");
  583. error = -ETIMEDOUT;
  584. goto out_unmap_reports;
  585. }
  586. ps3vram_cache_init(dev);
  587. ps3vram_proc_init(dev);
  588. queue = blk_alloc_queue(GFP_KERNEL);
  589. if (!queue) {
  590. dev_err(&dev->core, "blk_alloc_queue failed\n");
  591. error = -ENOMEM;
  592. goto out_cache_cleanup;
  593. }
  594. priv->queue = queue;
  595. queue->queuedata = dev;
  596. blk_queue_make_request(queue, ps3vram_make_request);
  597. blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS);
  598. blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS);
  599. blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE);
  600. blk_queue_max_sectors(queue, SAFE_MAX_SECTORS);
  601. gendisk = alloc_disk(1);
  602. if (!gendisk) {
  603. dev_err(&dev->core, "alloc_disk failed\n");
  604. error = -ENOMEM;
  605. goto fail_cleanup_queue;
  606. }
  607. priv->gendisk = gendisk;
  608. gendisk->major = ps3vram_major;
  609. gendisk->first_minor = 0;
  610. gendisk->fops = &ps3vram_fops;
  611. gendisk->queue = queue;
  612. gendisk->private_data = dev;
  613. gendisk->driverfs_dev = &dev->core;
  614. strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
  615. set_capacity(gendisk, priv->size >> 9);
  616. dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
  617. gendisk->disk_name, get_capacity(gendisk) >> 11);
  618. add_disk(gendisk);
  619. return 0;
  620. fail_cleanup_queue:
  621. blk_cleanup_queue(queue);
  622. out_cache_cleanup:
  623. remove_proc_entry(DEVICE_NAME, NULL);
  624. ps3vram_cache_cleanup(dev);
  625. out_unmap_reports:
  626. iounmap(priv->reports);
  627. out_unmap_ctrl:
  628. iounmap(priv->ctrl);
  629. out_unmap_context:
  630. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
  631. XDR_BUF_SIZE, CBE_IOPTE_M);
  632. out_free_context:
  633. lv1_gpu_context_free(priv->context_handle);
  634. out_free_memory:
  635. lv1_gpu_memory_free(priv->memory_handle);
  636. out_close_gpu:
  637. ps3_close_hv_device(dev);
  638. out_free_xdr_buf:
  639. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  640. fail_free_priv:
  641. kfree(priv);
  642. ps3_system_bus_set_drvdata(dev, NULL);
  643. fail:
  644. return error;
  645. }
  646. static int ps3vram_remove(struct ps3_system_bus_device *dev)
  647. {
  648. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  649. del_gendisk(priv->gendisk);
  650. put_disk(priv->gendisk);
  651. blk_cleanup_queue(priv->queue);
  652. remove_proc_entry(DEVICE_NAME, NULL);
  653. ps3vram_cache_cleanup(dev);
  654. iounmap(priv->reports);
  655. iounmap(priv->ctrl);
  656. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  657. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  658. XDR_BUF_SIZE, CBE_IOPTE_M);
  659. lv1_gpu_context_free(priv->context_handle);
  660. lv1_gpu_memory_free(priv->memory_handle);
  661. ps3_close_hv_device(dev);
  662. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  663. kfree(priv);
  664. ps3_system_bus_set_drvdata(dev, NULL);
  665. return 0;
  666. }
  667. static struct ps3_system_bus_driver ps3vram = {
  668. .match_id = PS3_MATCH_ID_GPU,
  669. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  670. .core.name = DEVICE_NAME,
  671. .core.owner = THIS_MODULE,
  672. .probe = ps3vram_probe,
  673. .remove = ps3vram_remove,
  674. .shutdown = ps3vram_remove,
  675. };
  676. static int __init ps3vram_init(void)
  677. {
  678. int error;
  679. if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
  680. return -ENODEV;
  681. error = register_blkdev(0, DEVICE_NAME);
  682. if (error <= 0) {
  683. pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
  684. return error;
  685. }
  686. ps3vram_major = error;
  687. pr_info("%s: registered block device major %d\n", DEVICE_NAME,
  688. ps3vram_major);
  689. error = ps3_system_bus_driver_register(&ps3vram);
  690. if (error)
  691. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  692. return error;
  693. }
  694. static void __exit ps3vram_exit(void)
  695. {
  696. ps3_system_bus_driver_unregister(&ps3vram);
  697. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  698. }
  699. module_init(ps3vram_init);
  700. module_exit(ps3vram_exit);
  701. MODULE_LICENSE("GPL");
  702. MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
  703. MODULE_AUTHOR("Sony Corporation");
  704. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);