sata_mv.c 117 KB

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  1. /*
  2. * sata_mv.c - Marvell SATA support
  3. *
  4. * Copyright 2008-2009: Marvell Corporation, all rights reserved.
  5. * Copyright 2005: EMC Corporation, all rights reserved.
  6. * Copyright 2005 Red Hat, Inc. All rights reserved.
  7. *
  8. * Originally written by Brett Russ.
  9. * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
  10. *
  11. * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; version 2 of the License.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. /*
  28. * sata_mv TODO list:
  29. *
  30. * --> Develop a low-power-consumption strategy, and implement it.
  31. *
  32. * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
  33. *
  34. * --> [Experiment, Marvell value added] Is it possible to use target
  35. * mode to cross-connect two Linux boxes with Marvell cards? If so,
  36. * creating LibATA target mode support would be very interesting.
  37. *
  38. * Target mode, for those without docs, is the ability to directly
  39. * connect two SATA ports.
  40. */
  41. /*
  42. * 80x1-B2 errata PCI#11:
  43. *
  44. * Users of the 6041/6081 Rev.B2 chips (current is C0)
  45. * should be careful to insert those cards only onto PCI-X bus #0,
  46. * and only in device slots 0..7, not higher. The chips may not
  47. * work correctly otherwise (note: this is a pretty rare condition).
  48. */
  49. #include <linux/kernel.h>
  50. #include <linux/module.h>
  51. #include <linux/pci.h>
  52. #include <linux/init.h>
  53. #include <linux/blkdev.h>
  54. #include <linux/delay.h>
  55. #include <linux/interrupt.h>
  56. #include <linux/dmapool.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/device.h>
  59. #include <linux/platform_device.h>
  60. #include <linux/ata_platform.h>
  61. #include <linux/mbus.h>
  62. #include <linux/bitops.h>
  63. #include <scsi/scsi_host.h>
  64. #include <scsi/scsi_cmnd.h>
  65. #include <scsi/scsi_device.h>
  66. #include <linux/libata.h>
  67. #define DRV_NAME "sata_mv"
  68. #define DRV_VERSION "1.28"
  69. /*
  70. * module options
  71. */
  72. static int msi;
  73. #ifdef CONFIG_PCI
  74. module_param(msi, int, S_IRUGO);
  75. MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  76. #endif
  77. static int irq_coalescing_io_count;
  78. module_param(irq_coalescing_io_count, int, S_IRUGO);
  79. MODULE_PARM_DESC(irq_coalescing_io_count,
  80. "IRQ coalescing I/O count threshold (0..255)");
  81. static int irq_coalescing_usecs;
  82. module_param(irq_coalescing_usecs, int, S_IRUGO);
  83. MODULE_PARM_DESC(irq_coalescing_usecs,
  84. "IRQ coalescing time threshold in usecs");
  85. enum {
  86. /* BAR's are enumerated in terms of pci_resource_start() terms */
  87. MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
  88. MV_IO_BAR = 2, /* offset 0x18: IO space */
  89. MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
  90. MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
  91. MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
  92. /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
  93. COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
  94. MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
  95. MAX_COAL_IO_COUNT = 255, /* completed I/O count */
  96. MV_PCI_REG_BASE = 0,
  97. /*
  98. * Per-chip ("all ports") interrupt coalescing feature.
  99. * This is only for GEN_II / GEN_IIE hardware.
  100. *
  101. * Coalescing defers the interrupt until either the IO_THRESHOLD
  102. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  103. */
  104. COAL_REG_BASE = 0x18000,
  105. IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
  106. ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
  107. IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
  108. IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
  109. /*
  110. * Registers for the (unused here) transaction coalescing feature:
  111. */
  112. TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
  113. TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
  114. SATAHC0_REG_BASE = 0x20000,
  115. FLASH_CTL = 0x1046c,
  116. GPIO_PORT_CTL = 0x104f0,
  117. RESET_CFG = 0x180d8,
  118. MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  119. MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  120. MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
  121. MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
  122. MV_MAX_Q_DEPTH = 32,
  123. MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
  124. /* CRQB needs alignment on a 1KB boundary. Size == 1KB
  125. * CRPB needs alignment on a 256B boundary. Size == 256B
  126. * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
  127. */
  128. MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
  129. MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
  130. MV_MAX_SG_CT = 256,
  131. MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
  132. /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
  133. MV_PORT_HC_SHIFT = 2,
  134. MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
  135. /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
  136. MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
  137. /* Host Flags */
  138. MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
  139. MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  140. ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
  141. MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
  142. MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
  143. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
  144. MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
  145. CRQB_FLAG_READ = (1 << 0),
  146. CRQB_TAG_SHIFT = 1,
  147. CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
  148. CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
  149. CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
  150. CRQB_CMD_ADDR_SHIFT = 8,
  151. CRQB_CMD_CS = (0x2 << 11),
  152. CRQB_CMD_LAST = (1 << 15),
  153. CRPB_FLAG_STATUS_SHIFT = 8,
  154. CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
  155. CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
  156. EPRD_FLAG_END_OF_TBL = (1 << 31),
  157. /* PCI interface registers */
  158. MV_PCI_COMMAND = 0xc00,
  159. MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
  160. MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
  161. PCI_MAIN_CMD_STS = 0xd30,
  162. STOP_PCI_MASTER = (1 << 2),
  163. PCI_MASTER_EMPTY = (1 << 3),
  164. GLOB_SFT_RST = (1 << 4),
  165. MV_PCI_MODE = 0xd00,
  166. MV_PCI_MODE_MASK = 0x30,
  167. MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
  168. MV_PCI_DISC_TIMER = 0xd04,
  169. MV_PCI_MSI_TRIGGER = 0xc38,
  170. MV_PCI_SERR_MASK = 0xc28,
  171. MV_PCI_XBAR_TMOUT = 0x1d04,
  172. MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
  173. MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
  174. MV_PCI_ERR_ATTRIBUTE = 0x1d48,
  175. MV_PCI_ERR_COMMAND = 0x1d50,
  176. PCI_IRQ_CAUSE = 0x1d58,
  177. PCI_IRQ_MASK = 0x1d5c,
  178. PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
  179. PCIE_IRQ_CAUSE = 0x1900,
  180. PCIE_IRQ_MASK = 0x1910,
  181. PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
  182. /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
  183. PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
  184. PCI_HC_MAIN_IRQ_MASK = 0x1d64,
  185. SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
  186. SOC_HC_MAIN_IRQ_MASK = 0x20024,
  187. ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
  188. DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
  189. HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
  190. HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
  191. DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
  192. DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
  193. PCI_ERR = (1 << 18),
  194. TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
  195. TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
  196. PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
  197. PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
  198. ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
  199. GPIO_INT = (1 << 22),
  200. SELF_INT = (1 << 23),
  201. TWSI_INT = (1 << 24),
  202. HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
  203. HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
  204. HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
  205. /* SATAHC registers */
  206. HC_CFG = 0x00,
  207. HC_IRQ_CAUSE = 0x14,
  208. DMA_IRQ = (1 << 0), /* shift by port # */
  209. HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
  210. DEV_IRQ = (1 << 8), /* shift by port # */
  211. /*
  212. * Per-HC (Host-Controller) interrupt coalescing feature.
  213. * This is present on all chip generations.
  214. *
  215. * Coalescing defers the interrupt until either the IO_THRESHOLD
  216. * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
  217. */
  218. HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
  219. HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
  220. SOC_LED_CTRL = 0x2c,
  221. SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
  222. SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
  223. /* with dev activity LED */
  224. /* Shadow block registers */
  225. SHD_BLK = 0x100,
  226. SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
  227. /* SATA registers */
  228. SATA_STATUS = 0x300, /* ctrl, err regs follow status */
  229. SATA_ACTIVE = 0x350,
  230. FIS_IRQ_CAUSE = 0x364,
  231. FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
  232. LTMODE = 0x30c, /* requires read-after-write */
  233. LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
  234. PHY_MODE2 = 0x330,
  235. PHY_MODE3 = 0x310,
  236. PHY_MODE4 = 0x314, /* requires read-after-write */
  237. PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
  238. PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
  239. PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
  240. PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
  241. SATA_IFCTL = 0x344,
  242. SATA_TESTCTL = 0x348,
  243. SATA_IFSTAT = 0x34c,
  244. VENDOR_UNIQUE_FIS = 0x35c,
  245. FISCFG = 0x360,
  246. FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
  247. FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
  248. PHY_MODE9_GEN2 = 0x398,
  249. PHY_MODE9_GEN1 = 0x39c,
  250. PHYCFG_OFS = 0x3a0, /* only in 65n devices */
  251. MV5_PHY_MODE = 0x74,
  252. MV5_LTMODE = 0x30,
  253. MV5_PHY_CTL = 0x0C,
  254. SATA_IFCFG = 0x050,
  255. MV_M2_PREAMP_MASK = 0x7e0,
  256. /* Port registers */
  257. EDMA_CFG = 0,
  258. EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
  259. EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
  260. EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
  261. EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
  262. EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
  263. EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
  264. EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
  265. EDMA_ERR_IRQ_CAUSE = 0x8,
  266. EDMA_ERR_IRQ_MASK = 0xc,
  267. EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
  268. EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
  269. EDMA_ERR_DEV = (1 << 2), /* device error */
  270. EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
  271. EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
  272. EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
  273. EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
  274. EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
  275. EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
  276. EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
  277. EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
  278. EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
  279. EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
  280. EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
  281. EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
  282. EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
  283. EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
  284. EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
  285. EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
  286. EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
  287. EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
  288. EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
  289. EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
  290. EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
  291. EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
  292. EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
  293. EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
  294. EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
  295. EDMA_ERR_OVERRUN_5 = (1 << 5),
  296. EDMA_ERR_UNDERRUN_5 = (1 << 6),
  297. EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
  298. EDMA_ERR_LNK_CTRL_RX_1 |
  299. EDMA_ERR_LNK_CTRL_RX_3 |
  300. EDMA_ERR_LNK_CTRL_TX,
  301. EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
  302. EDMA_ERR_PRD_PAR |
  303. EDMA_ERR_DEV_DCON |
  304. EDMA_ERR_DEV_CON |
  305. EDMA_ERR_SERR |
  306. EDMA_ERR_SELF_DIS |
  307. EDMA_ERR_CRQB_PAR |
  308. EDMA_ERR_CRPB_PAR |
  309. EDMA_ERR_INTRL_PAR |
  310. EDMA_ERR_IORDY |
  311. EDMA_ERR_LNK_CTRL_RX_2 |
  312. EDMA_ERR_LNK_DATA_RX |
  313. EDMA_ERR_LNK_DATA_TX |
  314. EDMA_ERR_TRANS_PROTO,
  315. EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
  316. EDMA_ERR_PRD_PAR |
  317. EDMA_ERR_DEV_DCON |
  318. EDMA_ERR_DEV_CON |
  319. EDMA_ERR_OVERRUN_5 |
  320. EDMA_ERR_UNDERRUN_5 |
  321. EDMA_ERR_SELF_DIS_5 |
  322. EDMA_ERR_CRQB_PAR |
  323. EDMA_ERR_CRPB_PAR |
  324. EDMA_ERR_INTRL_PAR |
  325. EDMA_ERR_IORDY,
  326. EDMA_REQ_Q_BASE_HI = 0x10,
  327. EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
  328. EDMA_REQ_Q_OUT_PTR = 0x18,
  329. EDMA_REQ_Q_PTR_SHIFT = 5,
  330. EDMA_RSP_Q_BASE_HI = 0x1c,
  331. EDMA_RSP_Q_IN_PTR = 0x20,
  332. EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
  333. EDMA_RSP_Q_PTR_SHIFT = 3,
  334. EDMA_CMD = 0x28, /* EDMA command register */
  335. EDMA_EN = (1 << 0), /* enable EDMA */
  336. EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
  337. EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
  338. EDMA_STATUS = 0x30, /* EDMA engine status */
  339. EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
  340. EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
  341. EDMA_IORDY_TMOUT = 0x34,
  342. EDMA_ARB_CFG = 0x38,
  343. EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
  344. EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
  345. BMDMA_CMD = 0x224, /* bmdma command register */
  346. BMDMA_STATUS = 0x228, /* bmdma status register */
  347. BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
  348. BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
  349. /* Host private flags (hp_flags) */
  350. MV_HP_FLAG_MSI = (1 << 0),
  351. MV_HP_ERRATA_50XXB0 = (1 << 1),
  352. MV_HP_ERRATA_50XXB2 = (1 << 2),
  353. MV_HP_ERRATA_60X1B2 = (1 << 3),
  354. MV_HP_ERRATA_60X1C0 = (1 << 4),
  355. MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
  356. MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
  357. MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
  358. MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
  359. MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
  360. MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
  361. MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
  362. /* Port private flags (pp_flags) */
  363. MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
  364. MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
  365. MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
  366. MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
  367. MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
  368. };
  369. #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
  370. #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
  371. #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
  372. #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
  373. #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
  374. #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
  375. #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
  376. enum {
  377. /* DMA boundary 0xffff is required by the s/g splitting
  378. * we need on /length/ in mv_fill-sg().
  379. */
  380. MV_DMA_BOUNDARY = 0xffffU,
  381. /* mask of register bits containing lower 32 bits
  382. * of EDMA request queue DMA address
  383. */
  384. EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
  385. /* ditto, for response queue */
  386. EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
  387. };
  388. enum chip_type {
  389. chip_504x,
  390. chip_508x,
  391. chip_5080,
  392. chip_604x,
  393. chip_608x,
  394. chip_6042,
  395. chip_7042,
  396. chip_soc,
  397. };
  398. /* Command ReQuest Block: 32B */
  399. struct mv_crqb {
  400. __le32 sg_addr;
  401. __le32 sg_addr_hi;
  402. __le16 ctrl_flags;
  403. __le16 ata_cmd[11];
  404. };
  405. struct mv_crqb_iie {
  406. __le32 addr;
  407. __le32 addr_hi;
  408. __le32 flags;
  409. __le32 len;
  410. __le32 ata_cmd[4];
  411. };
  412. /* Command ResPonse Block: 8B */
  413. struct mv_crpb {
  414. __le16 id;
  415. __le16 flags;
  416. __le32 tmstmp;
  417. };
  418. /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
  419. struct mv_sg {
  420. __le32 addr;
  421. __le32 flags_size;
  422. __le32 addr_hi;
  423. __le32 reserved;
  424. };
  425. /*
  426. * We keep a local cache of a few frequently accessed port
  427. * registers here, to avoid having to read them (very slow)
  428. * when switching between EDMA and non-EDMA modes.
  429. */
  430. struct mv_cached_regs {
  431. u32 fiscfg;
  432. u32 ltmode;
  433. u32 haltcond;
  434. u32 unknown_rsvd;
  435. };
  436. struct mv_port_priv {
  437. struct mv_crqb *crqb;
  438. dma_addr_t crqb_dma;
  439. struct mv_crpb *crpb;
  440. dma_addr_t crpb_dma;
  441. struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
  442. dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
  443. unsigned int req_idx;
  444. unsigned int resp_idx;
  445. u32 pp_flags;
  446. struct mv_cached_regs cached;
  447. unsigned int delayed_eh_pmp_map;
  448. };
  449. struct mv_port_signal {
  450. u32 amps;
  451. u32 pre;
  452. };
  453. struct mv_host_priv {
  454. u32 hp_flags;
  455. u32 main_irq_mask;
  456. struct mv_port_signal signal[8];
  457. const struct mv_hw_ops *ops;
  458. int n_ports;
  459. void __iomem *base;
  460. void __iomem *main_irq_cause_addr;
  461. void __iomem *main_irq_mask_addr;
  462. u32 irq_cause_offset;
  463. u32 irq_mask_offset;
  464. u32 unmask_all_irqs;
  465. /*
  466. * These consistent DMA memory pools give us guaranteed
  467. * alignment for hardware-accessed data structures,
  468. * and less memory waste in accomplishing the alignment.
  469. */
  470. struct dma_pool *crqb_pool;
  471. struct dma_pool *crpb_pool;
  472. struct dma_pool *sg_tbl_pool;
  473. };
  474. struct mv_hw_ops {
  475. void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
  476. unsigned int port);
  477. void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
  478. void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
  479. void __iomem *mmio);
  480. int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
  481. unsigned int n_hc);
  482. void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
  483. void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
  484. };
  485. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  486. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  487. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
  488. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
  489. static int mv_port_start(struct ata_port *ap);
  490. static void mv_port_stop(struct ata_port *ap);
  491. static int mv_qc_defer(struct ata_queued_cmd *qc);
  492. static void mv_qc_prep(struct ata_queued_cmd *qc);
  493. static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
  494. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
  495. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  496. unsigned long deadline);
  497. static void mv_eh_freeze(struct ata_port *ap);
  498. static void mv_eh_thaw(struct ata_port *ap);
  499. static void mv6_dev_config(struct ata_device *dev);
  500. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  501. unsigned int port);
  502. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  503. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  504. void __iomem *mmio);
  505. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  506. unsigned int n_hc);
  507. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  508. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
  509. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  510. unsigned int port);
  511. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  512. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  513. void __iomem *mmio);
  514. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  515. unsigned int n_hc);
  516. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  517. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  518. void __iomem *mmio);
  519. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  520. void __iomem *mmio);
  521. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  522. void __iomem *mmio, unsigned int n_hc);
  523. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  524. void __iomem *mmio);
  525. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
  526. static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
  527. void __iomem *mmio, unsigned int port);
  528. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
  529. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  530. unsigned int port_no);
  531. static int mv_stop_edma(struct ata_port *ap);
  532. static int mv_stop_edma_engine(void __iomem *port_mmio);
  533. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
  534. static void mv_pmp_select(struct ata_port *ap, int pmp);
  535. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  536. unsigned long deadline);
  537. static int mv_softreset(struct ata_link *link, unsigned int *class,
  538. unsigned long deadline);
  539. static void mv_pmp_error_handler(struct ata_port *ap);
  540. static void mv_process_crpb_entries(struct ata_port *ap,
  541. struct mv_port_priv *pp);
  542. static void mv_sff_irq_clear(struct ata_port *ap);
  543. static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
  544. static void mv_bmdma_setup(struct ata_queued_cmd *qc);
  545. static void mv_bmdma_start(struct ata_queued_cmd *qc);
  546. static void mv_bmdma_stop(struct ata_queued_cmd *qc);
  547. static u8 mv_bmdma_status(struct ata_port *ap);
  548. static u8 mv_sff_check_status(struct ata_port *ap);
  549. /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
  550. * because we have to allow room for worst case splitting of
  551. * PRDs for 64K boundaries in mv_fill_sg().
  552. */
  553. static struct scsi_host_template mv5_sht = {
  554. ATA_BASE_SHT(DRV_NAME),
  555. .sg_tablesize = MV_MAX_SG_CT / 2,
  556. .dma_boundary = MV_DMA_BOUNDARY,
  557. };
  558. static struct scsi_host_template mv6_sht = {
  559. ATA_NCQ_SHT(DRV_NAME),
  560. .can_queue = MV_MAX_Q_DEPTH - 1,
  561. .sg_tablesize = MV_MAX_SG_CT / 2,
  562. .dma_boundary = MV_DMA_BOUNDARY,
  563. };
  564. static struct ata_port_operations mv5_ops = {
  565. .inherits = &ata_sff_port_ops,
  566. .lost_interrupt = ATA_OP_NULL,
  567. .qc_defer = mv_qc_defer,
  568. .qc_prep = mv_qc_prep,
  569. .qc_issue = mv_qc_issue,
  570. .freeze = mv_eh_freeze,
  571. .thaw = mv_eh_thaw,
  572. .hardreset = mv_hardreset,
  573. .error_handler = ata_std_error_handler, /* avoid SFF EH */
  574. .post_internal_cmd = ATA_OP_NULL,
  575. .scr_read = mv5_scr_read,
  576. .scr_write = mv5_scr_write,
  577. .port_start = mv_port_start,
  578. .port_stop = mv_port_stop,
  579. };
  580. static struct ata_port_operations mv6_ops = {
  581. .inherits = &mv5_ops,
  582. .dev_config = mv6_dev_config,
  583. .scr_read = mv_scr_read,
  584. .scr_write = mv_scr_write,
  585. .pmp_hardreset = mv_pmp_hardreset,
  586. .pmp_softreset = mv_softreset,
  587. .softreset = mv_softreset,
  588. .error_handler = mv_pmp_error_handler,
  589. .sff_check_status = mv_sff_check_status,
  590. .sff_irq_clear = mv_sff_irq_clear,
  591. .check_atapi_dma = mv_check_atapi_dma,
  592. .bmdma_setup = mv_bmdma_setup,
  593. .bmdma_start = mv_bmdma_start,
  594. .bmdma_stop = mv_bmdma_stop,
  595. .bmdma_status = mv_bmdma_status,
  596. };
  597. static struct ata_port_operations mv_iie_ops = {
  598. .inherits = &mv6_ops,
  599. .dev_config = ATA_OP_NULL,
  600. .qc_prep = mv_qc_prep_iie,
  601. };
  602. static const struct ata_port_info mv_port_info[] = {
  603. { /* chip_504x */
  604. .flags = MV_GEN_I_FLAGS,
  605. .pio_mask = ATA_PIO4,
  606. .udma_mask = ATA_UDMA6,
  607. .port_ops = &mv5_ops,
  608. },
  609. { /* chip_508x */
  610. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  611. .pio_mask = ATA_PIO4,
  612. .udma_mask = ATA_UDMA6,
  613. .port_ops = &mv5_ops,
  614. },
  615. { /* chip_5080 */
  616. .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
  617. .pio_mask = ATA_PIO4,
  618. .udma_mask = ATA_UDMA6,
  619. .port_ops = &mv5_ops,
  620. },
  621. { /* chip_604x */
  622. .flags = MV_GEN_II_FLAGS,
  623. .pio_mask = ATA_PIO4,
  624. .udma_mask = ATA_UDMA6,
  625. .port_ops = &mv6_ops,
  626. },
  627. { /* chip_608x */
  628. .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
  629. .pio_mask = ATA_PIO4,
  630. .udma_mask = ATA_UDMA6,
  631. .port_ops = &mv6_ops,
  632. },
  633. { /* chip_6042 */
  634. .flags = MV_GEN_IIE_FLAGS,
  635. .pio_mask = ATA_PIO4,
  636. .udma_mask = ATA_UDMA6,
  637. .port_ops = &mv_iie_ops,
  638. },
  639. { /* chip_7042 */
  640. .flags = MV_GEN_IIE_FLAGS,
  641. .pio_mask = ATA_PIO4,
  642. .udma_mask = ATA_UDMA6,
  643. .port_ops = &mv_iie_ops,
  644. },
  645. { /* chip_soc */
  646. .flags = MV_GEN_IIE_FLAGS,
  647. .pio_mask = ATA_PIO4,
  648. .udma_mask = ATA_UDMA6,
  649. .port_ops = &mv_iie_ops,
  650. },
  651. };
  652. static const struct pci_device_id mv_pci_tbl[] = {
  653. { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
  654. { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
  655. { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
  656. { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
  657. /* RocketRAID 1720/174x have different identifiers */
  658. { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
  659. { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
  660. { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
  661. { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
  662. { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
  663. { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
  664. { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
  665. { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
  666. { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
  667. /* Adaptec 1430SA */
  668. { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
  669. /* Marvell 7042 support */
  670. { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
  671. /* Highpoint RocketRAID PCIe series */
  672. { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
  673. { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
  674. { } /* terminate list */
  675. };
  676. static const struct mv_hw_ops mv5xxx_ops = {
  677. .phy_errata = mv5_phy_errata,
  678. .enable_leds = mv5_enable_leds,
  679. .read_preamp = mv5_read_preamp,
  680. .reset_hc = mv5_reset_hc,
  681. .reset_flash = mv5_reset_flash,
  682. .reset_bus = mv5_reset_bus,
  683. };
  684. static const struct mv_hw_ops mv6xxx_ops = {
  685. .phy_errata = mv6_phy_errata,
  686. .enable_leds = mv6_enable_leds,
  687. .read_preamp = mv6_read_preamp,
  688. .reset_hc = mv6_reset_hc,
  689. .reset_flash = mv6_reset_flash,
  690. .reset_bus = mv_reset_pci_bus,
  691. };
  692. static const struct mv_hw_ops mv_soc_ops = {
  693. .phy_errata = mv6_phy_errata,
  694. .enable_leds = mv_soc_enable_leds,
  695. .read_preamp = mv_soc_read_preamp,
  696. .reset_hc = mv_soc_reset_hc,
  697. .reset_flash = mv_soc_reset_flash,
  698. .reset_bus = mv_soc_reset_bus,
  699. };
  700. static const struct mv_hw_ops mv_soc_65n_ops = {
  701. .phy_errata = mv_soc_65n_phy_errata,
  702. .enable_leds = mv_soc_enable_leds,
  703. .reset_hc = mv_soc_reset_hc,
  704. .reset_flash = mv_soc_reset_flash,
  705. .reset_bus = mv_soc_reset_bus,
  706. };
  707. /*
  708. * Functions
  709. */
  710. static inline void writelfl(unsigned long data, void __iomem *addr)
  711. {
  712. writel(data, addr);
  713. (void) readl(addr); /* flush to avoid PCI posted write */
  714. }
  715. static inline unsigned int mv_hc_from_port(unsigned int port)
  716. {
  717. return port >> MV_PORT_HC_SHIFT;
  718. }
  719. static inline unsigned int mv_hardport_from_port(unsigned int port)
  720. {
  721. return port & MV_PORT_MASK;
  722. }
  723. /*
  724. * Consolidate some rather tricky bit shift calculations.
  725. * This is hot-path stuff, so not a function.
  726. * Simple code, with two return values, so macro rather than inline.
  727. *
  728. * port is the sole input, in range 0..7.
  729. * shift is one output, for use with main_irq_cause / main_irq_mask registers.
  730. * hardport is the other output, in range 0..3.
  731. *
  732. * Note that port and hardport may be the same variable in some cases.
  733. */
  734. #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
  735. { \
  736. shift = mv_hc_from_port(port) * HC_SHIFT; \
  737. hardport = mv_hardport_from_port(port); \
  738. shift += hardport * 2; \
  739. }
  740. static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
  741. {
  742. return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
  743. }
  744. static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
  745. unsigned int port)
  746. {
  747. return mv_hc_base(base, mv_hc_from_port(port));
  748. }
  749. static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
  750. {
  751. return mv_hc_base_from_port(base, port) +
  752. MV_SATAHC_ARBTR_REG_SZ +
  753. (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
  754. }
  755. static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
  756. {
  757. void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
  758. unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
  759. return hc_mmio + ofs;
  760. }
  761. static inline void __iomem *mv_host_base(struct ata_host *host)
  762. {
  763. struct mv_host_priv *hpriv = host->private_data;
  764. return hpriv->base;
  765. }
  766. static inline void __iomem *mv_ap_base(struct ata_port *ap)
  767. {
  768. return mv_port_base(mv_host_base(ap->host), ap->port_no);
  769. }
  770. static inline int mv_get_hc_count(unsigned long port_flags)
  771. {
  772. return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
  773. }
  774. /**
  775. * mv_save_cached_regs - (re-)initialize cached port registers
  776. * @ap: the port whose registers we are caching
  777. *
  778. * Initialize the local cache of port registers,
  779. * so that reading them over and over again can
  780. * be avoided on the hotter paths of this driver.
  781. * This saves a few microseconds each time we switch
  782. * to/from EDMA mode to perform (eg.) a drive cache flush.
  783. */
  784. static void mv_save_cached_regs(struct ata_port *ap)
  785. {
  786. void __iomem *port_mmio = mv_ap_base(ap);
  787. struct mv_port_priv *pp = ap->private_data;
  788. pp->cached.fiscfg = readl(port_mmio + FISCFG);
  789. pp->cached.ltmode = readl(port_mmio + LTMODE);
  790. pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
  791. pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
  792. }
  793. /**
  794. * mv_write_cached_reg - write to a cached port register
  795. * @addr: hardware address of the register
  796. * @old: pointer to cached value of the register
  797. * @new: new value for the register
  798. *
  799. * Write a new value to a cached register,
  800. * but only if the value is different from before.
  801. */
  802. static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
  803. {
  804. if (new != *old) {
  805. unsigned long laddr;
  806. *old = new;
  807. /*
  808. * Workaround for 88SX60x1-B2 FEr SATA#13:
  809. * Read-after-write is needed to prevent generating 64-bit
  810. * write cycles on the PCI bus for SATA interface registers
  811. * at offsets ending in 0x4 or 0xc.
  812. *
  813. * Looks like a lot of fuss, but it avoids an unnecessary
  814. * +1 usec read-after-write delay for unaffected registers.
  815. */
  816. laddr = (long)addr & 0xffff;
  817. if (laddr >= 0x300 && laddr <= 0x33c) {
  818. laddr &= 0x000f;
  819. if (laddr == 0x4 || laddr == 0xc) {
  820. writelfl(new, addr); /* read after write */
  821. return;
  822. }
  823. }
  824. writel(new, addr); /* unaffected by the errata */
  825. }
  826. }
  827. static void mv_set_edma_ptrs(void __iomem *port_mmio,
  828. struct mv_host_priv *hpriv,
  829. struct mv_port_priv *pp)
  830. {
  831. u32 index;
  832. /*
  833. * initialize request queue
  834. */
  835. pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  836. index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  837. WARN_ON(pp->crqb_dma & 0x3ff);
  838. writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
  839. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
  840. port_mmio + EDMA_REQ_Q_IN_PTR);
  841. writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
  842. /*
  843. * initialize response queue
  844. */
  845. pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
  846. index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
  847. WARN_ON(pp->crpb_dma & 0xff);
  848. writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
  849. writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
  850. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
  851. port_mmio + EDMA_RSP_Q_OUT_PTR);
  852. }
  853. static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
  854. {
  855. /*
  856. * When writing to the main_irq_mask in hardware,
  857. * we must ensure exclusivity between the interrupt coalescing bits
  858. * and the corresponding individual port DONE_IRQ bits.
  859. *
  860. * Note that this register is really an "IRQ enable" register,
  861. * not an "IRQ mask" register as Marvell's naming might suggest.
  862. */
  863. if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
  864. mask &= ~DONE_IRQ_0_3;
  865. if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
  866. mask &= ~DONE_IRQ_4_7;
  867. writelfl(mask, hpriv->main_irq_mask_addr);
  868. }
  869. static void mv_set_main_irq_mask(struct ata_host *host,
  870. u32 disable_bits, u32 enable_bits)
  871. {
  872. struct mv_host_priv *hpriv = host->private_data;
  873. u32 old_mask, new_mask;
  874. old_mask = hpriv->main_irq_mask;
  875. new_mask = (old_mask & ~disable_bits) | enable_bits;
  876. if (new_mask != old_mask) {
  877. hpriv->main_irq_mask = new_mask;
  878. mv_write_main_irq_mask(new_mask, hpriv);
  879. }
  880. }
  881. static void mv_enable_port_irqs(struct ata_port *ap,
  882. unsigned int port_bits)
  883. {
  884. unsigned int shift, hardport, port = ap->port_no;
  885. u32 disable_bits, enable_bits;
  886. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  887. disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
  888. enable_bits = port_bits << shift;
  889. mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
  890. }
  891. static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
  892. void __iomem *port_mmio,
  893. unsigned int port_irqs)
  894. {
  895. struct mv_host_priv *hpriv = ap->host->private_data;
  896. int hardport = mv_hardport_from_port(ap->port_no);
  897. void __iomem *hc_mmio = mv_hc_base_from_port(
  898. mv_host_base(ap->host), ap->port_no);
  899. u32 hc_irq_cause;
  900. /* clear EDMA event indicators, if any */
  901. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  902. /* clear pending irq events */
  903. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  904. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  905. /* clear FIS IRQ Cause */
  906. if (IS_GEN_IIE(hpriv))
  907. writelfl(0, port_mmio + FIS_IRQ_CAUSE);
  908. mv_enable_port_irqs(ap, port_irqs);
  909. }
  910. static void mv_set_irq_coalescing(struct ata_host *host,
  911. unsigned int count, unsigned int usecs)
  912. {
  913. struct mv_host_priv *hpriv = host->private_data;
  914. void __iomem *mmio = hpriv->base, *hc_mmio;
  915. u32 coal_enable = 0;
  916. unsigned long flags;
  917. unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
  918. const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
  919. ALL_PORTS_COAL_DONE;
  920. /* Disable IRQ coalescing if either threshold is zero */
  921. if (!usecs || !count) {
  922. clks = count = 0;
  923. } else {
  924. /* Respect maximum limits of the hardware */
  925. clks = usecs * COAL_CLOCKS_PER_USEC;
  926. if (clks > MAX_COAL_TIME_THRESHOLD)
  927. clks = MAX_COAL_TIME_THRESHOLD;
  928. if (count > MAX_COAL_IO_COUNT)
  929. count = MAX_COAL_IO_COUNT;
  930. }
  931. spin_lock_irqsave(&host->lock, flags);
  932. mv_set_main_irq_mask(host, coal_disable, 0);
  933. if (is_dual_hc && !IS_GEN_I(hpriv)) {
  934. /*
  935. * GEN_II/GEN_IIE with dual host controllers:
  936. * one set of global thresholds for the entire chip.
  937. */
  938. writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
  939. writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
  940. /* clear leftover coal IRQ bit */
  941. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  942. if (count)
  943. coal_enable = ALL_PORTS_COAL_DONE;
  944. clks = count = 0; /* force clearing of regular regs below */
  945. }
  946. /*
  947. * All chips: independent thresholds for each HC on the chip.
  948. */
  949. hc_mmio = mv_hc_base_from_port(mmio, 0);
  950. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  951. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  952. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  953. if (count)
  954. coal_enable |= PORTS_0_3_COAL_DONE;
  955. if (is_dual_hc) {
  956. hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
  957. writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
  958. writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
  959. writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
  960. if (count)
  961. coal_enable |= PORTS_4_7_COAL_DONE;
  962. }
  963. mv_set_main_irq_mask(host, 0, coal_enable);
  964. spin_unlock_irqrestore(&host->lock, flags);
  965. }
  966. /**
  967. * mv_start_edma - Enable eDMA engine
  968. * @base: port base address
  969. * @pp: port private data
  970. *
  971. * Verify the local cache of the eDMA state is accurate with a
  972. * WARN_ON.
  973. *
  974. * LOCKING:
  975. * Inherited from caller.
  976. */
  977. static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
  978. struct mv_port_priv *pp, u8 protocol)
  979. {
  980. int want_ncq = (protocol == ATA_PROT_NCQ);
  981. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  982. int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
  983. if (want_ncq != using_ncq)
  984. mv_stop_edma(ap);
  985. }
  986. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
  987. struct mv_host_priv *hpriv = ap->host->private_data;
  988. mv_edma_cfg(ap, want_ncq, 1);
  989. mv_set_edma_ptrs(port_mmio, hpriv, pp);
  990. mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
  991. writelfl(EDMA_EN, port_mmio + EDMA_CMD);
  992. pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
  993. }
  994. }
  995. static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
  996. {
  997. void __iomem *port_mmio = mv_ap_base(ap);
  998. const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
  999. const int per_loop = 5, timeout = (15 * 1000 / per_loop);
  1000. int i;
  1001. /*
  1002. * Wait for the EDMA engine to finish transactions in progress.
  1003. * No idea what a good "timeout" value might be, but measurements
  1004. * indicate that it often requires hundreds of microseconds
  1005. * with two drives in-use. So we use the 15msec value above
  1006. * as a rough guess at what even more drives might require.
  1007. */
  1008. for (i = 0; i < timeout; ++i) {
  1009. u32 edma_stat = readl(port_mmio + EDMA_STATUS);
  1010. if ((edma_stat & empty_idle) == empty_idle)
  1011. break;
  1012. udelay(per_loop);
  1013. }
  1014. /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
  1015. }
  1016. /**
  1017. * mv_stop_edma_engine - Disable eDMA engine
  1018. * @port_mmio: io base address
  1019. *
  1020. * LOCKING:
  1021. * Inherited from caller.
  1022. */
  1023. static int mv_stop_edma_engine(void __iomem *port_mmio)
  1024. {
  1025. int i;
  1026. /* Disable eDMA. The disable bit auto clears. */
  1027. writelfl(EDMA_DS, port_mmio + EDMA_CMD);
  1028. /* Wait for the chip to confirm eDMA is off. */
  1029. for (i = 10000; i > 0; i--) {
  1030. u32 reg = readl(port_mmio + EDMA_CMD);
  1031. if (!(reg & EDMA_EN))
  1032. return 0;
  1033. udelay(10);
  1034. }
  1035. return -EIO;
  1036. }
  1037. static int mv_stop_edma(struct ata_port *ap)
  1038. {
  1039. void __iomem *port_mmio = mv_ap_base(ap);
  1040. struct mv_port_priv *pp = ap->private_data;
  1041. int err = 0;
  1042. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  1043. return 0;
  1044. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1045. mv_wait_for_edma_empty_idle(ap);
  1046. if (mv_stop_edma_engine(port_mmio)) {
  1047. ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
  1048. err = -EIO;
  1049. }
  1050. mv_edma_cfg(ap, 0, 0);
  1051. return err;
  1052. }
  1053. #ifdef ATA_DEBUG
  1054. static void mv_dump_mem(void __iomem *start, unsigned bytes)
  1055. {
  1056. int b, w;
  1057. for (b = 0; b < bytes; ) {
  1058. DPRINTK("%p: ", start + b);
  1059. for (w = 0; b < bytes && w < 4; w++) {
  1060. printk("%08x ", readl(start + b));
  1061. b += sizeof(u32);
  1062. }
  1063. printk("\n");
  1064. }
  1065. }
  1066. #endif
  1067. static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
  1068. {
  1069. #ifdef ATA_DEBUG
  1070. int b, w;
  1071. u32 dw;
  1072. for (b = 0; b < bytes; ) {
  1073. DPRINTK("%02x: ", b);
  1074. for (w = 0; b < bytes && w < 4; w++) {
  1075. (void) pci_read_config_dword(pdev, b, &dw);
  1076. printk("%08x ", dw);
  1077. b += sizeof(u32);
  1078. }
  1079. printk("\n");
  1080. }
  1081. #endif
  1082. }
  1083. static void mv_dump_all_regs(void __iomem *mmio_base, int port,
  1084. struct pci_dev *pdev)
  1085. {
  1086. #ifdef ATA_DEBUG
  1087. void __iomem *hc_base = mv_hc_base(mmio_base,
  1088. port >> MV_PORT_HC_SHIFT);
  1089. void __iomem *port_base;
  1090. int start_port, num_ports, p, start_hc, num_hcs, hc;
  1091. if (0 > port) {
  1092. start_hc = start_port = 0;
  1093. num_ports = 8; /* shld be benign for 4 port devs */
  1094. num_hcs = 2;
  1095. } else {
  1096. start_hc = port >> MV_PORT_HC_SHIFT;
  1097. start_port = port;
  1098. num_ports = num_hcs = 1;
  1099. }
  1100. DPRINTK("All registers for port(s) %u-%u:\n", start_port,
  1101. num_ports > 1 ? num_ports - 1 : start_port);
  1102. if (NULL != pdev) {
  1103. DPRINTK("PCI config space regs:\n");
  1104. mv_dump_pci_cfg(pdev, 0x68);
  1105. }
  1106. DPRINTK("PCI regs:\n");
  1107. mv_dump_mem(mmio_base+0xc00, 0x3c);
  1108. mv_dump_mem(mmio_base+0xd00, 0x34);
  1109. mv_dump_mem(mmio_base+0xf00, 0x4);
  1110. mv_dump_mem(mmio_base+0x1d00, 0x6c);
  1111. for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
  1112. hc_base = mv_hc_base(mmio_base, hc);
  1113. DPRINTK("HC regs (HC %i):\n", hc);
  1114. mv_dump_mem(hc_base, 0x1c);
  1115. }
  1116. for (p = start_port; p < start_port + num_ports; p++) {
  1117. port_base = mv_port_base(mmio_base, p);
  1118. DPRINTK("EDMA regs (port %i):\n", p);
  1119. mv_dump_mem(port_base, 0x54);
  1120. DPRINTK("SATA regs (port %i):\n", p);
  1121. mv_dump_mem(port_base+0x300, 0x60);
  1122. }
  1123. #endif
  1124. }
  1125. static unsigned int mv_scr_offset(unsigned int sc_reg_in)
  1126. {
  1127. unsigned int ofs;
  1128. switch (sc_reg_in) {
  1129. case SCR_STATUS:
  1130. case SCR_CONTROL:
  1131. case SCR_ERROR:
  1132. ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
  1133. break;
  1134. case SCR_ACTIVE:
  1135. ofs = SATA_ACTIVE; /* active is not with the others */
  1136. break;
  1137. default:
  1138. ofs = 0xffffffffU;
  1139. break;
  1140. }
  1141. return ofs;
  1142. }
  1143. static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  1144. {
  1145. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1146. if (ofs != 0xffffffffU) {
  1147. *val = readl(mv_ap_base(link->ap) + ofs);
  1148. return 0;
  1149. } else
  1150. return -EINVAL;
  1151. }
  1152. static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  1153. {
  1154. unsigned int ofs = mv_scr_offset(sc_reg_in);
  1155. if (ofs != 0xffffffffU) {
  1156. void __iomem *addr = mv_ap_base(link->ap) + ofs;
  1157. if (sc_reg_in == SCR_CONTROL) {
  1158. /*
  1159. * Workaround for 88SX60x1 FEr SATA#26:
  1160. *
  1161. * COMRESETs have to take care not to accidently
  1162. * put the drive to sleep when writing SCR_CONTROL.
  1163. * Setting bits 12..15 prevents this problem.
  1164. *
  1165. * So if we see an outbound COMMRESET, set those bits.
  1166. * Ditto for the followup write that clears the reset.
  1167. *
  1168. * The proprietary driver does this for
  1169. * all chip versions, and so do we.
  1170. */
  1171. if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
  1172. val |= 0xf000;
  1173. }
  1174. writelfl(val, addr);
  1175. return 0;
  1176. } else
  1177. return -EINVAL;
  1178. }
  1179. static void mv6_dev_config(struct ata_device *adev)
  1180. {
  1181. /*
  1182. * Deal with Gen-II ("mv6") hardware quirks/restrictions:
  1183. *
  1184. * Gen-II does not support NCQ over a port multiplier
  1185. * (no FIS-based switching).
  1186. */
  1187. if (adev->flags & ATA_DFLAG_NCQ) {
  1188. if (sata_pmp_attached(adev->link->ap)) {
  1189. adev->flags &= ~ATA_DFLAG_NCQ;
  1190. ata_dev_printk(adev, KERN_INFO,
  1191. "NCQ disabled for command-based switching\n");
  1192. }
  1193. }
  1194. }
  1195. static int mv_qc_defer(struct ata_queued_cmd *qc)
  1196. {
  1197. struct ata_link *link = qc->dev->link;
  1198. struct ata_port *ap = link->ap;
  1199. struct mv_port_priv *pp = ap->private_data;
  1200. /*
  1201. * Don't allow new commands if we're in a delayed EH state
  1202. * for NCQ and/or FIS-based switching.
  1203. */
  1204. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  1205. return ATA_DEFER_PORT;
  1206. /* PIO commands need exclusive link: no other commands [DMA or PIO]
  1207. * can run concurrently.
  1208. * set excl_link when we want to send a PIO command in DMA mode
  1209. * or a non-NCQ command in NCQ mode.
  1210. * When we receive a command from that link, and there are no
  1211. * outstanding commands, mark a flag to clear excl_link and let
  1212. * the command go through.
  1213. */
  1214. if (unlikely(ap->excl_link)) {
  1215. if (link == ap->excl_link) {
  1216. if (ap->nr_active_links)
  1217. return ATA_DEFER_PORT;
  1218. qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
  1219. return 0;
  1220. } else
  1221. return ATA_DEFER_PORT;
  1222. }
  1223. /*
  1224. * If the port is completely idle, then allow the new qc.
  1225. */
  1226. if (ap->nr_active_links == 0)
  1227. return 0;
  1228. /*
  1229. * The port is operating in host queuing mode (EDMA) with NCQ
  1230. * enabled, allow multiple NCQ commands. EDMA also allows
  1231. * queueing multiple DMA commands but libata core currently
  1232. * doesn't allow it.
  1233. */
  1234. if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
  1235. (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
  1236. if (ata_is_ncq(qc->tf.protocol))
  1237. return 0;
  1238. else {
  1239. ap->excl_link = link;
  1240. return ATA_DEFER_PORT;
  1241. }
  1242. }
  1243. return ATA_DEFER_PORT;
  1244. }
  1245. static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
  1246. {
  1247. struct mv_port_priv *pp = ap->private_data;
  1248. void __iomem *port_mmio;
  1249. u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
  1250. u32 ltmode, *old_ltmode = &pp->cached.ltmode;
  1251. u32 haltcond, *old_haltcond = &pp->cached.haltcond;
  1252. ltmode = *old_ltmode & ~LTMODE_BIT8;
  1253. haltcond = *old_haltcond | EDMA_ERR_DEV;
  1254. if (want_fbs) {
  1255. fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
  1256. ltmode = *old_ltmode | LTMODE_BIT8;
  1257. if (want_ncq)
  1258. haltcond &= ~EDMA_ERR_DEV;
  1259. else
  1260. fiscfg |= FISCFG_WAIT_DEV_ERR;
  1261. } else {
  1262. fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
  1263. }
  1264. port_mmio = mv_ap_base(ap);
  1265. mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
  1266. mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
  1267. mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
  1268. }
  1269. static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
  1270. {
  1271. struct mv_host_priv *hpriv = ap->host->private_data;
  1272. u32 old, new;
  1273. /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
  1274. old = readl(hpriv->base + GPIO_PORT_CTL);
  1275. if (want_ncq)
  1276. new = old | (1 << 22);
  1277. else
  1278. new = old & ~(1 << 22);
  1279. if (new != old)
  1280. writel(new, hpriv->base + GPIO_PORT_CTL);
  1281. }
  1282. /**
  1283. * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
  1284. * @ap: Port being initialized
  1285. *
  1286. * There are two DMA modes on these chips: basic DMA, and EDMA.
  1287. *
  1288. * Bit-0 of the "EDMA RESERVED" register enables/disables use
  1289. * of basic DMA on the GEN_IIE versions of the chips.
  1290. *
  1291. * This bit survives EDMA resets, and must be set for basic DMA
  1292. * to function, and should be cleared when EDMA is active.
  1293. */
  1294. static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
  1295. {
  1296. struct mv_port_priv *pp = ap->private_data;
  1297. u32 new, *old = &pp->cached.unknown_rsvd;
  1298. if (enable_bmdma)
  1299. new = *old | 1;
  1300. else
  1301. new = *old & ~1;
  1302. mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
  1303. }
  1304. /*
  1305. * SOC chips have an issue whereby the HDD LEDs don't always blink
  1306. * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
  1307. * of the SOC takes care of it, generating a steady blink rate when
  1308. * any drive on the chip is active.
  1309. *
  1310. * Unfortunately, the blink mode is a global hardware setting for the SOC,
  1311. * so we must use it whenever at least one port on the SOC has NCQ enabled.
  1312. *
  1313. * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
  1314. * LED operation works then, and provides better (more accurate) feedback.
  1315. *
  1316. * Note that this code assumes that an SOC never has more than one HC onboard.
  1317. */
  1318. static void mv_soc_led_blink_enable(struct ata_port *ap)
  1319. {
  1320. struct ata_host *host = ap->host;
  1321. struct mv_host_priv *hpriv = host->private_data;
  1322. void __iomem *hc_mmio;
  1323. u32 led_ctrl;
  1324. if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
  1325. return;
  1326. hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
  1327. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1328. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1329. writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1330. }
  1331. static void mv_soc_led_blink_disable(struct ata_port *ap)
  1332. {
  1333. struct ata_host *host = ap->host;
  1334. struct mv_host_priv *hpriv = host->private_data;
  1335. void __iomem *hc_mmio;
  1336. u32 led_ctrl;
  1337. unsigned int port;
  1338. if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
  1339. return;
  1340. /* disable led-blink only if no ports are using NCQ */
  1341. for (port = 0; port < hpriv->n_ports; port++) {
  1342. struct ata_port *this_ap = host->ports[port];
  1343. struct mv_port_priv *pp = this_ap->private_data;
  1344. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  1345. return;
  1346. }
  1347. hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
  1348. hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
  1349. led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
  1350. writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
  1351. }
  1352. static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
  1353. {
  1354. u32 cfg;
  1355. struct mv_port_priv *pp = ap->private_data;
  1356. struct mv_host_priv *hpriv = ap->host->private_data;
  1357. void __iomem *port_mmio = mv_ap_base(ap);
  1358. /* set up non-NCQ EDMA configuration */
  1359. cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
  1360. pp->pp_flags &=
  1361. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  1362. if (IS_GEN_I(hpriv))
  1363. cfg |= (1 << 8); /* enab config burst size mask */
  1364. else if (IS_GEN_II(hpriv)) {
  1365. cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
  1366. mv_60x1_errata_sata25(ap, want_ncq);
  1367. } else if (IS_GEN_IIE(hpriv)) {
  1368. int want_fbs = sata_pmp_attached(ap);
  1369. /*
  1370. * Possible future enhancement:
  1371. *
  1372. * The chip can use FBS with non-NCQ, if we allow it,
  1373. * But first we need to have the error handling in place
  1374. * for this mode (datasheet section 7.3.15.4.2.3).
  1375. * So disallow non-NCQ FBS for now.
  1376. */
  1377. want_fbs &= want_ncq;
  1378. mv_config_fbs(ap, want_ncq, want_fbs);
  1379. if (want_fbs) {
  1380. pp->pp_flags |= MV_PP_FLAG_FBS_EN;
  1381. cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
  1382. }
  1383. cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
  1384. if (want_edma) {
  1385. cfg |= (1 << 22); /* enab 4-entry host queue cache */
  1386. if (!IS_SOC(hpriv))
  1387. cfg |= (1 << 18); /* enab early completion */
  1388. }
  1389. if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
  1390. cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
  1391. mv_bmdma_enable_iie(ap, !want_edma);
  1392. if (IS_SOC(hpriv)) {
  1393. if (want_ncq)
  1394. mv_soc_led_blink_enable(ap);
  1395. else
  1396. mv_soc_led_blink_disable(ap);
  1397. }
  1398. }
  1399. if (want_ncq) {
  1400. cfg |= EDMA_CFG_NCQ;
  1401. pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
  1402. }
  1403. writelfl(cfg, port_mmio + EDMA_CFG);
  1404. }
  1405. static void mv_port_free_dma_mem(struct ata_port *ap)
  1406. {
  1407. struct mv_host_priv *hpriv = ap->host->private_data;
  1408. struct mv_port_priv *pp = ap->private_data;
  1409. int tag;
  1410. if (pp->crqb) {
  1411. dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
  1412. pp->crqb = NULL;
  1413. }
  1414. if (pp->crpb) {
  1415. dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
  1416. pp->crpb = NULL;
  1417. }
  1418. /*
  1419. * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
  1420. * For later hardware, we have one unique sg_tbl per NCQ tag.
  1421. */
  1422. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1423. if (pp->sg_tbl[tag]) {
  1424. if (tag == 0 || !IS_GEN_I(hpriv))
  1425. dma_pool_free(hpriv->sg_tbl_pool,
  1426. pp->sg_tbl[tag],
  1427. pp->sg_tbl_dma[tag]);
  1428. pp->sg_tbl[tag] = NULL;
  1429. }
  1430. }
  1431. }
  1432. /**
  1433. * mv_port_start - Port specific init/start routine.
  1434. * @ap: ATA channel to manipulate
  1435. *
  1436. * Allocate and point to DMA memory, init port private memory,
  1437. * zero indices.
  1438. *
  1439. * LOCKING:
  1440. * Inherited from caller.
  1441. */
  1442. static int mv_port_start(struct ata_port *ap)
  1443. {
  1444. struct device *dev = ap->host->dev;
  1445. struct mv_host_priv *hpriv = ap->host->private_data;
  1446. struct mv_port_priv *pp;
  1447. unsigned long flags;
  1448. int tag;
  1449. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1450. if (!pp)
  1451. return -ENOMEM;
  1452. ap->private_data = pp;
  1453. pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
  1454. if (!pp->crqb)
  1455. return -ENOMEM;
  1456. memset(pp->crqb, 0, MV_CRQB_Q_SZ);
  1457. pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
  1458. if (!pp->crpb)
  1459. goto out_port_free_dma_mem;
  1460. memset(pp->crpb, 0, MV_CRPB_Q_SZ);
  1461. /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
  1462. if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
  1463. ap->flags |= ATA_FLAG_AN;
  1464. /*
  1465. * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
  1466. * For later hardware, we need one unique sg_tbl per NCQ tag.
  1467. */
  1468. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1469. if (tag == 0 || !IS_GEN_I(hpriv)) {
  1470. pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
  1471. GFP_KERNEL, &pp->sg_tbl_dma[tag]);
  1472. if (!pp->sg_tbl[tag])
  1473. goto out_port_free_dma_mem;
  1474. } else {
  1475. pp->sg_tbl[tag] = pp->sg_tbl[0];
  1476. pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
  1477. }
  1478. }
  1479. spin_lock_irqsave(ap->lock, flags);
  1480. mv_save_cached_regs(ap);
  1481. mv_edma_cfg(ap, 0, 0);
  1482. spin_unlock_irqrestore(ap->lock, flags);
  1483. return 0;
  1484. out_port_free_dma_mem:
  1485. mv_port_free_dma_mem(ap);
  1486. return -ENOMEM;
  1487. }
  1488. /**
  1489. * mv_port_stop - Port specific cleanup/stop routine.
  1490. * @ap: ATA channel to manipulate
  1491. *
  1492. * Stop DMA, cleanup port memory.
  1493. *
  1494. * LOCKING:
  1495. * This routine uses the host lock to protect the DMA stop.
  1496. */
  1497. static void mv_port_stop(struct ata_port *ap)
  1498. {
  1499. unsigned long flags;
  1500. spin_lock_irqsave(ap->lock, flags);
  1501. mv_stop_edma(ap);
  1502. mv_enable_port_irqs(ap, 0);
  1503. spin_unlock_irqrestore(ap->lock, flags);
  1504. mv_port_free_dma_mem(ap);
  1505. }
  1506. /**
  1507. * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
  1508. * @qc: queued command whose SG list to source from
  1509. *
  1510. * Populate the SG list and mark the last entry.
  1511. *
  1512. * LOCKING:
  1513. * Inherited from caller.
  1514. */
  1515. static void mv_fill_sg(struct ata_queued_cmd *qc)
  1516. {
  1517. struct mv_port_priv *pp = qc->ap->private_data;
  1518. struct scatterlist *sg;
  1519. struct mv_sg *mv_sg, *last_sg = NULL;
  1520. unsigned int si;
  1521. mv_sg = pp->sg_tbl[qc->tag];
  1522. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1523. dma_addr_t addr = sg_dma_address(sg);
  1524. u32 sg_len = sg_dma_len(sg);
  1525. while (sg_len) {
  1526. u32 offset = addr & 0xffff;
  1527. u32 len = sg_len;
  1528. if (offset + len > 0x10000)
  1529. len = 0x10000 - offset;
  1530. mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
  1531. mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1532. mv_sg->flags_size = cpu_to_le32(len & 0xffff);
  1533. mv_sg->reserved = 0;
  1534. sg_len -= len;
  1535. addr += len;
  1536. last_sg = mv_sg;
  1537. mv_sg++;
  1538. }
  1539. }
  1540. if (likely(last_sg))
  1541. last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
  1542. mb(); /* ensure data structure is visible to the chipset */
  1543. }
  1544. static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
  1545. {
  1546. u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
  1547. (last ? CRQB_CMD_LAST : 0);
  1548. *cmdw = cpu_to_le16(tmp);
  1549. }
  1550. /**
  1551. * mv_sff_irq_clear - Clear hardware interrupt after DMA.
  1552. * @ap: Port associated with this ATA transaction.
  1553. *
  1554. * We need this only for ATAPI bmdma transactions,
  1555. * as otherwise we experience spurious interrupts
  1556. * after libata-sff handles the bmdma interrupts.
  1557. */
  1558. static void mv_sff_irq_clear(struct ata_port *ap)
  1559. {
  1560. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
  1561. }
  1562. /**
  1563. * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
  1564. * @qc: queued command to check for chipset/DMA compatibility.
  1565. *
  1566. * The bmdma engines cannot handle speculative data sizes
  1567. * (bytecount under/over flow). So only allow DMA for
  1568. * data transfer commands with known data sizes.
  1569. *
  1570. * LOCKING:
  1571. * Inherited from caller.
  1572. */
  1573. static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
  1574. {
  1575. struct scsi_cmnd *scmd = qc->scsicmd;
  1576. if (scmd) {
  1577. switch (scmd->cmnd[0]) {
  1578. case READ_6:
  1579. case READ_10:
  1580. case READ_12:
  1581. case WRITE_6:
  1582. case WRITE_10:
  1583. case WRITE_12:
  1584. case GPCMD_READ_CD:
  1585. case GPCMD_SEND_DVD_STRUCTURE:
  1586. case GPCMD_SEND_CUE_SHEET:
  1587. return 0; /* DMA is safe */
  1588. }
  1589. }
  1590. return -EOPNOTSUPP; /* use PIO instead */
  1591. }
  1592. /**
  1593. * mv_bmdma_setup - Set up BMDMA transaction
  1594. * @qc: queued command to prepare DMA for.
  1595. *
  1596. * LOCKING:
  1597. * Inherited from caller.
  1598. */
  1599. static void mv_bmdma_setup(struct ata_queued_cmd *qc)
  1600. {
  1601. struct ata_port *ap = qc->ap;
  1602. void __iomem *port_mmio = mv_ap_base(ap);
  1603. struct mv_port_priv *pp = ap->private_data;
  1604. mv_fill_sg(qc);
  1605. /* clear all DMA cmd bits */
  1606. writel(0, port_mmio + BMDMA_CMD);
  1607. /* load PRD table addr. */
  1608. writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
  1609. port_mmio + BMDMA_PRD_HIGH);
  1610. writelfl(pp->sg_tbl_dma[qc->tag],
  1611. port_mmio + BMDMA_PRD_LOW);
  1612. /* issue r/w command */
  1613. ap->ops->sff_exec_command(ap, &qc->tf);
  1614. }
  1615. /**
  1616. * mv_bmdma_start - Start a BMDMA transaction
  1617. * @qc: queued command to start DMA on.
  1618. *
  1619. * LOCKING:
  1620. * Inherited from caller.
  1621. */
  1622. static void mv_bmdma_start(struct ata_queued_cmd *qc)
  1623. {
  1624. struct ata_port *ap = qc->ap;
  1625. void __iomem *port_mmio = mv_ap_base(ap);
  1626. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  1627. u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
  1628. /* start host DMA transaction */
  1629. writelfl(cmd, port_mmio + BMDMA_CMD);
  1630. }
  1631. /**
  1632. * mv_bmdma_stop - Stop BMDMA transfer
  1633. * @qc: queued command to stop DMA on.
  1634. *
  1635. * Clears the ATA_DMA_START flag in the bmdma control register
  1636. *
  1637. * LOCKING:
  1638. * Inherited from caller.
  1639. */
  1640. static void mv_bmdma_stop(struct ata_queued_cmd *qc)
  1641. {
  1642. struct ata_port *ap = qc->ap;
  1643. void __iomem *port_mmio = mv_ap_base(ap);
  1644. u32 cmd;
  1645. /* clear start/stop bit */
  1646. cmd = readl(port_mmio + BMDMA_CMD);
  1647. cmd &= ~ATA_DMA_START;
  1648. writelfl(cmd, port_mmio + BMDMA_CMD);
  1649. /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
  1650. ata_sff_dma_pause(ap);
  1651. }
  1652. /**
  1653. * mv_bmdma_status - Read BMDMA status
  1654. * @ap: port for which to retrieve DMA status.
  1655. *
  1656. * Read and return equivalent of the sff BMDMA status register.
  1657. *
  1658. * LOCKING:
  1659. * Inherited from caller.
  1660. */
  1661. static u8 mv_bmdma_status(struct ata_port *ap)
  1662. {
  1663. void __iomem *port_mmio = mv_ap_base(ap);
  1664. u32 reg, status;
  1665. /*
  1666. * Other bits are valid only if ATA_DMA_ACTIVE==0,
  1667. * and the ATA_DMA_INTR bit doesn't exist.
  1668. */
  1669. reg = readl(port_mmio + BMDMA_STATUS);
  1670. if (reg & ATA_DMA_ACTIVE)
  1671. status = ATA_DMA_ACTIVE;
  1672. else
  1673. status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
  1674. return status;
  1675. }
  1676. static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
  1677. {
  1678. struct ata_taskfile *tf = &qc->tf;
  1679. /*
  1680. * Workaround for 88SX60x1 FEr SATA#24.
  1681. *
  1682. * Chip may corrupt WRITEs if multi_count >= 4kB.
  1683. * Note that READs are unaffected.
  1684. *
  1685. * It's not clear if this errata really means "4K bytes",
  1686. * or if it always happens for multi_count > 7
  1687. * regardless of device sector_size.
  1688. *
  1689. * So, for safety, any write with multi_count > 7
  1690. * gets converted here into a regular PIO write instead:
  1691. */
  1692. if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
  1693. if (qc->dev->multi_count > 7) {
  1694. switch (tf->command) {
  1695. case ATA_CMD_WRITE_MULTI:
  1696. tf->command = ATA_CMD_PIO_WRITE;
  1697. break;
  1698. case ATA_CMD_WRITE_MULTI_FUA_EXT:
  1699. tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
  1700. /* fall through */
  1701. case ATA_CMD_WRITE_MULTI_EXT:
  1702. tf->command = ATA_CMD_PIO_WRITE_EXT;
  1703. break;
  1704. }
  1705. }
  1706. }
  1707. }
  1708. /**
  1709. * mv_qc_prep - Host specific command preparation.
  1710. * @qc: queued command to prepare
  1711. *
  1712. * This routine simply redirects to the general purpose routine
  1713. * if command is not DMA. Else, it handles prep of the CRQB
  1714. * (command request block), does some sanity checking, and calls
  1715. * the SG load routine.
  1716. *
  1717. * LOCKING:
  1718. * Inherited from caller.
  1719. */
  1720. static void mv_qc_prep(struct ata_queued_cmd *qc)
  1721. {
  1722. struct ata_port *ap = qc->ap;
  1723. struct mv_port_priv *pp = ap->private_data;
  1724. __le16 *cw;
  1725. struct ata_taskfile *tf = &qc->tf;
  1726. u16 flags = 0;
  1727. unsigned in_index;
  1728. switch (tf->protocol) {
  1729. case ATA_PROT_DMA:
  1730. case ATA_PROT_NCQ:
  1731. break; /* continue below */
  1732. case ATA_PROT_PIO:
  1733. mv_rw_multi_errata_sata24(qc);
  1734. return;
  1735. default:
  1736. return;
  1737. }
  1738. /* Fill in command request block
  1739. */
  1740. if (!(tf->flags & ATA_TFLAG_WRITE))
  1741. flags |= CRQB_FLAG_READ;
  1742. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1743. flags |= qc->tag << CRQB_TAG_SHIFT;
  1744. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1745. /* get current queue index from software */
  1746. in_index = pp->req_idx;
  1747. pp->crqb[in_index].sg_addr =
  1748. cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1749. pp->crqb[in_index].sg_addr_hi =
  1750. cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1751. pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
  1752. cw = &pp->crqb[in_index].ata_cmd[0];
  1753. /* Sadly, the CRQB cannot accomodate all registers--there are
  1754. * only 11 bytes...so we must pick and choose required
  1755. * registers based on the command. So, we drop feature and
  1756. * hob_feature for [RW] DMA commands, but they are needed for
  1757. * NCQ. NCQ will drop hob_nsect, which is not needed there
  1758. * (nsect is used only for the tag; feat/hob_feat hold true nsect).
  1759. */
  1760. switch (tf->command) {
  1761. case ATA_CMD_READ:
  1762. case ATA_CMD_READ_EXT:
  1763. case ATA_CMD_WRITE:
  1764. case ATA_CMD_WRITE_EXT:
  1765. case ATA_CMD_WRITE_FUA_EXT:
  1766. mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
  1767. break;
  1768. case ATA_CMD_FPDMA_READ:
  1769. case ATA_CMD_FPDMA_WRITE:
  1770. mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
  1771. mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
  1772. break;
  1773. default:
  1774. /* The only other commands EDMA supports in non-queued and
  1775. * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
  1776. * of which are defined/used by Linux. If we get here, this
  1777. * driver needs work.
  1778. *
  1779. * FIXME: modify libata to give qc_prep a return value and
  1780. * return error here.
  1781. */
  1782. BUG_ON(tf->command);
  1783. break;
  1784. }
  1785. mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
  1786. mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
  1787. mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
  1788. mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
  1789. mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
  1790. mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
  1791. mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
  1792. mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
  1793. mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
  1794. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1795. return;
  1796. mv_fill_sg(qc);
  1797. }
  1798. /**
  1799. * mv_qc_prep_iie - Host specific command preparation.
  1800. * @qc: queued command to prepare
  1801. *
  1802. * This routine simply redirects to the general purpose routine
  1803. * if command is not DMA. Else, it handles prep of the CRQB
  1804. * (command request block), does some sanity checking, and calls
  1805. * the SG load routine.
  1806. *
  1807. * LOCKING:
  1808. * Inherited from caller.
  1809. */
  1810. static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
  1811. {
  1812. struct ata_port *ap = qc->ap;
  1813. struct mv_port_priv *pp = ap->private_data;
  1814. struct mv_crqb_iie *crqb;
  1815. struct ata_taskfile *tf = &qc->tf;
  1816. unsigned in_index;
  1817. u32 flags = 0;
  1818. if ((tf->protocol != ATA_PROT_DMA) &&
  1819. (tf->protocol != ATA_PROT_NCQ))
  1820. return;
  1821. /* Fill in Gen IIE command request block */
  1822. if (!(tf->flags & ATA_TFLAG_WRITE))
  1823. flags |= CRQB_FLAG_READ;
  1824. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1825. flags |= qc->tag << CRQB_TAG_SHIFT;
  1826. flags |= qc->tag << CRQB_HOSTQ_SHIFT;
  1827. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1828. /* get current queue index from software */
  1829. in_index = pp->req_idx;
  1830. crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
  1831. crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1832. crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1833. crqb->flags = cpu_to_le32(flags);
  1834. crqb->ata_cmd[0] = cpu_to_le32(
  1835. (tf->command << 16) |
  1836. (tf->feature << 24)
  1837. );
  1838. crqb->ata_cmd[1] = cpu_to_le32(
  1839. (tf->lbal << 0) |
  1840. (tf->lbam << 8) |
  1841. (tf->lbah << 16) |
  1842. (tf->device << 24)
  1843. );
  1844. crqb->ata_cmd[2] = cpu_to_le32(
  1845. (tf->hob_lbal << 0) |
  1846. (tf->hob_lbam << 8) |
  1847. (tf->hob_lbah << 16) |
  1848. (tf->hob_feature << 24)
  1849. );
  1850. crqb->ata_cmd[3] = cpu_to_le32(
  1851. (tf->nsect << 0) |
  1852. (tf->hob_nsect << 8)
  1853. );
  1854. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1855. return;
  1856. mv_fill_sg(qc);
  1857. }
  1858. /**
  1859. * mv_sff_check_status - fetch device status, if valid
  1860. * @ap: ATA port to fetch status from
  1861. *
  1862. * When using command issue via mv_qc_issue_fis(),
  1863. * the initial ATA_BUSY state does not show up in the
  1864. * ATA status (shadow) register. This can confuse libata!
  1865. *
  1866. * So we have a hook here to fake ATA_BUSY for that situation,
  1867. * until the first time a BUSY, DRQ, or ERR bit is seen.
  1868. *
  1869. * The rest of the time, it simply returns the ATA status register.
  1870. */
  1871. static u8 mv_sff_check_status(struct ata_port *ap)
  1872. {
  1873. u8 stat = ioread8(ap->ioaddr.status_addr);
  1874. struct mv_port_priv *pp = ap->private_data;
  1875. if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
  1876. if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
  1877. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
  1878. else
  1879. stat = ATA_BUSY;
  1880. }
  1881. return stat;
  1882. }
  1883. /**
  1884. * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
  1885. * @fis: fis to be sent
  1886. * @nwords: number of 32-bit words in the fis
  1887. */
  1888. static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
  1889. {
  1890. void __iomem *port_mmio = mv_ap_base(ap);
  1891. u32 ifctl, old_ifctl, ifstat;
  1892. int i, timeout = 200, final_word = nwords - 1;
  1893. /* Initiate FIS transmission mode */
  1894. old_ifctl = readl(port_mmio + SATA_IFCTL);
  1895. ifctl = 0x100 | (old_ifctl & 0xf);
  1896. writelfl(ifctl, port_mmio + SATA_IFCTL);
  1897. /* Send all words of the FIS except for the final word */
  1898. for (i = 0; i < final_word; ++i)
  1899. writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
  1900. /* Flag end-of-transmission, and then send the final word */
  1901. writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
  1902. writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
  1903. /*
  1904. * Wait for FIS transmission to complete.
  1905. * This typically takes just a single iteration.
  1906. */
  1907. do {
  1908. ifstat = readl(port_mmio + SATA_IFSTAT);
  1909. } while (!(ifstat & 0x1000) && --timeout);
  1910. /* Restore original port configuration */
  1911. writelfl(old_ifctl, port_mmio + SATA_IFCTL);
  1912. /* See if it worked */
  1913. if ((ifstat & 0x3000) != 0x1000) {
  1914. ata_port_printk(ap, KERN_WARNING,
  1915. "%s transmission error, ifstat=%08x\n",
  1916. __func__, ifstat);
  1917. return AC_ERR_OTHER;
  1918. }
  1919. return 0;
  1920. }
  1921. /**
  1922. * mv_qc_issue_fis - Issue a command directly as a FIS
  1923. * @qc: queued command to start
  1924. *
  1925. * Note that the ATA shadow registers are not updated
  1926. * after command issue, so the device will appear "READY"
  1927. * if polled, even while it is BUSY processing the command.
  1928. *
  1929. * So we use a status hook to fake ATA_BUSY until the drive changes state.
  1930. *
  1931. * Note: we don't get updated shadow regs on *completion*
  1932. * of non-data commands. So avoid sending them via this function,
  1933. * as they will appear to have completed immediately.
  1934. *
  1935. * GEN_IIE has special registers that we could get the result tf from,
  1936. * but earlier chipsets do not. For now, we ignore those registers.
  1937. */
  1938. static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
  1939. {
  1940. struct ata_port *ap = qc->ap;
  1941. struct mv_port_priv *pp = ap->private_data;
  1942. struct ata_link *link = qc->dev->link;
  1943. u32 fis[5];
  1944. int err = 0;
  1945. ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
  1946. err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
  1947. if (err)
  1948. return err;
  1949. switch (qc->tf.protocol) {
  1950. case ATAPI_PROT_PIO:
  1951. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  1952. /* fall through */
  1953. case ATAPI_PROT_NODATA:
  1954. ap->hsm_task_state = HSM_ST_FIRST;
  1955. break;
  1956. case ATA_PROT_PIO:
  1957. pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
  1958. if (qc->tf.flags & ATA_TFLAG_WRITE)
  1959. ap->hsm_task_state = HSM_ST_FIRST;
  1960. else
  1961. ap->hsm_task_state = HSM_ST;
  1962. break;
  1963. default:
  1964. ap->hsm_task_state = HSM_ST_LAST;
  1965. break;
  1966. }
  1967. if (qc->tf.flags & ATA_TFLAG_POLLING)
  1968. ata_pio_queue_task(ap, qc, 0);
  1969. return 0;
  1970. }
  1971. /**
  1972. * mv_qc_issue - Initiate a command to the host
  1973. * @qc: queued command to start
  1974. *
  1975. * This routine simply redirects to the general purpose routine
  1976. * if command is not DMA. Else, it sanity checks our local
  1977. * caches of the request producer/consumer indices then enables
  1978. * DMA and bumps the request producer index.
  1979. *
  1980. * LOCKING:
  1981. * Inherited from caller.
  1982. */
  1983. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
  1984. {
  1985. static int limit_warnings = 10;
  1986. struct ata_port *ap = qc->ap;
  1987. void __iomem *port_mmio = mv_ap_base(ap);
  1988. struct mv_port_priv *pp = ap->private_data;
  1989. u32 in_index;
  1990. unsigned int port_irqs;
  1991. pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
  1992. switch (qc->tf.protocol) {
  1993. case ATA_PROT_DMA:
  1994. case ATA_PROT_NCQ:
  1995. mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
  1996. pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  1997. in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
  1998. /* Write the request in pointer to kick the EDMA to life */
  1999. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
  2000. port_mmio + EDMA_REQ_Q_IN_PTR);
  2001. return 0;
  2002. case ATA_PROT_PIO:
  2003. /*
  2004. * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
  2005. *
  2006. * Someday, we might implement special polling workarounds
  2007. * for these, but it all seems rather unnecessary since we
  2008. * normally use only DMA for commands which transfer more
  2009. * than a single block of data.
  2010. *
  2011. * Much of the time, this could just work regardless.
  2012. * So for now, just log the incident, and allow the attempt.
  2013. */
  2014. if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
  2015. --limit_warnings;
  2016. ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
  2017. ": attempting PIO w/multiple DRQ: "
  2018. "this may fail due to h/w errata\n");
  2019. }
  2020. /* drop through */
  2021. case ATA_PROT_NODATA:
  2022. case ATAPI_PROT_PIO:
  2023. case ATAPI_PROT_NODATA:
  2024. if (ap->flags & ATA_FLAG_PIO_POLLING)
  2025. qc->tf.flags |= ATA_TFLAG_POLLING;
  2026. break;
  2027. }
  2028. if (qc->tf.flags & ATA_TFLAG_POLLING)
  2029. port_irqs = ERR_IRQ; /* mask device interrupt when polling */
  2030. else
  2031. port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
  2032. /*
  2033. * We're about to send a non-EDMA capable command to the
  2034. * port. Turn off EDMA so there won't be problems accessing
  2035. * shadow block, etc registers.
  2036. */
  2037. mv_stop_edma(ap);
  2038. mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
  2039. mv_pmp_select(ap, qc->dev->link->pmp);
  2040. if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
  2041. struct mv_host_priv *hpriv = ap->host->private_data;
  2042. /*
  2043. * Workaround for 88SX60x1 FEr SATA#25 (part 2).
  2044. *
  2045. * After any NCQ error, the READ_LOG_EXT command
  2046. * from libata-eh *must* use mv_qc_issue_fis().
  2047. * Otherwise it might fail, due to chip errata.
  2048. *
  2049. * Rather than special-case it, we'll just *always*
  2050. * use this method here for READ_LOG_EXT, making for
  2051. * easier testing.
  2052. */
  2053. if (IS_GEN_II(hpriv))
  2054. return mv_qc_issue_fis(qc);
  2055. }
  2056. return ata_sff_qc_issue(qc);
  2057. }
  2058. static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
  2059. {
  2060. struct mv_port_priv *pp = ap->private_data;
  2061. struct ata_queued_cmd *qc;
  2062. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
  2063. return NULL;
  2064. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2065. if (qc) {
  2066. if (qc->tf.flags & ATA_TFLAG_POLLING)
  2067. qc = NULL;
  2068. else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
  2069. qc = NULL;
  2070. }
  2071. return qc;
  2072. }
  2073. static void mv_pmp_error_handler(struct ata_port *ap)
  2074. {
  2075. unsigned int pmp, pmp_map;
  2076. struct mv_port_priv *pp = ap->private_data;
  2077. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
  2078. /*
  2079. * Perform NCQ error analysis on failed PMPs
  2080. * before we freeze the port entirely.
  2081. *
  2082. * The failed PMPs are marked earlier by mv_pmp_eh_prep().
  2083. */
  2084. pmp_map = pp->delayed_eh_pmp_map;
  2085. pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
  2086. for (pmp = 0; pmp_map != 0; pmp++) {
  2087. unsigned int this_pmp = (1 << pmp);
  2088. if (pmp_map & this_pmp) {
  2089. struct ata_link *link = &ap->pmp_link[pmp];
  2090. pmp_map &= ~this_pmp;
  2091. ata_eh_analyze_ncq_error(link);
  2092. }
  2093. }
  2094. ata_port_freeze(ap);
  2095. }
  2096. sata_pmp_error_handler(ap);
  2097. }
  2098. static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
  2099. {
  2100. void __iomem *port_mmio = mv_ap_base(ap);
  2101. return readl(port_mmio + SATA_TESTCTL) >> 16;
  2102. }
  2103. static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
  2104. {
  2105. struct ata_eh_info *ehi;
  2106. unsigned int pmp;
  2107. /*
  2108. * Initialize EH info for PMPs which saw device errors
  2109. */
  2110. ehi = &ap->link.eh_info;
  2111. for (pmp = 0; pmp_map != 0; pmp++) {
  2112. unsigned int this_pmp = (1 << pmp);
  2113. if (pmp_map & this_pmp) {
  2114. struct ata_link *link = &ap->pmp_link[pmp];
  2115. pmp_map &= ~this_pmp;
  2116. ehi = &link->eh_info;
  2117. ata_ehi_clear_desc(ehi);
  2118. ata_ehi_push_desc(ehi, "dev err");
  2119. ehi->err_mask |= AC_ERR_DEV;
  2120. ehi->action |= ATA_EH_RESET;
  2121. ata_link_abort(link);
  2122. }
  2123. }
  2124. }
  2125. static int mv_req_q_empty(struct ata_port *ap)
  2126. {
  2127. void __iomem *port_mmio = mv_ap_base(ap);
  2128. u32 in_ptr, out_ptr;
  2129. in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
  2130. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2131. out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
  2132. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2133. return (in_ptr == out_ptr); /* 1 == queue_is_empty */
  2134. }
  2135. static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
  2136. {
  2137. struct mv_port_priv *pp = ap->private_data;
  2138. int failed_links;
  2139. unsigned int old_map, new_map;
  2140. /*
  2141. * Device error during FBS+NCQ operation:
  2142. *
  2143. * Set a port flag to prevent further I/O being enqueued.
  2144. * Leave the EDMA running to drain outstanding commands from this port.
  2145. * Perform the post-mortem/EH only when all responses are complete.
  2146. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
  2147. */
  2148. if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
  2149. pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
  2150. pp->delayed_eh_pmp_map = 0;
  2151. }
  2152. old_map = pp->delayed_eh_pmp_map;
  2153. new_map = old_map | mv_get_err_pmp_map(ap);
  2154. if (old_map != new_map) {
  2155. pp->delayed_eh_pmp_map = new_map;
  2156. mv_pmp_eh_prep(ap, new_map & ~old_map);
  2157. }
  2158. failed_links = hweight16(new_map);
  2159. ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
  2160. "failed_links=%d nr_active_links=%d\n",
  2161. __func__, pp->delayed_eh_pmp_map,
  2162. ap->qc_active, failed_links,
  2163. ap->nr_active_links);
  2164. if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
  2165. mv_process_crpb_entries(ap, pp);
  2166. mv_stop_edma(ap);
  2167. mv_eh_freeze(ap);
  2168. ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
  2169. return 1; /* handled */
  2170. }
  2171. ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
  2172. return 1; /* handled */
  2173. }
  2174. static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
  2175. {
  2176. /*
  2177. * Possible future enhancement:
  2178. *
  2179. * FBS+non-NCQ operation is not yet implemented.
  2180. * See related notes in mv_edma_cfg().
  2181. *
  2182. * Device error during FBS+non-NCQ operation:
  2183. *
  2184. * We need to snapshot the shadow registers for each failed command.
  2185. * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
  2186. */
  2187. return 0; /* not handled */
  2188. }
  2189. static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
  2190. {
  2191. struct mv_port_priv *pp = ap->private_data;
  2192. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  2193. return 0; /* EDMA was not active: not handled */
  2194. if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
  2195. return 0; /* FBS was not active: not handled */
  2196. if (!(edma_err_cause & EDMA_ERR_DEV))
  2197. return 0; /* non DEV error: not handled */
  2198. edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
  2199. if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
  2200. return 0; /* other problems: not handled */
  2201. if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
  2202. /*
  2203. * EDMA should NOT have self-disabled for this case.
  2204. * If it did, then something is wrong elsewhere,
  2205. * and we cannot handle it here.
  2206. */
  2207. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2208. ata_port_printk(ap, KERN_WARNING,
  2209. "%s: err_cause=0x%x pp_flags=0x%x\n",
  2210. __func__, edma_err_cause, pp->pp_flags);
  2211. return 0; /* not handled */
  2212. }
  2213. return mv_handle_fbs_ncq_dev_err(ap);
  2214. } else {
  2215. /*
  2216. * EDMA should have self-disabled for this case.
  2217. * If it did not, then something is wrong elsewhere,
  2218. * and we cannot handle it here.
  2219. */
  2220. if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
  2221. ata_port_printk(ap, KERN_WARNING,
  2222. "%s: err_cause=0x%x pp_flags=0x%x\n",
  2223. __func__, edma_err_cause, pp->pp_flags);
  2224. return 0; /* not handled */
  2225. }
  2226. return mv_handle_fbs_non_ncq_dev_err(ap);
  2227. }
  2228. return 0; /* not handled */
  2229. }
  2230. static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
  2231. {
  2232. struct ata_eh_info *ehi = &ap->link.eh_info;
  2233. char *when = "idle";
  2234. ata_ehi_clear_desc(ehi);
  2235. if (ap->flags & ATA_FLAG_DISABLED) {
  2236. when = "disabled";
  2237. } else if (edma_was_enabled) {
  2238. when = "EDMA enabled";
  2239. } else {
  2240. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2241. if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
  2242. when = "polling";
  2243. }
  2244. ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
  2245. ehi->err_mask |= AC_ERR_OTHER;
  2246. ehi->action |= ATA_EH_RESET;
  2247. ata_port_freeze(ap);
  2248. }
  2249. /**
  2250. * mv_err_intr - Handle error interrupts on the port
  2251. * @ap: ATA channel to manipulate
  2252. *
  2253. * Most cases require a full reset of the chip's state machine,
  2254. * which also performs a COMRESET.
  2255. * Also, if the port disabled DMA, update our cached copy to match.
  2256. *
  2257. * LOCKING:
  2258. * Inherited from caller.
  2259. */
  2260. static void mv_err_intr(struct ata_port *ap)
  2261. {
  2262. void __iomem *port_mmio = mv_ap_base(ap);
  2263. u32 edma_err_cause, eh_freeze_mask, serr = 0;
  2264. u32 fis_cause = 0;
  2265. struct mv_port_priv *pp = ap->private_data;
  2266. struct mv_host_priv *hpriv = ap->host->private_data;
  2267. unsigned int action = 0, err_mask = 0;
  2268. struct ata_eh_info *ehi = &ap->link.eh_info;
  2269. struct ata_queued_cmd *qc;
  2270. int abort = 0;
  2271. /*
  2272. * Read and clear the SError and err_cause bits.
  2273. * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
  2274. * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
  2275. */
  2276. sata_scr_read(&ap->link, SCR_ERROR, &serr);
  2277. sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
  2278. edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
  2279. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2280. fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
  2281. writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
  2282. }
  2283. writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
  2284. if (edma_err_cause & EDMA_ERR_DEV) {
  2285. /*
  2286. * Device errors during FIS-based switching operation
  2287. * require special handling.
  2288. */
  2289. if (mv_handle_dev_err(ap, edma_err_cause))
  2290. return;
  2291. }
  2292. qc = mv_get_active_qc(ap);
  2293. ata_ehi_clear_desc(ehi);
  2294. ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
  2295. edma_err_cause, pp->pp_flags);
  2296. if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
  2297. ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
  2298. if (fis_cause & FIS_IRQ_CAUSE_AN) {
  2299. u32 ec = edma_err_cause &
  2300. ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
  2301. sata_async_notification(ap);
  2302. if (!ec)
  2303. return; /* Just an AN; no need for the nukes */
  2304. ata_ehi_push_desc(ehi, "SDB notify");
  2305. }
  2306. }
  2307. /*
  2308. * All generations share these EDMA error cause bits:
  2309. */
  2310. if (edma_err_cause & EDMA_ERR_DEV) {
  2311. err_mask |= AC_ERR_DEV;
  2312. action |= ATA_EH_RESET;
  2313. ata_ehi_push_desc(ehi, "dev error");
  2314. }
  2315. if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
  2316. EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
  2317. EDMA_ERR_INTRL_PAR)) {
  2318. err_mask |= AC_ERR_ATA_BUS;
  2319. action |= ATA_EH_RESET;
  2320. ata_ehi_push_desc(ehi, "parity error");
  2321. }
  2322. if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
  2323. ata_ehi_hotplugged(ehi);
  2324. ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
  2325. "dev disconnect" : "dev connect");
  2326. action |= ATA_EH_RESET;
  2327. }
  2328. /*
  2329. * Gen-I has a different SELF_DIS bit,
  2330. * different FREEZE bits, and no SERR bit:
  2331. */
  2332. if (IS_GEN_I(hpriv)) {
  2333. eh_freeze_mask = EDMA_EH_FREEZE_5;
  2334. if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
  2335. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2336. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2337. }
  2338. } else {
  2339. eh_freeze_mask = EDMA_EH_FREEZE;
  2340. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  2341. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2342. ata_ehi_push_desc(ehi, "EDMA self-disable");
  2343. }
  2344. if (edma_err_cause & EDMA_ERR_SERR) {
  2345. ata_ehi_push_desc(ehi, "SError=%08x", serr);
  2346. err_mask |= AC_ERR_ATA_BUS;
  2347. action |= ATA_EH_RESET;
  2348. }
  2349. }
  2350. if (!err_mask) {
  2351. err_mask = AC_ERR_OTHER;
  2352. action |= ATA_EH_RESET;
  2353. }
  2354. ehi->serror |= serr;
  2355. ehi->action |= action;
  2356. if (qc)
  2357. qc->err_mask |= err_mask;
  2358. else
  2359. ehi->err_mask |= err_mask;
  2360. if (err_mask == AC_ERR_DEV) {
  2361. /*
  2362. * Cannot do ata_port_freeze() here,
  2363. * because it would kill PIO access,
  2364. * which is needed for further diagnosis.
  2365. */
  2366. mv_eh_freeze(ap);
  2367. abort = 1;
  2368. } else if (edma_err_cause & eh_freeze_mask) {
  2369. /*
  2370. * Note to self: ata_port_freeze() calls ata_port_abort()
  2371. */
  2372. ata_port_freeze(ap);
  2373. } else {
  2374. abort = 1;
  2375. }
  2376. if (abort) {
  2377. if (qc)
  2378. ata_link_abort(qc->dev->link);
  2379. else
  2380. ata_port_abort(ap);
  2381. }
  2382. }
  2383. static void mv_process_crpb_response(struct ata_port *ap,
  2384. struct mv_crpb *response, unsigned int tag, int ncq_enabled)
  2385. {
  2386. struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
  2387. if (qc) {
  2388. u8 ata_status;
  2389. u16 edma_status = le16_to_cpu(response->flags);
  2390. /*
  2391. * edma_status from a response queue entry:
  2392. * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
  2393. * MSB is saved ATA status from command completion.
  2394. */
  2395. if (!ncq_enabled) {
  2396. u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
  2397. if (err_cause) {
  2398. /*
  2399. * Error will be seen/handled by mv_err_intr().
  2400. * So do nothing at all here.
  2401. */
  2402. return;
  2403. }
  2404. }
  2405. ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
  2406. if (!ac_err_mask(ata_status))
  2407. ata_qc_complete(qc);
  2408. /* else: leave it for mv_err_intr() */
  2409. } else {
  2410. ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
  2411. __func__, tag);
  2412. }
  2413. }
  2414. static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
  2415. {
  2416. void __iomem *port_mmio = mv_ap_base(ap);
  2417. struct mv_host_priv *hpriv = ap->host->private_data;
  2418. u32 in_index;
  2419. bool work_done = false;
  2420. int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
  2421. /* Get the hardware queue position index */
  2422. in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
  2423. >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  2424. /* Process new responses from since the last time we looked */
  2425. while (in_index != pp->resp_idx) {
  2426. unsigned int tag;
  2427. struct mv_crpb *response = &pp->crpb[pp->resp_idx];
  2428. pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
  2429. if (IS_GEN_I(hpriv)) {
  2430. /* 50xx: no NCQ, only one command active at a time */
  2431. tag = ap->link.active_tag;
  2432. } else {
  2433. /* Gen II/IIE: get command tag from CRPB entry */
  2434. tag = le16_to_cpu(response->id) & 0x1f;
  2435. }
  2436. mv_process_crpb_response(ap, response, tag, ncq_enabled);
  2437. work_done = true;
  2438. }
  2439. /* Update the software queue position index in hardware */
  2440. if (work_done)
  2441. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
  2442. (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
  2443. port_mmio + EDMA_RSP_Q_OUT_PTR);
  2444. }
  2445. static void mv_port_intr(struct ata_port *ap, u32 port_cause)
  2446. {
  2447. struct mv_port_priv *pp;
  2448. int edma_was_enabled;
  2449. if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
  2450. mv_unexpected_intr(ap, 0);
  2451. return;
  2452. }
  2453. /*
  2454. * Grab a snapshot of the EDMA_EN flag setting,
  2455. * so that we have a consistent view for this port,
  2456. * even if something we call of our routines changes it.
  2457. */
  2458. pp = ap->private_data;
  2459. edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
  2460. /*
  2461. * Process completed CRPB response(s) before other events.
  2462. */
  2463. if (edma_was_enabled && (port_cause & DONE_IRQ)) {
  2464. mv_process_crpb_entries(ap, pp);
  2465. if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
  2466. mv_handle_fbs_ncq_dev_err(ap);
  2467. }
  2468. /*
  2469. * Handle chip-reported errors, or continue on to handle PIO.
  2470. */
  2471. if (unlikely(port_cause & ERR_IRQ)) {
  2472. mv_err_intr(ap);
  2473. } else if (!edma_was_enabled) {
  2474. struct ata_queued_cmd *qc = mv_get_active_qc(ap);
  2475. if (qc)
  2476. ata_sff_host_intr(ap, qc);
  2477. else
  2478. mv_unexpected_intr(ap, edma_was_enabled);
  2479. }
  2480. }
  2481. /**
  2482. * mv_host_intr - Handle all interrupts on the given host controller
  2483. * @host: host specific structure
  2484. * @main_irq_cause: Main interrupt cause register for the chip.
  2485. *
  2486. * LOCKING:
  2487. * Inherited from caller.
  2488. */
  2489. static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
  2490. {
  2491. struct mv_host_priv *hpriv = host->private_data;
  2492. void __iomem *mmio = hpriv->base, *hc_mmio;
  2493. unsigned int handled = 0, port;
  2494. /* If asserted, clear the "all ports" IRQ coalescing bit */
  2495. if (main_irq_cause & ALL_PORTS_COAL_DONE)
  2496. writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
  2497. for (port = 0; port < hpriv->n_ports; port++) {
  2498. struct ata_port *ap = host->ports[port];
  2499. unsigned int p, shift, hardport, port_cause;
  2500. MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
  2501. /*
  2502. * Each hc within the host has its own hc_irq_cause register,
  2503. * where the interrupting ports bits get ack'd.
  2504. */
  2505. if (hardport == 0) { /* first port on this hc ? */
  2506. u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
  2507. u32 port_mask, ack_irqs;
  2508. /*
  2509. * Skip this entire hc if nothing pending for any ports
  2510. */
  2511. if (!hc_cause) {
  2512. port += MV_PORTS_PER_HC - 1;
  2513. continue;
  2514. }
  2515. /*
  2516. * We don't need/want to read the hc_irq_cause register,
  2517. * because doing so hurts performance, and
  2518. * main_irq_cause already gives us everything we need.
  2519. *
  2520. * But we do have to *write* to the hc_irq_cause to ack
  2521. * the ports that we are handling this time through.
  2522. *
  2523. * This requires that we create a bitmap for those
  2524. * ports which interrupted us, and use that bitmap
  2525. * to ack (only) those ports via hc_irq_cause.
  2526. */
  2527. ack_irqs = 0;
  2528. if (hc_cause & PORTS_0_3_COAL_DONE)
  2529. ack_irqs = HC_COAL_IRQ;
  2530. for (p = 0; p < MV_PORTS_PER_HC; ++p) {
  2531. if ((port + p) >= hpriv->n_ports)
  2532. break;
  2533. port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
  2534. if (hc_cause & port_mask)
  2535. ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
  2536. }
  2537. hc_mmio = mv_hc_base_from_port(mmio, port);
  2538. writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
  2539. handled = 1;
  2540. }
  2541. /*
  2542. * Handle interrupts signalled for this port:
  2543. */
  2544. port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
  2545. if (port_cause)
  2546. mv_port_intr(ap, port_cause);
  2547. }
  2548. return handled;
  2549. }
  2550. static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
  2551. {
  2552. struct mv_host_priv *hpriv = host->private_data;
  2553. struct ata_port *ap;
  2554. struct ata_queued_cmd *qc;
  2555. struct ata_eh_info *ehi;
  2556. unsigned int i, err_mask, printed = 0;
  2557. u32 err_cause;
  2558. err_cause = readl(mmio + hpriv->irq_cause_offset);
  2559. dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
  2560. err_cause);
  2561. DPRINTK("All regs @ PCI error\n");
  2562. mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
  2563. writelfl(0, mmio + hpriv->irq_cause_offset);
  2564. for (i = 0; i < host->n_ports; i++) {
  2565. ap = host->ports[i];
  2566. if (!ata_link_offline(&ap->link)) {
  2567. ehi = &ap->link.eh_info;
  2568. ata_ehi_clear_desc(ehi);
  2569. if (!printed++)
  2570. ata_ehi_push_desc(ehi,
  2571. "PCI err cause 0x%08x", err_cause);
  2572. err_mask = AC_ERR_HOST_BUS;
  2573. ehi->action = ATA_EH_RESET;
  2574. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  2575. if (qc)
  2576. qc->err_mask |= err_mask;
  2577. else
  2578. ehi->err_mask |= err_mask;
  2579. ata_port_freeze(ap);
  2580. }
  2581. }
  2582. return 1; /* handled */
  2583. }
  2584. /**
  2585. * mv_interrupt - Main interrupt event handler
  2586. * @irq: unused
  2587. * @dev_instance: private data; in this case the host structure
  2588. *
  2589. * Read the read only register to determine if any host
  2590. * controllers have pending interrupts. If so, call lower level
  2591. * routine to handle. Also check for PCI errors which are only
  2592. * reported here.
  2593. *
  2594. * LOCKING:
  2595. * This routine holds the host lock while processing pending
  2596. * interrupts.
  2597. */
  2598. static irqreturn_t mv_interrupt(int irq, void *dev_instance)
  2599. {
  2600. struct ata_host *host = dev_instance;
  2601. struct mv_host_priv *hpriv = host->private_data;
  2602. unsigned int handled = 0;
  2603. int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
  2604. u32 main_irq_cause, pending_irqs;
  2605. spin_lock(&host->lock);
  2606. /* for MSI: block new interrupts while in here */
  2607. if (using_msi)
  2608. mv_write_main_irq_mask(0, hpriv);
  2609. main_irq_cause = readl(hpriv->main_irq_cause_addr);
  2610. pending_irqs = main_irq_cause & hpriv->main_irq_mask;
  2611. /*
  2612. * Deal with cases where we either have nothing pending, or have read
  2613. * a bogus register value which can indicate HW removal or PCI fault.
  2614. */
  2615. if (pending_irqs && main_irq_cause != 0xffffffffU) {
  2616. if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
  2617. handled = mv_pci_error(host, hpriv->base);
  2618. else
  2619. handled = mv_host_intr(host, pending_irqs);
  2620. }
  2621. /* for MSI: unmask; interrupt cause bits will retrigger now */
  2622. if (using_msi)
  2623. mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
  2624. spin_unlock(&host->lock);
  2625. return IRQ_RETVAL(handled);
  2626. }
  2627. static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
  2628. {
  2629. unsigned int ofs;
  2630. switch (sc_reg_in) {
  2631. case SCR_STATUS:
  2632. case SCR_ERROR:
  2633. case SCR_CONTROL:
  2634. ofs = sc_reg_in * sizeof(u32);
  2635. break;
  2636. default:
  2637. ofs = 0xffffffffU;
  2638. break;
  2639. }
  2640. return ofs;
  2641. }
  2642. static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
  2643. {
  2644. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2645. void __iomem *mmio = hpriv->base;
  2646. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2647. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2648. if (ofs != 0xffffffffU) {
  2649. *val = readl(addr + ofs);
  2650. return 0;
  2651. } else
  2652. return -EINVAL;
  2653. }
  2654. static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
  2655. {
  2656. struct mv_host_priv *hpriv = link->ap->host->private_data;
  2657. void __iomem *mmio = hpriv->base;
  2658. void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
  2659. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  2660. if (ofs != 0xffffffffU) {
  2661. writelfl(val, addr + ofs);
  2662. return 0;
  2663. } else
  2664. return -EINVAL;
  2665. }
  2666. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
  2667. {
  2668. struct pci_dev *pdev = to_pci_dev(host->dev);
  2669. int early_5080;
  2670. early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
  2671. if (!early_5080) {
  2672. u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2673. tmp |= (1 << 0);
  2674. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2675. }
  2676. mv_reset_pci_bus(host, mmio);
  2677. }
  2678. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2679. {
  2680. writel(0x0fcfffff, mmio + FLASH_CTL);
  2681. }
  2682. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  2683. void __iomem *mmio)
  2684. {
  2685. void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
  2686. u32 tmp;
  2687. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2688. hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
  2689. hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
  2690. }
  2691. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2692. {
  2693. u32 tmp;
  2694. writel(0, mmio + GPIO_PORT_CTL);
  2695. /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
  2696. tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2697. tmp |= ~(1 << 0);
  2698. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  2699. }
  2700. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2701. unsigned int port)
  2702. {
  2703. void __iomem *phy_mmio = mv5_phy_base(mmio, port);
  2704. const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
  2705. u32 tmp;
  2706. int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
  2707. if (fix_apm_sq) {
  2708. tmp = readl(phy_mmio + MV5_LTMODE);
  2709. tmp |= (1 << 19);
  2710. writel(tmp, phy_mmio + MV5_LTMODE);
  2711. tmp = readl(phy_mmio + MV5_PHY_CTL);
  2712. tmp &= ~0x3;
  2713. tmp |= 0x1;
  2714. writel(tmp, phy_mmio + MV5_PHY_CTL);
  2715. }
  2716. tmp = readl(phy_mmio + MV5_PHY_MODE);
  2717. tmp &= ~mask;
  2718. tmp |= hpriv->signal[port].pre;
  2719. tmp |= hpriv->signal[port].amps;
  2720. writel(tmp, phy_mmio + MV5_PHY_MODE);
  2721. }
  2722. #undef ZERO
  2723. #define ZERO(reg) writel(0, port_mmio + (reg))
  2724. static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
  2725. unsigned int port)
  2726. {
  2727. void __iomem *port_mmio = mv_port_base(mmio, port);
  2728. mv_reset_channel(hpriv, mmio, port);
  2729. ZERO(0x028); /* command */
  2730. writel(0x11f, port_mmio + EDMA_CFG);
  2731. ZERO(0x004); /* timer */
  2732. ZERO(0x008); /* irq err cause */
  2733. ZERO(0x00c); /* irq err mask */
  2734. ZERO(0x010); /* rq bah */
  2735. ZERO(0x014); /* rq inp */
  2736. ZERO(0x018); /* rq outp */
  2737. ZERO(0x01c); /* respq bah */
  2738. ZERO(0x024); /* respq outp */
  2739. ZERO(0x020); /* respq inp */
  2740. ZERO(0x02c); /* test control */
  2741. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  2742. }
  2743. #undef ZERO
  2744. #define ZERO(reg) writel(0, hc_mmio + (reg))
  2745. static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2746. unsigned int hc)
  2747. {
  2748. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  2749. u32 tmp;
  2750. ZERO(0x00c);
  2751. ZERO(0x010);
  2752. ZERO(0x014);
  2753. ZERO(0x018);
  2754. tmp = readl(hc_mmio + 0x20);
  2755. tmp &= 0x1c1c1c1c;
  2756. tmp |= 0x03030303;
  2757. writel(tmp, hc_mmio + 0x20);
  2758. }
  2759. #undef ZERO
  2760. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2761. unsigned int n_hc)
  2762. {
  2763. unsigned int hc, port;
  2764. for (hc = 0; hc < n_hc; hc++) {
  2765. for (port = 0; port < MV_PORTS_PER_HC; port++)
  2766. mv5_reset_hc_port(hpriv, mmio,
  2767. (hc * MV_PORTS_PER_HC) + port);
  2768. mv5_reset_one_hc(hpriv, mmio, hc);
  2769. }
  2770. return 0;
  2771. }
  2772. #undef ZERO
  2773. #define ZERO(reg) writel(0, mmio + (reg))
  2774. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
  2775. {
  2776. struct mv_host_priv *hpriv = host->private_data;
  2777. u32 tmp;
  2778. tmp = readl(mmio + MV_PCI_MODE);
  2779. tmp &= 0xff00ffff;
  2780. writel(tmp, mmio + MV_PCI_MODE);
  2781. ZERO(MV_PCI_DISC_TIMER);
  2782. ZERO(MV_PCI_MSI_TRIGGER);
  2783. writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
  2784. ZERO(MV_PCI_SERR_MASK);
  2785. ZERO(hpriv->irq_cause_offset);
  2786. ZERO(hpriv->irq_mask_offset);
  2787. ZERO(MV_PCI_ERR_LOW_ADDRESS);
  2788. ZERO(MV_PCI_ERR_HIGH_ADDRESS);
  2789. ZERO(MV_PCI_ERR_ATTRIBUTE);
  2790. ZERO(MV_PCI_ERR_COMMAND);
  2791. }
  2792. #undef ZERO
  2793. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  2794. {
  2795. u32 tmp;
  2796. mv5_reset_flash(hpriv, mmio);
  2797. tmp = readl(mmio + GPIO_PORT_CTL);
  2798. tmp &= 0x3;
  2799. tmp |= (1 << 5) | (1 << 6);
  2800. writel(tmp, mmio + GPIO_PORT_CTL);
  2801. }
  2802. /**
  2803. * mv6_reset_hc - Perform the 6xxx global soft reset
  2804. * @mmio: base address of the HBA
  2805. *
  2806. * This routine only applies to 6xxx parts.
  2807. *
  2808. * LOCKING:
  2809. * Inherited from caller.
  2810. */
  2811. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  2812. unsigned int n_hc)
  2813. {
  2814. void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
  2815. int i, rc = 0;
  2816. u32 t;
  2817. /* Following procedure defined in PCI "main command and status
  2818. * register" table.
  2819. */
  2820. t = readl(reg);
  2821. writel(t | STOP_PCI_MASTER, reg);
  2822. for (i = 0; i < 1000; i++) {
  2823. udelay(1);
  2824. t = readl(reg);
  2825. if (PCI_MASTER_EMPTY & t)
  2826. break;
  2827. }
  2828. if (!(PCI_MASTER_EMPTY & t)) {
  2829. printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
  2830. rc = 1;
  2831. goto done;
  2832. }
  2833. /* set reset */
  2834. i = 5;
  2835. do {
  2836. writel(t | GLOB_SFT_RST, reg);
  2837. t = readl(reg);
  2838. udelay(1);
  2839. } while (!(GLOB_SFT_RST & t) && (i-- > 0));
  2840. if (!(GLOB_SFT_RST & t)) {
  2841. printk(KERN_ERR DRV_NAME ": can't set global reset\n");
  2842. rc = 1;
  2843. goto done;
  2844. }
  2845. /* clear reset and *reenable the PCI master* (not mentioned in spec) */
  2846. i = 5;
  2847. do {
  2848. writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
  2849. t = readl(reg);
  2850. udelay(1);
  2851. } while ((GLOB_SFT_RST & t) && (i-- > 0));
  2852. if (GLOB_SFT_RST & t) {
  2853. printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
  2854. rc = 1;
  2855. }
  2856. done:
  2857. return rc;
  2858. }
  2859. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  2860. void __iomem *mmio)
  2861. {
  2862. void __iomem *port_mmio;
  2863. u32 tmp;
  2864. tmp = readl(mmio + RESET_CFG);
  2865. if ((tmp & (1 << 0)) == 0) {
  2866. hpriv->signal[idx].amps = 0x7 << 8;
  2867. hpriv->signal[idx].pre = 0x1 << 5;
  2868. return;
  2869. }
  2870. port_mmio = mv_port_base(mmio, idx);
  2871. tmp = readl(port_mmio + PHY_MODE2);
  2872. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2873. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2874. }
  2875. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  2876. {
  2877. writel(0x00000060, mmio + GPIO_PORT_CTL);
  2878. }
  2879. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  2880. unsigned int port)
  2881. {
  2882. void __iomem *port_mmio = mv_port_base(mmio, port);
  2883. u32 hp_flags = hpriv->hp_flags;
  2884. int fix_phy_mode2 =
  2885. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2886. int fix_phy_mode4 =
  2887. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  2888. u32 m2, m3;
  2889. if (fix_phy_mode2) {
  2890. m2 = readl(port_mmio + PHY_MODE2);
  2891. m2 &= ~(1 << 16);
  2892. m2 |= (1 << 31);
  2893. writel(m2, port_mmio + PHY_MODE2);
  2894. udelay(200);
  2895. m2 = readl(port_mmio + PHY_MODE2);
  2896. m2 &= ~((1 << 16) | (1 << 31));
  2897. writel(m2, port_mmio + PHY_MODE2);
  2898. udelay(200);
  2899. }
  2900. /*
  2901. * Gen-II/IIe PHY_MODE3 errata RM#2:
  2902. * Achieves better receiver noise performance than the h/w default:
  2903. */
  2904. m3 = readl(port_mmio + PHY_MODE3);
  2905. m3 = (m3 & 0x1f) | (0x5555601 << 5);
  2906. /* Guideline 88F5182 (GL# SATA-S11) */
  2907. if (IS_SOC(hpriv))
  2908. m3 &= ~0x1c;
  2909. if (fix_phy_mode4) {
  2910. u32 m4 = readl(port_mmio + PHY_MODE4);
  2911. /*
  2912. * Enforce reserved-bit restrictions on GenIIe devices only.
  2913. * For earlier chipsets, force only the internal config field
  2914. * (workaround for errata FEr SATA#10 part 1).
  2915. */
  2916. if (IS_GEN_IIE(hpriv))
  2917. m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
  2918. else
  2919. m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
  2920. writel(m4, port_mmio + PHY_MODE4);
  2921. }
  2922. /*
  2923. * Workaround for 60x1-B2 errata SATA#13:
  2924. * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
  2925. * so we must always rewrite PHY_MODE3 after PHY_MODE4.
  2926. * Or ensure we use writelfl() when writing PHY_MODE4.
  2927. */
  2928. writel(m3, port_mmio + PHY_MODE3);
  2929. /* Revert values of pre-emphasis and signal amps to the saved ones */
  2930. m2 = readl(port_mmio + PHY_MODE2);
  2931. m2 &= ~MV_M2_PREAMP_MASK;
  2932. m2 |= hpriv->signal[port].amps;
  2933. m2 |= hpriv->signal[port].pre;
  2934. m2 &= ~(1 << 16);
  2935. /* according to mvSata 3.6.1, some IIE values are fixed */
  2936. if (IS_GEN_IIE(hpriv)) {
  2937. m2 &= ~0xC30FF01F;
  2938. m2 |= 0x0000900F;
  2939. }
  2940. writel(m2, port_mmio + PHY_MODE2);
  2941. }
  2942. /* TODO: use the generic LED interface to configure the SATA Presence */
  2943. /* & Acitivy LEDs on the board */
  2944. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  2945. void __iomem *mmio)
  2946. {
  2947. return;
  2948. }
  2949. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  2950. void __iomem *mmio)
  2951. {
  2952. void __iomem *port_mmio;
  2953. u32 tmp;
  2954. port_mmio = mv_port_base(mmio, idx);
  2955. tmp = readl(port_mmio + PHY_MODE2);
  2956. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  2957. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  2958. }
  2959. #undef ZERO
  2960. #define ZERO(reg) writel(0, port_mmio + (reg))
  2961. static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
  2962. void __iomem *mmio, unsigned int port)
  2963. {
  2964. void __iomem *port_mmio = mv_port_base(mmio, port);
  2965. mv_reset_channel(hpriv, mmio, port);
  2966. ZERO(0x028); /* command */
  2967. writel(0x101f, port_mmio + EDMA_CFG);
  2968. ZERO(0x004); /* timer */
  2969. ZERO(0x008); /* irq err cause */
  2970. ZERO(0x00c); /* irq err mask */
  2971. ZERO(0x010); /* rq bah */
  2972. ZERO(0x014); /* rq inp */
  2973. ZERO(0x018); /* rq outp */
  2974. ZERO(0x01c); /* respq bah */
  2975. ZERO(0x024); /* respq outp */
  2976. ZERO(0x020); /* respq inp */
  2977. ZERO(0x02c); /* test control */
  2978. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  2979. }
  2980. #undef ZERO
  2981. #define ZERO(reg) writel(0, hc_mmio + (reg))
  2982. static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
  2983. void __iomem *mmio)
  2984. {
  2985. void __iomem *hc_mmio = mv_hc_base(mmio, 0);
  2986. ZERO(0x00c);
  2987. ZERO(0x010);
  2988. ZERO(0x014);
  2989. }
  2990. #undef ZERO
  2991. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  2992. void __iomem *mmio, unsigned int n_hc)
  2993. {
  2994. unsigned int port;
  2995. for (port = 0; port < hpriv->n_ports; port++)
  2996. mv_soc_reset_hc_port(hpriv, mmio, port);
  2997. mv_soc_reset_one_hc(hpriv, mmio);
  2998. return 0;
  2999. }
  3000. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  3001. void __iomem *mmio)
  3002. {
  3003. return;
  3004. }
  3005. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
  3006. {
  3007. return;
  3008. }
  3009. static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
  3010. void __iomem *mmio, unsigned int port)
  3011. {
  3012. void __iomem *port_mmio = mv_port_base(mmio, port);
  3013. u32 reg;
  3014. reg = readl(port_mmio + PHY_MODE3);
  3015. reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
  3016. reg |= (0x1 << 27);
  3017. reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
  3018. reg |= (0x1 << 29);
  3019. writel(reg, port_mmio + PHY_MODE3);
  3020. reg = readl(port_mmio + PHY_MODE4);
  3021. reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
  3022. reg |= (0x1 << 16);
  3023. writel(reg, port_mmio + PHY_MODE4);
  3024. reg = readl(port_mmio + PHY_MODE9_GEN2);
  3025. reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
  3026. reg |= 0x8;
  3027. reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
  3028. writel(reg, port_mmio + PHY_MODE9_GEN2);
  3029. reg = readl(port_mmio + PHY_MODE9_GEN1);
  3030. reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
  3031. reg |= 0x8;
  3032. reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
  3033. writel(reg, port_mmio + PHY_MODE9_GEN1);
  3034. }
  3035. /**
  3036. * soc_is_65 - check if the soc is 65 nano device
  3037. *
  3038. * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
  3039. * register, this register should contain non-zero value and it exists only
  3040. * in the 65 nano devices, when reading it from older devices we get 0.
  3041. */
  3042. static bool soc_is_65n(struct mv_host_priv *hpriv)
  3043. {
  3044. void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
  3045. if (readl(port0_mmio + PHYCFG_OFS))
  3046. return true;
  3047. return false;
  3048. }
  3049. static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
  3050. {
  3051. u32 ifcfg = readl(port_mmio + SATA_IFCFG);
  3052. ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
  3053. if (want_gen2i)
  3054. ifcfg |= (1 << 7); /* enable gen2i speed */
  3055. writelfl(ifcfg, port_mmio + SATA_IFCFG);
  3056. }
  3057. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  3058. unsigned int port_no)
  3059. {
  3060. void __iomem *port_mmio = mv_port_base(mmio, port_no);
  3061. /*
  3062. * The datasheet warns against setting EDMA_RESET when EDMA is active
  3063. * (but doesn't say what the problem might be). So we first try
  3064. * to disable the EDMA engine before doing the EDMA_RESET operation.
  3065. */
  3066. mv_stop_edma_engine(port_mmio);
  3067. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  3068. if (!IS_GEN_I(hpriv)) {
  3069. /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
  3070. mv_setup_ifcfg(port_mmio, 1);
  3071. }
  3072. /*
  3073. * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
  3074. * link, and physical layers. It resets all SATA interface registers
  3075. * (except for SATA_IFCFG), and issues a COMRESET to the dev.
  3076. */
  3077. writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
  3078. udelay(25); /* allow reset propagation */
  3079. writelfl(0, port_mmio + EDMA_CMD);
  3080. hpriv->ops->phy_errata(hpriv, mmio, port_no);
  3081. if (IS_GEN_I(hpriv))
  3082. mdelay(1);
  3083. }
  3084. static void mv_pmp_select(struct ata_port *ap, int pmp)
  3085. {
  3086. if (sata_pmp_supported(ap)) {
  3087. void __iomem *port_mmio = mv_ap_base(ap);
  3088. u32 reg = readl(port_mmio + SATA_IFCTL);
  3089. int old = reg & 0xf;
  3090. if (old != pmp) {
  3091. reg = (reg & ~0xf) | pmp;
  3092. writelfl(reg, port_mmio + SATA_IFCTL);
  3093. }
  3094. }
  3095. }
  3096. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  3097. unsigned long deadline)
  3098. {
  3099. mv_pmp_select(link->ap, sata_srst_pmp(link));
  3100. return sata_std_hardreset(link, class, deadline);
  3101. }
  3102. static int mv_softreset(struct ata_link *link, unsigned int *class,
  3103. unsigned long deadline)
  3104. {
  3105. mv_pmp_select(link->ap, sata_srst_pmp(link));
  3106. return ata_sff_softreset(link, class, deadline);
  3107. }
  3108. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  3109. unsigned long deadline)
  3110. {
  3111. struct ata_port *ap = link->ap;
  3112. struct mv_host_priv *hpriv = ap->host->private_data;
  3113. struct mv_port_priv *pp = ap->private_data;
  3114. void __iomem *mmio = hpriv->base;
  3115. int rc, attempts = 0, extra = 0;
  3116. u32 sstatus;
  3117. bool online;
  3118. mv_reset_channel(hpriv, mmio, ap->port_no);
  3119. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  3120. pp->pp_flags &=
  3121. ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
  3122. /* Workaround for errata FEr SATA#10 (part 2) */
  3123. do {
  3124. const unsigned long *timing =
  3125. sata_ehc_deb_timing(&link->eh_context);
  3126. rc = sata_link_hardreset(link, timing, deadline + extra,
  3127. &online, NULL);
  3128. rc = online ? -EAGAIN : rc;
  3129. if (rc)
  3130. return rc;
  3131. sata_scr_read(link, SCR_STATUS, &sstatus);
  3132. if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
  3133. /* Force 1.5gb/s link speed and try again */
  3134. mv_setup_ifcfg(mv_ap_base(ap), 0);
  3135. if (time_after(jiffies + HZ, deadline))
  3136. extra = HZ; /* only extend it once, max */
  3137. }
  3138. } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
  3139. mv_save_cached_regs(ap);
  3140. mv_edma_cfg(ap, 0, 0);
  3141. return rc;
  3142. }
  3143. static void mv_eh_freeze(struct ata_port *ap)
  3144. {
  3145. mv_stop_edma(ap);
  3146. mv_enable_port_irqs(ap, 0);
  3147. }
  3148. static void mv_eh_thaw(struct ata_port *ap)
  3149. {
  3150. struct mv_host_priv *hpriv = ap->host->private_data;
  3151. unsigned int port = ap->port_no;
  3152. unsigned int hardport = mv_hardport_from_port(port);
  3153. void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
  3154. void __iomem *port_mmio = mv_ap_base(ap);
  3155. u32 hc_irq_cause;
  3156. /* clear EDMA errors on this port */
  3157. writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3158. /* clear pending irq events */
  3159. hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
  3160. writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
  3161. mv_enable_port_irqs(ap, ERR_IRQ);
  3162. }
  3163. /**
  3164. * mv_port_init - Perform some early initialization on a single port.
  3165. * @port: libata data structure storing shadow register addresses
  3166. * @port_mmio: base address of the port
  3167. *
  3168. * Initialize shadow register mmio addresses, clear outstanding
  3169. * interrupts on the port, and unmask interrupts for the future
  3170. * start of the port.
  3171. *
  3172. * LOCKING:
  3173. * Inherited from caller.
  3174. */
  3175. static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
  3176. {
  3177. void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
  3178. /* PIO related setup
  3179. */
  3180. port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
  3181. port->error_addr =
  3182. port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
  3183. port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
  3184. port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
  3185. port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
  3186. port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
  3187. port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
  3188. port->status_addr =
  3189. port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
  3190. /* special case: control/altstatus doesn't have ATA_REG_ address */
  3191. port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
  3192. /* unused: */
  3193. port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
  3194. /* Clear any currently outstanding port interrupt conditions */
  3195. serr = port_mmio + mv_scr_offset(SCR_ERROR);
  3196. writelfl(readl(serr), serr);
  3197. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
  3198. /* unmask all non-transient EDMA error interrupts */
  3199. writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
  3200. VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
  3201. readl(port_mmio + EDMA_CFG),
  3202. readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
  3203. readl(port_mmio + EDMA_ERR_IRQ_MASK));
  3204. }
  3205. static unsigned int mv_in_pcix_mode(struct ata_host *host)
  3206. {
  3207. struct mv_host_priv *hpriv = host->private_data;
  3208. void __iomem *mmio = hpriv->base;
  3209. u32 reg;
  3210. if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
  3211. return 0; /* not PCI-X capable */
  3212. reg = readl(mmio + MV_PCI_MODE);
  3213. if ((reg & MV_PCI_MODE_MASK) == 0)
  3214. return 0; /* conventional PCI mode */
  3215. return 1; /* chip is in PCI-X mode */
  3216. }
  3217. static int mv_pci_cut_through_okay(struct ata_host *host)
  3218. {
  3219. struct mv_host_priv *hpriv = host->private_data;
  3220. void __iomem *mmio = hpriv->base;
  3221. u32 reg;
  3222. if (!mv_in_pcix_mode(host)) {
  3223. reg = readl(mmio + MV_PCI_COMMAND);
  3224. if (reg & MV_PCI_COMMAND_MRDTRIG)
  3225. return 0; /* not okay */
  3226. }
  3227. return 1; /* okay */
  3228. }
  3229. static void mv_60x1b2_errata_pci7(struct ata_host *host)
  3230. {
  3231. struct mv_host_priv *hpriv = host->private_data;
  3232. void __iomem *mmio = hpriv->base;
  3233. /* workaround for 60x1-B2 errata PCI#7 */
  3234. if (mv_in_pcix_mode(host)) {
  3235. u32 reg = readl(mmio + MV_PCI_COMMAND);
  3236. writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
  3237. }
  3238. }
  3239. static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
  3240. {
  3241. struct pci_dev *pdev = to_pci_dev(host->dev);
  3242. struct mv_host_priv *hpriv = host->private_data;
  3243. u32 hp_flags = hpriv->hp_flags;
  3244. switch (board_idx) {
  3245. case chip_5080:
  3246. hpriv->ops = &mv5xxx_ops;
  3247. hp_flags |= MV_HP_GEN_I;
  3248. switch (pdev->revision) {
  3249. case 0x1:
  3250. hp_flags |= MV_HP_ERRATA_50XXB0;
  3251. break;
  3252. case 0x3:
  3253. hp_flags |= MV_HP_ERRATA_50XXB2;
  3254. break;
  3255. default:
  3256. dev_printk(KERN_WARNING, &pdev->dev,
  3257. "Applying 50XXB2 workarounds to unknown rev\n");
  3258. hp_flags |= MV_HP_ERRATA_50XXB2;
  3259. break;
  3260. }
  3261. break;
  3262. case chip_504x:
  3263. case chip_508x:
  3264. hpriv->ops = &mv5xxx_ops;
  3265. hp_flags |= MV_HP_GEN_I;
  3266. switch (pdev->revision) {
  3267. case 0x0:
  3268. hp_flags |= MV_HP_ERRATA_50XXB0;
  3269. break;
  3270. case 0x3:
  3271. hp_flags |= MV_HP_ERRATA_50XXB2;
  3272. break;
  3273. default:
  3274. dev_printk(KERN_WARNING, &pdev->dev,
  3275. "Applying B2 workarounds to unknown rev\n");
  3276. hp_flags |= MV_HP_ERRATA_50XXB2;
  3277. break;
  3278. }
  3279. break;
  3280. case chip_604x:
  3281. case chip_608x:
  3282. hpriv->ops = &mv6xxx_ops;
  3283. hp_flags |= MV_HP_GEN_II;
  3284. switch (pdev->revision) {
  3285. case 0x7:
  3286. mv_60x1b2_errata_pci7(host);
  3287. hp_flags |= MV_HP_ERRATA_60X1B2;
  3288. break;
  3289. case 0x9:
  3290. hp_flags |= MV_HP_ERRATA_60X1C0;
  3291. break;
  3292. default:
  3293. dev_printk(KERN_WARNING, &pdev->dev,
  3294. "Applying B2 workarounds to unknown rev\n");
  3295. hp_flags |= MV_HP_ERRATA_60X1B2;
  3296. break;
  3297. }
  3298. break;
  3299. case chip_7042:
  3300. hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
  3301. if (pdev->vendor == PCI_VENDOR_ID_TTI &&
  3302. (pdev->device == 0x2300 || pdev->device == 0x2310))
  3303. {
  3304. /*
  3305. * Highpoint RocketRAID PCIe 23xx series cards:
  3306. *
  3307. * Unconfigured drives are treated as "Legacy"
  3308. * by the BIOS, and it overwrites sector 8 with
  3309. * a "Lgcy" metadata block prior to Linux boot.
  3310. *
  3311. * Configured drives (RAID or JBOD) leave sector 8
  3312. * alone, but instead overwrite a high numbered
  3313. * sector for the RAID metadata. This sector can
  3314. * be determined exactly, by truncating the physical
  3315. * drive capacity to a nice even GB value.
  3316. *
  3317. * RAID metadata is at: (dev->n_sectors & ~0xfffff)
  3318. *
  3319. * Warn the user, lest they think we're just buggy.
  3320. */
  3321. printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
  3322. " BIOS CORRUPTS DATA on all attached drives,"
  3323. " regardless of if/how they are configured."
  3324. " BEWARE!\n");
  3325. printk(KERN_WARNING DRV_NAME ": For data safety, do not"
  3326. " use sectors 8-9 on \"Legacy\" drives,"
  3327. " and avoid the final two gigabytes on"
  3328. " all RocketRAID BIOS initialized drives.\n");
  3329. }
  3330. /* drop through */
  3331. case chip_6042:
  3332. hpriv->ops = &mv6xxx_ops;
  3333. hp_flags |= MV_HP_GEN_IIE;
  3334. if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
  3335. hp_flags |= MV_HP_CUT_THROUGH;
  3336. switch (pdev->revision) {
  3337. case 0x2: /* Rev.B0: the first/only public release */
  3338. hp_flags |= MV_HP_ERRATA_60X1C0;
  3339. break;
  3340. default:
  3341. dev_printk(KERN_WARNING, &pdev->dev,
  3342. "Applying 60X1C0 workarounds to unknown rev\n");
  3343. hp_flags |= MV_HP_ERRATA_60X1C0;
  3344. break;
  3345. }
  3346. break;
  3347. case chip_soc:
  3348. if (soc_is_65n(hpriv))
  3349. hpriv->ops = &mv_soc_65n_ops;
  3350. else
  3351. hpriv->ops = &mv_soc_ops;
  3352. hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
  3353. MV_HP_ERRATA_60X1C0;
  3354. break;
  3355. default:
  3356. dev_printk(KERN_ERR, host->dev,
  3357. "BUG: invalid board index %u\n", board_idx);
  3358. return 1;
  3359. }
  3360. hpriv->hp_flags = hp_flags;
  3361. if (hp_flags & MV_HP_PCIE) {
  3362. hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
  3363. hpriv->irq_mask_offset = PCIE_IRQ_MASK;
  3364. hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
  3365. } else {
  3366. hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
  3367. hpriv->irq_mask_offset = PCI_IRQ_MASK;
  3368. hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
  3369. }
  3370. return 0;
  3371. }
  3372. /**
  3373. * mv_init_host - Perform some early initialization of the host.
  3374. * @host: ATA host to initialize
  3375. * @board_idx: controller index
  3376. *
  3377. * If possible, do an early global reset of the host. Then do
  3378. * our port init and clear/unmask all/relevant host interrupts.
  3379. *
  3380. * LOCKING:
  3381. * Inherited from caller.
  3382. */
  3383. static int mv_init_host(struct ata_host *host, unsigned int board_idx)
  3384. {
  3385. int rc = 0, n_hc, port, hc;
  3386. struct mv_host_priv *hpriv = host->private_data;
  3387. void __iomem *mmio = hpriv->base;
  3388. rc = mv_chip_id(host, board_idx);
  3389. if (rc)
  3390. goto done;
  3391. if (IS_SOC(hpriv)) {
  3392. hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
  3393. hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
  3394. } else {
  3395. hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
  3396. hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
  3397. }
  3398. /* initialize shadow irq mask with register's value */
  3399. hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
  3400. /* global interrupt mask: 0 == mask everything */
  3401. mv_set_main_irq_mask(host, ~0, 0);
  3402. n_hc = mv_get_hc_count(host->ports[0]->flags);
  3403. for (port = 0; port < host->n_ports; port++)
  3404. if (hpriv->ops->read_preamp)
  3405. hpriv->ops->read_preamp(hpriv, port, mmio);
  3406. rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
  3407. if (rc)
  3408. goto done;
  3409. hpriv->ops->reset_flash(hpriv, mmio);
  3410. hpriv->ops->reset_bus(host, mmio);
  3411. hpriv->ops->enable_leds(hpriv, mmio);
  3412. for (port = 0; port < host->n_ports; port++) {
  3413. struct ata_port *ap = host->ports[port];
  3414. void __iomem *port_mmio = mv_port_base(mmio, port);
  3415. mv_port_init(&ap->ioaddr, port_mmio);
  3416. #ifdef CONFIG_PCI
  3417. if (!IS_SOC(hpriv)) {
  3418. unsigned int offset = port_mmio - mmio;
  3419. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
  3420. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
  3421. }
  3422. #endif
  3423. }
  3424. for (hc = 0; hc < n_hc; hc++) {
  3425. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  3426. VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
  3427. "(before clear)=0x%08x\n", hc,
  3428. readl(hc_mmio + HC_CFG),
  3429. readl(hc_mmio + HC_IRQ_CAUSE));
  3430. /* Clear any currently outstanding hc interrupt conditions */
  3431. writelfl(0, hc_mmio + HC_IRQ_CAUSE);
  3432. }
  3433. if (!IS_SOC(hpriv)) {
  3434. /* Clear any currently outstanding host interrupt conditions */
  3435. writelfl(0, mmio + hpriv->irq_cause_offset);
  3436. /* and unmask interrupt generation for host regs */
  3437. writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
  3438. }
  3439. /*
  3440. * enable only global host interrupts for now.
  3441. * The per-port interrupts get done later as ports are set up.
  3442. */
  3443. mv_set_main_irq_mask(host, 0, PCI_ERR);
  3444. mv_set_irq_coalescing(host, irq_coalescing_io_count,
  3445. irq_coalescing_usecs);
  3446. done:
  3447. return rc;
  3448. }
  3449. static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
  3450. {
  3451. hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
  3452. MV_CRQB_Q_SZ, 0);
  3453. if (!hpriv->crqb_pool)
  3454. return -ENOMEM;
  3455. hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
  3456. MV_CRPB_Q_SZ, 0);
  3457. if (!hpriv->crpb_pool)
  3458. return -ENOMEM;
  3459. hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
  3460. MV_SG_TBL_SZ, 0);
  3461. if (!hpriv->sg_tbl_pool)
  3462. return -ENOMEM;
  3463. return 0;
  3464. }
  3465. static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
  3466. struct mbus_dram_target_info *dram)
  3467. {
  3468. int i;
  3469. for (i = 0; i < 4; i++) {
  3470. writel(0, hpriv->base + WINDOW_CTRL(i));
  3471. writel(0, hpriv->base + WINDOW_BASE(i));
  3472. }
  3473. for (i = 0; i < dram->num_cs; i++) {
  3474. struct mbus_dram_window *cs = dram->cs + i;
  3475. writel(((cs->size - 1) & 0xffff0000) |
  3476. (cs->mbus_attr << 8) |
  3477. (dram->mbus_dram_target_id << 4) | 1,
  3478. hpriv->base + WINDOW_CTRL(i));
  3479. writel(cs->base, hpriv->base + WINDOW_BASE(i));
  3480. }
  3481. }
  3482. /**
  3483. * mv_platform_probe - handle a positive probe of an soc Marvell
  3484. * host
  3485. * @pdev: platform device found
  3486. *
  3487. * LOCKING:
  3488. * Inherited from caller.
  3489. */
  3490. static int mv_platform_probe(struct platform_device *pdev)
  3491. {
  3492. static int printed_version;
  3493. const struct mv_sata_platform_data *mv_platform_data;
  3494. const struct ata_port_info *ppi[] =
  3495. { &mv_port_info[chip_soc], NULL };
  3496. struct ata_host *host;
  3497. struct mv_host_priv *hpriv;
  3498. struct resource *res;
  3499. int n_ports, rc;
  3500. if (!printed_version++)
  3501. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  3502. /*
  3503. * Simple resource validation ..
  3504. */
  3505. if (unlikely(pdev->num_resources != 2)) {
  3506. dev_err(&pdev->dev, "invalid number of resources\n");
  3507. return -EINVAL;
  3508. }
  3509. /*
  3510. * Get the register base first
  3511. */
  3512. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3513. if (res == NULL)
  3514. return -EINVAL;
  3515. /* allocate host */
  3516. mv_platform_data = pdev->dev.platform_data;
  3517. n_ports = mv_platform_data->n_ports;
  3518. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3519. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3520. if (!host || !hpriv)
  3521. return -ENOMEM;
  3522. host->private_data = hpriv;
  3523. hpriv->n_ports = n_ports;
  3524. host->iomap = NULL;
  3525. hpriv->base = devm_ioremap(&pdev->dev, res->start,
  3526. resource_size(res));
  3527. hpriv->base -= SATAHC0_REG_BASE;
  3528. /*
  3529. * (Re-)program MBUS remapping windows if we are asked to.
  3530. */
  3531. if (mv_platform_data->dram != NULL)
  3532. mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
  3533. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3534. if (rc)
  3535. return rc;
  3536. /* initialize adapter */
  3537. rc = mv_init_host(host, chip_soc);
  3538. if (rc)
  3539. return rc;
  3540. dev_printk(KERN_INFO, &pdev->dev,
  3541. "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
  3542. host->n_ports);
  3543. return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
  3544. IRQF_SHARED, &mv6_sht);
  3545. }
  3546. /*
  3547. *
  3548. * mv_platform_remove - unplug a platform interface
  3549. * @pdev: platform device
  3550. *
  3551. * A platform bus SATA device has been unplugged. Perform the needed
  3552. * cleanup. Also called on module unload for any active devices.
  3553. */
  3554. static int __devexit mv_platform_remove(struct platform_device *pdev)
  3555. {
  3556. struct device *dev = &pdev->dev;
  3557. struct ata_host *host = dev_get_drvdata(dev);
  3558. ata_host_detach(host);
  3559. return 0;
  3560. }
  3561. static struct platform_driver mv_platform_driver = {
  3562. .probe = mv_platform_probe,
  3563. .remove = __devexit_p(mv_platform_remove),
  3564. .driver = {
  3565. .name = DRV_NAME,
  3566. .owner = THIS_MODULE,
  3567. },
  3568. };
  3569. #ifdef CONFIG_PCI
  3570. static int mv_pci_init_one(struct pci_dev *pdev,
  3571. const struct pci_device_id *ent);
  3572. static struct pci_driver mv_pci_driver = {
  3573. .name = DRV_NAME,
  3574. .id_table = mv_pci_tbl,
  3575. .probe = mv_pci_init_one,
  3576. .remove = ata_pci_remove_one,
  3577. };
  3578. /* move to PCI layer or libata core? */
  3579. static int pci_go_64(struct pci_dev *pdev)
  3580. {
  3581. int rc;
  3582. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  3583. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  3584. if (rc) {
  3585. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3586. if (rc) {
  3587. dev_printk(KERN_ERR, &pdev->dev,
  3588. "64-bit DMA enable failed\n");
  3589. return rc;
  3590. }
  3591. }
  3592. } else {
  3593. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3594. if (rc) {
  3595. dev_printk(KERN_ERR, &pdev->dev,
  3596. "32-bit DMA enable failed\n");
  3597. return rc;
  3598. }
  3599. rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3600. if (rc) {
  3601. dev_printk(KERN_ERR, &pdev->dev,
  3602. "32-bit consistent DMA enable failed\n");
  3603. return rc;
  3604. }
  3605. }
  3606. return rc;
  3607. }
  3608. /**
  3609. * mv_print_info - Dump key info to kernel log for perusal.
  3610. * @host: ATA host to print info about
  3611. *
  3612. * FIXME: complete this.
  3613. *
  3614. * LOCKING:
  3615. * Inherited from caller.
  3616. */
  3617. static void mv_print_info(struct ata_host *host)
  3618. {
  3619. struct pci_dev *pdev = to_pci_dev(host->dev);
  3620. struct mv_host_priv *hpriv = host->private_data;
  3621. u8 scc;
  3622. const char *scc_s, *gen;
  3623. /* Use this to determine the HW stepping of the chip so we know
  3624. * what errata to workaround
  3625. */
  3626. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
  3627. if (scc == 0)
  3628. scc_s = "SCSI";
  3629. else if (scc == 0x01)
  3630. scc_s = "RAID";
  3631. else
  3632. scc_s = "?";
  3633. if (IS_GEN_I(hpriv))
  3634. gen = "I";
  3635. else if (IS_GEN_II(hpriv))
  3636. gen = "II";
  3637. else if (IS_GEN_IIE(hpriv))
  3638. gen = "IIE";
  3639. else
  3640. gen = "?";
  3641. dev_printk(KERN_INFO, &pdev->dev,
  3642. "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
  3643. gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
  3644. scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
  3645. }
  3646. /**
  3647. * mv_pci_init_one - handle a positive probe of a PCI Marvell host
  3648. * @pdev: PCI device found
  3649. * @ent: PCI device ID entry for the matched host
  3650. *
  3651. * LOCKING:
  3652. * Inherited from caller.
  3653. */
  3654. static int mv_pci_init_one(struct pci_dev *pdev,
  3655. const struct pci_device_id *ent)
  3656. {
  3657. static int printed_version;
  3658. unsigned int board_idx = (unsigned int)ent->driver_data;
  3659. const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
  3660. struct ata_host *host;
  3661. struct mv_host_priv *hpriv;
  3662. int n_ports, rc;
  3663. if (!printed_version++)
  3664. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  3665. /* allocate host */
  3666. n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
  3667. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  3668. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  3669. if (!host || !hpriv)
  3670. return -ENOMEM;
  3671. host->private_data = hpriv;
  3672. hpriv->n_ports = n_ports;
  3673. /* acquire resources */
  3674. rc = pcim_enable_device(pdev);
  3675. if (rc)
  3676. return rc;
  3677. rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
  3678. if (rc == -EBUSY)
  3679. pcim_pin_device(pdev);
  3680. if (rc)
  3681. return rc;
  3682. host->iomap = pcim_iomap_table(pdev);
  3683. hpriv->base = host->iomap[MV_PRIMARY_BAR];
  3684. rc = pci_go_64(pdev);
  3685. if (rc)
  3686. return rc;
  3687. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  3688. if (rc)
  3689. return rc;
  3690. /* initialize adapter */
  3691. rc = mv_init_host(host, board_idx);
  3692. if (rc)
  3693. return rc;
  3694. /* Enable message-switched interrupts, if requested */
  3695. if (msi && pci_enable_msi(pdev) == 0)
  3696. hpriv->hp_flags |= MV_HP_FLAG_MSI;
  3697. mv_dump_pci_cfg(pdev, 0x68);
  3698. mv_print_info(host);
  3699. pci_set_master(pdev);
  3700. pci_try_set_mwi(pdev);
  3701. return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
  3702. IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
  3703. }
  3704. #endif
  3705. static int mv_platform_probe(struct platform_device *pdev);
  3706. static int __devexit mv_platform_remove(struct platform_device *pdev);
  3707. static int __init mv_init(void)
  3708. {
  3709. int rc = -ENODEV;
  3710. #ifdef CONFIG_PCI
  3711. rc = pci_register_driver(&mv_pci_driver);
  3712. if (rc < 0)
  3713. return rc;
  3714. #endif
  3715. rc = platform_driver_register(&mv_platform_driver);
  3716. #ifdef CONFIG_PCI
  3717. if (rc < 0)
  3718. pci_unregister_driver(&mv_pci_driver);
  3719. #endif
  3720. return rc;
  3721. }
  3722. static void __exit mv_exit(void)
  3723. {
  3724. #ifdef CONFIG_PCI
  3725. pci_unregister_driver(&mv_pci_driver);
  3726. #endif
  3727. platform_driver_unregister(&mv_platform_driver);
  3728. }
  3729. MODULE_AUTHOR("Brett Russ");
  3730. MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
  3731. MODULE_LICENSE("GPL");
  3732. MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
  3733. MODULE_VERSION(DRV_VERSION);
  3734. MODULE_ALIAS("platform:" DRV_NAME);
  3735. module_init(mv_init);
  3736. module_exit(mv_exit);