x2apic_phys.c 5.3 KB

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  1. #include <linux/threads.h>
  2. #include <linux/cpumask.h>
  3. #include <linux/string.h>
  4. #include <linux/kernel.h>
  5. #include <linux/ctype.h>
  6. #include <linux/init.h>
  7. #include <linux/dmar.h>
  8. #include <asm/smp.h>
  9. #include <asm/apic.h>
  10. #include <asm/ipi.h>
  11. int x2apic_phys;
  12. static int set_x2apic_phys_mode(char *arg)
  13. {
  14. x2apic_phys = 1;
  15. return 0;
  16. }
  17. early_param("x2apic_phys", set_x2apic_phys_mode);
  18. static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  19. {
  20. if (x2apic_phys)
  21. return x2apic_enabled();
  22. else
  23. return 0;
  24. }
  25. /*
  26. * need to use more than cpu 0, because we need more vectors when
  27. * MSI-X are used.
  28. */
  29. static const struct cpumask *x2apic_target_cpus(void)
  30. {
  31. return cpu_online_mask;
  32. }
  33. static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
  34. {
  35. cpumask_clear(retmask);
  36. cpumask_set_cpu(cpu, retmask);
  37. }
  38. static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
  39. unsigned int dest)
  40. {
  41. unsigned long cfg;
  42. cfg = __prepare_ICR(0, vector, dest);
  43. /*
  44. * send the IPI.
  45. */
  46. native_x2apic_icr_write(cfg, apicid);
  47. }
  48. static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
  49. {
  50. unsigned long query_cpu;
  51. unsigned long flags;
  52. x2apic_wrmsr_fence();
  53. local_irq_save(flags);
  54. for_each_cpu(query_cpu, mask) {
  55. __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
  56. vector, APIC_DEST_PHYSICAL);
  57. }
  58. local_irq_restore(flags);
  59. }
  60. static void
  61. x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
  62. {
  63. unsigned long this_cpu = smp_processor_id();
  64. unsigned long query_cpu;
  65. unsigned long flags;
  66. x2apic_wrmsr_fence();
  67. local_irq_save(flags);
  68. for_each_cpu(query_cpu, mask) {
  69. if (query_cpu != this_cpu)
  70. __x2apic_send_IPI_dest(
  71. per_cpu(x86_cpu_to_apicid, query_cpu),
  72. vector, APIC_DEST_PHYSICAL);
  73. }
  74. local_irq_restore(flags);
  75. }
  76. static void x2apic_send_IPI_allbutself(int vector)
  77. {
  78. unsigned long this_cpu = smp_processor_id();
  79. unsigned long query_cpu;
  80. unsigned long flags;
  81. x2apic_wrmsr_fence();
  82. local_irq_save(flags);
  83. for_each_online_cpu(query_cpu) {
  84. if (query_cpu == this_cpu)
  85. continue;
  86. __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
  87. vector, APIC_DEST_PHYSICAL);
  88. }
  89. local_irq_restore(flags);
  90. }
  91. static void x2apic_send_IPI_all(int vector)
  92. {
  93. x2apic_send_IPI_mask(cpu_online_mask, vector);
  94. }
  95. static int x2apic_apic_id_registered(void)
  96. {
  97. return 1;
  98. }
  99. static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
  100. {
  101. /*
  102. * We're using fixed IRQ delivery, can only return one phys APIC ID.
  103. * May as well be the first.
  104. */
  105. int cpu = cpumask_first(cpumask);
  106. if ((unsigned)cpu < nr_cpu_ids)
  107. return per_cpu(x86_cpu_to_apicid, cpu);
  108. else
  109. return BAD_APICID;
  110. }
  111. static unsigned int
  112. x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
  113. const struct cpumask *andmask)
  114. {
  115. int cpu;
  116. /*
  117. * We're using fixed IRQ delivery, can only return one phys APIC ID.
  118. * May as well be the first.
  119. */
  120. for_each_cpu_and(cpu, cpumask, andmask) {
  121. if (cpumask_test_cpu(cpu, cpu_online_mask))
  122. break;
  123. }
  124. if (cpu < nr_cpu_ids)
  125. return per_cpu(x86_cpu_to_apicid, cpu);
  126. return BAD_APICID;
  127. }
  128. static unsigned int x2apic_phys_get_apic_id(unsigned long x)
  129. {
  130. return x;
  131. }
  132. static unsigned long set_apic_id(unsigned int id)
  133. {
  134. return id;
  135. }
  136. static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
  137. {
  138. return initial_apicid >> index_msb;
  139. }
  140. static void x2apic_send_IPI_self(int vector)
  141. {
  142. apic_write(APIC_SELF_IPI, vector);
  143. }
  144. static void init_x2apic_ldr(void)
  145. {
  146. }
  147. struct apic apic_x2apic_phys = {
  148. .name = "physical x2apic",
  149. .probe = NULL,
  150. .acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
  151. .apic_id_registered = x2apic_apic_id_registered,
  152. .irq_delivery_mode = dest_Fixed,
  153. .irq_dest_mode = 0, /* physical */
  154. .target_cpus = x2apic_target_cpus,
  155. .disable_esr = 0,
  156. .dest_logical = 0,
  157. .check_apicid_used = NULL,
  158. .check_apicid_present = NULL,
  159. .vector_allocation_domain = x2apic_vector_allocation_domain,
  160. .init_apic_ldr = init_x2apic_ldr,
  161. .ioapic_phys_id_map = NULL,
  162. .setup_apic_routing = NULL,
  163. .multi_timer_check = NULL,
  164. .apicid_to_node = NULL,
  165. .cpu_to_logical_apicid = NULL,
  166. .cpu_present_to_apicid = default_cpu_present_to_apicid,
  167. .apicid_to_cpu_present = NULL,
  168. .setup_portio_remap = NULL,
  169. .check_phys_apicid_present = default_check_phys_apicid_present,
  170. .enable_apic_mode = NULL,
  171. .phys_pkg_id = x2apic_phys_pkg_id,
  172. .mps_oem_check = NULL,
  173. .get_apic_id = x2apic_phys_get_apic_id,
  174. .set_apic_id = set_apic_id,
  175. .apic_id_mask = 0xFFFFFFFFu,
  176. .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
  177. .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
  178. .send_IPI_mask = x2apic_send_IPI_mask,
  179. .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
  180. .send_IPI_allbutself = x2apic_send_IPI_allbutself,
  181. .send_IPI_all = x2apic_send_IPI_all,
  182. .send_IPI_self = x2apic_send_IPI_self,
  183. .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
  184. .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
  185. .wait_for_init_deassert = NULL,
  186. .smp_callin_clear_local_apic = NULL,
  187. .inquire_remote_apic = NULL,
  188. .read = native_apic_msr_read,
  189. .write = native_apic_msr_write,
  190. .icr_read = native_x2apic_icr_read,
  191. .icr_write = native_x2apic_icr_write,
  192. .wait_icr_idle = native_x2apic_wait_icr_idle,
  193. .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
  194. };