sun4d_smp.c 9.7 KB

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  1. /* sun4d_smp.c: Sparc SS1000/SC2000 SMP support.
  2. *
  3. * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  4. *
  5. * Based on sun4m's smp.c, which is:
  6. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  7. */
  8. #include <asm/head.h>
  9. #include <linux/kernel.h>
  10. #include <linux/sched.h>
  11. #include <linux/threads.h>
  12. #include <linux/smp.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/init.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/mm.h>
  18. #include <linux/swap.h>
  19. #include <linux/profile.h>
  20. #include <linux/delay.h>
  21. #include <linux/cpu.h>
  22. #include <asm/ptrace.h>
  23. #include <asm/atomic.h>
  24. #include <asm/irq_regs.h>
  25. #include <asm/irq.h>
  26. #include <asm/page.h>
  27. #include <asm/pgalloc.h>
  28. #include <asm/pgtable.h>
  29. #include <asm/oplib.h>
  30. #include <asm/sbi.h>
  31. #include <asm/tlbflush.h>
  32. #include <asm/cacheflush.h>
  33. #include <asm/cpudata.h>
  34. #include "irq.h"
  35. #define IRQ_CROSS_CALL 15
  36. extern ctxd_t *srmmu_ctx_table_phys;
  37. static volatile int smp_processors_ready = 0;
  38. static int smp_highest_cpu;
  39. extern volatile unsigned long cpu_callin_map[NR_CPUS];
  40. extern cpuinfo_sparc cpu_data[NR_CPUS];
  41. extern unsigned char boot_cpu_id;
  42. extern volatile int smp_process_available;
  43. extern cpumask_t smp_commenced_mask;
  44. extern int __smp4d_processor_id(void);
  45. /* #define SMP_DEBUG */
  46. #ifdef SMP_DEBUG
  47. #define SMP_PRINTK(x) printk x
  48. #else
  49. #define SMP_PRINTK(x)
  50. #endif
  51. static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
  52. {
  53. __asm__ __volatile__("swap [%1], %0\n\t" :
  54. "=&r" (val), "=&r" (ptr) :
  55. "0" (val), "1" (ptr));
  56. return val;
  57. }
  58. static void smp_setup_percpu_timer(void);
  59. extern void cpu_probe(void);
  60. extern void sun4d_distribute_irqs(void);
  61. static unsigned char cpu_leds[32];
  62. static inline void show_leds(int cpuid)
  63. {
  64. cpuid &= 0x1e;
  65. __asm__ __volatile__ ("stba %0, [%1] %2" : :
  66. "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
  67. "r" (ECSR_BASE(cpuid) | BB_LEDS),
  68. "i" (ASI_M_CTL));
  69. }
  70. void __cpuinit smp4d_callin(void)
  71. {
  72. int cpuid = hard_smp4d_processor_id();
  73. extern spinlock_t sun4d_imsk_lock;
  74. unsigned long flags;
  75. /* Show we are alive */
  76. cpu_leds[cpuid] = 0x6;
  77. show_leds(cpuid);
  78. /* Enable level15 interrupt, disable level14 interrupt for now */
  79. cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
  80. local_flush_cache_all();
  81. local_flush_tlb_all();
  82. notify_cpu_starting(cpuid);
  83. /*
  84. * Unblock the master CPU _only_ when the scheduler state
  85. * of all secondary CPUs will be up-to-date, so after
  86. * the SMP initialization the master will be just allowed
  87. * to call the scheduler code.
  88. */
  89. /* Get our local ticker going. */
  90. smp_setup_percpu_timer();
  91. calibrate_delay();
  92. smp_store_cpu_info(cpuid);
  93. local_flush_cache_all();
  94. local_flush_tlb_all();
  95. /* Allow master to continue. */
  96. sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
  97. local_flush_cache_all();
  98. local_flush_tlb_all();
  99. cpu_probe();
  100. while((unsigned long)current_set[cpuid] < PAGE_OFFSET)
  101. barrier();
  102. while(current_set[cpuid]->cpu != cpuid)
  103. barrier();
  104. /* Fix idle thread fields. */
  105. __asm__ __volatile__("ld [%0], %%g6\n\t"
  106. : : "r" (&current_set[cpuid])
  107. : "memory" /* paranoid */);
  108. cpu_leds[cpuid] = 0x9;
  109. show_leds(cpuid);
  110. /* Attach to the address space of init_task. */
  111. atomic_inc(&init_mm.mm_count);
  112. current->active_mm = &init_mm;
  113. local_flush_cache_all();
  114. local_flush_tlb_all();
  115. local_irq_enable(); /* We don't allow PIL 14 yet */
  116. while (!cpu_isset(cpuid, smp_commenced_mask))
  117. barrier();
  118. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  119. cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
  120. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  121. set_cpu_online(cpuid, true);
  122. }
  123. extern void init_IRQ(void);
  124. extern void cpu_panic(void);
  125. /*
  126. * Cycle through the processors asking the PROM to start each one.
  127. */
  128. extern struct linux_prom_registers smp_penguin_ctable;
  129. void __init smp4d_boot_cpus(void)
  130. {
  131. if (boot_cpu_id)
  132. current_set[0] = NULL;
  133. smp_setup_percpu_timer();
  134. local_flush_cache_all();
  135. }
  136. int __cpuinit smp4d_boot_one_cpu(int i)
  137. {
  138. extern unsigned long sun4d_cpu_startup;
  139. unsigned long *entry = &sun4d_cpu_startup;
  140. struct task_struct *p;
  141. int timeout;
  142. int cpu_node;
  143. cpu_find_by_instance(i, &cpu_node,NULL);
  144. /* Cook up an idler for this guy. */
  145. p = fork_idle(i);
  146. current_set[i] = task_thread_info(p);
  147. /*
  148. * Initialize the contexts table
  149. * Since the call to prom_startcpu() trashes the structure,
  150. * we need to re-initialize it for each cpu
  151. */
  152. smp_penguin_ctable.which_io = 0;
  153. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  154. smp_penguin_ctable.reg_size = 0;
  155. /* whirrr, whirrr, whirrrrrrrrr... */
  156. SMP_PRINTK(("Starting CPU %d at %p \n", i, entry));
  157. local_flush_cache_all();
  158. prom_startcpu(cpu_node,
  159. &smp_penguin_ctable, 0, (char *)entry);
  160. SMP_PRINTK(("prom_startcpu returned :)\n"));
  161. /* wheee... it's going... */
  162. for(timeout = 0; timeout < 10000; timeout++) {
  163. if(cpu_callin_map[i])
  164. break;
  165. udelay(200);
  166. }
  167. if (!(cpu_callin_map[i])) {
  168. printk("Processor %d is stuck.\n", i);
  169. return -ENODEV;
  170. }
  171. local_flush_cache_all();
  172. return 0;
  173. }
  174. void __init smp4d_smp_done(void)
  175. {
  176. int i, first;
  177. int *prev;
  178. /* setup cpu list for irq rotation */
  179. first = 0;
  180. prev = &first;
  181. for_each_online_cpu(i) {
  182. *prev = i;
  183. prev = &cpu_data(i).next;
  184. }
  185. *prev = first;
  186. local_flush_cache_all();
  187. /* Ok, they are spinning and ready to go. */
  188. smp_processors_ready = 1;
  189. sun4d_distribute_irqs();
  190. }
  191. static struct smp_funcall {
  192. smpfunc_t func;
  193. unsigned long arg1;
  194. unsigned long arg2;
  195. unsigned long arg3;
  196. unsigned long arg4;
  197. unsigned long arg5;
  198. unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
  199. unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
  200. } ccall_info __attribute__((aligned(8)));
  201. static DEFINE_SPINLOCK(cross_call_lock);
  202. /* Cross calls must be serialized, at least currently. */
  203. static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  204. unsigned long arg2, unsigned long arg3,
  205. unsigned long arg4)
  206. {
  207. if(smp_processors_ready) {
  208. register int high = smp_highest_cpu;
  209. unsigned long flags;
  210. spin_lock_irqsave(&cross_call_lock, flags);
  211. {
  212. /* If you make changes here, make sure gcc generates proper code... */
  213. register smpfunc_t f asm("i0") = func;
  214. register unsigned long a1 asm("i1") = arg1;
  215. register unsigned long a2 asm("i2") = arg2;
  216. register unsigned long a3 asm("i3") = arg3;
  217. register unsigned long a4 asm("i4") = arg4;
  218. register unsigned long a5 asm("i5") = 0;
  219. __asm__ __volatile__(
  220. "std %0, [%6]\n\t"
  221. "std %2, [%6 + 8]\n\t"
  222. "std %4, [%6 + 16]\n\t" : :
  223. "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
  224. "r" (&ccall_info.func));
  225. }
  226. /* Init receive/complete mapping, plus fire the IPI's off. */
  227. {
  228. register int i;
  229. cpu_clear(smp_processor_id(), mask);
  230. cpus_and(mask, cpu_online_map, mask);
  231. for(i = 0; i <= high; i++) {
  232. if (cpu_isset(i, mask)) {
  233. ccall_info.processors_in[i] = 0;
  234. ccall_info.processors_out[i] = 0;
  235. sun4d_send_ipi(i, IRQ_CROSS_CALL);
  236. }
  237. }
  238. }
  239. {
  240. register int i;
  241. i = 0;
  242. do {
  243. if (!cpu_isset(i, mask))
  244. continue;
  245. while(!ccall_info.processors_in[i])
  246. barrier();
  247. } while(++i <= high);
  248. i = 0;
  249. do {
  250. if (!cpu_isset(i, mask))
  251. continue;
  252. while(!ccall_info.processors_out[i])
  253. barrier();
  254. } while(++i <= high);
  255. }
  256. spin_unlock_irqrestore(&cross_call_lock, flags);
  257. }
  258. }
  259. /* Running cross calls. */
  260. void smp4d_cross_call_irq(void)
  261. {
  262. int i = hard_smp4d_processor_id();
  263. ccall_info.processors_in[i] = 1;
  264. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  265. ccall_info.arg4, ccall_info.arg5);
  266. ccall_info.processors_out[i] = 1;
  267. }
  268. void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
  269. {
  270. struct pt_regs *old_regs;
  271. int cpu = hard_smp4d_processor_id();
  272. static int cpu_tick[NR_CPUS];
  273. static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
  274. old_regs = set_irq_regs(regs);
  275. bw_get_prof_limit(cpu);
  276. bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
  277. cpu_tick[cpu]++;
  278. if (!(cpu_tick[cpu] & 15)) {
  279. if (cpu_tick[cpu] == 0x60)
  280. cpu_tick[cpu] = 0;
  281. cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
  282. show_leds(cpu);
  283. }
  284. profile_tick(CPU_PROFILING);
  285. if(!--prof_counter(cpu)) {
  286. int user = user_mode(regs);
  287. irq_enter();
  288. update_process_times(user);
  289. irq_exit();
  290. prof_counter(cpu) = prof_multiplier(cpu);
  291. }
  292. set_irq_regs(old_regs);
  293. }
  294. extern unsigned int lvl14_resolution;
  295. static void __cpuinit smp_setup_percpu_timer(void)
  296. {
  297. int cpu = hard_smp4d_processor_id();
  298. prof_counter(cpu) = prof_multiplier(cpu) = 1;
  299. load_profile_irq(cpu, lvl14_resolution);
  300. }
  301. void __init smp4d_blackbox_id(unsigned *addr)
  302. {
  303. int rd = *addr & 0x3e000000;
  304. addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
  305. addr[1] = 0x01000000; /* nop */
  306. addr[2] = 0x01000000; /* nop */
  307. }
  308. void __init smp4d_blackbox_current(unsigned *addr)
  309. {
  310. int rd = *addr & 0x3e000000;
  311. addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
  312. addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */
  313. addr[4] = 0x01000000; /* nop */
  314. }
  315. void __init sun4d_init_smp(void)
  316. {
  317. int i;
  318. extern unsigned int t_nmi[], linux_trap_ipi15_sun4d[], linux_trap_ipi15_sun4m[];
  319. /* Patch ipi15 trap table */
  320. t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
  321. /* And set btfixup... */
  322. BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
  323. BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
  324. BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
  325. BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
  326. for (i = 0; i < NR_CPUS; i++) {
  327. ccall_info.processors_in[i] = 1;
  328. ccall_info.processors_out[i] = 1;
  329. }
  330. }