hwblk-sh7724.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121
  1. /*
  2. * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
  3. *
  4. * SH7724 hardware block support
  5. *
  6. * Copyright (C) 2009 Magnus Damm
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/kernel.h>
  23. #include <linux/io.h>
  24. #include <asm/suspend.h>
  25. #include <asm/hwblk.h>
  26. #include <cpu/sh7724.h>
  27. /* SH7724 registers */
  28. #define MSTPCR0 0xa4150030
  29. #define MSTPCR1 0xa4150034
  30. #define MSTPCR2 0xa4150038
  31. /* SH7724 Power Domains */
  32. enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
  33. static struct hwblk_area sh7724_hwblk_area[] = {
  34. [CORE_AREA] = HWBLK_AREA(0, 0),
  35. [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
  36. [SUB_AREA] = HWBLK_AREA(0, 0),
  37. };
  38. /* Table mapping HWBLK to Module Stop Bit and Power Domain */
  39. static struct hwblk sh7724_hwblk[HWBLK_NR] = {
  40. [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
  41. [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
  42. [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
  43. [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
  44. [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
  45. [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
  46. [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
  47. [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
  48. [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
  49. [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
  50. [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
  51. [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
  52. [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
  53. [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
  54. [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
  55. [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
  56. [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
  57. [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
  58. [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
  59. [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
  60. [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
  61. [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
  62. [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
  63. [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
  64. [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
  65. [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
  66. [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
  67. [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
  68. [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
  69. [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
  70. [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
  71. [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
  72. [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
  73. [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
  74. [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
  75. [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
  76. [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
  77. [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
  78. [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
  79. [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
  80. [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
  81. [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
  82. [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
  83. [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
  84. [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
  85. [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
  86. [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
  87. [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
  88. [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
  89. [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
  90. [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
  91. [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
  92. [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
  93. };
  94. static struct hwblk_info sh7724_hwblk_info = {
  95. .areas = sh7724_hwblk_area,
  96. .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
  97. .hwblks = sh7724_hwblk,
  98. .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
  99. };
  100. int arch_hwblk_sleep_mode(void)
  101. {
  102. if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
  103. return SUSP_SH_STANDBY | SUSP_SH_SF;
  104. if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
  105. return SUSP_SH_SLEEP | SUSP_SH_SF;
  106. return SUSP_SH_SLEEP;
  107. }
  108. int __init arch_hwblk_init(void)
  109. {
  110. return hwblk_register(&sh7724_hwblk_info);
  111. }