clock-sh7763.c 2.4 KB

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  1. /*
  2. * arch/sh/kernel/cpu/sh4a/clock-sh7763.c
  3. *
  4. * SH7763 support for the clock framework
  5. *
  6. * Copyright (C) 2005 Paul Mundt
  7. * Copyright (C) 2007 Yoshihiro Shimoda
  8. *
  9. * This file is subject to the terms and conditions of the GNU General Public
  10. * License. See the file "COPYING" in the main directory of this archive
  11. * for more details.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <asm/clock.h>
  16. #include <asm/freq.h>
  17. #include <asm/io.h>
  18. static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
  19. static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
  20. static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
  21. static void master_clk_init(struct clk *clk)
  22. {
  23. clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
  24. }
  25. static struct clk_ops sh7763_master_clk_ops = {
  26. .init = master_clk_init,
  27. };
  28. static unsigned long module_clk_recalc(struct clk *clk)
  29. {
  30. int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
  31. return clk->parent->rate / p0fc_divisors[idx];
  32. }
  33. static struct clk_ops sh7763_module_clk_ops = {
  34. .recalc = module_clk_recalc,
  35. };
  36. static unsigned long bus_clk_recalc(struct clk *clk)
  37. {
  38. int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
  39. return clk->parent->rate / bfc_divisors[idx];
  40. }
  41. static struct clk_ops sh7763_bus_clk_ops = {
  42. .recalc = bus_clk_recalc,
  43. };
  44. static struct clk_ops sh7763_cpu_clk_ops = {
  45. .recalc = followparent_recalc,
  46. };
  47. static struct clk_ops *sh7763_clk_ops[] = {
  48. &sh7763_master_clk_ops,
  49. &sh7763_module_clk_ops,
  50. &sh7763_bus_clk_ops,
  51. &sh7763_cpu_clk_ops,
  52. };
  53. void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
  54. {
  55. if (idx < ARRAY_SIZE(sh7763_clk_ops))
  56. *ops = sh7763_clk_ops[idx];
  57. }
  58. static unsigned long shyway_clk_recalc(struct clk *clk)
  59. {
  60. int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
  61. return clk->parent->rate / cfc_divisors[idx];
  62. }
  63. static struct clk_ops sh7763_shyway_clk_ops = {
  64. .recalc = shyway_clk_recalc,
  65. };
  66. static struct clk sh7763_shyway_clk = {
  67. .name = "shyway_clk",
  68. .flags = CLK_ENABLE_ON_INIT,
  69. .ops = &sh7763_shyway_clk_ops,
  70. };
  71. /*
  72. * Additional SH7763-specific on-chip clocks that aren't already part of the
  73. * clock framework
  74. */
  75. static struct clk *sh7763_onchip_clocks[] = {
  76. &sh7763_shyway_clk,
  77. };
  78. int __init arch_clk_init(void)
  79. {
  80. struct clk *clk;
  81. int i, ret = 0;
  82. cpg_clk_init();
  83. clk = clk_get(NULL, "master_clk");
  84. for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
  85. struct clk *clkp = sh7763_onchip_clocks[i];
  86. clkp->parent = clk;
  87. ret |= clk_register(clkp);
  88. }
  89. clk_put(clk);
  90. return ret;
  91. }