setup-sh7619.c 4.8 KB

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  1. /*
  2. * SH7619 Setup
  3. *
  4. * Copyright (C) 2006 Yoshinori Sato
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/platform_device.h>
  12. #include <linux/init.h>
  13. #include <linux/serial.h>
  14. #include <linux/serial_sci.h>
  15. #include <linux/sh_timer.h>
  16. #include <linux/io.h>
  17. enum {
  18. UNUSED = 0,
  19. /* interrupt sources */
  20. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  21. WDT, EDMAC, CMT0, CMT1,
  22. SCIF0, SCIF1, SCIF2,
  23. HIF_HIFI, HIF_HIFBI,
  24. DMAC0, DMAC1, DMAC2, DMAC3,
  25. SIOF,
  26. };
  27. static struct intc_vect vectors[] __initdata = {
  28. INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  29. INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  30. INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
  31. INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
  32. INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
  33. INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
  34. INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
  35. INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
  36. INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
  37. INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
  38. INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
  39. INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
  40. INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
  41. INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
  42. INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
  43. INTC_IRQ(SIOF, 108),
  44. };
  45. static struct intc_prio_reg prio_registers[] __initdata = {
  46. { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
  47. { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
  48. { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
  49. { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
  50. { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
  51. { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
  52. { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
  53. };
  54. static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
  55. NULL, prio_registers, NULL);
  56. static struct plat_sci_port sci_platform_data[] = {
  57. {
  58. .mapbase = 0xf8400000,
  59. .flags = UPF_BOOT_AUTOCONF,
  60. .type = PORT_SCIF,
  61. .irqs = { 88, 88, 88, 88 },
  62. }, {
  63. .mapbase = 0xf8410000,
  64. .flags = UPF_BOOT_AUTOCONF,
  65. .type = PORT_SCIF,
  66. .irqs = { 92, 92, 92, 92 },
  67. }, {
  68. .mapbase = 0xf8420000,
  69. .flags = UPF_BOOT_AUTOCONF,
  70. .type = PORT_SCIF,
  71. .irqs = { 96, 96, 96, 96 },
  72. }, {
  73. .flags = 0,
  74. }
  75. };
  76. static struct platform_device sci_device = {
  77. .name = "sh-sci",
  78. .id = -1,
  79. .dev = {
  80. .platform_data = sci_platform_data,
  81. },
  82. };
  83. static struct resource eth_resources[] = {
  84. [0] = {
  85. .start = 0xfb000000,
  86. .end = 0xfb0001c8,
  87. .flags = IORESOURCE_MEM,
  88. },
  89. [1] = {
  90. .start = 85,
  91. .end = 85,
  92. .flags = IORESOURCE_IRQ,
  93. },
  94. };
  95. static struct platform_device eth_device = {
  96. .name = "sh-eth",
  97. .id = -1,
  98. .dev = {
  99. .platform_data = (void *)1,
  100. },
  101. .num_resources = ARRAY_SIZE(eth_resources),
  102. .resource = eth_resources,
  103. };
  104. static struct sh_timer_config cmt0_platform_data = {
  105. .name = "CMT0",
  106. .channel_offset = 0x02,
  107. .timer_bit = 0,
  108. .clk = "peripheral_clk",
  109. .clockevent_rating = 125,
  110. .clocksource_rating = 0, /* disabled due to code generation issues */
  111. };
  112. static struct resource cmt0_resources[] = {
  113. [0] = {
  114. .name = "CMT0",
  115. .start = 0xf84a0072,
  116. .end = 0xf84a0077,
  117. .flags = IORESOURCE_MEM,
  118. },
  119. [1] = {
  120. .start = 86,
  121. .flags = IORESOURCE_IRQ,
  122. },
  123. };
  124. static struct platform_device cmt0_device = {
  125. .name = "sh_cmt",
  126. .id = 0,
  127. .dev = {
  128. .platform_data = &cmt0_platform_data,
  129. },
  130. .resource = cmt0_resources,
  131. .num_resources = ARRAY_SIZE(cmt0_resources),
  132. };
  133. static struct sh_timer_config cmt1_platform_data = {
  134. .name = "CMT1",
  135. .channel_offset = 0x08,
  136. .timer_bit = 1,
  137. .clk = "peripheral_clk",
  138. .clockevent_rating = 125,
  139. .clocksource_rating = 0, /* disabled due to code generation issues */
  140. };
  141. static struct resource cmt1_resources[] = {
  142. [0] = {
  143. .name = "CMT1",
  144. .start = 0xf84a0078,
  145. .end = 0xf84a007d,
  146. .flags = IORESOURCE_MEM,
  147. },
  148. [1] = {
  149. .start = 87,
  150. .flags = IORESOURCE_IRQ,
  151. },
  152. };
  153. static struct platform_device cmt1_device = {
  154. .name = "sh_cmt",
  155. .id = 1,
  156. .dev = {
  157. .platform_data = &cmt1_platform_data,
  158. },
  159. .resource = cmt1_resources,
  160. .num_resources = ARRAY_SIZE(cmt1_resources),
  161. };
  162. static struct platform_device *sh7619_devices[] __initdata = {
  163. &sci_device,
  164. &eth_device,
  165. &cmt0_device,
  166. &cmt1_device,
  167. };
  168. static int __init sh7619_devices_setup(void)
  169. {
  170. return platform_add_devices(sh7619_devices,
  171. ARRAY_SIZE(sh7619_devices));
  172. }
  173. arch_initcall(sh7619_devices_setup);
  174. void __init plat_irq_setup(void)
  175. {
  176. register_intc_controller(&intc_desc);
  177. }
  178. static struct platform_device *sh7619_early_devices[] __initdata = {
  179. &cmt0_device,
  180. &cmt1_device,
  181. };
  182. #define STBCR3 0xf80a0000
  183. void __init plat_early_device_setup(void)
  184. {
  185. /* enable CMT clock */
  186. __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
  187. early_platform_add_devices(sh7619_early_devices,
  188. ARRAY_SIZE(sh7619_early_devices));
  189. }