ops-sh7786.c 3.3 KB

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  1. /*
  2. * Generic SH7786 PCI-Express operations.
  3. *
  4. * Copyright (C) 2009 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License v2. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/pci.h>
  13. #include <linux/io.h>
  14. #include <linux/spinlock.h>
  15. #include "pcie-sh7786.h"
  16. enum {
  17. PCI_ACCESS_READ,
  18. PCI_ACCESS_WRITE,
  19. };
  20. static DEFINE_SPINLOCK(sh7786_pcie_lock);
  21. static int sh7786_pcie_config_access(unsigned char access_type,
  22. struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
  23. {
  24. struct pci_channel *chan = bus->sysdata;
  25. int dev, func;
  26. dev = PCI_SLOT(devfn);
  27. func = PCI_FUNC(devfn);
  28. if (bus->number > 255 || dev > 31 || func > 7)
  29. return PCIBIOS_FUNC_NOT_SUPPORTED;
  30. if (devfn)
  31. return PCIBIOS_DEVICE_NOT_FOUND;
  32. /* Set the PIO address */
  33. pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
  34. (func << 16) | (where & ~3), SH4A_PCIEPAR);
  35. /* Enable the configuration access */
  36. pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
  37. if (access_type == PCI_ACCESS_READ)
  38. *data = pci_read_reg(chan, SH4A_PCIEPDR);
  39. else
  40. pci_write_reg(chan, *data, SH4A_PCIEPDR);
  41. /* Check for master and target aborts */
  42. if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
  43. return PCIBIOS_DEVICE_NOT_FOUND;
  44. return PCIBIOS_SUCCESSFUL;
  45. }
  46. static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
  47. int where, int size, u32 *val)
  48. {
  49. unsigned long flags;
  50. int ret;
  51. u32 data;
  52. if ((size == 2) && (where & 1))
  53. return PCIBIOS_BAD_REGISTER_NUMBER;
  54. else if ((size == 4) && (where & 3))
  55. return PCIBIOS_BAD_REGISTER_NUMBER;
  56. spin_lock_irqsave(&sh7786_pcie_lock, flags);
  57. ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
  58. devfn, where, &data);
  59. if (ret != PCIBIOS_SUCCESSFUL)
  60. goto out;
  61. if (size == 1)
  62. *val = (data >> ((where & 3) << 3)) & 0xff;
  63. else if (size == 2)
  64. *val = (data >> ((where & 2) << 3)) & 0xffff;
  65. else
  66. *val = data;
  67. dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
  68. "where=0x%04x size=%d val=0x%08lx\n", bus->number,
  69. devfn, where, size, (unsigned long)*val);
  70. out:
  71. spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
  72. return ret;
  73. }
  74. static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
  75. int where, int size, u32 val)
  76. {
  77. unsigned long flags;
  78. int shift, ret;
  79. u32 data;
  80. if ((size == 2) && (where & 1))
  81. return PCIBIOS_BAD_REGISTER_NUMBER;
  82. else if ((size == 4) && (where & 3))
  83. return PCIBIOS_BAD_REGISTER_NUMBER;
  84. spin_lock_irqsave(&sh7786_pcie_lock, flags);
  85. ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
  86. devfn, where, &data);
  87. if (ret != PCIBIOS_SUCCESSFUL)
  88. goto out;
  89. dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
  90. "where=0x%04x size=%d val=%08lx\n", bus->number,
  91. devfn, where, size, (unsigned long)val);
  92. if (size == 1) {
  93. shift = (where & 3) << 3;
  94. data &= ~(0xff << shift);
  95. data |= ((val & 0xff) << shift);
  96. } else if (size == 2) {
  97. shift = (where & 2) << 3;
  98. data &= ~(0xffff << shift);
  99. data |= ((val & 0xffff) << shift);
  100. } else
  101. data = val;
  102. ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
  103. devfn, where, &data);
  104. out:
  105. spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
  106. return ret;
  107. }
  108. struct pci_ops sh7786_pci_ops = {
  109. .read = sh7786_pcie_read,
  110. .write = sh7786_pcie_write,
  111. };