setup.c 18 KB

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  1. /*
  2. * linux/arch/sh/boards/se/7724/setup.c
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. *
  6. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/delay.h>
  18. #include <linux/smc91x.h>
  19. #include <linux/gpio.h>
  20. #include <linux/input.h>
  21. #include <linux/usb/r8a66597.h>
  22. #include <video/sh_mobile_lcdc.h>
  23. #include <media/sh_mobile_ceu.h>
  24. #include <sound/sh_fsi.h>
  25. #include <asm/io.h>
  26. #include <asm/heartbeat.h>
  27. #include <asm/sh_eth.h>
  28. #include <asm/clock.h>
  29. #include <asm/sh_keysc.h>
  30. #include <cpu/sh7724.h>
  31. #include <mach-se/mach/se7724.h>
  32. /*
  33. * SWx 1234 5678
  34. * ------------------------------------
  35. * SW31 : 1001 1100 : default
  36. * SW32 : 0111 1111 : use on board flash
  37. *
  38. * SW41 : abxx xxxx -> a = 0 : Analog monitor
  39. * 1 : Digital monitor
  40. * b = 0 : VGA
  41. * 1 : 720p
  42. */
  43. /*
  44. * about 720p
  45. *
  46. * When you use 1280 x 720 lcdc output,
  47. * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
  48. * and change SW41 to use 720p
  49. */
  50. /* Heartbeat */
  51. static struct heartbeat_data heartbeat_data = {
  52. .regsize = 16,
  53. };
  54. static struct resource heartbeat_resources[] = {
  55. [0] = {
  56. .start = PA_LED,
  57. .end = PA_LED,
  58. .flags = IORESOURCE_MEM,
  59. },
  60. };
  61. static struct platform_device heartbeat_device = {
  62. .name = "heartbeat",
  63. .id = -1,
  64. .dev = {
  65. .platform_data = &heartbeat_data,
  66. },
  67. .num_resources = ARRAY_SIZE(heartbeat_resources),
  68. .resource = heartbeat_resources,
  69. };
  70. /* LAN91C111 */
  71. static struct smc91x_platdata smc91x_info = {
  72. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  73. };
  74. static struct resource smc91x_eth_resources[] = {
  75. [0] = {
  76. .name = "SMC91C111" ,
  77. .start = 0x1a300300,
  78. .end = 0x1a30030f,
  79. .flags = IORESOURCE_MEM,
  80. },
  81. [1] = {
  82. .start = IRQ0_SMC,
  83. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  84. },
  85. };
  86. static struct platform_device smc91x_eth_device = {
  87. .name = "smc91x",
  88. .num_resources = ARRAY_SIZE(smc91x_eth_resources),
  89. .resource = smc91x_eth_resources,
  90. .dev = {
  91. .platform_data = &smc91x_info,
  92. },
  93. };
  94. /* MTD */
  95. static struct mtd_partition nor_flash_partitions[] = {
  96. {
  97. .name = "uboot",
  98. .offset = 0,
  99. .size = (1 * 1024 * 1024),
  100. .mask_flags = MTD_WRITEABLE, /* Read-only */
  101. }, {
  102. .name = "kernel",
  103. .offset = MTDPART_OFS_APPEND,
  104. .size = (2 * 1024 * 1024),
  105. }, {
  106. .name = "free-area",
  107. .offset = MTDPART_OFS_APPEND,
  108. .size = MTDPART_SIZ_FULL,
  109. },
  110. };
  111. static struct physmap_flash_data nor_flash_data = {
  112. .width = 2,
  113. .parts = nor_flash_partitions,
  114. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  115. };
  116. static struct resource nor_flash_resources[] = {
  117. [0] = {
  118. .name = "NOR Flash",
  119. .start = 0x00000000,
  120. .end = 0x01ffffff,
  121. .flags = IORESOURCE_MEM,
  122. }
  123. };
  124. static struct platform_device nor_flash_device = {
  125. .name = "physmap-flash",
  126. .resource = nor_flash_resources,
  127. .num_resources = ARRAY_SIZE(nor_flash_resources),
  128. .dev = {
  129. .platform_data = &nor_flash_data,
  130. },
  131. };
  132. /* LCDC */
  133. static struct sh_mobile_lcdc_info lcdc_info = {
  134. .clock_source = LCDC_CLK_EXTERNAL,
  135. .ch[0] = {
  136. .chan = LCDC_CHAN_MAINLCD,
  137. .bpp = 16,
  138. .clock_divider = 1,
  139. .lcd_cfg = {
  140. .name = "LB070WV1",
  141. .sync = 0, /* hsync and vsync are active low */
  142. },
  143. .lcd_size_cfg = { /* 7.0 inch */
  144. .width = 152,
  145. .height = 91,
  146. },
  147. .board_cfg = {
  148. },
  149. }
  150. };
  151. static struct resource lcdc_resources[] = {
  152. [0] = {
  153. .name = "LCDC",
  154. .start = 0xfe940000,
  155. .end = 0xfe942fff,
  156. .flags = IORESOURCE_MEM,
  157. },
  158. [1] = {
  159. .start = 106,
  160. .flags = IORESOURCE_IRQ,
  161. },
  162. };
  163. static struct platform_device lcdc_device = {
  164. .name = "sh_mobile_lcdc_fb",
  165. .num_resources = ARRAY_SIZE(lcdc_resources),
  166. .resource = lcdc_resources,
  167. .dev = {
  168. .platform_data = &lcdc_info,
  169. },
  170. .archdata = {
  171. .hwblk_id = HWBLK_LCDC,
  172. },
  173. };
  174. /* CEU0 */
  175. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  176. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  177. };
  178. static struct resource ceu0_resources[] = {
  179. [0] = {
  180. .name = "CEU0",
  181. .start = 0xfe910000,
  182. .end = 0xfe91009f,
  183. .flags = IORESOURCE_MEM,
  184. },
  185. [1] = {
  186. .start = 52,
  187. .flags = IORESOURCE_IRQ,
  188. },
  189. [2] = {
  190. /* place holder for contiguous memory */
  191. },
  192. };
  193. static struct platform_device ceu0_device = {
  194. .name = "sh_mobile_ceu",
  195. .id = 0, /* "ceu0" clock */
  196. .num_resources = ARRAY_SIZE(ceu0_resources),
  197. .resource = ceu0_resources,
  198. .dev = {
  199. .platform_data = &sh_mobile_ceu0_info,
  200. },
  201. .archdata = {
  202. .hwblk_id = HWBLK_CEU0,
  203. },
  204. };
  205. /* CEU1 */
  206. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  207. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  208. };
  209. static struct resource ceu1_resources[] = {
  210. [0] = {
  211. .name = "CEU1",
  212. .start = 0xfe914000,
  213. .end = 0xfe91409f,
  214. .flags = IORESOURCE_MEM,
  215. },
  216. [1] = {
  217. .start = 63,
  218. .flags = IORESOURCE_IRQ,
  219. },
  220. [2] = {
  221. /* place holder for contiguous memory */
  222. },
  223. };
  224. static struct platform_device ceu1_device = {
  225. .name = "sh_mobile_ceu",
  226. .id = 1, /* "ceu1" clock */
  227. .num_resources = ARRAY_SIZE(ceu1_resources),
  228. .resource = ceu1_resources,
  229. .dev = {
  230. .platform_data = &sh_mobile_ceu1_info,
  231. },
  232. .archdata = {
  233. .hwblk_id = HWBLK_CEU1,
  234. },
  235. };
  236. /* FSI */
  237. /*
  238. * FSI-A use external clock which came from ak464x.
  239. * So, we should change parent of fsi
  240. */
  241. #define FCLKACR 0xa4150008
  242. static void fsimck_init(struct clk *clk)
  243. {
  244. u32 status = ctrl_inl(clk->enable_reg);
  245. /* use external clock */
  246. status &= ~0x000000ff;
  247. status |= 0x00000080;
  248. ctrl_outl(status, clk->enable_reg);
  249. }
  250. static struct clk_ops fsimck_clk_ops = {
  251. .init = fsimck_init,
  252. };
  253. static struct clk fsimcka_clk = {
  254. .name = "fsimcka_clk",
  255. .id = -1,
  256. .ops = &fsimck_clk_ops,
  257. .enable_reg = (void __iomem *)FCLKACR,
  258. .rate = 0, /* unknown */
  259. };
  260. struct sh_fsi_platform_info fsi_info = {
  261. .porta_flags = SH_FSI_BRS_INV |
  262. SH_FSI_OUT_SLAVE_MODE |
  263. SH_FSI_IN_SLAVE_MODE |
  264. SH_FSI_OFMT(PCM) |
  265. SH_FSI_IFMT(PCM),
  266. };
  267. static struct resource fsi_resources[] = {
  268. [0] = {
  269. .name = "FSI",
  270. .start = 0xFE3C0000,
  271. .end = 0xFE3C021d,
  272. .flags = IORESOURCE_MEM,
  273. },
  274. [1] = {
  275. .start = 108,
  276. .flags = IORESOURCE_IRQ,
  277. },
  278. };
  279. static struct platform_device fsi_device = {
  280. .name = "sh_fsi",
  281. .id = 0,
  282. .num_resources = ARRAY_SIZE(fsi_resources),
  283. .resource = fsi_resources,
  284. .dev = {
  285. .platform_data = &fsi_info,
  286. },
  287. };
  288. /* KEYSC in SoC (Needs SW33-2 set to ON) */
  289. static struct sh_keysc_info keysc_info = {
  290. .mode = SH_KEYSC_MODE_1,
  291. .scan_timing = 10,
  292. .delay = 50,
  293. .keycodes = {
  294. KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
  295. KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
  296. KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
  297. KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
  298. KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
  299. KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
  300. },
  301. };
  302. static struct resource keysc_resources[] = {
  303. [0] = {
  304. .name = "KEYSC",
  305. .start = 0x044b0000,
  306. .end = 0x044b000f,
  307. .flags = IORESOURCE_MEM,
  308. },
  309. [1] = {
  310. .start = 79,
  311. .flags = IORESOURCE_IRQ,
  312. },
  313. };
  314. static struct platform_device keysc_device = {
  315. .name = "sh_keysc",
  316. .id = 0, /* "keysc0" clock */
  317. .num_resources = ARRAY_SIZE(keysc_resources),
  318. .resource = keysc_resources,
  319. .dev = {
  320. .platform_data = &keysc_info,
  321. },
  322. .archdata = {
  323. .hwblk_id = HWBLK_KEYSC,
  324. },
  325. };
  326. /* SH Eth */
  327. static struct resource sh_eth_resources[] = {
  328. [0] = {
  329. .start = SH_ETH_ADDR,
  330. .end = SH_ETH_ADDR + 0x1FC,
  331. .flags = IORESOURCE_MEM,
  332. },
  333. [1] = {
  334. .start = 91,
  335. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  336. },
  337. };
  338. struct sh_eth_plat_data sh_eth_plat = {
  339. .phy = 0x1f, /* SMSC LAN8187 */
  340. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  341. };
  342. static struct platform_device sh_eth_device = {
  343. .name = "sh-eth",
  344. .id = 0,
  345. .dev = {
  346. .platform_data = &sh_eth_plat,
  347. },
  348. .num_resources = ARRAY_SIZE(sh_eth_resources),
  349. .resource = sh_eth_resources,
  350. .archdata = {
  351. .hwblk_id = HWBLK_ETHER,
  352. },
  353. };
  354. static struct r8a66597_platdata sh7724_usb0_host_data = {
  355. .on_chip = 1,
  356. };
  357. static struct resource sh7724_usb0_host_resources[] = {
  358. [0] = {
  359. .start = 0xa4d80000,
  360. .end = 0xa4d80124 - 1,
  361. .flags = IORESOURCE_MEM,
  362. },
  363. [1] = {
  364. .start = 65,
  365. .end = 65,
  366. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  367. },
  368. };
  369. static struct platform_device sh7724_usb0_host_device = {
  370. .name = "r8a66597_hcd",
  371. .id = 0,
  372. .dev = {
  373. .dma_mask = NULL, /* not use dma */
  374. .coherent_dma_mask = 0xffffffff,
  375. .platform_data = &sh7724_usb0_host_data,
  376. },
  377. .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
  378. .resource = sh7724_usb0_host_resources,
  379. .archdata = {
  380. .hwblk_id = HWBLK_USB0,
  381. },
  382. };
  383. static struct r8a66597_platdata sh7724_usb1_gadget_data = {
  384. .on_chip = 1,
  385. };
  386. static struct resource sh7724_usb1_gadget_resources[] = {
  387. [0] = {
  388. .start = 0xa4d90000,
  389. .end = 0xa4d90123,
  390. .flags = IORESOURCE_MEM,
  391. },
  392. [1] = {
  393. .start = 66,
  394. .end = 66,
  395. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  396. },
  397. };
  398. static struct platform_device sh7724_usb1_gadget_device = {
  399. .name = "r8a66597_udc",
  400. .id = 1, /* USB1 */
  401. .dev = {
  402. .dma_mask = NULL, /* not use dma */
  403. .coherent_dma_mask = 0xffffffff,
  404. .platform_data = &sh7724_usb1_gadget_data,
  405. },
  406. .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
  407. .resource = sh7724_usb1_gadget_resources,
  408. };
  409. static struct platform_device *ms7724se_devices[] __initdata = {
  410. &heartbeat_device,
  411. &smc91x_eth_device,
  412. &lcdc_device,
  413. &nor_flash_device,
  414. &ceu0_device,
  415. &ceu1_device,
  416. &keysc_device,
  417. &sh_eth_device,
  418. &sh7724_usb0_host_device,
  419. &sh7724_usb1_gadget_device,
  420. &fsi_device,
  421. };
  422. #define EEPROM_OP 0xBA206000
  423. #define EEPROM_ADR 0xBA206004
  424. #define EEPROM_DATA 0xBA20600C
  425. #define EEPROM_STAT 0xBA206010
  426. #define EEPROM_STRT 0xBA206014
  427. static int __init sh_eth_is_eeprom_ready(void)
  428. {
  429. int t = 10000;
  430. while (t--) {
  431. if (!ctrl_inw(EEPROM_STAT))
  432. return 1;
  433. cpu_relax();
  434. }
  435. printk(KERN_ERR "ms7724se can not access to eeprom\n");
  436. return 0;
  437. }
  438. static void __init sh_eth_init(void)
  439. {
  440. int i;
  441. u16 mac[3];
  442. /* check EEPROM status */
  443. if (!sh_eth_is_eeprom_ready())
  444. return;
  445. /* read MAC addr from EEPROM */
  446. for (i = 0 ; i < 3 ; i++) {
  447. ctrl_outw(0x0, EEPROM_OP); /* read */
  448. ctrl_outw(i*2, EEPROM_ADR);
  449. ctrl_outw(0x1, EEPROM_STRT);
  450. if (!sh_eth_is_eeprom_ready())
  451. return;
  452. mac[i] = ctrl_inw(EEPROM_DATA);
  453. mac[i] = ((mac[i] & 0xFF) << 8) | (mac[i] >> 8); /* swap */
  454. }
  455. /* reset sh-eth */
  456. ctrl_outl(0x1, SH_ETH_ADDR + 0x0);
  457. /* set MAC addr */
  458. ctrl_outl(((mac[0] << 16) | (mac[1])), SH_ETH_MAHR);
  459. ctrl_outl((mac[2]), SH_ETH_MALR);
  460. }
  461. #define SW4140 0xBA201000
  462. #define FPGA_OUT 0xBA200400
  463. #define PORT_HIZA 0xA4050158
  464. #define PORT_MSELCRB 0xA4050182
  465. #define SW41_A 0x0100
  466. #define SW41_B 0x0200
  467. #define SW41_C 0x0400
  468. #define SW41_D 0x0800
  469. #define SW41_E 0x1000
  470. #define SW41_F 0x2000
  471. #define SW41_G 0x4000
  472. #define SW41_H 0x8000
  473. static int __init devices_setup(void)
  474. {
  475. u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
  476. struct clk *fsia_clk;
  477. /* Reset Release */
  478. ctrl_outw(ctrl_inw(FPGA_OUT) &
  479. ~((1 << 1) | /* LAN */
  480. (1 << 6) | /* VIDEO DAC */
  481. (1 << 7) | /* AK4643 */
  482. (1 << 12) | /* USB0 */
  483. (1 << 14)), /* RMII */
  484. FPGA_OUT);
  485. /* turn on USB clocks, use external clock */
  486. ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
  487. #ifdef CONFIG_PM
  488. /* Let LED9 show STATUS2 */
  489. gpio_request(GPIO_FN_STATUS2, NULL);
  490. /* Lit LED10 show STATUS0 */
  491. gpio_request(GPIO_FN_STATUS0, NULL);
  492. /* Lit LED11 show PDSTATUS */
  493. gpio_request(GPIO_FN_PDSTATUS, NULL);
  494. #else
  495. /* Lit LED9 */
  496. gpio_request(GPIO_PTJ6, NULL);
  497. gpio_direction_output(GPIO_PTJ6, 1);
  498. gpio_export(GPIO_PTJ6, 0);
  499. /* Lit LED10 */
  500. gpio_request(GPIO_PTJ5, NULL);
  501. gpio_direction_output(GPIO_PTJ5, 1);
  502. gpio_export(GPIO_PTJ5, 0);
  503. /* Lit LED11 */
  504. gpio_request(GPIO_PTJ7, NULL);
  505. gpio_direction_output(GPIO_PTJ7, 1);
  506. gpio_export(GPIO_PTJ7, 0);
  507. #endif
  508. /* enable USB0 port */
  509. ctrl_outw(0x0600, 0xa40501d4);
  510. /* enable USB1 port */
  511. ctrl_outw(0x0600, 0xa4050192);
  512. /* enable IRQ 0,1,2 */
  513. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  514. gpio_request(GPIO_FN_INTC_IRQ1, NULL);
  515. gpio_request(GPIO_FN_INTC_IRQ2, NULL);
  516. /* enable SCIFA3 */
  517. gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
  518. gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
  519. gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
  520. gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
  521. gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
  522. /* enable LCDC */
  523. gpio_request(GPIO_FN_LCDD23, NULL);
  524. gpio_request(GPIO_FN_LCDD22, NULL);
  525. gpio_request(GPIO_FN_LCDD21, NULL);
  526. gpio_request(GPIO_FN_LCDD20, NULL);
  527. gpio_request(GPIO_FN_LCDD19, NULL);
  528. gpio_request(GPIO_FN_LCDD18, NULL);
  529. gpio_request(GPIO_FN_LCDD17, NULL);
  530. gpio_request(GPIO_FN_LCDD16, NULL);
  531. gpio_request(GPIO_FN_LCDD15, NULL);
  532. gpio_request(GPIO_FN_LCDD14, NULL);
  533. gpio_request(GPIO_FN_LCDD13, NULL);
  534. gpio_request(GPIO_FN_LCDD12, NULL);
  535. gpio_request(GPIO_FN_LCDD11, NULL);
  536. gpio_request(GPIO_FN_LCDD10, NULL);
  537. gpio_request(GPIO_FN_LCDD9, NULL);
  538. gpio_request(GPIO_FN_LCDD8, NULL);
  539. gpio_request(GPIO_FN_LCDD7, NULL);
  540. gpio_request(GPIO_FN_LCDD6, NULL);
  541. gpio_request(GPIO_FN_LCDD5, NULL);
  542. gpio_request(GPIO_FN_LCDD4, NULL);
  543. gpio_request(GPIO_FN_LCDD3, NULL);
  544. gpio_request(GPIO_FN_LCDD2, NULL);
  545. gpio_request(GPIO_FN_LCDD1, NULL);
  546. gpio_request(GPIO_FN_LCDD0, NULL);
  547. gpio_request(GPIO_FN_LCDDISP, NULL);
  548. gpio_request(GPIO_FN_LCDHSYN, NULL);
  549. gpio_request(GPIO_FN_LCDDCK, NULL);
  550. gpio_request(GPIO_FN_LCDVSYN, NULL);
  551. gpio_request(GPIO_FN_LCDDON, NULL);
  552. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  553. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  554. gpio_request(GPIO_FN_LCDRD, NULL);
  555. gpio_request(GPIO_FN_LCDLCLK, NULL);
  556. ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  557. /* enable CEU0 */
  558. gpio_request(GPIO_FN_VIO0_D15, NULL);
  559. gpio_request(GPIO_FN_VIO0_D14, NULL);
  560. gpio_request(GPIO_FN_VIO0_D13, NULL);
  561. gpio_request(GPIO_FN_VIO0_D12, NULL);
  562. gpio_request(GPIO_FN_VIO0_D11, NULL);
  563. gpio_request(GPIO_FN_VIO0_D10, NULL);
  564. gpio_request(GPIO_FN_VIO0_D9, NULL);
  565. gpio_request(GPIO_FN_VIO0_D8, NULL);
  566. gpio_request(GPIO_FN_VIO0_D7, NULL);
  567. gpio_request(GPIO_FN_VIO0_D6, NULL);
  568. gpio_request(GPIO_FN_VIO0_D5, NULL);
  569. gpio_request(GPIO_FN_VIO0_D4, NULL);
  570. gpio_request(GPIO_FN_VIO0_D3, NULL);
  571. gpio_request(GPIO_FN_VIO0_D2, NULL);
  572. gpio_request(GPIO_FN_VIO0_D1, NULL);
  573. gpio_request(GPIO_FN_VIO0_D0, NULL);
  574. gpio_request(GPIO_FN_VIO0_VD, NULL);
  575. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  576. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  577. gpio_request(GPIO_FN_VIO0_HD, NULL);
  578. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  579. /* enable CEU1 */
  580. gpio_request(GPIO_FN_VIO1_D7, NULL);
  581. gpio_request(GPIO_FN_VIO1_D6, NULL);
  582. gpio_request(GPIO_FN_VIO1_D5, NULL);
  583. gpio_request(GPIO_FN_VIO1_D4, NULL);
  584. gpio_request(GPIO_FN_VIO1_D3, NULL);
  585. gpio_request(GPIO_FN_VIO1_D2, NULL);
  586. gpio_request(GPIO_FN_VIO1_D1, NULL);
  587. gpio_request(GPIO_FN_VIO1_D0, NULL);
  588. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  589. gpio_request(GPIO_FN_VIO1_HD, NULL);
  590. gpio_request(GPIO_FN_VIO1_VD, NULL);
  591. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  592. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  593. /* KEYSC */
  594. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  595. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  596. gpio_request(GPIO_FN_KEYIN4, NULL);
  597. gpio_request(GPIO_FN_KEYIN3, NULL);
  598. gpio_request(GPIO_FN_KEYIN2, NULL);
  599. gpio_request(GPIO_FN_KEYIN1, NULL);
  600. gpio_request(GPIO_FN_KEYIN0, NULL);
  601. gpio_request(GPIO_FN_KEYOUT3, NULL);
  602. gpio_request(GPIO_FN_KEYOUT2, NULL);
  603. gpio_request(GPIO_FN_KEYOUT1, NULL);
  604. gpio_request(GPIO_FN_KEYOUT0, NULL);
  605. /* enable FSI */
  606. gpio_request(GPIO_FN_FSIMCKB, NULL);
  607. gpio_request(GPIO_FN_FSIMCKA, NULL);
  608. gpio_request(GPIO_FN_FSIOASD, NULL);
  609. gpio_request(GPIO_FN_FSIIABCK, NULL);
  610. gpio_request(GPIO_FN_FSIIALRCK, NULL);
  611. gpio_request(GPIO_FN_FSIOABCK, NULL);
  612. gpio_request(GPIO_FN_FSIOALRCK, NULL);
  613. gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
  614. gpio_request(GPIO_FN_FSIIBSD, NULL);
  615. gpio_request(GPIO_FN_FSIOBSD, NULL);
  616. gpio_request(GPIO_FN_FSIIBBCK, NULL);
  617. gpio_request(GPIO_FN_FSIIBLRCK, NULL);
  618. gpio_request(GPIO_FN_FSIOBBCK, NULL);
  619. gpio_request(GPIO_FN_FSIOBLRCK, NULL);
  620. gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
  621. gpio_request(GPIO_FN_FSIIASD, NULL);
  622. /* change parent of FSI A */
  623. fsia_clk = clk_get(NULL, "fsia_clk");
  624. clk_register(&fsimcka_clk);
  625. clk_set_parent(fsia_clk, &fsimcka_clk);
  626. clk_set_rate(fsia_clk, 11000);
  627. clk_set_rate(&fsimcka_clk, 11000);
  628. clk_put(fsia_clk);
  629. /*
  630. * enable SH-Eth
  631. *
  632. * please remove J33 pin from your board !!
  633. *
  634. * ms7724 board should not use GPIO_FN_LNKSTA pin
  635. * So, This time PTX5 is set to input pin
  636. */
  637. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  638. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  639. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  640. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  641. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  642. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  643. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  644. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  645. gpio_request(GPIO_FN_MDIO, NULL);
  646. gpio_request(GPIO_FN_MDC, NULL);
  647. gpio_request(GPIO_PTX5, NULL);
  648. gpio_direction_input(GPIO_PTX5);
  649. sh_eth_init();
  650. if (sw & SW41_B) {
  651. /* 720p */
  652. lcdc_info.ch[0].lcd_cfg.xres = 1280;
  653. lcdc_info.ch[0].lcd_cfg.yres = 720;
  654. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  655. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  656. lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
  657. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  658. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  659. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  660. } else {
  661. /* VGA */
  662. lcdc_info.ch[0].lcd_cfg.xres = 640;
  663. lcdc_info.ch[0].lcd_cfg.yres = 480;
  664. lcdc_info.ch[0].lcd_cfg.left_margin = 105;
  665. lcdc_info.ch[0].lcd_cfg.right_margin = 50;
  666. lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
  667. lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
  668. lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
  669. lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
  670. }
  671. if (sw & SW41_A) {
  672. /* Digital monitor */
  673. lcdc_info.ch[0].interface_type = RGB18;
  674. lcdc_info.ch[0].flags = 0;
  675. } else {
  676. /* Analog monitor */
  677. lcdc_info.ch[0].interface_type = RGB24;
  678. lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
  679. }
  680. return platform_add_devices(ms7724se_devices,
  681. ARRAY_SIZE(ms7724se_devices));
  682. }
  683. device_initcall(devices_setup);
  684. static struct sh_machine_vector mv_ms7724se __initmv = {
  685. .mv_name = "ms7724se",
  686. .mv_init_irq = init_se7724_IRQ,
  687. .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
  688. };