board-ap325rxa.c 14 KB

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  1. /*
  2. * Renesas - AP-325RXA
  3. * (Compatible with Algo System ., LTD. - AP-320A)
  4. *
  5. * Copyright (C) 2008 Renesas Solutions Corp.
  6. * Author : Yusuke Goda <goda.yuske@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/mtd/sh_flctl.h>
  18. #include <linux/delay.h>
  19. #include <linux/i2c.h>
  20. #include <linux/smsc911x.h>
  21. #include <linux/gpio.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/spi_gpio.h>
  24. #include <media/ov772x.h>
  25. #include <media/soc_camera.h>
  26. #include <media/soc_camera_platform.h>
  27. #include <media/sh_mobile_ceu.h>
  28. #include <video/sh_mobile_lcdc.h>
  29. #include <asm/io.h>
  30. #include <asm/clock.h>
  31. #include <cpu/sh7723.h>
  32. static struct smsc911x_platform_config smsc911x_config = {
  33. .phy_interface = PHY_INTERFACE_MODE_MII,
  34. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  35. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  36. .flags = SMSC911X_USE_32BIT,
  37. };
  38. static struct resource smsc9118_resources[] = {
  39. [0] = {
  40. .start = 0xb6080000,
  41. .end = 0xb60fffff,
  42. .flags = IORESOURCE_MEM,
  43. },
  44. [1] = {
  45. .start = 35,
  46. .end = 35,
  47. .flags = IORESOURCE_IRQ,
  48. }
  49. };
  50. static struct platform_device smsc9118_device = {
  51. .name = "smsc911x",
  52. .id = -1,
  53. .num_resources = ARRAY_SIZE(smsc9118_resources),
  54. .resource = smsc9118_resources,
  55. .dev = {
  56. .platform_data = &smsc911x_config,
  57. },
  58. };
  59. /*
  60. * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
  61. * If this area erased, this board can not boot.
  62. */
  63. static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
  64. {
  65. .name = "uboot",
  66. .offset = 0,
  67. .size = (1 * 1024 * 1024),
  68. .mask_flags = MTD_WRITEABLE, /* Read-only */
  69. }, {
  70. .name = "kernel",
  71. .offset = MTDPART_OFS_APPEND,
  72. .size = (2 * 1024 * 1024),
  73. }, {
  74. .name = "free-area0",
  75. .offset = MTDPART_OFS_APPEND,
  76. .size = ((7 * 1024 * 1024) + (512 * 1024)),
  77. }, {
  78. .name = "CPLD-Data",
  79. .offset = MTDPART_OFS_APPEND,
  80. .mask_flags = MTD_WRITEABLE, /* Read-only */
  81. .size = (1024 * 128 * 2),
  82. }, {
  83. .name = "free-area1",
  84. .offset = MTDPART_OFS_APPEND,
  85. .size = MTDPART_SIZ_FULL,
  86. },
  87. };
  88. static struct physmap_flash_data ap325rxa_nor_flash_data = {
  89. .width = 2,
  90. .parts = ap325rxa_nor_flash_partitions,
  91. .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
  92. };
  93. static struct resource ap325rxa_nor_flash_resources[] = {
  94. [0] = {
  95. .name = "NOR Flash",
  96. .start = 0x00000000,
  97. .end = 0x00ffffff,
  98. .flags = IORESOURCE_MEM,
  99. }
  100. };
  101. static struct platform_device ap325rxa_nor_flash_device = {
  102. .name = "physmap-flash",
  103. .resource = ap325rxa_nor_flash_resources,
  104. .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
  105. .dev = {
  106. .platform_data = &ap325rxa_nor_flash_data,
  107. },
  108. };
  109. static struct mtd_partition nand_partition_info[] = {
  110. {
  111. .name = "nand_data",
  112. .offset = 0,
  113. .size = MTDPART_SIZ_FULL,
  114. },
  115. };
  116. static struct resource nand_flash_resources[] = {
  117. [0] = {
  118. .start = 0xa4530000,
  119. .end = 0xa45300ff,
  120. .flags = IORESOURCE_MEM,
  121. }
  122. };
  123. static struct sh_flctl_platform_data nand_flash_data = {
  124. .parts = nand_partition_info,
  125. .nr_parts = ARRAY_SIZE(nand_partition_info),
  126. .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
  127. .has_hwecc = 1,
  128. };
  129. static struct platform_device nand_flash_device = {
  130. .name = "sh_flctl",
  131. .resource = nand_flash_resources,
  132. .num_resources = ARRAY_SIZE(nand_flash_resources),
  133. .dev = {
  134. .platform_data = &nand_flash_data,
  135. },
  136. };
  137. #define FPGA_LCDREG 0xB4100180
  138. #define FPGA_BKLREG 0xB4100212
  139. #define FPGA_LCDREG_VAL 0x0018
  140. #define PORT_MSELCRB 0xA4050182
  141. #define PORT_HIZCRC 0xA405015C
  142. #define PORT_DRVCRA 0xA405018A
  143. #define PORT_DRVCRB 0xA405018C
  144. static void ap320_wvga_power_on(void *board_data)
  145. {
  146. msleep(100);
  147. /* ASD AP-320/325 LCD ON */
  148. ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
  149. /* backlight */
  150. gpio_set_value(GPIO_PTS3, 0);
  151. ctrl_outw(0x100, FPGA_BKLREG);
  152. }
  153. static void ap320_wvga_power_off(void *board_data)
  154. {
  155. /* backlight */
  156. ctrl_outw(0, FPGA_BKLREG);
  157. gpio_set_value(GPIO_PTS3, 1);
  158. /* ASD AP-320/325 LCD OFF */
  159. ctrl_outw(0, FPGA_LCDREG);
  160. }
  161. static struct sh_mobile_lcdc_info lcdc_info = {
  162. .clock_source = LCDC_CLK_EXTERNAL,
  163. .ch[0] = {
  164. .chan = LCDC_CHAN_MAINLCD,
  165. .bpp = 16,
  166. .interface_type = RGB18,
  167. .clock_divider = 1,
  168. .lcd_cfg = {
  169. .name = "LB070WV1",
  170. .xres = 800,
  171. .yres = 480,
  172. .left_margin = 32,
  173. .right_margin = 160,
  174. .hsync_len = 8,
  175. .upper_margin = 63,
  176. .lower_margin = 80,
  177. .vsync_len = 1,
  178. .sync = 0, /* hsync and vsync are active low */
  179. },
  180. .lcd_size_cfg = { /* 7.0 inch */
  181. .width = 152,
  182. .height = 91,
  183. },
  184. .board_cfg = {
  185. .display_on = ap320_wvga_power_on,
  186. .display_off = ap320_wvga_power_off,
  187. },
  188. }
  189. };
  190. static struct resource lcdc_resources[] = {
  191. [0] = {
  192. .name = "LCDC",
  193. .start = 0xfe940000, /* P4-only space */
  194. .end = 0xfe942fff,
  195. .flags = IORESOURCE_MEM,
  196. },
  197. [1] = {
  198. .start = 28,
  199. .flags = IORESOURCE_IRQ,
  200. },
  201. };
  202. static struct platform_device lcdc_device = {
  203. .name = "sh_mobile_lcdc_fb",
  204. .num_resources = ARRAY_SIZE(lcdc_resources),
  205. .resource = lcdc_resources,
  206. .dev = {
  207. .platform_data = &lcdc_info,
  208. },
  209. .archdata = {
  210. .hwblk_id = HWBLK_LCDC,
  211. },
  212. };
  213. static void camera_power(int val)
  214. {
  215. gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
  216. mdelay(10);
  217. }
  218. #ifdef CONFIG_I2C
  219. /* support for the old ncm03j camera */
  220. static unsigned char camera_ncm03j_magic[] =
  221. {
  222. 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
  223. 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
  224. 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
  225. 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
  226. 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
  227. 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
  228. 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
  229. 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
  230. 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
  231. 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
  232. 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
  233. 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
  234. 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
  235. 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
  236. 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
  237. 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
  238. };
  239. static int camera_probe(void)
  240. {
  241. struct i2c_adapter *a = i2c_get_adapter(0);
  242. struct i2c_msg msg;
  243. int ret;
  244. if (!a)
  245. return -ENODEV;
  246. camera_power(1);
  247. msg.addr = 0x6e;
  248. msg.buf = camera_ncm03j_magic;
  249. msg.len = 2;
  250. msg.flags = 0;
  251. ret = i2c_transfer(a, &msg, 1);
  252. camera_power(0);
  253. return ret;
  254. }
  255. static int camera_set_capture(struct soc_camera_platform_info *info,
  256. int enable)
  257. {
  258. struct i2c_adapter *a = i2c_get_adapter(0);
  259. struct i2c_msg msg;
  260. int ret = 0;
  261. int i;
  262. camera_power(0);
  263. if (!enable)
  264. return 0; /* no disable for now */
  265. camera_power(1);
  266. for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
  267. u_int8_t buf[8];
  268. msg.addr = 0x6e;
  269. msg.buf = buf;
  270. msg.len = 2;
  271. msg.flags = 0;
  272. buf[0] = camera_ncm03j_magic[i];
  273. buf[1] = camera_ncm03j_magic[i + 1];
  274. ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
  275. }
  276. return ret;
  277. }
  278. static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev);
  279. static void ap325rxa_camera_del(struct soc_camera_link *icl);
  280. static struct soc_camera_platform_info camera_info = {
  281. .format_name = "UYVY",
  282. .format_depth = 16,
  283. .format = {
  284. .pixelformat = V4L2_PIX_FMT_UYVY,
  285. .colorspace = V4L2_COLORSPACE_SMPTE170M,
  286. .width = 640,
  287. .height = 480,
  288. },
  289. .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
  290. SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
  291. .set_capture = camera_set_capture,
  292. .link = {
  293. .bus_id = 0,
  294. .add_device = ap325rxa_camera_add,
  295. .del_device = ap325rxa_camera_del,
  296. .module_name = "soc_camera_platform",
  297. },
  298. };
  299. static void dummy_release(struct device *dev)
  300. {
  301. }
  302. static struct platform_device camera_device = {
  303. .name = "soc_camera_platform",
  304. .dev = {
  305. .platform_data = &camera_info,
  306. .release = dummy_release,
  307. },
  308. };
  309. static int ap325rxa_camera_add(struct soc_camera_link *icl,
  310. struct device *dev)
  311. {
  312. if (icl != &camera_info.link || camera_probe() <= 0)
  313. return -ENODEV;
  314. camera_info.dev = dev;
  315. return platform_device_register(&camera_device);
  316. }
  317. static void ap325rxa_camera_del(struct soc_camera_link *icl)
  318. {
  319. if (icl != &camera_info.link)
  320. return;
  321. platform_device_unregister(&camera_device);
  322. memset(&camera_device.dev.kobj, 0,
  323. sizeof(camera_device.dev.kobj));
  324. }
  325. #endif /* CONFIG_I2C */
  326. static int ov7725_power(struct device *dev, int mode)
  327. {
  328. camera_power(0);
  329. if (mode)
  330. camera_power(1);
  331. return 0;
  332. }
  333. static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
  334. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  335. };
  336. static struct resource ceu_resources[] = {
  337. [0] = {
  338. .name = "CEU",
  339. .start = 0xfe910000,
  340. .end = 0xfe91009f,
  341. .flags = IORESOURCE_MEM,
  342. },
  343. [1] = {
  344. .start = 52,
  345. .flags = IORESOURCE_IRQ,
  346. },
  347. [2] = {
  348. /* place holder for contiguous memory */
  349. },
  350. };
  351. static struct platform_device ceu_device = {
  352. .name = "sh_mobile_ceu",
  353. .id = 0, /* "ceu0" clock */
  354. .num_resources = ARRAY_SIZE(ceu_resources),
  355. .resource = ceu_resources,
  356. .dev = {
  357. .platform_data = &sh_mobile_ceu_info,
  358. },
  359. .archdata = {
  360. .hwblk_id = HWBLK_CEU,
  361. },
  362. };
  363. struct spi_gpio_platform_data sdcard_cn3_platform_data = {
  364. .sck = GPIO_PTD0,
  365. .mosi = GPIO_PTD1,
  366. .miso = GPIO_PTD2,
  367. .num_chipselect = 1,
  368. };
  369. static struct platform_device sdcard_cn3_device = {
  370. .name = "spi_gpio",
  371. .dev = {
  372. .platform_data = &sdcard_cn3_platform_data,
  373. },
  374. };
  375. static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
  376. {
  377. I2C_BOARD_INFO("pcf8563", 0x51),
  378. },
  379. };
  380. static struct i2c_board_info ap325rxa_i2c_camera[] = {
  381. {
  382. I2C_BOARD_INFO("ov772x", 0x21),
  383. },
  384. };
  385. static struct ov772x_camera_info ov7725_info = {
  386. .buswidth = SOCAM_DATAWIDTH_8,
  387. .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
  388. .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
  389. .link = {
  390. .bus_id = 0,
  391. .power = ov7725_power,
  392. .board_info = &ap325rxa_i2c_camera[0],
  393. .i2c_adapter_id = 0,
  394. .module_name = "ov772x",
  395. },
  396. };
  397. static struct platform_device ap325rxa_camera[] = {
  398. {
  399. .name = "soc-camera-pdrv",
  400. .id = 0,
  401. .dev = {
  402. .platform_data = &ov7725_info.link,
  403. },
  404. }, {
  405. .name = "soc-camera-pdrv",
  406. .id = 1,
  407. .dev = {
  408. .platform_data = &camera_info.link,
  409. },
  410. },
  411. };
  412. static struct platform_device *ap325rxa_devices[] __initdata = {
  413. &smsc9118_device,
  414. &ap325rxa_nor_flash_device,
  415. &lcdc_device,
  416. &ceu_device,
  417. &nand_flash_device,
  418. &sdcard_cn3_device,
  419. &ap325rxa_camera[0],
  420. &ap325rxa_camera[1],
  421. };
  422. static struct spi_board_info ap325rxa_spi_devices[] = {
  423. {
  424. .modalias = "mmc_spi",
  425. .max_speed_hz = 5000000,
  426. .chip_select = 0,
  427. .controller_data = (void *) GPIO_PTD5,
  428. },
  429. };
  430. static int __init ap325rxa_devices_setup(void)
  431. {
  432. /* LD3 and LD4 LEDs */
  433. gpio_request(GPIO_PTX5, NULL); /* RUN */
  434. gpio_direction_output(GPIO_PTX5, 1);
  435. gpio_export(GPIO_PTX5, 0);
  436. gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
  437. gpio_direction_output(GPIO_PTX4, 0);
  438. gpio_export(GPIO_PTX4, 0);
  439. /* SW1 input */
  440. gpio_request(GPIO_PTF7, NULL); /* MODE */
  441. gpio_direction_input(GPIO_PTF7);
  442. gpio_export(GPIO_PTF7, 0);
  443. /* LCDC */
  444. gpio_request(GPIO_FN_LCDD15, NULL);
  445. gpio_request(GPIO_FN_LCDD14, NULL);
  446. gpio_request(GPIO_FN_LCDD13, NULL);
  447. gpio_request(GPIO_FN_LCDD12, NULL);
  448. gpio_request(GPIO_FN_LCDD11, NULL);
  449. gpio_request(GPIO_FN_LCDD10, NULL);
  450. gpio_request(GPIO_FN_LCDD9, NULL);
  451. gpio_request(GPIO_FN_LCDD8, NULL);
  452. gpio_request(GPIO_FN_LCDD7, NULL);
  453. gpio_request(GPIO_FN_LCDD6, NULL);
  454. gpio_request(GPIO_FN_LCDD5, NULL);
  455. gpio_request(GPIO_FN_LCDD4, NULL);
  456. gpio_request(GPIO_FN_LCDD3, NULL);
  457. gpio_request(GPIO_FN_LCDD2, NULL);
  458. gpio_request(GPIO_FN_LCDD1, NULL);
  459. gpio_request(GPIO_FN_LCDD0, NULL);
  460. gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
  461. gpio_request(GPIO_FN_LCDDCK, NULL);
  462. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  463. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  464. gpio_request(GPIO_FN_LCDVSYN, NULL);
  465. gpio_request(GPIO_FN_LCDHSYN, NULL);
  466. gpio_request(GPIO_FN_LCDDISP, NULL);
  467. gpio_request(GPIO_FN_LCDDON, NULL);
  468. /* LCD backlight */
  469. gpio_request(GPIO_PTS3, NULL);
  470. gpio_direction_output(GPIO_PTS3, 1);
  471. /* CEU */
  472. gpio_request(GPIO_FN_VIO_CLK2, NULL);
  473. gpio_request(GPIO_FN_VIO_VD2, NULL);
  474. gpio_request(GPIO_FN_VIO_HD2, NULL);
  475. gpio_request(GPIO_FN_VIO_FLD, NULL);
  476. gpio_request(GPIO_FN_VIO_CKO, NULL);
  477. gpio_request(GPIO_FN_VIO_D15, NULL);
  478. gpio_request(GPIO_FN_VIO_D14, NULL);
  479. gpio_request(GPIO_FN_VIO_D13, NULL);
  480. gpio_request(GPIO_FN_VIO_D12, NULL);
  481. gpio_request(GPIO_FN_VIO_D11, NULL);
  482. gpio_request(GPIO_FN_VIO_D10, NULL);
  483. gpio_request(GPIO_FN_VIO_D9, NULL);
  484. gpio_request(GPIO_FN_VIO_D8, NULL);
  485. gpio_request(GPIO_PTZ7, NULL);
  486. gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
  487. gpio_request(GPIO_PTZ6, NULL);
  488. gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
  489. gpio_request(GPIO_PTZ5, NULL);
  490. gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
  491. gpio_request(GPIO_PTZ4, NULL);
  492. gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
  493. ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
  494. /* FLCTL */
  495. gpio_request(GPIO_FN_FCE, NULL);
  496. gpio_request(GPIO_FN_NAF7, NULL);
  497. gpio_request(GPIO_FN_NAF6, NULL);
  498. gpio_request(GPIO_FN_NAF5, NULL);
  499. gpio_request(GPIO_FN_NAF4, NULL);
  500. gpio_request(GPIO_FN_NAF3, NULL);
  501. gpio_request(GPIO_FN_NAF2, NULL);
  502. gpio_request(GPIO_FN_NAF1, NULL);
  503. gpio_request(GPIO_FN_NAF0, NULL);
  504. gpio_request(GPIO_FN_FCDE, NULL);
  505. gpio_request(GPIO_FN_FOE, NULL);
  506. gpio_request(GPIO_FN_FSC, NULL);
  507. gpio_request(GPIO_FN_FWE, NULL);
  508. gpio_request(GPIO_FN_FRB, NULL);
  509. ctrl_outw(0, PORT_HIZCRC);
  510. ctrl_outw(0xFFFF, PORT_DRVCRA);
  511. ctrl_outw(0xFFFF, PORT_DRVCRB);
  512. platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
  513. i2c_register_board_info(0, ap325rxa_i2c_devices,
  514. ARRAY_SIZE(ap325rxa_i2c_devices));
  515. spi_register_board_info(ap325rxa_spi_devices,
  516. ARRAY_SIZE(ap325rxa_spi_devices));
  517. return platform_add_devices(ap325rxa_devices,
  518. ARRAY_SIZE(ap325rxa_devices));
  519. }
  520. arch_initcall(ap325rxa_devices_setup);
  521. /* Return the board specific boot mode pin configuration */
  522. static int ap325rxa_mode_pins(void)
  523. {
  524. /* MD0=0, MD1=0, MD2=0: Clock Mode 0
  525. * MD3=0: 16-bit Area0 Bus Width
  526. * MD5=1: Little Endian
  527. * TSTMD=1, MD8=1: Test Mode Disabled
  528. */
  529. return MODE_PIN5 | MODE_PIN8;
  530. }
  531. static struct sh_machine_vector mv_ap325rxa __initmv = {
  532. .mv_name = "AP-325RXA",
  533. .mv_mode_pins = ap325rxa_mode_pins,
  534. };