lite5200_pm.c 6.2 KB

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  1. #include <linux/init.h>
  2. #include <linux/suspend.h>
  3. #include <asm/io.h>
  4. #include <asm/time.h>
  5. #include <asm/mpc52xx.h>
  6. /* defined in lite5200_sleep.S and only used here */
  7. extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar);
  8. static struct mpc52xx_cdm __iomem *cdm;
  9. static struct mpc52xx_intr __iomem *pic;
  10. static struct mpc52xx_sdma __iomem *bes;
  11. static struct mpc52xx_xlb __iomem *xlb;
  12. static struct mpc52xx_gpio __iomem *gps;
  13. static struct mpc52xx_gpio_wkup __iomem *gpw;
  14. static void __iomem *pci;
  15. static void __iomem *sram;
  16. static const int sram_size = 0x4000; /* 16 kBytes */
  17. static void __iomem *mbar;
  18. static suspend_state_t lite5200_pm_target_state;
  19. static int lite5200_pm_valid(suspend_state_t state)
  20. {
  21. switch (state) {
  22. case PM_SUSPEND_STANDBY:
  23. case PM_SUSPEND_MEM:
  24. return 1;
  25. default:
  26. return 0;
  27. }
  28. }
  29. static int lite5200_pm_begin(suspend_state_t state)
  30. {
  31. if (lite5200_pm_valid(state)) {
  32. lite5200_pm_target_state = state;
  33. return 0;
  34. }
  35. return -EINVAL;
  36. }
  37. static int lite5200_pm_prepare(void)
  38. {
  39. struct device_node *np;
  40. const struct of_device_id immr_ids[] = {
  41. { .compatible = "fsl,mpc5200-immr", },
  42. { .compatible = "fsl,mpc5200b-immr", },
  43. { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
  44. { .type = "builtin", .compatible = "mpc5200", }, /* efika */
  45. {}
  46. };
  47. u64 regaddr64 = 0;
  48. const u32 *regaddr_p;
  49. /* deep sleep? let mpc52xx code handle that */
  50. if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
  51. return mpc52xx_pm_prepare();
  52. if (lite5200_pm_target_state != PM_SUSPEND_MEM)
  53. return -EINVAL;
  54. /* map registers */
  55. np = of_find_matching_node(NULL, immr_ids);
  56. regaddr_p = of_get_address(np, 0, NULL, NULL);
  57. if (regaddr_p)
  58. regaddr64 = of_translate_address(np, regaddr_p);
  59. of_node_put(np);
  60. mbar = ioremap((u32) regaddr64, 0xC000);
  61. if (!mbar) {
  62. printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
  63. return -ENOSYS;
  64. }
  65. cdm = mbar + 0x200;
  66. pic = mbar + 0x500;
  67. gps = mbar + 0xb00;
  68. gpw = mbar + 0xc00;
  69. pci = mbar + 0xd00;
  70. bes = mbar + 0x1200;
  71. xlb = mbar + 0x1f00;
  72. sram = mbar + 0x8000;
  73. return 0;
  74. }
  75. /* save and restore registers not bound to any real devices */
  76. static struct mpc52xx_cdm scdm;
  77. static struct mpc52xx_intr spic;
  78. static struct mpc52xx_sdma sbes;
  79. static struct mpc52xx_xlb sxlb;
  80. static struct mpc52xx_gpio sgps;
  81. static struct mpc52xx_gpio_wkup sgpw;
  82. static char spci[0x200];
  83. static void lite5200_save_regs(void)
  84. {
  85. _memcpy_fromio(&spic, pic, sizeof(*pic));
  86. _memcpy_fromio(&sbes, bes, sizeof(*bes));
  87. _memcpy_fromio(&scdm, cdm, sizeof(*cdm));
  88. _memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
  89. _memcpy_fromio(&sgps, gps, sizeof(*gps));
  90. _memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
  91. _memcpy_fromio(spci, pci, 0x200);
  92. _memcpy_fromio(saved_sram, sram, sram_size);
  93. }
  94. static void lite5200_restore_regs(void)
  95. {
  96. int i;
  97. _memcpy_toio(sram, saved_sram, sram_size);
  98. /* PCI Configuration */
  99. _memcpy_toio(pci, spci, 0x200);
  100. /*
  101. * GPIOs. Interrupt Master Enable has higher address then other
  102. * registers, so just memcpy is ok.
  103. */
  104. _memcpy_toio(gpw, &sgpw, sizeof(*gpw));
  105. _memcpy_toio(gps, &sgps, sizeof(*gps));
  106. /* XLB Arbitrer */
  107. out_be32(&xlb->snoop_window, sxlb.snoop_window);
  108. out_be32(&xlb->master_priority, sxlb.master_priority);
  109. out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable);
  110. /* enable */
  111. out_be32(&xlb->int_enable, sxlb.int_enable);
  112. out_be32(&xlb->config, sxlb.config);
  113. /* CDM - Clock Distribution Module */
  114. out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel);
  115. out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel);
  116. out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en);
  117. out_8(&cdm->fd_enable, scdm.fd_enable);
  118. out_be16(&cdm->fd_counters, scdm.fd_counters);
  119. out_be32(&cdm->clk_enables, scdm.clk_enables);
  120. out_8(&cdm->osc_disable, scdm.osc_disable);
  121. out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1);
  122. out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2);
  123. out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3);
  124. out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6);
  125. /* BESTCOMM */
  126. out_be32(&bes->taskBar, sbes.taskBar);
  127. out_be32(&bes->currentPointer, sbes.currentPointer);
  128. out_be32(&bes->endPointer, sbes.endPointer);
  129. out_be32(&bes->variablePointer, sbes.variablePointer);
  130. out_8(&bes->IntVect1, sbes.IntVect1);
  131. out_8(&bes->IntVect2, sbes.IntVect2);
  132. out_be16(&bes->PtdCntrl, sbes.PtdCntrl);
  133. for (i=0; i<32; i++)
  134. out_8(&bes->ipr[i], sbes.ipr[i]);
  135. out_be32(&bes->cReqSelect, sbes.cReqSelect);
  136. out_be32(&bes->task_size0, sbes.task_size0);
  137. out_be32(&bes->task_size1, sbes.task_size1);
  138. out_be32(&bes->MDEDebug, sbes.MDEDebug);
  139. out_be32(&bes->ADSDebug, sbes.ADSDebug);
  140. out_be32(&bes->Value1, sbes.Value1);
  141. out_be32(&bes->Value2, sbes.Value2);
  142. out_be32(&bes->Control, sbes.Control);
  143. out_be32(&bes->Status, sbes.Status);
  144. out_be32(&bes->PTDDebug, sbes.PTDDebug);
  145. /* restore tasks */
  146. for (i=0; i<16; i++)
  147. out_be16(&bes->tcr[i], sbes.tcr[i]);
  148. /* enable interrupts */
  149. out_be32(&bes->IntPend, sbes.IntPend);
  150. out_be32(&bes->IntMask, sbes.IntMask);
  151. /* PIC */
  152. out_be32(&pic->per_pri1, spic.per_pri1);
  153. out_be32(&pic->per_pri2, spic.per_pri2);
  154. out_be32(&pic->per_pri3, spic.per_pri3);
  155. out_be32(&pic->main_pri1, spic.main_pri1);
  156. out_be32(&pic->main_pri2, spic.main_pri2);
  157. out_be32(&pic->enc_status, spic.enc_status);
  158. /* unmask and enable interrupts */
  159. out_be32(&pic->per_mask, spic.per_mask);
  160. out_be32(&pic->main_mask, spic.main_mask);
  161. out_be32(&pic->ctrl, spic.ctrl);
  162. }
  163. static int lite5200_pm_enter(suspend_state_t state)
  164. {
  165. /* deep sleep? let mpc52xx code handle that */
  166. if (state == PM_SUSPEND_STANDBY) {
  167. return mpc52xx_pm_enter(state);
  168. }
  169. lite5200_save_regs();
  170. /* effectively save FP regs */
  171. enable_kernel_fp();
  172. lite5200_low_power(sram, mbar);
  173. lite5200_restore_regs();
  174. /* restart jiffies */
  175. wakeup_decrementer();
  176. iounmap(mbar);
  177. return 0;
  178. }
  179. static void lite5200_pm_finish(void)
  180. {
  181. /* deep sleep? let mpc52xx code handle that */
  182. if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
  183. mpc52xx_pm_finish();
  184. }
  185. static void lite5200_pm_end(void)
  186. {
  187. lite5200_pm_target_state = PM_SUSPEND_ON;
  188. }
  189. static struct platform_suspend_ops lite5200_pm_ops = {
  190. .valid = lite5200_pm_valid,
  191. .begin = lite5200_pm_begin,
  192. .prepare = lite5200_pm_prepare,
  193. .enter = lite5200_pm_enter,
  194. .finish = lite5200_pm_finish,
  195. .end = lite5200_pm_end,
  196. };
  197. int __init lite5200_pm_init(void)
  198. {
  199. suspend_set_ops(&lite5200_pm_ops);
  200. return 0;
  201. }