exception-64s.h 9.0 KB

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  1. #ifndef _ASM_POWERPC_EXCEPTION_H
  2. #define _ASM_POWERPC_EXCEPTION_H
  3. /*
  4. * Extracted from head_64.S
  5. *
  6. * PowerPC version
  7. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  8. *
  9. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  10. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  11. * Adapted for Power Macintosh by Paul Mackerras.
  12. * Low-level exception handlers and MMU support
  13. * rewritten by Paul Mackerras.
  14. * Copyright (C) 1996 Paul Mackerras.
  15. *
  16. * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  17. * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  18. *
  19. * This file contains the low-level support and setup for the
  20. * PowerPC-64 platform, including trap and interrupt dispatch.
  21. *
  22. * This program is free software; you can redistribute it and/or
  23. * modify it under the terms of the GNU General Public License
  24. * as published by the Free Software Foundation; either version
  25. * 2 of the License, or (at your option) any later version.
  26. */
  27. /*
  28. * The following macros define the code that appears as
  29. * the prologue to each of the exception handlers. They
  30. * are split into two parts to allow a single kernel binary
  31. * to be used for pSeries and iSeries.
  32. *
  33. * We make as much of the exception code common between native
  34. * exception handlers (including pSeries LPAR) and iSeries LPAR
  35. * implementations as possible.
  36. */
  37. #define EX_R9 0
  38. #define EX_R10 8
  39. #define EX_R11 16
  40. #define EX_R12 24
  41. #define EX_R13 32
  42. #define EX_SRR0 40
  43. #define EX_DAR 48
  44. #define EX_DSISR 56
  45. #define EX_CCR 60
  46. #define EX_R3 64
  47. #define EX_LR 72
  48. /*
  49. * We're short on space and time in the exception prolog, so we can't
  50. * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
  51. * low halfword of the address, but for Kdump we need the whole low
  52. * word.
  53. */
  54. #define LOAD_HANDLER(reg, label) \
  55. addi reg,reg,(label)-_stext; /* virt addr of handler ... */
  56. #define EXCEPTION_PROLOG_1(area) \
  57. mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
  58. std r9,area+EX_R9(r13); /* save r9 - r12 */ \
  59. std r10,area+EX_R10(r13); \
  60. std r11,area+EX_R11(r13); \
  61. std r12,area+EX_R12(r13); \
  62. mfspr r9,SPRN_SPRG_SCRATCH0; \
  63. std r9,area+EX_R13(r13); \
  64. mfcr r9
  65. #define EXCEPTION_PROLOG_PSERIES_1(label) \
  66. ld r12,PACAKBASE(r13); /* get high part of &label */ \
  67. ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
  68. mfspr r11,SPRN_SRR0; /* save SRR0 */ \
  69. LOAD_HANDLER(r12,label) \
  70. mtspr SPRN_SRR0,r12; \
  71. mfspr r12,SPRN_SRR1; /* and SRR1 */ \
  72. mtspr SPRN_SRR1,r10; \
  73. rfid; \
  74. b . /* prevent speculative execution */
  75. #define EXCEPTION_PROLOG_PSERIES(area, label) \
  76. EXCEPTION_PROLOG_1(area); \
  77. EXCEPTION_PROLOG_PSERIES_1(label);
  78. /*
  79. * The common exception prolog is used for all except a few exceptions
  80. * such as a segment miss on a kernel address. We have to be prepared
  81. * to take another exception from the point where we first touch the
  82. * kernel stack onwards.
  83. *
  84. * On entry r13 points to the paca, r9-r13 are saved in the paca,
  85. * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
  86. * SRR1, and relocation is on.
  87. */
  88. #define EXCEPTION_PROLOG_COMMON(n, area) \
  89. andi. r10,r12,MSR_PR; /* See if coming from user */ \
  90. mr r10,r1; /* Save r1 */ \
  91. subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
  92. beq- 1f; \
  93. ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
  94. 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
  95. bge- cr1,2f; /* abort if it is */ \
  96. b 3f; \
  97. 2: li r1,(n); /* will be reloaded later */ \
  98. sth r1,PACA_TRAP_SAVE(r13); \
  99. b bad_stack; \
  100. 3: std r9,_CCR(r1); /* save CR in stackframe */ \
  101. std r11,_NIP(r1); /* save SRR0 in stackframe */ \
  102. std r12,_MSR(r1); /* save SRR1 in stackframe */ \
  103. std r10,0(r1); /* make stack chain pointer */ \
  104. std r0,GPR0(r1); /* save r0 in stackframe */ \
  105. std r10,GPR1(r1); /* save r1 in stackframe */ \
  106. ACCOUNT_CPU_USER_ENTRY(r9, r10); \
  107. std r2,GPR2(r1); /* save r2 in stackframe */ \
  108. SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
  109. SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
  110. ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
  111. ld r10,area+EX_R10(r13); \
  112. std r9,GPR9(r1); \
  113. std r10,GPR10(r1); \
  114. ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
  115. ld r10,area+EX_R12(r13); \
  116. ld r11,area+EX_R13(r13); \
  117. std r9,GPR11(r1); \
  118. std r10,GPR12(r1); \
  119. std r11,GPR13(r1); \
  120. ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
  121. mflr r9; /* save LR in stackframe */ \
  122. std r9,_LINK(r1); \
  123. mfctr r10; /* save CTR in stackframe */ \
  124. std r10,_CTR(r1); \
  125. lbz r10,PACASOFTIRQEN(r13); \
  126. mfspr r11,SPRN_XER; /* save XER in stackframe */ \
  127. std r10,SOFTE(r1); \
  128. std r11,_XER(r1); \
  129. li r9,(n)+1; \
  130. std r9,_TRAP(r1); /* set trap number */ \
  131. li r10,0; \
  132. ld r11,exception_marker@toc(r2); \
  133. std r10,RESULT(r1); /* clear regs->result */ \
  134. std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
  135. /*
  136. * Exception vectors.
  137. */
  138. #define STD_EXCEPTION_PSERIES(n, label) \
  139. . = n; \
  140. .globl label##_pSeries; \
  141. label##_pSeries: \
  142. HMT_MEDIUM; \
  143. mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
  144. EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
  145. #define HSTD_EXCEPTION_PSERIES(n, label) \
  146. . = n; \
  147. .globl label##_pSeries; \
  148. label##_pSeries: \
  149. HMT_MEDIUM; \
  150. mtspr SPRN_SPRG_SCRATCH0,r20; /* save r20 */ \
  151. mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
  152. mtspr SPRN_SRR0,r20; \
  153. mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
  154. mtspr SPRN_SRR1,r20; \
  155. mfspr r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
  156. mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
  157. EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
  158. #define MASKABLE_EXCEPTION_PSERIES(n, label) \
  159. . = n; \
  160. .globl label##_pSeries; \
  161. label##_pSeries: \
  162. HMT_MEDIUM; \
  163. mtspr SPRN_SPRG_SCRATCH0,r13; /* save r13 */ \
  164. mfspr r13,SPRN_SPRG_PACA; /* get paca address into r13 */ \
  165. std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
  166. std r10,PACA_EXGEN+EX_R10(r13); \
  167. lbz r10,PACASOFTIRQEN(r13); \
  168. mfcr r9; \
  169. cmpwi r10,0; \
  170. beq masked_interrupt; \
  171. mfspr r10,SPRN_SPRG_SCRATCH0; \
  172. std r10,PACA_EXGEN+EX_R13(r13); \
  173. std r11,PACA_EXGEN+EX_R11(r13); \
  174. std r12,PACA_EXGEN+EX_R12(r13); \
  175. ld r12,PACAKBASE(r13); /* get high part of &label */ \
  176. ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \
  177. mfspr r11,SPRN_SRR0; /* save SRR0 */ \
  178. LOAD_HANDLER(r12,label##_common) \
  179. mtspr SPRN_SRR0,r12; \
  180. mfspr r12,SPRN_SRR1; /* and SRR1 */ \
  181. mtspr SPRN_SRR1,r10; \
  182. rfid; \
  183. b . /* prevent speculative execution */
  184. #ifdef CONFIG_PPC_ISERIES
  185. #define DISABLE_INTS \
  186. li r11,0; \
  187. stb r11,PACASOFTIRQEN(r13); \
  188. BEGIN_FW_FTR_SECTION; \
  189. stb r11,PACAHARDIRQEN(r13); \
  190. END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
  191. TRACE_DISABLE_INTS; \
  192. BEGIN_FW_FTR_SECTION; \
  193. mfmsr r10; \
  194. ori r10,r10,MSR_EE; \
  195. mtmsrd r10,1; \
  196. END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
  197. #else
  198. #define DISABLE_INTS \
  199. li r11,0; \
  200. stb r11,PACASOFTIRQEN(r13); \
  201. stb r11,PACAHARDIRQEN(r13); \
  202. TRACE_DISABLE_INTS
  203. #endif /* CONFIG_PPC_ISERIES */
  204. #define ENABLE_INTS \
  205. ld r12,_MSR(r1); \
  206. mfmsr r11; \
  207. rlwimi r11,r12,0,MSR_EE; \
  208. mtmsrd r11,1
  209. #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
  210. .align 7; \
  211. .globl label##_common; \
  212. label##_common: \
  213. EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
  214. DISABLE_INTS; \
  215. bl .save_nvgprs; \
  216. addi r3,r1,STACK_FRAME_OVERHEAD; \
  217. bl hdlr; \
  218. b .ret_from_except
  219. /*
  220. * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
  221. * in the idle task and therefore need the special idle handling.
  222. */
  223. #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
  224. .align 7; \
  225. .globl label##_common; \
  226. label##_common: \
  227. EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
  228. FINISH_NAP; \
  229. DISABLE_INTS; \
  230. bl .save_nvgprs; \
  231. addi r3,r1,STACK_FRAME_OVERHEAD; \
  232. bl hdlr; \
  233. b .ret_from_except
  234. #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
  235. .align 7; \
  236. .globl label##_common; \
  237. label##_common: \
  238. EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
  239. FINISH_NAP; \
  240. DISABLE_INTS; \
  241. BEGIN_FTR_SECTION \
  242. bl .ppc64_runlatch_on; \
  243. END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \
  244. addi r3,r1,STACK_FRAME_OVERHEAD; \
  245. bl hdlr; \
  246. b .ret_from_except_lite
  247. /*
  248. * When the idle code in power4_idle puts the CPU into NAP mode,
  249. * it has to do so in a loop, and relies on the external interrupt
  250. * and decrementer interrupt entry code to get it out of the loop.
  251. * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
  252. * to signal that it is in the loop and needs help to get out.
  253. */
  254. #ifdef CONFIG_PPC_970_NAP
  255. #define FINISH_NAP \
  256. BEGIN_FTR_SECTION \
  257. clrrdi r11,r1,THREAD_SHIFT; \
  258. ld r9,TI_LOCAL_FLAGS(r11); \
  259. andi. r10,r9,_TLF_NAPPING; \
  260. bnel power4_fixup_nap; \
  261. END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
  262. #else
  263. #define FINISH_NAP
  264. #endif
  265. #endif /* _ASM_POWERPC_EXCEPTION_H */