kilauea.dts 11 KB

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  1. /*
  2. * Device Tree Source for AMCC Kilauea (405EX)
  3. *
  4. * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. /dts-v1/;
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. model = "amcc,kilauea";
  15. compatible = "amcc,kilauea";
  16. dcr-parent = <&{/cpus/cpu@0}>;
  17. aliases {
  18. ethernet0 = &EMAC0;
  19. ethernet1 = &EMAC1;
  20. serial0 = &UART0;
  21. serial1 = &UART1;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. cpu@0 {
  27. device_type = "cpu";
  28. model = "PowerPC,405EX";
  29. reg = <0x00000000>;
  30. clock-frequency = <0>; /* Filled in by U-Boot */
  31. timebase-frequency = <0>; /* Filled in by U-Boot */
  32. i-cache-line-size = <32>;
  33. d-cache-line-size = <32>;
  34. i-cache-size = <16384>; /* 16 kB */
  35. d-cache-size = <16384>; /* 16 kB */
  36. dcr-controller;
  37. dcr-access-method = "native";
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
  43. };
  44. UIC0: interrupt-controller {
  45. compatible = "ibm,uic-405ex", "ibm,uic";
  46. interrupt-controller;
  47. cell-index = <0>;
  48. dcr-reg = <0x0c0 0x009>;
  49. #address-cells = <0>;
  50. #size-cells = <0>;
  51. #interrupt-cells = <2>;
  52. };
  53. UIC1: interrupt-controller1 {
  54. compatible = "ibm,uic-405ex","ibm,uic";
  55. interrupt-controller;
  56. cell-index = <1>;
  57. dcr-reg = <0x0d0 0x009>;
  58. #address-cells = <0>;
  59. #size-cells = <0>;
  60. #interrupt-cells = <2>;
  61. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  62. interrupt-parent = <&UIC0>;
  63. };
  64. UIC2: interrupt-controller2 {
  65. compatible = "ibm,uic-405ex","ibm,uic";
  66. interrupt-controller;
  67. cell-index = <2>;
  68. dcr-reg = <0x0e0 0x009>;
  69. #address-cells = <0>;
  70. #size-cells = <0>;
  71. #interrupt-cells = <2>;
  72. interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
  73. interrupt-parent = <&UIC0>;
  74. };
  75. plb {
  76. compatible = "ibm,plb-405ex", "ibm,plb4";
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. ranges;
  80. clock-frequency = <0>; /* Filled in by U-Boot */
  81. SDRAM0: memory-controller {
  82. compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
  83. dcr-reg = <0x010 0x002>;
  84. interrupt-parent = <&UIC2>;
  85. interrupts = <0x5 0x4 /* ECC DED Error */
  86. 0x6 0x4>; /* ECC SEC Error */
  87. };
  88. CRYPTO: crypto@ef700000 {
  89. compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
  90. reg = <0xef700000 0x80400>;
  91. interrupt-parent = <&UIC0>;
  92. interrupts = <0x17 0x2>;
  93. };
  94. MAL0: mcmal {
  95. compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
  96. dcr-reg = <0x180 0x062>;
  97. num-tx-chans = <2>;
  98. num-rx-chans = <2>;
  99. interrupt-parent = <&MAL0>;
  100. interrupts = <0x0 0x1 0x2 0x3 0x4>;
  101. #interrupt-cells = <1>;
  102. #address-cells = <0>;
  103. #size-cells = <0>;
  104. interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
  105. /*RXEOB*/ 0x1 &UIC0 0xb 0x4
  106. /*SERR*/ 0x2 &UIC1 0x0 0x4
  107. /*TXDE*/ 0x3 &UIC1 0x1 0x4
  108. /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
  109. interrupt-map-mask = <0xffffffff>;
  110. };
  111. POB0: opb {
  112. compatible = "ibm,opb-405ex", "ibm,opb";
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. ranges = <0x80000000 0x80000000 0x10000000
  116. 0xef600000 0xef600000 0x00a00000
  117. 0xf0000000 0xf0000000 0x10000000>;
  118. dcr-reg = <0x0a0 0x005>;
  119. clock-frequency = <0>; /* Filled in by U-Boot */
  120. EBC0: ebc {
  121. compatible = "ibm,ebc-405ex", "ibm,ebc";
  122. dcr-reg = <0x012 0x002>;
  123. #address-cells = <2>;
  124. #size-cells = <1>;
  125. clock-frequency = <0>; /* Filled in by U-Boot */
  126. /* ranges property is supplied by U-Boot */
  127. interrupts = <0x5 0x1>;
  128. interrupt-parent = <&UIC1>;
  129. nor_flash@0,0 {
  130. compatible = "amd,s29gl512n", "cfi-flash";
  131. bank-width = <2>;
  132. reg = <0x00000000 0x00000000 0x04000000>;
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. partition@0 {
  136. label = "kernel";
  137. reg = <0x00000000 0x001e0000>;
  138. };
  139. partition@1e0000 {
  140. label = "dtb";
  141. reg = <0x001e0000 0x00020000>;
  142. };
  143. partition@200000 {
  144. label = "root";
  145. reg = <0x00200000 0x00200000>;
  146. };
  147. partition@400000 {
  148. label = "user";
  149. reg = <0x00400000 0x03b60000>;
  150. };
  151. partition@3f60000 {
  152. label = "env";
  153. reg = <0x03f60000 0x00040000>;
  154. };
  155. partition@3fa0000 {
  156. label = "u-boot";
  157. reg = <0x03fa0000 0x00060000>;
  158. };
  159. };
  160. ndfc@1,0 {
  161. compatible = "ibm,ndfc";
  162. reg = <0x00000001 0x00000000 0x00002000>;
  163. ccr = <0x00001000>;
  164. bank-settings = <0x80002222>;
  165. #address-cells = <1>;
  166. #size-cells = <1>;
  167. nand {
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. partition@0 {
  171. label = "u-boot";
  172. reg = <0x00000000 0x00100000>;
  173. };
  174. partition@100000 {
  175. label = "user";
  176. reg = <0x00000000 0x03f00000>;
  177. };
  178. };
  179. };
  180. };
  181. UART0: serial@ef600200 {
  182. device_type = "serial";
  183. compatible = "ns16550";
  184. reg = <0xef600200 0x00000008>;
  185. virtual-reg = <0xef600200>;
  186. clock-frequency = <0>; /* Filled in by U-Boot */
  187. current-speed = <0>;
  188. interrupt-parent = <&UIC0>;
  189. interrupts = <0x1a 0x4>;
  190. };
  191. UART1: serial@ef600300 {
  192. device_type = "serial";
  193. compatible = "ns16550";
  194. reg = <0xef600300 0x00000008>;
  195. virtual-reg = <0xef600300>;
  196. clock-frequency = <0>; /* Filled in by U-Boot */
  197. current-speed = <0>;
  198. interrupt-parent = <&UIC0>;
  199. interrupts = <0x1 0x4>;
  200. };
  201. IIC0: i2c@ef600400 {
  202. compatible = "ibm,iic-405ex", "ibm,iic";
  203. reg = <0xef600400 0x00000014>;
  204. interrupt-parent = <&UIC0>;
  205. interrupts = <0x2 0x4>;
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. rtc@68 {
  209. compatible = "dallas,ds1338";
  210. reg = <0x68>;
  211. };
  212. dtt@48 {
  213. compatible = "dallas,ds1775";
  214. reg = <0x48>;
  215. };
  216. };
  217. IIC1: i2c@ef600500 {
  218. compatible = "ibm,iic-405ex", "ibm,iic";
  219. reg = <0xef600500 0x00000014>;
  220. interrupt-parent = <&UIC0>;
  221. interrupts = <0x7 0x4>;
  222. };
  223. RGMII0: emac-rgmii@ef600b00 {
  224. compatible = "ibm,rgmii-405ex", "ibm,rgmii";
  225. reg = <0xef600b00 0x00000104>;
  226. has-mdio;
  227. };
  228. EMAC0: ethernet@ef600900 {
  229. linux,network-index = <0x0>;
  230. device_type = "network";
  231. compatible = "ibm,emac-405ex", "ibm,emac4sync";
  232. interrupt-parent = <&EMAC0>;
  233. interrupts = <0x0 0x1>;
  234. #interrupt-cells = <1>;
  235. #address-cells = <0>;
  236. #size-cells = <0>;
  237. interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
  238. /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
  239. reg = <0xef600900 0x000000c4>;
  240. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  241. mal-device = <&MAL0>;
  242. mal-tx-channel = <0>;
  243. mal-rx-channel = <0>;
  244. cell-index = <0>;
  245. max-frame-size = <9000>;
  246. rx-fifo-size = <4096>;
  247. tx-fifo-size = <2048>;
  248. phy-mode = "rgmii";
  249. phy-map = <0x00000000>;
  250. rgmii-device = <&RGMII0>;
  251. rgmii-channel = <0>;
  252. has-inverted-stacr-oc;
  253. has-new-stacr-staopc;
  254. };
  255. EMAC1: ethernet@ef600a00 {
  256. linux,network-index = <0x1>;
  257. device_type = "network";
  258. compatible = "ibm,emac-405ex", "ibm,emac4sync";
  259. interrupt-parent = <&EMAC1>;
  260. interrupts = <0x0 0x1>;
  261. #interrupt-cells = <1>;
  262. #address-cells = <0>;
  263. #size-cells = <0>;
  264. interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
  265. /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
  266. reg = <0xef600a00 0x000000c4>;
  267. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  268. mal-device = <&MAL0>;
  269. mal-tx-channel = <1>;
  270. mal-rx-channel = <1>;
  271. cell-index = <1>;
  272. max-frame-size = <9000>;
  273. rx-fifo-size = <4096>;
  274. tx-fifo-size = <2048>;
  275. phy-mode = "rgmii";
  276. phy-map = <0x00000000>;
  277. rgmii-device = <&RGMII0>;
  278. rgmii-channel = <1>;
  279. has-inverted-stacr-oc;
  280. has-new-stacr-staopc;
  281. };
  282. };
  283. PCIE0: pciex@0a0000000 {
  284. device_type = "pci";
  285. #interrupt-cells = <1>;
  286. #size-cells = <2>;
  287. #address-cells = <3>;
  288. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  289. primary;
  290. port = <0x0>; /* port number */
  291. reg = <0xa0000000 0x20000000 /* Config space access */
  292. 0xef000000 0x00001000>; /* Registers */
  293. dcr-reg = <0x040 0x020>;
  294. sdr-base = <0x400>;
  295. /* Outbound ranges, one memory and one IO,
  296. * later cannot be changed
  297. */
  298. ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
  299. 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
  300. /* Inbound 2GB range starting at 0 */
  301. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
  302. /* This drives busses 0x00 to 0x3f */
  303. bus-range = <0x0 0x3f>;
  304. /* Legacy interrupts (note the weird polarity, the bridge seems
  305. * to invert PCIe legacy interrupts).
  306. * We are de-swizzling here because the numbers are actually for
  307. * port of the root complex virtual P2P bridge. But I want
  308. * to avoid putting a node for it in the tree, so the numbers
  309. * below are basically de-swizzled numbers.
  310. * The real slot is on idsel 0, so the swizzling is 1:1
  311. */
  312. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  313. interrupt-map = <
  314. 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
  315. 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
  316. 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
  317. 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
  318. };
  319. PCIE1: pciex@0c0000000 {
  320. device_type = "pci";
  321. #interrupt-cells = <1>;
  322. #size-cells = <2>;
  323. #address-cells = <3>;
  324. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  325. primary;
  326. port = <0x1>; /* port number */
  327. reg = <0xc0000000 0x20000000 /* Config space access */
  328. 0xef001000 0x00001000>; /* Registers */
  329. dcr-reg = <0x060 0x020>;
  330. sdr-base = <0x440>;
  331. /* Outbound ranges, one memory and one IO,
  332. * later cannot be changed
  333. */
  334. ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
  335. 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
  336. /* Inbound 2GB range starting at 0 */
  337. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
  338. /* This drives busses 0x40 to 0x7f */
  339. bus-range = <0x40 0x7f>;
  340. /* Legacy interrupts (note the weird polarity, the bridge seems
  341. * to invert PCIe legacy interrupts).
  342. * We are de-swizzling here because the numbers are actually for
  343. * port of the root complex virtual P2P bridge. But I want
  344. * to avoid putting a node for it in the tree, so the numbers
  345. * below are basically de-swizzled numbers.
  346. * The real slot is on idsel 0, so the swizzling is 1:1
  347. */
  348. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  349. interrupt-map = <
  350. 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
  351. 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
  352. 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
  353. 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
  354. };
  355. };
  356. };