arches.dts 8.7 KB

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  1. /*
  2. * Device Tree Source for AMCC Arches (dual 460GT board)
  3. *
  4. * (C) Copyright 2008 Applied Micro Circuits Corporation
  5. * Victor Gallardo <vgallardo@amcc.com>
  6. * Adam Graham <agraham@amcc.com>
  7. *
  8. * Based on the glacier.dts file
  9. * Stefan Roese <sr@denx.de>
  10. * Copyright 2008 DENX Software Engineering
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. /dts-v1/;
  31. / {
  32. #address-cells = <2>;
  33. #size-cells = <1>;
  34. model = "amcc,arches";
  35. compatible = "amcc,arches";
  36. dcr-parent = <&{/cpus/cpu@0}>;
  37. aliases {
  38. ethernet0 = &EMAC0;
  39. ethernet1 = &EMAC1;
  40. ethernet2 = &EMAC2;
  41. serial0 = &UART0;
  42. };
  43. cpus {
  44. #address-cells = <1>;
  45. #size-cells = <0>;
  46. cpu@0 {
  47. device_type = "cpu";
  48. model = "PowerPC,460GT";
  49. reg = <0x00000000>;
  50. clock-frequency = <0>; /* Filled in by U-Boot */
  51. timebase-frequency = <0>; /* Filled in by U-Boot */
  52. i-cache-line-size = <32>;
  53. d-cache-line-size = <32>;
  54. i-cache-size = <32768>;
  55. d-cache-size = <32768>;
  56. dcr-controller;
  57. dcr-access-method = "native";
  58. };
  59. };
  60. memory {
  61. device_type = "memory";
  62. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  63. };
  64. UIC0: interrupt-controller0 {
  65. compatible = "ibm,uic-460gt","ibm,uic";
  66. interrupt-controller;
  67. cell-index = <0>;
  68. dcr-reg = <0x0c0 0x009>;
  69. #address-cells = <0>;
  70. #size-cells = <0>;
  71. #interrupt-cells = <2>;
  72. };
  73. UIC1: interrupt-controller1 {
  74. compatible = "ibm,uic-460gt","ibm,uic";
  75. interrupt-controller;
  76. cell-index = <1>;
  77. dcr-reg = <0x0d0 0x009>;
  78. #address-cells = <0>;
  79. #size-cells = <0>;
  80. #interrupt-cells = <2>;
  81. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  82. interrupt-parent = <&UIC0>;
  83. };
  84. UIC2: interrupt-controller2 {
  85. compatible = "ibm,uic-460gt","ibm,uic";
  86. interrupt-controller;
  87. cell-index = <2>;
  88. dcr-reg = <0x0e0 0x009>;
  89. #address-cells = <0>;
  90. #size-cells = <0>;
  91. #interrupt-cells = <2>;
  92. interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
  93. interrupt-parent = <&UIC0>;
  94. };
  95. UIC3: interrupt-controller3 {
  96. compatible = "ibm,uic-460gt","ibm,uic";
  97. interrupt-controller;
  98. cell-index = <3>;
  99. dcr-reg = <0x0f0 0x009>;
  100. #address-cells = <0>;
  101. #size-cells = <0>;
  102. #interrupt-cells = <2>;
  103. interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
  104. interrupt-parent = <&UIC0>;
  105. };
  106. SDR0: sdr {
  107. compatible = "ibm,sdr-460gt";
  108. dcr-reg = <0x00e 0x002>;
  109. };
  110. CPR0: cpr {
  111. compatible = "ibm,cpr-460gt";
  112. dcr-reg = <0x00c 0x002>;
  113. };
  114. L2C0: l2c {
  115. compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
  116. dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
  117. 0x030 0x008>; /* L2 cache DCR's */
  118. cache-line-size = <32>; /* 32 bytes */
  119. cache-size = <262144>; /* L2, 256K */
  120. interrupt-parent = <&UIC1>;
  121. interrupts = <11 1>;
  122. };
  123. plb {
  124. compatible = "ibm,plb-460gt", "ibm,plb4";
  125. #address-cells = <2>;
  126. #size-cells = <1>;
  127. ranges;
  128. clock-frequency = <0>; /* Filled in by U-Boot */
  129. SDRAM0: sdram {
  130. compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
  131. dcr-reg = <0x010 0x002>;
  132. };
  133. MAL0: mcmal {
  134. compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
  135. dcr-reg = <0x180 0x062>;
  136. num-tx-chans = <3>;
  137. num-rx-chans = <24>;
  138. #address-cells = <0>;
  139. #size-cells = <0>;
  140. interrupt-parent = <&UIC2>;
  141. interrupts = < /*TXEOB*/ 0x6 0x4
  142. /*RXEOB*/ 0x7 0x4
  143. /*SERR*/ 0x3 0x4
  144. /*TXDE*/ 0x4 0x4
  145. /*RXDE*/ 0x5 0x4>;
  146. desc-base-addr-high = <0x8>;
  147. };
  148. POB0: opb {
  149. compatible = "ibm,opb-460gt", "ibm,opb";
  150. #address-cells = <1>;
  151. #size-cells = <1>;
  152. ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
  153. clock-frequency = <0>; /* Filled in by U-Boot */
  154. EBC0: ebc {
  155. compatible = "ibm,ebc-460gt", "ibm,ebc";
  156. dcr-reg = <0x012 0x002>;
  157. #address-cells = <2>;
  158. #size-cells = <1>;
  159. clock-frequency = <0>; /* Filled in by U-Boot */
  160. /* ranges property is supplied by U-Boot */
  161. interrupts = <0x6 0x4>;
  162. interrupt-parent = <&UIC1>;
  163. nor_flash@0,0 {
  164. compatible = "amd,s29gl256n", "cfi-flash";
  165. bank-width = <2>;
  166. reg = <0x00000000 0x00000000 0x02000000>;
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. partition@0 {
  170. label = "kernel";
  171. reg = <0x00000000 0x001e0000>;
  172. };
  173. partition@1e0000 {
  174. label = "dtb";
  175. reg = <0x001e0000 0x00020000>;
  176. };
  177. partition@200000 {
  178. label = "root";
  179. reg = <0x00200000 0x00200000>;
  180. };
  181. partition@400000 {
  182. label = "user";
  183. reg = <0x00400000 0x01b60000>;
  184. };
  185. partition@1f60000 {
  186. label = "env";
  187. reg = <0x01f60000 0x00040000>;
  188. };
  189. partition@1fa0000 {
  190. label = "u-boot";
  191. reg = <0x01fa0000 0x00060000>;
  192. };
  193. };
  194. };
  195. UART0: serial@ef600300 {
  196. device_type = "serial";
  197. compatible = "ns16550";
  198. reg = <0xef600300 0x00000008>;
  199. virtual-reg = <0xef600300>;
  200. clock-frequency = <0>; /* Filled in by U-Boot */
  201. current-speed = <0>; /* Filled in by U-Boot */
  202. interrupt-parent = <&UIC1>;
  203. interrupts = <0x1 0x4>;
  204. };
  205. IIC0: i2c@ef600700 {
  206. compatible = "ibm,iic-460gt", "ibm,iic";
  207. reg = <0xef600700 0x00000014>;
  208. interrupt-parent = <&UIC0>;
  209. interrupts = <0x2 0x4>;
  210. #address-cells = <1>;
  211. #size-cells = <0>;
  212. sttm@4a {
  213. compatible = "ad,ad7414";
  214. reg = <0x4a>;
  215. interrupt-parent = <&UIC1>;
  216. interrupts = <0x0 0x8>;
  217. };
  218. };
  219. IIC1: i2c@ef600800 {
  220. compatible = "ibm,iic-460gt", "ibm,iic";
  221. reg = <0xef600800 0x00000014>;
  222. interrupt-parent = <&UIC0>;
  223. interrupts = <0x3 0x4>;
  224. };
  225. TAH0: emac-tah@ef601350 {
  226. compatible = "ibm,tah-460gt", "ibm,tah";
  227. reg = <0xef601350 0x00000030>;
  228. };
  229. TAH1: emac-tah@ef601450 {
  230. compatible = "ibm,tah-460gt", "ibm,tah";
  231. reg = <0xef601450 0x00000030>;
  232. };
  233. EMAC0: ethernet@ef600e00 {
  234. device_type = "network";
  235. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  236. interrupt-parent = <&EMAC0>;
  237. interrupts = <0x0 0x1>;
  238. #interrupt-cells = <1>;
  239. #address-cells = <0>;
  240. #size-cells = <0>;
  241. interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
  242. /*Wake*/ 0x1 &UIC2 0x14 0x4>;
  243. reg = <0xef600e00 0x000000c4>;
  244. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  245. mal-device = <&MAL0>;
  246. mal-tx-channel = <0>;
  247. mal-rx-channel = <0>;
  248. cell-index = <0>;
  249. max-frame-size = <9000>;
  250. rx-fifo-size = <4096>;
  251. tx-fifo-size = <2048>;
  252. phy-mode = "sgmii";
  253. phy-map = <0xffffffff>;
  254. gpcs-address = <0x0000000a>;
  255. tah-device = <&TAH0>;
  256. tah-channel = <0>;
  257. has-inverted-stacr-oc;
  258. has-new-stacr-staopc;
  259. };
  260. EMAC1: ethernet@ef600f00 {
  261. device_type = "network";
  262. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  263. interrupt-parent = <&EMAC1>;
  264. interrupts = <0x0 0x1>;
  265. #interrupt-cells = <1>;
  266. #address-cells = <0>;
  267. #size-cells = <0>;
  268. interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
  269. /*Wake*/ 0x1 &UIC2 0x15 0x4>;
  270. reg = <0xef600f00 0x000000c4>;
  271. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  272. mal-device = <&MAL0>;
  273. mal-tx-channel = <1>;
  274. mal-rx-channel = <8>;
  275. cell-index = <1>;
  276. max-frame-size = <9000>;
  277. rx-fifo-size = <4096>;
  278. tx-fifo-size = <2048>;
  279. phy-mode = "sgmii";
  280. phy-map = <0x00000000>;
  281. gpcs-address = <0x0000000b>;
  282. tah-device = <&TAH1>;
  283. tah-channel = <1>;
  284. has-inverted-stacr-oc;
  285. has-new-stacr-staopc;
  286. mdio-device = <&EMAC0>;
  287. };
  288. EMAC2: ethernet@ef601100 {
  289. device_type = "network";
  290. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  291. interrupt-parent = <&EMAC2>;
  292. interrupts = <0x0 0x1>;
  293. #interrupt-cells = <1>;
  294. #address-cells = <0>;
  295. #size-cells = <0>;
  296. interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
  297. /*Wake*/ 0x1 &UIC2 0x16 0x4>;
  298. reg = <0xef601100 0x000000c4>;
  299. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  300. mal-device = <&MAL0>;
  301. mal-tx-channel = <2>;
  302. mal-rx-channel = <16>;
  303. cell-index = <2>;
  304. max-frame-size = <9000>;
  305. rx-fifo-size = <4096>;
  306. tx-fifo-size = <2048>;
  307. phy-mode = "sgmii";
  308. phy-map = <0x00000001>;
  309. gpcs-address = <0x0000000C>;
  310. has-inverted-stacr-oc;
  311. has-new-stacr-staopc;
  312. mdio-device = <&EMAC0>;
  313. };
  314. };
  315. };
  316. };