smp.c 11 KB

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  1. /*
  2. * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
  3. *
  4. * Copyright 2007-2009 Analog Devices Inc.
  5. * Philippe Gerum <rpm@xenomai.org>
  6. *
  7. * Licensed under the GPL-2.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/sched.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/cache.h>
  16. #include <linux/profile.h>
  17. #include <linux/errno.h>
  18. #include <linux/mm.h>
  19. #include <linux/cpu.h>
  20. #include <linux/smp.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/irq.h>
  23. #include <asm/atomic.h>
  24. #include <asm/cacheflush.h>
  25. #include <asm/mmu_context.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/pgalloc.h>
  28. #include <asm/processor.h>
  29. #include <asm/ptrace.h>
  30. #include <asm/cpu.h>
  31. #include <asm/time.h>
  32. #include <linux/err.h>
  33. /*
  34. * Anomaly notes:
  35. * 05000120 - we always define corelock as 32-bit integer in L2
  36. */
  37. struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
  38. void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
  39. *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
  40. *init_saved_dcplb_fault_addr_coreb;
  41. cpumask_t cpu_possible_map;
  42. EXPORT_SYMBOL(cpu_possible_map);
  43. cpumask_t cpu_online_map;
  44. EXPORT_SYMBOL(cpu_online_map);
  45. #define BFIN_IPI_RESCHEDULE 0
  46. #define BFIN_IPI_CALL_FUNC 1
  47. #define BFIN_IPI_CPU_STOP 2
  48. struct blackfin_flush_data {
  49. unsigned long start;
  50. unsigned long end;
  51. };
  52. void *secondary_stack;
  53. struct smp_call_struct {
  54. void (*func)(void *info);
  55. void *info;
  56. int wait;
  57. cpumask_t pending;
  58. cpumask_t waitmask;
  59. };
  60. static struct blackfin_flush_data smp_flush_data;
  61. static DEFINE_SPINLOCK(stop_lock);
  62. struct ipi_message {
  63. struct list_head list;
  64. unsigned long type;
  65. struct smp_call_struct call_struct;
  66. };
  67. struct ipi_message_queue {
  68. struct list_head head;
  69. spinlock_t lock;
  70. unsigned long count;
  71. };
  72. static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
  73. static void ipi_cpu_stop(unsigned int cpu)
  74. {
  75. spin_lock(&stop_lock);
  76. printk(KERN_CRIT "CPU%u: stopping\n", cpu);
  77. dump_stack();
  78. spin_unlock(&stop_lock);
  79. cpu_clear(cpu, cpu_online_map);
  80. local_irq_disable();
  81. while (1)
  82. SSYNC();
  83. }
  84. static void ipi_flush_icache(void *info)
  85. {
  86. struct blackfin_flush_data *fdata = info;
  87. /* Invalidate the memory holding the bounds of the flushed region. */
  88. blackfin_dcache_invalidate_range((unsigned long)fdata,
  89. (unsigned long)fdata + sizeof(*fdata));
  90. blackfin_icache_flush_range(fdata->start, fdata->end);
  91. }
  92. static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
  93. {
  94. int wait;
  95. void (*func)(void *info);
  96. void *info;
  97. func = msg->call_struct.func;
  98. info = msg->call_struct.info;
  99. wait = msg->call_struct.wait;
  100. cpu_clear(cpu, msg->call_struct.pending);
  101. func(info);
  102. if (wait)
  103. cpu_clear(cpu, msg->call_struct.waitmask);
  104. else
  105. kfree(msg);
  106. }
  107. static irqreturn_t ipi_handler(int irq, void *dev_instance)
  108. {
  109. struct ipi_message *msg;
  110. struct ipi_message_queue *msg_queue;
  111. unsigned int cpu = smp_processor_id();
  112. platform_clear_ipi(cpu);
  113. msg_queue = &__get_cpu_var(ipi_msg_queue);
  114. msg_queue->count++;
  115. spin_lock(&msg_queue->lock);
  116. while (!list_empty(&msg_queue->head)) {
  117. msg = list_entry(msg_queue->head.next, typeof(*msg), list);
  118. list_del(&msg->list);
  119. switch (msg->type) {
  120. case BFIN_IPI_RESCHEDULE:
  121. /* That's the easiest one; leave it to
  122. * return_from_int. */
  123. kfree(msg);
  124. break;
  125. case BFIN_IPI_CALL_FUNC:
  126. spin_unlock(&msg_queue->lock);
  127. ipi_call_function(cpu, msg);
  128. spin_lock(&msg_queue->lock);
  129. break;
  130. case BFIN_IPI_CPU_STOP:
  131. spin_unlock(&msg_queue->lock);
  132. ipi_cpu_stop(cpu);
  133. spin_lock(&msg_queue->lock);
  134. kfree(msg);
  135. break;
  136. default:
  137. printk(KERN_CRIT "CPU%u: Unknown IPI message \
  138. 0x%lx\n", cpu, msg->type);
  139. kfree(msg);
  140. break;
  141. }
  142. }
  143. spin_unlock(&msg_queue->lock);
  144. return IRQ_HANDLED;
  145. }
  146. static void ipi_queue_init(void)
  147. {
  148. unsigned int cpu;
  149. struct ipi_message_queue *msg_queue;
  150. for_each_possible_cpu(cpu) {
  151. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  152. INIT_LIST_HEAD(&msg_queue->head);
  153. spin_lock_init(&msg_queue->lock);
  154. msg_queue->count = 0;
  155. }
  156. }
  157. int smp_call_function(void (*func)(void *info), void *info, int wait)
  158. {
  159. unsigned int cpu;
  160. cpumask_t callmap;
  161. unsigned long flags;
  162. struct ipi_message_queue *msg_queue;
  163. struct ipi_message *msg;
  164. callmap = cpu_online_map;
  165. cpu_clear(smp_processor_id(), callmap);
  166. if (cpus_empty(callmap))
  167. return 0;
  168. msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
  169. if (!msg)
  170. return -ENOMEM;
  171. INIT_LIST_HEAD(&msg->list);
  172. msg->call_struct.func = func;
  173. msg->call_struct.info = info;
  174. msg->call_struct.wait = wait;
  175. msg->call_struct.pending = callmap;
  176. msg->call_struct.waitmask = callmap;
  177. msg->type = BFIN_IPI_CALL_FUNC;
  178. for_each_cpu_mask(cpu, callmap) {
  179. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  180. spin_lock_irqsave(&msg_queue->lock, flags);
  181. list_add_tail(&msg->list, &msg_queue->head);
  182. spin_unlock_irqrestore(&msg_queue->lock, flags);
  183. platform_send_ipi_cpu(cpu);
  184. }
  185. if (wait) {
  186. while (!cpus_empty(msg->call_struct.waitmask))
  187. blackfin_dcache_invalidate_range(
  188. (unsigned long)(&msg->call_struct.waitmask),
  189. (unsigned long)(&msg->call_struct.waitmask));
  190. kfree(msg);
  191. }
  192. return 0;
  193. }
  194. EXPORT_SYMBOL_GPL(smp_call_function);
  195. int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
  196. int wait)
  197. {
  198. unsigned int cpu = cpuid;
  199. cpumask_t callmap;
  200. unsigned long flags;
  201. struct ipi_message_queue *msg_queue;
  202. struct ipi_message *msg;
  203. if (cpu_is_offline(cpu))
  204. return 0;
  205. cpus_clear(callmap);
  206. cpu_set(cpu, callmap);
  207. msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
  208. if (!msg)
  209. return -ENOMEM;
  210. INIT_LIST_HEAD(&msg->list);
  211. msg->call_struct.func = func;
  212. msg->call_struct.info = info;
  213. msg->call_struct.wait = wait;
  214. msg->call_struct.pending = callmap;
  215. msg->call_struct.waitmask = callmap;
  216. msg->type = BFIN_IPI_CALL_FUNC;
  217. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  218. spin_lock_irqsave(&msg_queue->lock, flags);
  219. list_add_tail(&msg->list, &msg_queue->head);
  220. spin_unlock_irqrestore(&msg_queue->lock, flags);
  221. platform_send_ipi_cpu(cpu);
  222. if (wait) {
  223. while (!cpus_empty(msg->call_struct.waitmask))
  224. blackfin_dcache_invalidate_range(
  225. (unsigned long)(&msg->call_struct.waitmask),
  226. (unsigned long)(&msg->call_struct.waitmask));
  227. kfree(msg);
  228. }
  229. return 0;
  230. }
  231. EXPORT_SYMBOL_GPL(smp_call_function_single);
  232. void smp_send_reschedule(int cpu)
  233. {
  234. unsigned long flags;
  235. struct ipi_message_queue *msg_queue;
  236. struct ipi_message *msg;
  237. if (cpu_is_offline(cpu))
  238. return;
  239. msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
  240. if (!msg)
  241. return;
  242. memset(msg, 0, sizeof(msg));
  243. INIT_LIST_HEAD(&msg->list);
  244. msg->type = BFIN_IPI_RESCHEDULE;
  245. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  246. spin_lock_irqsave(&msg_queue->lock, flags);
  247. list_add_tail(&msg->list, &msg_queue->head);
  248. spin_unlock_irqrestore(&msg_queue->lock, flags);
  249. platform_send_ipi_cpu(cpu);
  250. return;
  251. }
  252. void smp_send_stop(void)
  253. {
  254. unsigned int cpu;
  255. cpumask_t callmap;
  256. unsigned long flags;
  257. struct ipi_message_queue *msg_queue;
  258. struct ipi_message *msg;
  259. callmap = cpu_online_map;
  260. cpu_clear(smp_processor_id(), callmap);
  261. if (cpus_empty(callmap))
  262. return;
  263. msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
  264. if (!msg)
  265. return;
  266. memset(msg, 0, sizeof(msg));
  267. INIT_LIST_HEAD(&msg->list);
  268. msg->type = BFIN_IPI_CPU_STOP;
  269. for_each_cpu_mask(cpu, callmap) {
  270. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  271. spin_lock_irqsave(&msg_queue->lock, flags);
  272. list_add_tail(&msg->list, &msg_queue->head);
  273. spin_unlock_irqrestore(&msg_queue->lock, flags);
  274. platform_send_ipi_cpu(cpu);
  275. }
  276. return;
  277. }
  278. int __cpuinit __cpu_up(unsigned int cpu)
  279. {
  280. struct task_struct *idle;
  281. int ret;
  282. idle = fork_idle(cpu);
  283. if (IS_ERR(idle)) {
  284. printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
  285. return PTR_ERR(idle);
  286. }
  287. secondary_stack = task_stack_page(idle) + THREAD_SIZE;
  288. smp_wmb();
  289. ret = platform_boot_secondary(cpu, idle);
  290. if (ret) {
  291. cpu_clear(cpu, cpu_present_map);
  292. printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret);
  293. free_task(idle);
  294. } else
  295. cpu_set(cpu, cpu_online_map);
  296. secondary_stack = NULL;
  297. return ret;
  298. }
  299. static void __cpuinit setup_secondary(unsigned int cpu)
  300. {
  301. #if !defined(CONFIG_TICKSOURCE_GPTMR0)
  302. struct irq_desc *timer_desc;
  303. #endif
  304. unsigned long ilat;
  305. bfin_write_IMASK(0);
  306. CSYNC();
  307. ilat = bfin_read_ILAT();
  308. CSYNC();
  309. bfin_write_ILAT(ilat);
  310. CSYNC();
  311. /* Enable interrupt levels IVG7-15. IARs have been already
  312. * programmed by the boot CPU. */
  313. bfin_irq_flags |= IMASK_IVG15 |
  314. IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
  315. IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
  316. #if defined(CONFIG_TICKSOURCE_GPTMR0)
  317. /* Power down the core timer, just to play safe. */
  318. bfin_write_TCNTL(0);
  319. /* system timer0 has been setup by CoreA. */
  320. #else
  321. timer_desc = irq_desc + IRQ_CORETMR;
  322. setup_core_timer();
  323. timer_desc->chip->enable(IRQ_CORETMR);
  324. #endif
  325. }
  326. void __cpuinit secondary_start_kernel(void)
  327. {
  328. unsigned int cpu = smp_processor_id();
  329. struct mm_struct *mm = &init_mm;
  330. if (_bfin_swrst & SWRST_DBL_FAULT_B) {
  331. printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
  332. #ifdef CONFIG_DEBUG_DOUBLEFAULT
  333. printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
  334. (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
  335. printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
  336. printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
  337. #endif
  338. printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
  339. init_retx_coreb);
  340. }
  341. /*
  342. * We want the D-cache to be enabled early, in case the atomic
  343. * support code emulates cache coherence (see
  344. * __ARCH_SYNC_CORE_DCACHE).
  345. */
  346. init_exception_vectors();
  347. bfin_setup_caches(cpu);
  348. local_irq_disable();
  349. /* Attach the new idle task to the global mm. */
  350. atomic_inc(&mm->mm_users);
  351. atomic_inc(&mm->mm_count);
  352. current->active_mm = mm;
  353. BUG_ON(current->mm); /* Can't be, but better be safe than sorry. */
  354. preempt_disable();
  355. setup_secondary(cpu);
  356. local_irq_enable();
  357. platform_secondary_init(cpu);
  358. cpu_idle();
  359. }
  360. void __init smp_prepare_boot_cpu(void)
  361. {
  362. }
  363. void __init smp_prepare_cpus(unsigned int max_cpus)
  364. {
  365. platform_prepare_cpus(max_cpus);
  366. ipi_queue_init();
  367. platform_request_ipi(&ipi_handler);
  368. }
  369. void __init smp_cpus_done(unsigned int max_cpus)
  370. {
  371. unsigned long bogosum = 0;
  372. unsigned int cpu;
  373. for_each_online_cpu(cpu)
  374. bogosum += loops_per_jiffy;
  375. printk(KERN_INFO "SMP: Total of %d processors activated "
  376. "(%lu.%02lu BogoMIPS).\n",
  377. num_online_cpus(),
  378. bogosum / (500000/HZ),
  379. (bogosum / (5000/HZ)) % 100);
  380. }
  381. void smp_icache_flush_range_others(unsigned long start, unsigned long end)
  382. {
  383. smp_flush_data.start = start;
  384. smp_flush_data.end = end;
  385. if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
  386. printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
  387. }
  388. EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
  389. #ifdef __ARCH_SYNC_CORE_ICACHE
  390. void resync_core_icache(void)
  391. {
  392. unsigned int cpu = get_cpu();
  393. blackfin_invalidate_entire_icache();
  394. ++per_cpu(cpu_data, cpu).icache_invld_count;
  395. put_cpu();
  396. }
  397. EXPORT_SYMBOL(resync_core_icache);
  398. #endif
  399. #ifdef __ARCH_SYNC_CORE_DCACHE
  400. unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
  401. void resync_core_dcache(void)
  402. {
  403. unsigned int cpu = get_cpu();
  404. blackfin_invalidate_entire_dcache();
  405. ++per_cpu(cpu_data, cpu).dcache_invld_count;
  406. put_cpu();
  407. }
  408. EXPORT_SYMBOL(resync_core_dcache);
  409. #endif