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linux-vybrid_pu...
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arch
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blackfin
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mach-bf548
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Kconfig

Kconfig 6.0 KB
文件历史 原始文件

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  1. if (BF54x)
    2. 

  2. 

  3. source "arch/blackfin/mach-bf548/boards/Kconfig"
    4. 

  4. 

  5. menu "BF548 Specific Configuration"
    6. 

  6. 

  7. config DEB_DMA_URGENT
    8. 

  8. 	bool "DMA has priority over core for ext. accesses"
    9. 

  9. 	depends on BF54x
    10. 

  10. 	default y
    11. 

  11. 	help
    12. 

  12. 	  Treat any DEB1, DEB2 and DEB3 request as Urgent
    13. 

  13. 

  14. config BF548_ATAPI_ALTERNATIVE_PORT
    15. 

  15. 	bool "BF548 ATAPI alternative port via GPIO"
    16. 

  16. 	help
    17. 

  17. 	  BF548 ATAPI data and address PINs can be routed through
    18. 

  18. 	  async address or GPIO port F and G. Select y to route it
    19. 

  19. 	  to GPIO.
    20. 

  20. 

  21. comment "Interrupt Priority Assignment"
    22. 

  22. menu "Priority"
    23. 

  23. 

  24. config IRQ_PLL_WAKEUP
    25. 

  25. 	int "IRQ_PLL_WAKEUP"
    26. 

  26. 	default 7
    27. 

  27. config IRQ_DMAC0_ERR
    28. 

  28. 	int "IRQ_DMAC0_ERR"
    29. 

  29. 	default 7
    30. 

  30. config IRQ_EPPI0_ERR
    31. 

  31. 	int "IRQ_EPPI0_ERR"
    32. 

  32. 	default 7
    33. 

  33. config IRQ_SPORT0_ERR
    34. 

  34. 	int "IRQ_SPORT0_ERR"
    35. 

  35. 	default 7
    36. 

  36. config IRQ_SPORT1_ERR
    37. 

  37. 	int "IRQ_SPORT1_ERR"
    38. 

  38. 	default 7
    39. 

  39. config IRQ_SPI0_ERR
    40. 

  40. 	int "IRQ_SPI0_ERR"
    41. 

  41. 	default 7
    42. 

  42. config IRQ_UART0_ERR
    43. 

  43. 	int "IRQ_UART0_ERR"
    44. 

  44. 	default 7
    45. 

  45. config IRQ_RTC
    46. 

  46. 	int "IRQ_RTC"
    47. 

  47. 	default 8
    48. 

  48. config IRQ_EPPI0
    49. 

  49. 	int "IRQ_EPPI0"
    50. 

  50. 	default 8
    51. 

  51. config IRQ_SPORT0_RX
    52. 

  52. 	int "IRQ_SPORT0_RX"
    53. 

  53. 	default 9
    54. 

  54. config IRQ_SPORT0_TX
    55. 

  55. 	int "IRQ_SPORT0_TX"
    56. 

  56. 	default 9
    57. 

  57. config IRQ_SPORT1_RX
    58. 

  58. 	int "IRQ_SPORT1_RX"
    59. 

  59. 	default 9
    60. 

  60. config IRQ_SPORT1_TX
    61. 

  61. 	int "IRQ_SPORT1_TX"
    62. 

  62. 	default 9
    63. 

  63. config IRQ_SPI0
    64. 

  64. 	int "IRQ_SPI0"
    65. 

  65. 	default 10
    66. 

  66. config IRQ_UART0_RX
    67. 

  67. 	int "IRQ_UART0_RX"
    68. 

  68. 	default 10
    69. 

  69. config IRQ_UART0_TX
    70. 

  70. 	int "IRQ_UART0_TX"
    71. 

  71. 	default 10
    72. 

  72. config IRQ_TIMER8
    73. 

  73. 	int "IRQ_TIMER8"
    74. 

  74. 	default 11
    75. 

  75. config IRQ_TIMER9
    76. 

  76. 	int "IRQ_TIMER9"
    77. 

  77. 	default 11
    78. 

  78. config IRQ_TIMER10
    79. 

  79. 	int "IRQ_TIMER10"
    80. 

  80. 	default 11
    81. 

  81. config IRQ_PINT0
    82. 

  82. 	int "IRQ_PINT0"
    83. 

  83. 	default 12
    84. 

  84. config IRQ_PINT1
    85. 

  85. 	int "IRQ_PINT0"
    86. 

  86. 	default 12
    87. 

  87. config IRQ_MDMAS0
    88. 

  88. 	int "IRQ_MDMAS0"
    89. 

  89. 	default 13
    90. 

  90. config IRQ_MDMAS1
    91. 

  91. 	int "IRQ_DMDMAS1"
    92. 

  92. 	default 13
    93. 

  93. config IRQ_WATCHDOG
    94. 

  94. 	int "IRQ_WATCHDOG"
    95. 

  95. 	default 13
    96. 

  96. config IRQ_DMAC1_ERR
    97. 

  97. 	int "IRQ_DMAC1_ERR"
    98. 

  98. 	default 7
    99. 

  99. config IRQ_SPORT2_ERR
    100. 

  100. 	int "IRQ_SPORT2_ERR"
    101. 

  101. 	default 7
    102. 

  102. config IRQ_SPORT3_ERR
    103. 

  103. 	int "IRQ_SPORT3_ERR"
    104. 

  104. 	default 7
    105. 

  105. config IRQ_MXVR_DATA
    106. 

  106. 	int "IRQ MXVR Data"
    107. 

  107. 	default 7
    108. 

  108. config IRQ_SPI1_ERR
    109. 

  109. 	int "IRQ_SPI1_ERR"
    110. 

  110. 	default 7
    111. 

  111. config IRQ_SPI2_ERR
    112. 

  112. 	int "IRQ_SPI2_ERR"
    113. 

  113. 	default 7
    114. 

  114. config IRQ_UART1_ERR
    115. 

  115. 	int "IRQ_UART1_ERR"
    116. 

  116. 	default 7
    117. 

  117. config IRQ_UART2_ERR
    118. 

  118. 	int "IRQ_UART2_ERR"
    119. 

  119. 	default 7
    120. 

  120. config IRQ_CAN0_ERR
    121. 

  121. 	int "IRQ_CAN0_ERR"
    122. 

  122. 	default 7
    123. 

  123. config IRQ_SPORT2_RX
    124. 

  124. 	int "IRQ_SPORT2_RX"
    125. 

  125. 	default 9
    126. 

  126. config IRQ_SPORT2_TX
    127. 

  127. 	int "IRQ_SPORT2_TX"
    128. 

  128. 	default 9
    129. 

  129. config IRQ_SPORT3_RX
    130. 

  130. 	int "IRQ_SPORT3_RX"
    131. 

  131. 	default 9
    132. 

  132. config IRQ_SPORT3_TX
    133. 

  133. 	int "IRQ_SPORT3_TX"
    134. 

  134. 	default 9
    135. 

  135. config IRQ_EPPI1
    136. 

  136. 	int "IRQ_EPPI1"
    137. 

  137. 	default 9
    138. 

  138. config IRQ_EPPI2
    139. 

  139. 	int "IRQ_EPPI2"
    140. 

  140. 	default 9
    141. 

  141. config IRQ_SPI1
    142. 

  142. 	int "IRQ_SPI1"
    143. 

  143. 	default 10
    144. 

  144. config IRQ_SPI2
    145. 

  145. 	int "IRQ_SPI2"
    146. 

  146. 	default 10
    147. 

  147. config IRQ_UART1_RX
    148. 

  148. 	int "IRQ_UART1_RX"
    149. 

  149. 	default 10
    150. 

  150. config IRQ_UART1_TX
    151. 

  151. 	int "IRQ_UART1_TX"
    152. 

  152. 	default 10
    153. 

  153. config IRQ_ATAPI_RX
    154. 

  154. 	int "IRQ_ATAPI_RX"
    155. 

  155. 	default 10
    156. 

  156. config IRQ_ATAPI_TX
    157. 

  157. 	int "IRQ_ATAPI_TX"
    158. 

  158. 	default 10
    159. 

  159. config IRQ_TWI0
    160. 

  160. 	int "IRQ_TWI0"
    161. 

  161. 	default 11
    162. 

  162. config IRQ_TWI1
    163. 

  163. 	int "IRQ_TWI1"
    164. 

  164. 	default 11
    165. 

  165. config IRQ_CAN0_RX
    166. 

  166. 	int "IRQ_CAN_RX"
    167. 

  167. 	default 11
    168. 

  168. config IRQ_CAN0_TX
    169. 

  169. 	int "IRQ_CAN_TX"
    170. 

  170. 	default 11
    171. 

  171. config IRQ_MDMAS2
    172. 

  172. 	int "IRQ_MDMAS2"
    173. 

  173. 	default 13
    174. 

  174. config IRQ_MDMAS3
    175. 

  175. 	int "IRQ_DMMAS3"
    176. 

  176. 	default 13
    177. 

  177. config IRQ_MXVR_ERR
    178. 

  178. 	int "IRQ_MXVR_ERR"
    179. 

  179. 	default 11
    180. 

  180. config IRQ_MXVR_MSG
    181. 

  181. 	int "IRQ_MXVR_MSG"
    182. 

  182. 	default 11
    183. 

  183. config IRQ_MXVR_PKT
    184. 

  184. 	int "IRQ_MXVR_PKT"
    185. 

  185. 	default 11
    186. 

  186. config IRQ_EPPI1_ERR
    187. 

  187. 	int "IRQ_EPPI1_ERR"
    188. 

  188. 	default 7
    189. 

  189. config IRQ_EPPI2_ERR
    190. 

  190. 	int "IRQ_EPPI2_ERR"
    191. 

  191. 	default 7
    192. 

  192. config IRQ_UART3_ERR
    193. 

  193. 	int "IRQ_UART3_ERR"
    194. 

  194. 	default 7
    195. 

  195. config IRQ_HOST_ERR
    196. 

  196. 	int "IRQ_HOST_ERR"
    197. 

  197. 	default 7
    198. 

  198. config IRQ_PIXC_ERR
    199. 

  199. 	int "IRQ_PIXC_ERR"
    200. 

  200. 	default 7
    201. 

  201. config IRQ_NFC_ERR
    202. 

  202. 	int "IRQ_NFC_ERR"
    203. 

  203. 	default 7
    204. 

  204. config IRQ_ATAPI_ERR
    205. 

  205. 	int "IRQ_ATAPI_ERR"
    206. 

  206. 	default 7
    207. 

  207. config IRQ_CAN1_ERR
    208. 

  208. 	int "IRQ_CAN1_ERR"
    209. 

  209. 	default 7
    210. 

  210. config IRQ_HS_DMA_ERR
    211. 

  211. 	int "IRQ Handshake DMA Status"
    212. 

  212. 	default 7
    213. 

  213. config IRQ_PIXC_IN0
    214. 

  214. 	int "IRQ PIXC IN0"
    215. 

  215. 	default 8
    216. 

  216. config IRQ_PIXC_IN1
    217. 

  217. 	int "IRQ PIXC IN1"
    218. 

  218. 	default 8
    219. 

  219. config IRQ_PIXC_OUT
    220. 

  220. 	int "IRQ PIXC OUT"
    221. 

  221. 	default 8
    222. 

  222. config IRQ_SDH
    223. 

  223. 	int "IRQ SDH"
    224. 

  224. 	default 8
    225. 

  225. config IRQ_CNT
    226. 

  226. 	int "IRQ CNT"
    227. 

  227. 	default 8
    228. 

  228. config IRQ_KEY
    229. 

  229. 	int "IRQ KEY"
    230. 

  230. 	default 8
    231. 

  231. config IRQ_CAN1_RX
    232. 

  232. 	int "IRQ CAN1 RX"
    233. 

  233. 	default 11
    234. 

  234. config IRQ_CAN1_TX
    235. 

  235. 	int "IRQ_CAN1_TX"
    236. 

  236. 	default 11
    237. 

  237. config IRQ_SDH_MASK0
    238. 

  238. 	int "IRQ_SDH_MASK0"
    239. 

  239. 	default 11
    240. 

  240. config IRQ_SDH_MASK1
    241. 

  241. 	int "IRQ_SDH_MASK1"
    242. 

  242. 	default 11
    243. 

  243. config IRQ_USB_INT0
    244. 

  244. 	int "IRQ USB INT0"
    245. 

  245. 	default 11
    246. 

  246. config IRQ_USB_INT1
    247. 

  247. 	int "IRQ USB INT1"
    248. 

  248. 	default 11
    249. 

  249. config IRQ_USB_INT2
    250. 

  250. 	int "IRQ USB INT2"
    251. 

  251. 	default 11
    252. 

  252. config IRQ_USB_DMA
    253. 

  253. 	int "IRQ USB DMA"
    254. 

  254. 	default 11
    255. 

  255. config IRQ_OTPSEC
    256. 

  256. 	int "IRQ OPTSEC"
    257. 

  257. 	default 11
    258. 

  258. config IRQ_TIMER0
    259. 

  259. 	int "IRQ_TIMER0"
    260. 

  260. 	default 7 if TICKSOURCE_GPTMR0
    261. 

  261. 	default 8
    262. 

  262. config IRQ_TIMER1
    263. 

  263. 	int "IRQ_TIMER1"
    264. 

  264. 	default 11
    265. 

  265. config IRQ_TIMER2
    266. 

  266. 	int "IRQ_TIMER2"
    267. 

  267. 	default 11
    268. 

  268. config IRQ_TIMER3
    269. 

  269. 	int "IRQ_TIMER3"
    270. 

  270. 	default 11
    271. 

  271. config IRQ_TIMER4
    272. 

  272. 	int "IRQ_TIMER4"
    273. 

  273. 	default 11
    274. 

  274. config IRQ_TIMER5
    275. 

  275. 	int "IRQ_TIMER5"
    276. 

  276. 	default 11
    277. 

  277. config IRQ_TIMER6
    278. 

  278. 	int "IRQ_TIMER6"
    279. 

  279. 	default 11
    280. 

  280. config IRQ_TIMER7
    281. 

  281. 	int "IRQ_TIMER7"
    282. 

  282. 	default 11
    283. 

  283. config IRQ_PINT2
    284. 

  284. 	int "IRQ_PIN2"
    285. 

  285. 	default 11
    286. 

  286. config IRQ_PINT3
    287. 

  287. 	int "IRQ_PIN3"
    288. 

  288. 	default 11
    289. 

  289. 

  290. 	help
    291. 

  291. 	  Enter the priority numbers between 7-13 ONLY.  Others are Reserved.
    292. 

  292. 	  This applies to all the above.  It is not recommended to assign the
    293. 

  293. 	  highest priority number 7 to UART or any other device.
    294. 

  294. 

  295. endmenu
    296. 

  296. 

  297. comment "Pin Interrupt to Port Assignment"
    298. 

  298. menu "Assignment"
    299. 

  299. 

  300. config PINTx_REASSIGN
    301. 

  301. 	bool "Reprogram PINT Assignment"
    302. 

  302. 	default y
    303. 

  303. 	help
    304. 

  304. 	  The interrupt assignment registers controls the pin-to-interrupt
    305. 

  305. 	  assignment in a byte-wide manner. Each option allows you to select
    306. 

  306. 	  a set of pins (High/Low Byte) of an specific Port being mapped
    307. 

  307. 	  to one of the four PIN Interrupts IRQ_PINTx.
    308. 

  308. 

  309. 	  You shouldn't change any of these unless you know exactly what you're doing.
    310. 

  310. 	  Please consult the Blackfin BF54x Processor Hardware Reference Manual.
    311. 

  311. 

  312. config PINT0_ASSIGN
    313. 

  313. 	hex "PINT0_ASSIGN"
    314. 

  314. 	depends on PINTx_REASSIGN
    315. 

  315. 	default 0x00000101
    316. 

  316. config PINT1_ASSIGN
    317. 

  317. 	hex "PINT1_ASSIGN"
    318. 

  318. 	depends on PINTx_REASSIGN
    319. 

  319. 	default 0x01010000
    320. 

  320. config PINT2_ASSIGN
    321. 

  321. 	hex "PINT2_ASSIGN"
    322. 

  322. 	depends on PINTx_REASSIGN
    323. 

  323. 	default 0x07000101
    324. 

  324. config PINT3_ASSIGN
    325. 

  325. 	hex "PINT3_ASSIGN"
    326. 

  326. 	depends on PINTx_REASSIGN
    327. 

  327. 	default 0x02020303
    328. 

  328. 

  329. endmenu
    330. 

  330. 

  331. endmenu
    332. 

  332. 

  333. endif
    334.