ezbrd.c 18 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mtd/mtd.h>
  11. #include <linux/mtd/partitions.h>
  12. #include <linux/mtd/physmap.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/i2c.h>
  16. #include <linux/irq.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/usb/musb.h>
  19. #include <asm/dma.h>
  20. #include <asm/bfin5xx_spi.h>
  21. #include <asm/reboot.h>
  22. #include <asm/nand.h>
  23. #include <asm/portmux.h>
  24. #include <asm/dpmc.h>
  25. #include <linux/spi/ad7877.h>
  26. /*
  27. * Name the Board for the /proc/cpuinfo
  28. */
  29. const char bfin_board_name[] = "ADI BF526-EZBRD";
  30. /*
  31. * Driver needs to know address, irq and flag pin.
  32. */
  33. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  34. static struct resource musb_resources[] = {
  35. [0] = {
  36. .start = 0xffc03800,
  37. .end = 0xffc03cff,
  38. .flags = IORESOURCE_MEM,
  39. },
  40. [1] = { /* general IRQ */
  41. .start = IRQ_USB_INT0,
  42. .end = IRQ_USB_INT0,
  43. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  44. },
  45. [2] = { /* DMA IRQ */
  46. .start = IRQ_USB_DMA,
  47. .end = IRQ_USB_DMA,
  48. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  49. },
  50. };
  51. static struct musb_hdrc_config musb_config = {
  52. .multipoint = 0,
  53. .dyn_fifo = 0,
  54. .soft_con = 1,
  55. .dma = 1,
  56. .num_eps = 8,
  57. .dma_channels = 8,
  58. .gpio_vrsel = GPIO_PG13,
  59. };
  60. static struct musb_hdrc_platform_data musb_plat = {
  61. #if defined(CONFIG_USB_MUSB_OTG)
  62. .mode = MUSB_OTG,
  63. #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
  64. .mode = MUSB_HOST,
  65. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  66. .mode = MUSB_PERIPHERAL,
  67. #endif
  68. .config = &musb_config,
  69. };
  70. static u64 musb_dmamask = ~(u32)0;
  71. static struct platform_device musb_device = {
  72. .name = "musb_hdrc",
  73. .id = 0,
  74. .dev = {
  75. .dma_mask = &musb_dmamask,
  76. .coherent_dma_mask = 0xffffffff,
  77. .platform_data = &musb_plat,
  78. },
  79. .num_resources = ARRAY_SIZE(musb_resources),
  80. .resource = musb_resources,
  81. };
  82. #endif
  83. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  84. static struct mtd_partition ezbrd_partitions[] = {
  85. {
  86. .name = "bootloader(nor)",
  87. .size = 0x40000,
  88. .offset = 0,
  89. }, {
  90. .name = "linux kernel(nor)",
  91. .size = 0x1C0000,
  92. .offset = MTDPART_OFS_APPEND,
  93. }, {
  94. .name = "file system(nor)",
  95. .size = MTDPART_SIZ_FULL,
  96. .offset = MTDPART_OFS_APPEND,
  97. }
  98. };
  99. static struct physmap_flash_data ezbrd_flash_data = {
  100. .width = 2,
  101. .parts = ezbrd_partitions,
  102. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  103. };
  104. static struct resource ezbrd_flash_resource = {
  105. .start = 0x20000000,
  106. .end = 0x203fffff,
  107. .flags = IORESOURCE_MEM,
  108. };
  109. static struct platform_device ezbrd_flash_device = {
  110. .name = "physmap-flash",
  111. .id = 0,
  112. .dev = {
  113. .platform_data = &ezbrd_flash_data,
  114. },
  115. .num_resources = 1,
  116. .resource = &ezbrd_flash_resource,
  117. };
  118. #endif
  119. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  120. static struct mtd_partition partition_info[] = {
  121. {
  122. .name = "linux kernel(nand)",
  123. .offset = 0,
  124. .size = 4 * 1024 * 1024,
  125. },
  126. {
  127. .name = "file system(nand)",
  128. .offset = MTDPART_OFS_APPEND,
  129. .size = MTDPART_SIZ_FULL,
  130. },
  131. };
  132. static struct bf5xx_nand_platform bf5xx_nand_platform = {
  133. .page_size = NFC_PG_SIZE_256,
  134. .data_width = NFC_NWIDTH_8,
  135. .partitions = partition_info,
  136. .nr_partitions = ARRAY_SIZE(partition_info),
  137. .rd_dly = 3,
  138. .wr_dly = 3,
  139. };
  140. static struct resource bf5xx_nand_resources[] = {
  141. {
  142. .start = NFC_CTL,
  143. .end = NFC_DATA_RD + 2,
  144. .flags = IORESOURCE_MEM,
  145. },
  146. {
  147. .start = CH_NFC,
  148. .end = CH_NFC,
  149. .flags = IORESOURCE_IRQ,
  150. },
  151. };
  152. static struct platform_device bf5xx_nand_device = {
  153. .name = "bf5xx-nand",
  154. .id = 0,
  155. .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
  156. .resource = bf5xx_nand_resources,
  157. .dev = {
  158. .platform_data = &bf5xx_nand_platform,
  159. },
  160. };
  161. #endif
  162. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  163. static struct platform_device rtc_device = {
  164. .name = "rtc-bfin",
  165. .id = -1,
  166. };
  167. #endif
  168. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  169. static struct platform_device bfin_mii_bus = {
  170. .name = "bfin_mii_bus",
  171. };
  172. static struct platform_device bfin_mac_device = {
  173. .name = "bfin_mac",
  174. .dev.platform_data = &bfin_mii_bus,
  175. };
  176. #endif
  177. #if defined(CONFIG_MTD_M25P80) \
  178. || defined(CONFIG_MTD_M25P80_MODULE)
  179. static struct mtd_partition bfin_spi_flash_partitions[] = {
  180. {
  181. .name = "bootloader(spi)",
  182. .size = 0x00040000,
  183. .offset = 0,
  184. .mask_flags = MTD_CAP_ROM
  185. }, {
  186. .name = "linux kernel(spi)",
  187. .size = MTDPART_SIZ_FULL,
  188. .offset = MTDPART_OFS_APPEND,
  189. }
  190. };
  191. static struct flash_platform_data bfin_spi_flash_data = {
  192. .name = "m25p80",
  193. .parts = bfin_spi_flash_partitions,
  194. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  195. .type = "sst25wf040",
  196. };
  197. /* SPI flash chip (sst25wf040) */
  198. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  199. .enable_dma = 0, /* use dma transfer with this chip*/
  200. .bits_per_word = 8,
  201. };
  202. #endif
  203. #if defined(CONFIG_BFIN_SPI_ADC) \
  204. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  205. /* SPI ADC chip */
  206. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  207. .enable_dma = 1, /* use dma transfer with this chip*/
  208. .bits_per_word = 16,
  209. };
  210. #endif
  211. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  212. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  213. .enable_dma = 0,
  214. .bits_per_word = 8,
  215. };
  216. #endif
  217. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  218. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  219. .enable_dma = 0,
  220. .bits_per_word = 16,
  221. };
  222. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  223. .model = 7877,
  224. .vref_delay_usecs = 50, /* internal, no capacitor */
  225. .x_plate_ohms = 419,
  226. .y_plate_ohms = 486,
  227. .pressure_max = 1000,
  228. .pressure_min = 0,
  229. .stopacq_polarity = 1,
  230. .first_conversion_delay = 3,
  231. .acquisition_time = 1,
  232. .averaging = 1,
  233. .pen_down_acc_interval = 1,
  234. };
  235. #endif
  236. #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
  237. #include <linux/spi/ad7879.h>
  238. static const struct ad7879_platform_data bfin_ad7879_ts_info = {
  239. .model = 7879, /* Model = AD7879 */
  240. .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
  241. .pressure_max = 10000,
  242. .pressure_min = 0,
  243. .first_conversion_delay = 3, /* wait 512us before do a first conversion */
  244. .acquisition_time = 1, /* 4us acquisition time per sample */
  245. .median = 2, /* do 8 measurements */
  246. .averaging = 1, /* take the average of 4 middle samples */
  247. .pen_down_acc_interval = 255, /* 9.4 ms */
  248. .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
  249. .gpio_default = 1, /* During initialization set GPIO = HIGH */
  250. };
  251. #endif
  252. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  253. static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
  254. .enable_dma = 0,
  255. .bits_per_word = 16,
  256. };
  257. #endif
  258. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  259. && defined(CONFIG_SND_SOC_WM8731_SPI)
  260. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  261. .enable_dma = 0,
  262. .bits_per_word = 16,
  263. };
  264. #endif
  265. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  266. static struct bfin5xx_spi_chip spidev_chip_info = {
  267. .enable_dma = 0,
  268. .bits_per_word = 8,
  269. };
  270. #endif
  271. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  272. static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
  273. .enable_dma = 0,
  274. .bits_per_word = 8,
  275. };
  276. #endif
  277. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  278. #if defined(CONFIG_MTD_M25P80) \
  279. || defined(CONFIG_MTD_M25P80_MODULE)
  280. {
  281. /* the modalias must be the same as spi device driver name */
  282. .modalias = "m25p80", /* Name of spi_driver for this device */
  283. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  284. .bus_num = 0, /* Framework bus number */
  285. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  286. .platform_data = &bfin_spi_flash_data,
  287. .controller_data = &spi_flash_chip_info,
  288. .mode = SPI_MODE_3,
  289. },
  290. #endif
  291. #if defined(CONFIG_BFIN_SPI_ADC) \
  292. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  293. {
  294. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  295. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  296. .bus_num = 0, /* Framework bus number */
  297. .chip_select = 1, /* Framework chip select. */
  298. .platform_data = NULL, /* No spi_driver specific config */
  299. .controller_data = &spi_adc_chip_info,
  300. },
  301. #endif
  302. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  303. {
  304. .modalias = "mmc_spi",
  305. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  306. .bus_num = 0,
  307. .chip_select = 5,
  308. .controller_data = &mmc_spi_chip_info,
  309. .mode = SPI_MODE_3,
  310. },
  311. #endif
  312. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  313. {
  314. .modalias = "ad7877",
  315. .platform_data = &bfin_ad7877_ts_info,
  316. .irq = IRQ_PF8,
  317. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  318. .bus_num = 0,
  319. .chip_select = 2,
  320. .controller_data = &spi_ad7877_chip_info,
  321. },
  322. #endif
  323. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  324. {
  325. .modalias = "ad7879",
  326. .platform_data = &bfin_ad7879_ts_info,
  327. .irq = IRQ_PG0,
  328. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  329. .bus_num = 0,
  330. .chip_select = 5,
  331. .controller_data = &spi_ad7879_chip_info,
  332. .mode = SPI_CPHA | SPI_CPOL,
  333. },
  334. #endif
  335. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  336. && defined(CONFIG_SND_SOC_WM8731_SPI)
  337. {
  338. .modalias = "wm8731",
  339. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  340. .bus_num = 0,
  341. .chip_select = 5,
  342. .controller_data = &spi_wm8731_chip_info,
  343. .mode = SPI_MODE_0,
  344. },
  345. #endif
  346. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  347. {
  348. .modalias = "spidev",
  349. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  350. .bus_num = 0,
  351. .chip_select = 1,
  352. .controller_data = &spidev_chip_info,
  353. },
  354. #endif
  355. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  356. {
  357. .modalias = "bfin-lq035q1-spi",
  358. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  359. .bus_num = 0,
  360. .chip_select = 1,
  361. .controller_data = &lq035q1_spi_chip_info,
  362. .mode = SPI_CPHA | SPI_CPOL,
  363. },
  364. #endif
  365. };
  366. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  367. /* SPI controller data */
  368. static struct bfin5xx_spi_master bfin_spi0_info = {
  369. .num_chipselect = 8,
  370. .enable_dma = 1, /* master has the ability to do dma transfer */
  371. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  372. };
  373. /* SPI (0) */
  374. static struct resource bfin_spi0_resource[] = {
  375. [0] = {
  376. .start = SPI0_REGBASE,
  377. .end = SPI0_REGBASE + 0xFF,
  378. .flags = IORESOURCE_MEM,
  379. },
  380. [1] = {
  381. .start = CH_SPI,
  382. .end = CH_SPI,
  383. .flags = IORESOURCE_DMA,
  384. },
  385. [2] = {
  386. .start = IRQ_SPI,
  387. .end = IRQ_SPI,
  388. .flags = IORESOURCE_IRQ,
  389. },
  390. };
  391. static struct platform_device bfin_spi0_device = {
  392. .name = "bfin-spi",
  393. .id = 0, /* Bus number */
  394. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  395. .resource = bfin_spi0_resource,
  396. .dev = {
  397. .platform_data = &bfin_spi0_info, /* Passed to driver */
  398. },
  399. };
  400. #endif /* spi master and devices */
  401. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  402. static struct resource bfin_uart_resources[] = {
  403. #ifdef CONFIG_SERIAL_BFIN_UART0
  404. {
  405. .start = 0xFFC00400,
  406. .end = 0xFFC004FF,
  407. .flags = IORESOURCE_MEM,
  408. },
  409. #endif
  410. #ifdef CONFIG_SERIAL_BFIN_UART1
  411. {
  412. .start = 0xFFC02000,
  413. .end = 0xFFC020FF,
  414. .flags = IORESOURCE_MEM,
  415. },
  416. #endif
  417. };
  418. static struct platform_device bfin_uart_device = {
  419. .name = "bfin-uart",
  420. .id = 1,
  421. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  422. .resource = bfin_uart_resources,
  423. };
  424. #endif
  425. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  426. #ifdef CONFIG_BFIN_SIR0
  427. static struct resource bfin_sir0_resources[] = {
  428. {
  429. .start = 0xFFC00400,
  430. .end = 0xFFC004FF,
  431. .flags = IORESOURCE_MEM,
  432. },
  433. {
  434. .start = IRQ_UART0_RX,
  435. .end = IRQ_UART0_RX+1,
  436. .flags = IORESOURCE_IRQ,
  437. },
  438. {
  439. .start = CH_UART0_RX,
  440. .end = CH_UART0_RX+1,
  441. .flags = IORESOURCE_DMA,
  442. },
  443. };
  444. static struct platform_device bfin_sir0_device = {
  445. .name = "bfin_sir",
  446. .id = 0,
  447. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  448. .resource = bfin_sir0_resources,
  449. };
  450. #endif
  451. #ifdef CONFIG_BFIN_SIR1
  452. static struct resource bfin_sir1_resources[] = {
  453. {
  454. .start = 0xFFC02000,
  455. .end = 0xFFC020FF,
  456. .flags = IORESOURCE_MEM,
  457. },
  458. {
  459. .start = IRQ_UART1_RX,
  460. .end = IRQ_UART1_RX+1,
  461. .flags = IORESOURCE_IRQ,
  462. },
  463. {
  464. .start = CH_UART1_RX,
  465. .end = CH_UART1_RX+1,
  466. .flags = IORESOURCE_DMA,
  467. },
  468. };
  469. static struct platform_device bfin_sir1_device = {
  470. .name = "bfin_sir",
  471. .id = 1,
  472. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  473. .resource = bfin_sir1_resources,
  474. };
  475. #endif
  476. #endif
  477. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  478. static struct resource bfin_twi0_resource[] = {
  479. [0] = {
  480. .start = TWI0_REGBASE,
  481. .end = TWI0_REGBASE,
  482. .flags = IORESOURCE_MEM,
  483. },
  484. [1] = {
  485. .start = IRQ_TWI,
  486. .end = IRQ_TWI,
  487. .flags = IORESOURCE_IRQ,
  488. },
  489. };
  490. static struct platform_device i2c_bfin_twi_device = {
  491. .name = "i2c-bfin-twi",
  492. .id = 0,
  493. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  494. .resource = bfin_twi0_resource,
  495. };
  496. #endif
  497. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  498. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  499. {
  500. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  501. },
  502. #endif
  503. #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
  504. {
  505. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  506. .irq = IRQ_PF8,
  507. },
  508. #endif
  509. };
  510. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  511. static struct platform_device bfin_sport0_uart_device = {
  512. .name = "bfin-sport-uart",
  513. .id = 0,
  514. };
  515. static struct platform_device bfin_sport1_uart_device = {
  516. .name = "bfin-sport-uart",
  517. .id = 1,
  518. };
  519. #endif
  520. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  521. #include <linux/input.h>
  522. #include <linux/gpio_keys.h>
  523. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  524. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  525. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  526. };
  527. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  528. .buttons = bfin_gpio_keys_table,
  529. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  530. };
  531. static struct platform_device bfin_device_gpiokeys = {
  532. .name = "gpio-keys",
  533. .dev = {
  534. .platform_data = &bfin_gpio_keys_data,
  535. },
  536. };
  537. #endif
  538. static const unsigned int cclk_vlev_datasheet[] =
  539. {
  540. VRPAIR(VLEV_100, 400000000),
  541. VRPAIR(VLEV_105, 426000000),
  542. VRPAIR(VLEV_110, 500000000),
  543. VRPAIR(VLEV_115, 533000000),
  544. VRPAIR(VLEV_120, 600000000),
  545. };
  546. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  547. .tuple_tab = cclk_vlev_datasheet,
  548. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  549. .vr_settling_time = 25 /* us */,
  550. };
  551. static struct platform_device bfin_dpmc = {
  552. .name = "bfin dpmc",
  553. .dev = {
  554. .platform_data = &bfin_dmpc_vreg_data,
  555. },
  556. };
  557. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  558. #include <asm/bfin-lq035q1.h>
  559. static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
  560. .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
  561. .use_bl = 1,
  562. .gpio_bl = GPIO_PG12,
  563. };
  564. static struct resource bfin_lq035q1_resources[] = {
  565. {
  566. .start = IRQ_PPI_ERROR,
  567. .end = IRQ_PPI_ERROR,
  568. .flags = IORESOURCE_IRQ,
  569. },
  570. };
  571. static struct platform_device bfin_lq035q1_device = {
  572. .name = "bfin-lq035q1",
  573. .id = -1,
  574. .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
  575. .resource = bfin_lq035q1_resources,
  576. .dev = {
  577. .platform_data = &bfin_lq035q1_data,
  578. },
  579. };
  580. #endif
  581. static struct platform_device *stamp_devices[] __initdata = {
  582. &bfin_dpmc,
  583. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  584. &bf5xx_nand_device,
  585. #endif
  586. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  587. &rtc_device,
  588. #endif
  589. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  590. &musb_device,
  591. #endif
  592. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  593. &bfin_mii_bus,
  594. &bfin_mac_device,
  595. #endif
  596. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  597. &bfin_spi0_device,
  598. #endif
  599. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  600. &bfin_uart_device,
  601. #endif
  602. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  603. &bfin_lq035q1_device,
  604. #endif
  605. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  606. #ifdef CONFIG_BFIN_SIR0
  607. &bfin_sir0_device,
  608. #endif
  609. #ifdef CONFIG_BFIN_SIR1
  610. &bfin_sir1_device,
  611. #endif
  612. #endif
  613. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  614. &i2c_bfin_twi_device,
  615. #endif
  616. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  617. &bfin_sport0_uart_device,
  618. &bfin_sport1_uart_device,
  619. #endif
  620. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  621. &bfin_device_gpiokeys,
  622. #endif
  623. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  624. &ezbrd_flash_device,
  625. #endif
  626. };
  627. static int __init ezbrd_init(void)
  628. {
  629. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  630. i2c_register_board_info(0, bfin_i2c_board_info,
  631. ARRAY_SIZE(bfin_i2c_board_info));
  632. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  633. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  634. return 0;
  635. }
  636. arch_initcall(ezbrd_init);
  637. void native_machine_restart(char *cmd)
  638. {
  639. /* workaround reboot hang when booting from SPI */
  640. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  641. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  642. }
  643. void bfin_get_ether_addr(char *addr)
  644. {
  645. /* the MAC is stored in OTP memory page 0xDF */
  646. u32 ret;
  647. u64 otp_mac;
  648. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  649. ret = otp_read(0xDF, 0x00, &otp_mac);
  650. if (!(ret & 0x1)) {
  651. char *otp_mac_p = (char *)&otp_mac;
  652. for (ret = 0; ret < 6; ++ret)
  653. addr[ret] = otp_mac_p[5 - ret];
  654. }
  655. }
  656. EXPORT_SYMBOL(bfin_get_ether_addr);