ezbrd.c 16 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mtd/mtd.h>
  11. #include <linux/mtd/partitions.h>
  12. #include <linux/mtd/physmap.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/i2c.h>
  16. #include <linux/irq.h>
  17. #include <linux/interrupt.h>
  18. #include <asm/dma.h>
  19. #include <asm/bfin5xx_spi.h>
  20. #include <asm/reboot.h>
  21. #include <asm/portmux.h>
  22. #include <asm/dpmc.h>
  23. #include <asm/bfin_sdh.h>
  24. #include <linux/spi/ad7877.h>
  25. #include <net/dsa.h>
  26. /*
  27. * Name the Board for the /proc/cpuinfo
  28. */
  29. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  30. /*
  31. * Driver needs to know address, irq and flag pin.
  32. */
  33. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  34. static struct mtd_partition ezbrd_partitions[] = {
  35. {
  36. .name = "bootloader(nor)",
  37. .size = 0x40000,
  38. .offset = 0,
  39. }, {
  40. .name = "linux kernel(nor)",
  41. .size = 0x1C0000,
  42. .offset = MTDPART_OFS_APPEND,
  43. }, {
  44. .name = "file system(nor)",
  45. .size = MTDPART_SIZ_FULL,
  46. .offset = MTDPART_OFS_APPEND,
  47. }
  48. };
  49. static struct physmap_flash_data ezbrd_flash_data = {
  50. .width = 2,
  51. .parts = ezbrd_partitions,
  52. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  53. };
  54. static struct resource ezbrd_flash_resource = {
  55. .start = 0x20000000,
  56. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  57. .end = 0x202fffff,
  58. #else
  59. .end = 0x203fffff,
  60. #endif
  61. .flags = IORESOURCE_MEM,
  62. };
  63. static struct platform_device ezbrd_flash_device = {
  64. .name = "physmap-flash",
  65. .id = 0,
  66. .dev = {
  67. .platform_data = &ezbrd_flash_data,
  68. },
  69. .num_resources = 1,
  70. .resource = &ezbrd_flash_resource,
  71. };
  72. #endif
  73. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  74. static struct platform_device rtc_device = {
  75. .name = "rtc-bfin",
  76. .id = -1,
  77. };
  78. #endif
  79. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  80. static struct platform_device bfin_mii_bus = {
  81. .name = "bfin_mii_bus",
  82. };
  83. static struct platform_device bfin_mac_device = {
  84. .name = "bfin_mac",
  85. .dev.platform_data = &bfin_mii_bus,
  86. };
  87. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  88. static struct dsa_chip_data ksz8893m_switch_chip_data = {
  89. .mii_bus = &bfin_mii_bus.dev,
  90. .port_names = {
  91. NULL,
  92. "eth%d",
  93. "eth%d",
  94. "cpu",
  95. },
  96. };
  97. static struct dsa_platform_data ksz8893m_switch_data = {
  98. .nr_chips = 1,
  99. .netdev = &bfin_mac_device.dev,
  100. .chip = &ksz8893m_switch_chip_data,
  101. };
  102. static struct platform_device ksz8893m_switch_device = {
  103. .name = "dsa",
  104. .id = 0,
  105. .num_resources = 0,
  106. .dev.platform_data = &ksz8893m_switch_data,
  107. };
  108. #endif
  109. #endif
  110. #if defined(CONFIG_MTD_M25P80) \
  111. || defined(CONFIG_MTD_M25P80_MODULE)
  112. static struct mtd_partition bfin_spi_flash_partitions[] = {
  113. {
  114. .name = "bootloader(spi)",
  115. .size = 0x00040000,
  116. .offset = 0,
  117. .mask_flags = MTD_CAP_ROM
  118. }, {
  119. .name = "linux kernel(spi)",
  120. .size = MTDPART_SIZ_FULL,
  121. .offset = MTDPART_OFS_APPEND,
  122. }
  123. };
  124. static struct flash_platform_data bfin_spi_flash_data = {
  125. .name = "m25p80",
  126. .parts = bfin_spi_flash_partitions,
  127. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  128. .type = "m25p16",
  129. };
  130. /* SPI flash chip (m25p64) */
  131. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  132. .enable_dma = 0, /* use dma transfer with this chip*/
  133. .bits_per_word = 8,
  134. };
  135. #endif
  136. #if defined(CONFIG_BFIN_SPI_ADC) \
  137. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  138. /* SPI ADC chip */
  139. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  140. .enable_dma = 1, /* use dma transfer with this chip*/
  141. .bits_per_word = 16,
  142. };
  143. #endif
  144. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  145. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  146. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  147. /* SPI SWITCH CHIP */
  148. static struct bfin5xx_spi_chip spi_switch_info = {
  149. .enable_dma = 0,
  150. .bits_per_word = 8,
  151. };
  152. #endif
  153. #endif
  154. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  155. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  156. .enable_dma = 0,
  157. .bits_per_word = 8,
  158. };
  159. #endif
  160. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  161. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  162. .enable_dma = 0,
  163. .bits_per_word = 16,
  164. };
  165. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  166. .model = 7877,
  167. .vref_delay_usecs = 50, /* internal, no capacitor */
  168. .x_plate_ohms = 419,
  169. .y_plate_ohms = 486,
  170. .pressure_max = 1000,
  171. .pressure_min = 0,
  172. .stopacq_polarity = 1,
  173. .first_conversion_delay = 3,
  174. .acquisition_time = 1,
  175. .averaging = 1,
  176. .pen_down_acc_interval = 1,
  177. };
  178. #endif
  179. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  180. && defined(CONFIG_SND_SOC_WM8731_SPI)
  181. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  182. .enable_dma = 0,
  183. .bits_per_word = 16,
  184. };
  185. #endif
  186. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  187. static struct bfin5xx_spi_chip spidev_chip_info = {
  188. .enable_dma = 0,
  189. .bits_per_word = 8,
  190. };
  191. #endif
  192. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  193. #if defined(CONFIG_MTD_M25P80) \
  194. || defined(CONFIG_MTD_M25P80_MODULE)
  195. {
  196. /* the modalias must be the same as spi device driver name */
  197. .modalias = "m25p80", /* Name of spi_driver for this device */
  198. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  199. .bus_num = 0, /* Framework bus number */
  200. .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
  201. .platform_data = &bfin_spi_flash_data,
  202. .controller_data = &spi_flash_chip_info,
  203. .mode = SPI_MODE_3,
  204. },
  205. #endif
  206. #if defined(CONFIG_BFIN_SPI_ADC) \
  207. || defined(CONFIG_BFIN_SPI_ADC_MODULE)
  208. {
  209. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  210. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  211. .bus_num = 0, /* Framework bus number */
  212. .chip_select = 1, /* Framework chip select. */
  213. .platform_data = NULL, /* No spi_driver specific config */
  214. .controller_data = &spi_adc_chip_info,
  215. },
  216. #endif
  217. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  218. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  219. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  220. {
  221. .modalias = "ksz8893m",
  222. .max_speed_hz = 5000000,
  223. .bus_num = 0,
  224. .chip_select = 1,
  225. .platform_data = NULL,
  226. .controller_data = &spi_switch_info,
  227. .mode = SPI_MODE_3,
  228. },
  229. #endif
  230. #endif
  231. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  232. {
  233. .modalias = "mmc_spi",
  234. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  235. .bus_num = 0,
  236. .chip_select = 5,
  237. .controller_data = &mmc_spi_chip_info,
  238. .mode = SPI_MODE_3,
  239. },
  240. #endif
  241. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  242. {
  243. .modalias = "ad7877",
  244. .platform_data = &bfin_ad7877_ts_info,
  245. .irq = IRQ_PF8,
  246. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  247. .bus_num = 0,
  248. .chip_select = 2,
  249. .controller_data = &spi_ad7877_chip_info,
  250. },
  251. #endif
  252. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  253. && defined(CONFIG_SND_SOC_WM8731_SPI)
  254. {
  255. .modalias = "wm8731",
  256. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  257. .bus_num = 0,
  258. .chip_select = 5,
  259. .controller_data = &spi_wm8731_chip_info,
  260. .mode = SPI_MODE_0,
  261. },
  262. #endif
  263. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  264. {
  265. .modalias = "spidev",
  266. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  267. .bus_num = 0,
  268. .chip_select = 1,
  269. .controller_data = &spidev_chip_info,
  270. },
  271. #endif
  272. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  273. {
  274. .modalias = "bfin-lq035q1-spi",
  275. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  276. .bus_num = 0,
  277. .chip_select = 1,
  278. .controller_data = &lq035q1_spi_chip_info,
  279. .mode = SPI_CPHA | SPI_CPOL,
  280. },
  281. #endif
  282. };
  283. /* SPI controller data */
  284. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  285. /* SPI (0) */
  286. static struct bfin5xx_spi_master bfin_spi0_info = {
  287. .num_chipselect = 5,
  288. .enable_dma = 1, /* master has the ability to do dma transfer */
  289. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  290. };
  291. static struct resource bfin_spi0_resource[] = {
  292. [0] = {
  293. .start = SPI0_REGBASE,
  294. .end = SPI0_REGBASE + 0xFF,
  295. .flags = IORESOURCE_MEM,
  296. },
  297. [1] = {
  298. .start = CH_SPI0,
  299. .end = CH_SPI0,
  300. .flags = IORESOURCE_DMA,
  301. },
  302. [2] = {
  303. .start = IRQ_SPI0,
  304. .end = IRQ_SPI0,
  305. .flags = IORESOURCE_IRQ,
  306. },
  307. };
  308. static struct platform_device bfin_spi0_device = {
  309. .name = "bfin-spi",
  310. .id = 0, /* Bus number */
  311. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  312. .resource = bfin_spi0_resource,
  313. .dev = {
  314. .platform_data = &bfin_spi0_info, /* Passed to driver */
  315. },
  316. };
  317. /* SPI (1) */
  318. static struct bfin5xx_spi_master bfin_spi1_info = {
  319. .num_chipselect = 5,
  320. .enable_dma = 1, /* master has the ability to do dma transfer */
  321. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  322. };
  323. static struct resource bfin_spi1_resource[] = {
  324. [0] = {
  325. .start = SPI1_REGBASE,
  326. .end = SPI1_REGBASE + 0xFF,
  327. .flags = IORESOURCE_MEM,
  328. },
  329. [1] = {
  330. .start = CH_SPI1,
  331. .end = CH_SPI1,
  332. .flags = IORESOURCE_DMA,
  333. },
  334. [2] = {
  335. .start = IRQ_SPI1,
  336. .end = IRQ_SPI1,
  337. .flags = IORESOURCE_IRQ,
  338. },
  339. };
  340. static struct platform_device bfin_spi1_device = {
  341. .name = "bfin-spi",
  342. .id = 1, /* Bus number */
  343. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  344. .resource = bfin_spi1_resource,
  345. .dev = {
  346. .platform_data = &bfin_spi1_info, /* Passed to driver */
  347. },
  348. };
  349. #endif /* spi master and devices */
  350. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  351. static struct resource bfin_uart_resources[] = {
  352. #ifdef CONFIG_SERIAL_BFIN_UART0
  353. {
  354. .start = 0xFFC00400,
  355. .end = 0xFFC004FF,
  356. .flags = IORESOURCE_MEM,
  357. },
  358. #endif
  359. #ifdef CONFIG_SERIAL_BFIN_UART1
  360. {
  361. .start = 0xFFC02000,
  362. .end = 0xFFC020FF,
  363. .flags = IORESOURCE_MEM,
  364. },
  365. #endif
  366. };
  367. static struct platform_device bfin_uart_device = {
  368. .name = "bfin-uart",
  369. .id = 1,
  370. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  371. .resource = bfin_uart_resources,
  372. };
  373. #endif
  374. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  375. #ifdef CONFIG_BFIN_SIR0
  376. static struct resource bfin_sir0_resources[] = {
  377. {
  378. .start = 0xFFC00400,
  379. .end = 0xFFC004FF,
  380. .flags = IORESOURCE_MEM,
  381. },
  382. {
  383. .start = IRQ_UART0_RX,
  384. .end = IRQ_UART0_RX+1,
  385. .flags = IORESOURCE_IRQ,
  386. },
  387. {
  388. .start = CH_UART0_RX,
  389. .end = CH_UART0_RX+1,
  390. .flags = IORESOURCE_DMA,
  391. },
  392. };
  393. static struct platform_device bfin_sir0_device = {
  394. .name = "bfin_sir",
  395. .id = 0,
  396. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  397. .resource = bfin_sir0_resources,
  398. };
  399. #endif
  400. #ifdef CONFIG_BFIN_SIR1
  401. static struct resource bfin_sir1_resources[] = {
  402. {
  403. .start = 0xFFC02000,
  404. .end = 0xFFC020FF,
  405. .flags = IORESOURCE_MEM,
  406. },
  407. {
  408. .start = IRQ_UART1_RX,
  409. .end = IRQ_UART1_RX+1,
  410. .flags = IORESOURCE_IRQ,
  411. },
  412. {
  413. .start = CH_UART1_RX,
  414. .end = CH_UART1_RX+1,
  415. .flags = IORESOURCE_DMA,
  416. },
  417. };
  418. static struct platform_device bfin_sir1_device = {
  419. .name = "bfin_sir",
  420. .id = 1,
  421. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  422. .resource = bfin_sir1_resources,
  423. };
  424. #endif
  425. #endif
  426. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  427. static struct resource bfin_twi0_resource[] = {
  428. [0] = {
  429. .start = TWI0_REGBASE,
  430. .end = TWI0_REGBASE,
  431. .flags = IORESOURCE_MEM,
  432. },
  433. [1] = {
  434. .start = IRQ_TWI,
  435. .end = IRQ_TWI,
  436. .flags = IORESOURCE_IRQ,
  437. },
  438. };
  439. static struct platform_device i2c_bfin_twi_device = {
  440. .name = "i2c-bfin-twi",
  441. .id = 0,
  442. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  443. .resource = bfin_twi0_resource,
  444. };
  445. #endif
  446. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  447. #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
  448. {
  449. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  450. },
  451. #endif
  452. #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
  453. {
  454. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  455. .irq = IRQ_PF8,
  456. },
  457. #endif
  458. };
  459. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  460. static struct platform_device bfin_sport0_uart_device = {
  461. .name = "bfin-sport-uart",
  462. .id = 0,
  463. };
  464. static struct platform_device bfin_sport1_uart_device = {
  465. .name = "bfin-sport-uart",
  466. .id = 1,
  467. };
  468. #endif
  469. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  470. #include <linux/input.h>
  471. #include <linux/gpio_keys.h>
  472. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  473. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  474. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  475. };
  476. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  477. .buttons = bfin_gpio_keys_table,
  478. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  479. };
  480. static struct platform_device bfin_device_gpiokeys = {
  481. .name = "gpio-keys",
  482. .dev = {
  483. .platform_data = &bfin_gpio_keys_data,
  484. },
  485. };
  486. #endif
  487. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  488. static struct bfin_sd_host bfin_sdh_data = {
  489. .dma_chan = CH_RSI,
  490. .irq_int0 = IRQ_RSI_INT0,
  491. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  492. };
  493. static struct platform_device bf51x_sdh_device = {
  494. .name = "bfin-sdh",
  495. .id = 0,
  496. .dev = {
  497. .platform_data = &bfin_sdh_data,
  498. },
  499. };
  500. #endif
  501. static const unsigned int cclk_vlev_datasheet[] =
  502. {
  503. VRPAIR(VLEV_100, 400000000),
  504. VRPAIR(VLEV_105, 426000000),
  505. VRPAIR(VLEV_110, 500000000),
  506. VRPAIR(VLEV_115, 533000000),
  507. VRPAIR(VLEV_120, 600000000),
  508. };
  509. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  510. .tuple_tab = cclk_vlev_datasheet,
  511. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  512. .vr_settling_time = 25 /* us */,
  513. };
  514. static struct platform_device bfin_dpmc = {
  515. .name = "bfin dpmc",
  516. .dev = {
  517. .platform_data = &bfin_dmpc_vreg_data,
  518. },
  519. };
  520. static struct platform_device *stamp_devices[] __initdata = {
  521. &bfin_dpmc,
  522. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  523. &rtc_device,
  524. #endif
  525. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  526. &bfin_mii_bus,
  527. &bfin_mac_device,
  528. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  529. &ksz8893m_switch_device,
  530. #endif
  531. #endif
  532. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  533. &bfin_spi0_device,
  534. &bfin_spi1_device,
  535. #endif
  536. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  537. &bfin_uart_device,
  538. #endif
  539. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  540. #ifdef CONFIG_BFIN_SIR0
  541. &bfin_sir0_device,
  542. #endif
  543. #ifdef CONFIG_BFIN_SIR1
  544. &bfin_sir1_device,
  545. #endif
  546. #endif
  547. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  548. &i2c_bfin_twi_device,
  549. #endif
  550. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  551. &bfin_sport0_uart_device,
  552. &bfin_sport1_uart_device,
  553. #endif
  554. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  555. &bfin_device_gpiokeys,
  556. #endif
  557. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  558. &bf51x_sdh_device,
  559. #endif
  560. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  561. &ezbrd_flash_device,
  562. #endif
  563. };
  564. static int __init ezbrd_init(void)
  565. {
  566. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  567. i2c_register_board_info(0, bfin_i2c_board_info,
  568. ARRAY_SIZE(bfin_i2c_board_info));
  569. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  570. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  571. /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
  572. peripheral_request(P_AMS2, "ParaFlash");
  573. #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
  574. peripheral_request(P_AMS3, "ParaFlash");
  575. #endif
  576. return 0;
  577. }
  578. arch_initcall(ezbrd_init);
  579. void native_machine_restart(char *cmd)
  580. {
  581. /* workaround reboot hang when booting from SPI */
  582. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  583. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  584. }
  585. void bfin_get_ether_addr(char *addr)
  586. {
  587. /* the MAC is stored in OTP memory page 0xDF */
  588. u32 ret;
  589. u64 otp_mac;
  590. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  591. ret = otp_read(0xDF, 0x00, &otp_mac);
  592. if (!(ret & 0x1)) {
  593. char *otp_mac_p = (char *)&otp_mac;
  594. for (ret = 0; ret < 6; ++ret)
  595. addr[ret] = otp_mac_p[5 - ret];
  596. }
  597. }
  598. EXPORT_SYMBOL(bfin_get_ether_addr);