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regs-clock.h

regs-clock.h 8.0 KB
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  1. /* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
    2. 

  2.  *
    3. 

  3.  * Copyright 2008 Openmoko, Inc.
    4. 

  4.  * Copyright 2008 Simtec Electronics
    5. 

  5.  *	Ben Dooks <ben@simtec.co.uk>
    6. 

  6.  *	http://armlinux.simtec.co.uk/
    7. 

  7.  *
    8. 

  8.  * S3C64XX clock register definitions
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License version 2 as
    12. 

  12.  * published by the Free Software Foundation.
    13. 

  13. */
    14. 

  14. 

  15. #ifndef __PLAT_REGS_CLOCK_H
    16. 

  16. #define __PLAT_REGS_CLOCK_H __FILE__
    17. 

  17. 

  18. #define S3C_CLKREG(x)		(S3C_VA_SYS + (x))
    19. 

  19. 

  20. #define S3C_APLL_LOCK		S3C_CLKREG(0x00)
    21. 

  21. #define S3C_MPLL_LOCK		S3C_CLKREG(0x04)
    22. 

  22. #define S3C_EPLL_LOCK		S3C_CLKREG(0x08)
    23. 

  23. #define S3C_APLL_CON		S3C_CLKREG(0x0C)
    24. 

  24. #define S3C_MPLL_CON		S3C_CLKREG(0x10)
    25. 

  25. #define S3C_EPLL_CON0		S3C_CLKREG(0x14)
    26. 

  26. #define S3C_EPLL_CON1		S3C_CLKREG(0x18)
    27. 

  27. #define S3C_CLK_SRC		S3C_CLKREG(0x1C)
    28. 

  28. #define S3C_CLK_DIV0		S3C_CLKREG(0x20)
    29. 

  29. #define S3C_CLK_DIV1		S3C_CLKREG(0x24)
    30. 

  30. #define S3C_CLK_DIV2		S3C_CLKREG(0x28)
    31. 

  31. #define S3C_CLK_OUT		S3C_CLKREG(0x2C)
    32. 

  32. #define S3C_HCLK_GATE		S3C_CLKREG(0x30)
    33. 

  33. #define S3C_PCLK_GATE		S3C_CLKREG(0x34)
    34. 

  34. #define S3C_SCLK_GATE		S3C_CLKREG(0x38)
    35. 

  35. #define S3C_MEM0_GATE		S3C_CLKREG(0x3C)
    36. 

  36. 

  37. /* CLKDIV0 */
    38. 

  38. #define S3C6400_CLKDIV0_MFC_MASK	(0xf << 28)
    39. 

  39. #define S3C6400_CLKDIV0_MFC_SHIFT	(28)
    40. 

  40. #define S3C6400_CLKDIV0_JPEG_MASK	(0xf << 24)
    41. 

  41. #define S3C6400_CLKDIV0_JPEG_SHIFT	(24)
    42. 

  42. #define S3C6400_CLKDIV0_CAM_MASK	(0xf << 20)
    43. 

  43. #define S3C6400_CLKDIV0_CAM_SHIFT	(20)
    44. 

  44. #define S3C6400_CLKDIV0_SECURITY_MASK	(0x3 << 18)
    45. 

  45. #define S3C6400_CLKDIV0_SECURITY_SHIFT	(18)
    46. 

  46. #define S3C6400_CLKDIV0_PCLK_MASK	(0xf << 12)
    47. 

  47. #define S3C6400_CLKDIV0_PCLK_SHIFT	(12)
    48. 

  48. #define S3C6400_CLKDIV0_HCLK2_MASK	(0x7 << 9)
    49. 

  49. #define S3C6400_CLKDIV0_HCLK2_SHIFT	(9)
    50. 

  50. #define S3C6400_CLKDIV0_HCLK_MASK	(0x1 << 8)
    51. 

  51. #define S3C6400_CLKDIV0_HCLK_SHIFT	(8)
    52. 

  52. #define S3C6400_CLKDIV0_MPLL_MASK	(0x1 << 4)
    53. 

  53. #define S3C6400_CLKDIV0_MPLL_SHIFT	(4)
    54. 

  54. #define S3C6400_CLKDIV0_ARM_MASK	(0x7 << 0)
    55. 

  55. #define S3C6410_CLKDIV0_ARM_MASK	(0xf << 0)
    56. 

  56. #define S3C6400_CLKDIV0_ARM_SHIFT	(0)
    57. 

  57. 

  58. /* CLKDIV1 */
    59. 

  59. #define S3C6410_CLKDIV1_FIMC_MASK	(0xf << 24)
    60. 

  60. #define S3C6410_CLKDIV1_FIMC_SHIFT	(24)
    61. 

  61. #define S3C6400_CLKDIV1_UHOST_MASK	(0xf << 20)
    62. 

  62. #define S3C6400_CLKDIV1_UHOST_SHIFT	(20)
    63. 

  63. #define S3C6400_CLKDIV1_SCALER_MASK	(0xf << 16)
    64. 

  64. #define S3C6400_CLKDIV1_SCALER_SHIFT	(16)
    65. 

  65. #define S3C6400_CLKDIV1_LCD_MASK	(0xf << 12)
    66. 

  66. #define S3C6400_CLKDIV1_LCD_SHIFT	(12)
    67. 

  67. #define S3C6400_CLKDIV1_MMC2_MASK	(0xf << 8)
    68. 

  68. #define S3C6400_CLKDIV1_MMC2_SHIFT	(8)
    69. 

  69. #define S3C6400_CLKDIV1_MMC1_MASK	(0xf << 4)
    70. 

  70. #define S3C6400_CLKDIV1_MMC1_SHIFT	(4)
    71. 

  71. #define S3C6400_CLKDIV1_MMC0_MASK	(0xf << 0)
    72. 

  72. #define S3C6400_CLKDIV1_MMC0_SHIFT	(0)
    73. 

  73. 

  74. /* CLKDIV2 */
    75. 

  75. #define S3C6410_CLKDIV2_AUDIO2_MASK	(0xf << 24)
    76. 

  76. #define S3C6410_CLKDIV2_AUDIO2_SHIFT	(24)
    77. 

  77. #define S3C6400_CLKDIV2_IRDA_MASK	(0xf << 20)
    78. 

  78. #define S3C6400_CLKDIV2_IRDA_SHIFT	(20)
    79. 

  79. #define S3C6400_CLKDIV2_UART_MASK	(0xf << 16)
    80. 

  80. #define S3C6400_CLKDIV2_UART_SHIFT	(16)
    81. 

  81. #define S3C6400_CLKDIV2_AUDIO1_MASK	(0xf << 12)
    82. 

  82. #define S3C6400_CLKDIV2_AUDIO1_SHIFT	(12)
    83. 

  83. #define S3C6400_CLKDIV2_AUDIO0_MASK	(0xf << 8)
    84. 

  84. #define S3C6400_CLKDIV2_AUDIO0_SHIFT	(8)
    85. 

  85. #define S3C6400_CLKDIV2_SPI1_MASK	(0xf << 4)
    86. 

  86. #define S3C6400_CLKDIV2_SPI1_SHIFT	(4)
    87. 

  87. #define S3C6400_CLKDIV2_SPI0_MASK	(0xf << 0)
    88. 

  88. #define S3C6400_CLKDIV2_SPI0_SHIFT	(0)
    89. 

  89. 

  90. /* HCLK GATE Registers */
    91. 

  91. #define S3C_CLKCON_HCLK_3DSE	(1<<31)
    92. 

  92. #define S3C_CLKCON_HCLK_UHOST	(1<<29)
    93. 

  93. #define S3C_CLKCON_HCLK_SECUR	(1<<28)
    94. 

  94. #define S3C_CLKCON_HCLK_SDMA1	(1<<27)
    95. 

  95. #define S3C_CLKCON_HCLK_SDMA0	(1<<26)
    96. 

  96. #define S3C_CLKCON_HCLK_IROM	(1<<25)
    97. 

  97. #define S3C_CLKCON_HCLK_DDR1	(1<<24)
    98. 

  98. #define S3C_CLKCON_HCLK_DDR0	(1<<23)
    99. 

  99. #define S3C_CLKCON_HCLK_MEM1	(1<<22)
    100. 

  100. #define S3C_CLKCON_HCLK_MEM0	(1<<21)
    101. 

  101. #define S3C_CLKCON_HCLK_USB	(1<<20)
    102. 

  102. #define S3C_CLKCON_HCLK_HSMMC2	(1<<19)
    103. 

  103. #define S3C_CLKCON_HCLK_HSMMC1	(1<<18)
    104. 

  104. #define S3C_CLKCON_HCLK_HSMMC0	(1<<17)
    105. 

  105. #define S3C_CLKCON_HCLK_MDP	(1<<16)
    106. 

  106. #define S3C_CLKCON_HCLK_DHOST	(1<<15)
    107. 

  107. #define S3C_CLKCON_HCLK_IHOST	(1<<14)
    108. 

  108. #define S3C_CLKCON_HCLK_DMA1	(1<<13)
    109. 

  109. #define S3C_CLKCON_HCLK_DMA0	(1<<12)
    110. 

  110. #define S3C_CLKCON_HCLK_JPEG	(1<<11)
    111. 

  111. #define S3C_CLKCON_HCLK_CAMIF	(1<<10)
    112. 

  112. #define S3C_CLKCON_HCLK_SCALER	(1<<9)
    113. 

  113. #define S3C_CLKCON_HCLK_2D	(1<<8)
    114. 

  114. #define S3C_CLKCON_HCLK_TV	(1<<7)
    115. 

  115. #define S3C_CLKCON_HCLK_POST0	(1<<5)
    116. 

  116. #define S3C_CLKCON_HCLK_ROT	(1<<4)
    117. 

  117. #define S3C_CLKCON_HCLK_LCD	(1<<3)
    118. 

  118. #define S3C_CLKCON_HCLK_TZIC	(1<<2)
    119. 

  119. #define S3C_CLKCON_HCLK_INTC	(1<<1)
    120. 

  120. #define S3C_CLKCON_HCLK_MFC	(1<<0)
    121. 

  121. 

  122. /* PCLK GATE Registers */
    123. 

  123. #define S3C6410_CLKCON_PCLK_I2C1	(1<<27)
    124. 

  124. #define S3C6410_CLKCON_PCLK_IIS2	(1<<26)
    125. 

  125. #define S3C_CLKCON_PCLK_SKEY		(1<<24)
    126. 

  126. #define S3C_CLKCON_PCLK_CHIPID		(1<<23)
    127. 

  127. #define S3C_CLKCON_PCLK_SPI1		(1<<22)
    128. 

  128. #define S3C_CLKCON_PCLK_SPI0		(1<<21)
    129. 

  129. #define S3C_CLKCON_PCLK_HSIRX		(1<<20)
    130. 

  130. #define S3C_CLKCON_PCLK_HSITX		(1<<19)
    131. 

  131. #define S3C_CLKCON_PCLK_GPIO		(1<<18)
    132. 

  132. #define S3C_CLKCON_PCLK_IIC		(1<<17)
    133. 

  133. #define S3C_CLKCON_PCLK_IIS1		(1<<16)
    134. 

  134. #define S3C_CLKCON_PCLK_IIS0		(1<<15)
    135. 

  135. #define S3C_CLKCON_PCLK_AC97		(1<<14)
    136. 

  136. #define S3C_CLKCON_PCLK_TZPC		(1<<13)
    137. 

  137. #define S3C_CLKCON_PCLK_TSADC		(1<<12)
    138. 

  138. #define S3C_CLKCON_PCLK_KEYPAD		(1<<11)
    139. 

  139. #define S3C_CLKCON_PCLK_IRDA		(1<<10)
    140. 

  140. #define S3C_CLKCON_PCLK_PCM1		(1<<9)
    141. 

  141. #define S3C_CLKCON_PCLK_PCM0		(1<<8)
    142. 

  142. #define S3C_CLKCON_PCLK_PWM		(1<<7)
    143. 

  143. #define S3C_CLKCON_PCLK_RTC		(1<<6)
    144. 

  144. #define S3C_CLKCON_PCLK_WDT		(1<<5)
    145. 

  145. #define S3C_CLKCON_PCLK_UART3		(1<<4)
    146. 

  146. #define S3C_CLKCON_PCLK_UART2		(1<<3)
    147. 

  147. #define S3C_CLKCON_PCLK_UART1		(1<<2)
    148. 

  148. #define S3C_CLKCON_PCLK_UART0		(1<<1)
    149. 

  149. #define S3C_CLKCON_PCLK_MFC		(1<<0)
    150. 

  150. 

  151. /* SCLK GATE Registers */
    152. 

  152. #define S3C_CLKCON_SCLK_UHOST		(1<<30)
    153. 

  153. #define S3C_CLKCON_SCLK_MMC2_48		(1<<29)
    154. 

  154. #define S3C_CLKCON_SCLK_MMC1_48		(1<<28)
    155. 

  155. #define S3C_CLKCON_SCLK_MMC0_48		(1<<27)
    156. 

  156. #define S3C_CLKCON_SCLK_MMC2		(1<<26)
    157. 

  157. #define S3C_CLKCON_SCLK_MMC1		(1<<25)
    158. 

  158. #define S3C_CLKCON_SCLK_MMC0		(1<<24)
    159. 

  159. #define S3C_CLKCON_SCLK_SPI1_48 	(1<<23)
    160. 

  160. #define S3C_CLKCON_SCLK_SPI0_48 	(1<<22)
    161. 

  161. #define S3C_CLKCON_SCLK_SPI1		(1<<21)
    162. 

  162. #define S3C_CLKCON_SCLK_SPI0		(1<<20)
    163. 

  163. #define S3C_CLKCON_SCLK_DAC27		(1<<19)
    164. 

  164. #define S3C_CLKCON_SCLK_TV27		(1<<18)
    165. 

  165. #define S3C_CLKCON_SCLK_SCALER27	(1<<17)
    166. 

  166. #define S3C_CLKCON_SCLK_SCALER		(1<<16)
    167. 

  167. #define S3C_CLKCON_SCLK_LCD27		(1<<15)
    168. 

  168. #define S3C_CLKCON_SCLK_LCD		(1<<14)
    169. 

  169. #define S3C6400_CLKCON_SCLK_POST1_27	(1<<13)
    170. 

  170. #define S3C6410_CLKCON_FIMC		(1<<13)
    171. 

  171. #define S3C_CLKCON_SCLK_POST0_27	(1<<12)
    172. 

  172. #define S3C6400_CLKCON_SCLK_POST1	(1<<11)
    173. 

  173. #define S3C6410_CLKCON_SCLK_AUDIO2	(1<<11)
    174. 

  174. #define S3C_CLKCON_SCLK_POST0		(1<<10)
    175. 

  175. #define S3C_CLKCON_SCLK_AUDIO1		(1<<9)
    176. 

  176. #define S3C_CLKCON_SCLK_AUDIO0		(1<<8)
    177. 

  177. #define S3C_CLKCON_SCLK_SECUR		(1<<7)
    178. 

  178. #define S3C_CLKCON_SCLK_IRDA		(1<<6)
    179. 

  179. #define S3C_CLKCON_SCLK_UART		(1<<5)
    180. 

  180. #define S3C_CLKCON_SCLK_ONENAND 	(1<<4)
    181. 

  181. #define S3C_CLKCON_SCLK_MFC		(1<<3)
    182. 

  182. #define S3C_CLKCON_SCLK_CAM		(1<<2)
    183. 

  183. #define S3C_CLKCON_SCLK_JPEG		(1<<1)
    184. 

  184. 

  185. /* CLKSRC */
    186. 

  186. 

  187. #define S3C6400_CLKSRC_APLL_MOUT	(1 << 0)
    188. 

  188. #define S3C6400_CLKSRC_MPLL_MOUT	(1 << 1)
    189. 

  189. #define S3C6400_CLKSRC_EPLL_MOUT	(1 << 2)
    190. 

  190. #define S3C6400_CLKSRC_APLL_MOUT_SHIFT	(0)
    191. 

  191. #define S3C6400_CLKSRC_MPLL_MOUT_SHIFT	(1)
    192. 

  192. #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT	(2)
    193. 

  193. #define S3C6400_CLKSRC_MFC		(1 << 4)
    194. 

  194. 

  195. #define S3C6410_CLKSRC_TV27_MASK	(0x1 << 31)
    196. 

  196. #define S3C6410_CLKSRC_TV27_SHIFT	(31)
    197. 

  197. #define S3C6410_CLKSRC_DAC27_MASK	(0x1 << 30)
    198. 

  198. #define S3C6410_CLKSRC_DAC27_SHIFT	(30)
    199. 

  199. #define S3C6400_CLKSRC_SCALER_MASK	(0x3 << 28)
    200. 

  200. #define S3C6400_CLKSRC_SCALER_SHIFT	(28)
    201. 

  201. #define S3C6400_CLKSRC_LCD_MASK		(0x3 << 26)
    202. 

  202. #define S3C6400_CLKSRC_LCD_SHIFT	(26)
    203. 

  203. #define S3C6400_CLKSRC_IRDA_MASK	(0x3 << 24)
    204. 

  204. #define S3C6400_CLKSRC_IRDA_SHIFT	(24)
    205. 

  205. #define S3C6400_CLKSRC_MMC2_MASK	(0x3 << 22)
    206. 

  206. #define S3C6400_CLKSRC_MMC2_SHIFT	(22)
    207. 

  207. #define S3C6400_CLKSRC_MMC1_MASK	(0x3 << 20)
    208. 

  208. #define S3C6400_CLKSRC_MMC1_SHIFT	(20)
    209. 

  209. #define S3C6400_CLKSRC_MMC0_MASK	(0x3 << 18)
    210. 

  210. #define S3C6400_CLKSRC_MMC0_SHIFT	(18)
    211. 

  211. #define S3C6400_CLKSRC_SPI1_MASK	(0x3 << 16)
    212. 

  212. #define S3C6400_CLKSRC_SPI1_SHIFT	(16)
    213. 

  213. #define S3C6400_CLKSRC_SPI0_MASK	(0x3 << 14)
    214. 

  214. #define S3C6400_CLKSRC_SPI0_SHIFT	(14)
    215. 

  215. #define S3C6400_CLKSRC_UART_MASK	(0x1 << 13)
    216. 

  216. #define S3C6400_CLKSRC_UART_SHIFT	(13)
    217. 

  217. #define S3C6400_CLKSRC_AUDIO1_MASK	(0x7 << 10)
    218. 

  218. #define S3C6400_CLKSRC_AUDIO1_SHIFT	(10)
    219. 

  219. #define S3C6400_CLKSRC_AUDIO0_MASK	(0x7 << 7)
    220. 

  220. #define S3C6400_CLKSRC_AUDIO0_SHIFT	(7)
    221. 

  221. #define S3C6400_CLKSRC_UHOST_MASK	(0x3 << 5)
    222. 

  222. #define S3C6400_CLKSRC_UHOST_SHIFT	(5)
    223. 

  223. 

  224. 

  225. #endif /* _PLAT_REGS_CLOCK_H */
    226.