devs.c 10 KB

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  1. /* linux/arch/arm/plat-s3c24xx/devs.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Base S3C24XX platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <asm/mach/arch.h>
  23. #include <asm/mach/map.h>
  24. #include <asm/mach/irq.h>
  25. #include <mach/fb.h>
  26. #include <mach/hardware.h>
  27. #include <mach/dma.h>
  28. #include <mach/irqs.h>
  29. #include <asm/irq.h>
  30. #include <plat/regs-serial.h>
  31. #include <plat/udc.h>
  32. #include <plat/devs.h>
  33. #include <plat/cpu.h>
  34. #include <plat/regs-spi.h>
  35. /* Serial port registrations */
  36. static struct resource s3c2410_uart0_resource[] = {
  37. [0] = {
  38. .start = S3C2410_PA_UART0,
  39. .end = S3C2410_PA_UART0 + 0x3fff,
  40. .flags = IORESOURCE_MEM,
  41. },
  42. [1] = {
  43. .start = IRQ_S3CUART_RX0,
  44. .end = IRQ_S3CUART_ERR0,
  45. .flags = IORESOURCE_IRQ,
  46. }
  47. };
  48. static struct resource s3c2410_uart1_resource[] = {
  49. [0] = {
  50. .start = S3C2410_PA_UART1,
  51. .end = S3C2410_PA_UART1 + 0x3fff,
  52. .flags = IORESOURCE_MEM,
  53. },
  54. [1] = {
  55. .start = IRQ_S3CUART_RX1,
  56. .end = IRQ_S3CUART_ERR1,
  57. .flags = IORESOURCE_IRQ,
  58. }
  59. };
  60. static struct resource s3c2410_uart2_resource[] = {
  61. [0] = {
  62. .start = S3C2410_PA_UART2,
  63. .end = S3C2410_PA_UART2 + 0x3fff,
  64. .flags = IORESOURCE_MEM,
  65. },
  66. [1] = {
  67. .start = IRQ_S3CUART_RX2,
  68. .end = IRQ_S3CUART_ERR2,
  69. .flags = IORESOURCE_IRQ,
  70. }
  71. };
  72. static struct resource s3c2410_uart3_resource[] = {
  73. [0] = {
  74. .start = S3C2443_PA_UART3,
  75. .end = S3C2443_PA_UART3 + 0x3fff,
  76. .flags = IORESOURCE_MEM,
  77. },
  78. [1] = {
  79. .start = IRQ_S3CUART_RX3,
  80. .end = IRQ_S3CUART_ERR3,
  81. .flags = IORESOURCE_IRQ,
  82. },
  83. };
  84. struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
  85. [0] = {
  86. .resources = s3c2410_uart0_resource,
  87. .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
  88. },
  89. [1] = {
  90. .resources = s3c2410_uart1_resource,
  91. .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
  92. },
  93. [2] = {
  94. .resources = s3c2410_uart2_resource,
  95. .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
  96. },
  97. [3] = {
  98. .resources = s3c2410_uart3_resource,
  99. .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
  100. },
  101. };
  102. /* yart devices */
  103. static struct platform_device s3c24xx_uart_device0 = {
  104. .id = 0,
  105. };
  106. static struct platform_device s3c24xx_uart_device1 = {
  107. .id = 1,
  108. };
  109. static struct platform_device s3c24xx_uart_device2 = {
  110. .id = 2,
  111. };
  112. static struct platform_device s3c24xx_uart_device3 = {
  113. .id = 3,
  114. };
  115. struct platform_device *s3c24xx_uart_src[4] = {
  116. &s3c24xx_uart_device0,
  117. &s3c24xx_uart_device1,
  118. &s3c24xx_uart_device2,
  119. &s3c24xx_uart_device3,
  120. };
  121. struct platform_device *s3c24xx_uart_devs[4] = {
  122. };
  123. /* LCD Controller */
  124. static struct resource s3c_lcd_resource[] = {
  125. [0] = {
  126. .start = S3C24XX_PA_LCD,
  127. .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. [1] = {
  131. .start = IRQ_LCD,
  132. .end = IRQ_LCD,
  133. .flags = IORESOURCE_IRQ,
  134. }
  135. };
  136. static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
  137. struct platform_device s3c_device_lcd = {
  138. .name = "s3c2410-lcd",
  139. .id = -1,
  140. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  141. .resource = s3c_lcd_resource,
  142. .dev = {
  143. .dma_mask = &s3c_device_lcd_dmamask,
  144. .coherent_dma_mask = 0xffffffffUL
  145. }
  146. };
  147. EXPORT_SYMBOL(s3c_device_lcd);
  148. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  149. {
  150. struct s3c2410fb_mach_info *npd;
  151. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  152. if (npd) {
  153. memcpy(npd, pd, sizeof(*npd));
  154. s3c_device_lcd.dev.platform_data = npd;
  155. } else {
  156. printk(KERN_ERR "no memory for LCD platform data\n");
  157. }
  158. }
  159. /* USB Device (Gadget)*/
  160. static struct resource s3c_usbgadget_resource[] = {
  161. [0] = {
  162. .start = S3C24XX_PA_USBDEV,
  163. .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
  164. .flags = IORESOURCE_MEM,
  165. },
  166. [1] = {
  167. .start = IRQ_USBD,
  168. .end = IRQ_USBD,
  169. .flags = IORESOURCE_IRQ,
  170. }
  171. };
  172. struct platform_device s3c_device_usbgadget = {
  173. .name = "s3c2410-usbgadget",
  174. .id = -1,
  175. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  176. .resource = s3c_usbgadget_resource,
  177. };
  178. EXPORT_SYMBOL(s3c_device_usbgadget);
  179. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  180. {
  181. struct s3c2410_udc_mach_info *npd;
  182. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  183. if (npd) {
  184. memcpy(npd, pd, sizeof(*npd));
  185. s3c_device_usbgadget.dev.platform_data = npd;
  186. } else {
  187. printk(KERN_ERR "no memory for udc platform data\n");
  188. }
  189. }
  190. /* Watchdog */
  191. static struct resource s3c_wdt_resource[] = {
  192. [0] = {
  193. .start = S3C24XX_PA_WATCHDOG,
  194. .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
  195. .flags = IORESOURCE_MEM,
  196. },
  197. [1] = {
  198. .start = IRQ_WDT,
  199. .end = IRQ_WDT,
  200. .flags = IORESOURCE_IRQ,
  201. }
  202. };
  203. struct platform_device s3c_device_wdt = {
  204. .name = "s3c2410-wdt",
  205. .id = -1,
  206. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  207. .resource = s3c_wdt_resource,
  208. };
  209. EXPORT_SYMBOL(s3c_device_wdt);
  210. /* IIS */
  211. static struct resource s3c_iis_resource[] = {
  212. [0] = {
  213. .start = S3C24XX_PA_IIS,
  214. .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
  215. .flags = IORESOURCE_MEM,
  216. }
  217. };
  218. static u64 s3c_device_iis_dmamask = 0xffffffffUL;
  219. struct platform_device s3c_device_iis = {
  220. .name = "s3c2410-iis",
  221. .id = -1,
  222. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  223. .resource = s3c_iis_resource,
  224. .dev = {
  225. .dma_mask = &s3c_device_iis_dmamask,
  226. .coherent_dma_mask = 0xffffffffUL
  227. }
  228. };
  229. EXPORT_SYMBOL(s3c_device_iis);
  230. /* RTC */
  231. static struct resource s3c_rtc_resource[] = {
  232. [0] = {
  233. .start = S3C24XX_PA_RTC,
  234. .end = S3C24XX_PA_RTC + 0xff,
  235. .flags = IORESOURCE_MEM,
  236. },
  237. [1] = {
  238. .start = IRQ_RTC,
  239. .end = IRQ_RTC,
  240. .flags = IORESOURCE_IRQ,
  241. },
  242. [2] = {
  243. .start = IRQ_TICK,
  244. .end = IRQ_TICK,
  245. .flags = IORESOURCE_IRQ
  246. }
  247. };
  248. struct platform_device s3c_device_rtc = {
  249. .name = "s3c2410-rtc",
  250. .id = -1,
  251. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  252. .resource = s3c_rtc_resource,
  253. };
  254. EXPORT_SYMBOL(s3c_device_rtc);
  255. /* ADC */
  256. static struct resource s3c_adc_resource[] = {
  257. [0] = {
  258. .start = S3C24XX_PA_ADC,
  259. .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
  260. .flags = IORESOURCE_MEM,
  261. },
  262. [1] = {
  263. .start = IRQ_TC,
  264. .end = IRQ_TC,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. [2] = {
  268. .start = IRQ_ADC,
  269. .end = IRQ_ADC,
  270. .flags = IORESOURCE_IRQ,
  271. }
  272. };
  273. struct platform_device s3c_device_adc = {
  274. .name = "s3c24xx-adc",
  275. .id = -1,
  276. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  277. .resource = s3c_adc_resource,
  278. };
  279. /* HWMON */
  280. struct platform_device s3c_device_hwmon = {
  281. .name = "s3c-hwmon",
  282. .id = -1,
  283. .dev.parent = &s3c_device_adc.dev,
  284. };
  285. /* SDI */
  286. static struct resource s3c_sdi_resource[] = {
  287. [0] = {
  288. .start = S3C24XX_PA_SDI,
  289. .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
  290. .flags = IORESOURCE_MEM,
  291. },
  292. [1] = {
  293. .start = IRQ_SDI,
  294. .end = IRQ_SDI,
  295. .flags = IORESOURCE_IRQ,
  296. }
  297. };
  298. struct platform_device s3c_device_sdi = {
  299. .name = "s3c2410-sdi",
  300. .id = -1,
  301. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  302. .resource = s3c_sdi_resource,
  303. };
  304. EXPORT_SYMBOL(s3c_device_sdi);
  305. /* SPI (0) */
  306. static struct resource s3c_spi0_resource[] = {
  307. [0] = {
  308. .start = S3C24XX_PA_SPI,
  309. .end = S3C24XX_PA_SPI + 0x1f,
  310. .flags = IORESOURCE_MEM,
  311. },
  312. [1] = {
  313. .start = IRQ_SPI0,
  314. .end = IRQ_SPI0,
  315. .flags = IORESOURCE_IRQ,
  316. }
  317. };
  318. static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
  319. struct platform_device s3c_device_spi0 = {
  320. .name = "s3c2410-spi",
  321. .id = 0,
  322. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  323. .resource = s3c_spi0_resource,
  324. .dev = {
  325. .dma_mask = &s3c_device_spi0_dmamask,
  326. .coherent_dma_mask = 0xffffffffUL
  327. }
  328. };
  329. EXPORT_SYMBOL(s3c_device_spi0);
  330. /* SPI (1) */
  331. static struct resource s3c_spi1_resource[] = {
  332. [0] = {
  333. .start = S3C24XX_PA_SPI + S3C2410_SPI1,
  334. .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f,
  335. .flags = IORESOURCE_MEM,
  336. },
  337. [1] = {
  338. .start = IRQ_SPI1,
  339. .end = IRQ_SPI1,
  340. .flags = IORESOURCE_IRQ,
  341. }
  342. };
  343. static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
  344. struct platform_device s3c_device_spi1 = {
  345. .name = "s3c2410-spi",
  346. .id = 1,
  347. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  348. .resource = s3c_spi1_resource,
  349. .dev = {
  350. .dma_mask = &s3c_device_spi1_dmamask,
  351. .coherent_dma_mask = 0xffffffffUL
  352. }
  353. };
  354. EXPORT_SYMBOL(s3c_device_spi1);
  355. #ifdef CONFIG_CPU_S3C2440
  356. /* Camif Controller */
  357. static struct resource s3c_camif_resource[] = {
  358. [0] = {
  359. .start = S3C2440_PA_CAMIF,
  360. .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
  361. .flags = IORESOURCE_MEM,
  362. },
  363. [1] = {
  364. .start = IRQ_CAM,
  365. .end = IRQ_CAM,
  366. .flags = IORESOURCE_IRQ,
  367. }
  368. };
  369. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  370. struct platform_device s3c_device_camif = {
  371. .name = "s3c2440-camif",
  372. .id = -1,
  373. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  374. .resource = s3c_camif_resource,
  375. .dev = {
  376. .dma_mask = &s3c_device_camif_dmamask,
  377. .coherent_dma_mask = 0xffffffffUL
  378. }
  379. };
  380. EXPORT_SYMBOL(s3c_device_camif);
  381. /* AC97 */
  382. static struct resource s3c_ac97_resource[] = {
  383. [0] = {
  384. .start = S3C2440_PA_AC97,
  385. .end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1,
  386. .flags = IORESOURCE_MEM,
  387. },
  388. [1] = {
  389. .start = IRQ_S3C244x_AC97,
  390. .end = IRQ_S3C244x_AC97,
  391. .flags = IORESOURCE_IRQ,
  392. },
  393. [2] = {
  394. .name = "PCM out",
  395. .start = DMACH_PCM_OUT,
  396. .end = DMACH_PCM_OUT,
  397. .flags = IORESOURCE_DMA,
  398. },
  399. [3] = {
  400. .name = "PCM in",
  401. .start = DMACH_PCM_IN,
  402. .end = DMACH_PCM_IN,
  403. .flags = IORESOURCE_DMA,
  404. },
  405. [4] = {
  406. .name = "Mic in",
  407. .start = DMACH_MIC_IN,
  408. .end = DMACH_MIC_IN,
  409. .flags = IORESOURCE_DMA,
  410. },
  411. };
  412. static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
  413. struct platform_device s3c_device_ac97 = {
  414. .name = "s3c-ac97",
  415. .id = -1,
  416. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  417. .resource = s3c_ac97_resource,
  418. .dev = {
  419. .dma_mask = &s3c_device_ac97_dmamask,
  420. .coherent_dma_mask = 0xffffffffUL
  421. }
  422. };
  423. EXPORT_SYMBOL(s3c_device_ac97);
  424. #endif // CONFIG_CPU_S32440