uncompress.h 3.9 KB

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  1. /* linux/include/asm-arm/plat-s3c/uncompress.h
  2. *
  3. * Copyright 2003, 2007 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C - uncompress code
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #ifndef __ASM_PLAT_UNCOMPRESS_H
  14. #define __ASM_PLAT_UNCOMPRESS_H
  15. typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
  16. /* uart setup */
  17. static unsigned int fifo_mask;
  18. static unsigned int fifo_max;
  19. /* forward declerations */
  20. static void arch_detect_cpu(void);
  21. /* defines for UART registers */
  22. #include <plat/regs-serial.h>
  23. #include <plat/regs-watchdog.h>
  24. /* working in physical space... */
  25. #undef S3C2410_WDOGREG
  26. #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
  27. /* how many bytes we allow into the FIFO at a time in FIFO mode */
  28. #define FIFO_MAX (14)
  29. #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
  30. static __inline__ void
  31. uart_wr(unsigned int reg, unsigned int val)
  32. {
  33. volatile unsigned int *ptr;
  34. ptr = (volatile unsigned int *)(reg + uart_base);
  35. *ptr = val;
  36. }
  37. static __inline__ unsigned int
  38. uart_rd(unsigned int reg)
  39. {
  40. volatile unsigned int *ptr;
  41. ptr = (volatile unsigned int *)(reg + uart_base);
  42. return *ptr;
  43. }
  44. /* we can deal with the case the UARTs are being run
  45. * in FIFO mode, so that we don't hold up our execution
  46. * waiting for tx to happen...
  47. */
  48. static void putc(int ch)
  49. {
  50. if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
  51. int level;
  52. while (1) {
  53. level = uart_rd(S3C2410_UFSTAT);
  54. level &= fifo_mask;
  55. if (level < fifo_max)
  56. break;
  57. }
  58. } else {
  59. /* not using fifos */
  60. while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
  61. barrier();
  62. }
  63. /* write byte to transmission register */
  64. uart_wr(S3C2410_UTXH, ch);
  65. }
  66. static inline void flush(void)
  67. {
  68. }
  69. #define __raw_writel(d, ad) \
  70. do { \
  71. *((volatile unsigned int __force *)(ad)) = (d); \
  72. } while (0)
  73. /* CONFIG_S3C_BOOT_WATCHDOG
  74. *
  75. * Simple boot-time watchdog setup, to reboot the system if there is
  76. * any problem with the boot process
  77. */
  78. #ifdef CONFIG_S3C_BOOT_WATCHDOG
  79. #define WDOG_COUNT (0xff00)
  80. static inline void arch_decomp_wdog(void)
  81. {
  82. __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  83. }
  84. static void arch_decomp_wdog_start(void)
  85. {
  86. __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
  87. __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  88. __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
  89. }
  90. #else
  91. #define arch_decomp_wdog_start()
  92. #define arch_decomp_wdog()
  93. #endif
  94. #ifdef CONFIG_S3C_BOOT_ERROR_RESET
  95. static void arch_decomp_error(const char *x)
  96. {
  97. putstr("\n\n");
  98. putstr(x);
  99. putstr("\n\n -- System resetting\n");
  100. __raw_writel(0x4000, S3C2410_WTDAT);
  101. __raw_writel(0x4000, S3C2410_WTCNT);
  102. __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
  103. while(1);
  104. }
  105. #define arch_error arch_decomp_error
  106. #endif
  107. static void error(char *err);
  108. #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
  109. static inline void arch_enable_uart_fifo(void)
  110. {
  111. u32 fifocon = uart_rd(S3C2410_UFCON);
  112. if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
  113. fifocon |= S3C2410_UFCON_RESETBOTH;
  114. uart_wr(S3C2410_UFCON, fifocon);
  115. /* wait for fifo reset to complete */
  116. while (1) {
  117. fifocon = uart_rd(S3C2410_UFCON);
  118. if (!(fifocon & S3C2410_UFCON_RESETBOTH))
  119. break;
  120. }
  121. }
  122. }
  123. #else
  124. #define arch_enable_uart_fifo() do { } while(0)
  125. #endif
  126. static void
  127. arch_decomp_setup(void)
  128. {
  129. /* we may need to setup the uart(s) here if we are not running
  130. * on an BAST... the BAST will have left the uarts configured
  131. * after calling linux.
  132. */
  133. arch_detect_cpu();
  134. arch_decomp_wdog_start();
  135. /* Enable the UART FIFOs if they where not enabled and our
  136. * configuration says we should turn them on.
  137. */
  138. arch_enable_uart_fifo();
  139. }
  140. #endif /* __ASM_PLAT_UNCOMPRESS_H */