mx31.h 1.4 KB

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  1. /*
  2. * IRAM
  3. */
  4. #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
  5. #define MX31_IRAM_SIZE SZ_16K
  6. #define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
  7. #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
  8. #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
  9. #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
  10. #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
  11. #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
  12. #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
  13. #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
  14. #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
  15. #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
  16. #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
  17. #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
  18. #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
  19. #define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
  20. #define MXC_INT_MPEG4_ENCODER 5
  21. #define MXC_INT_FIRI 7
  22. #define MX31_INT_MMC_SDHC2 8
  23. #define MXC_INT_MMC_SDHC1 9
  24. #define MX31_INT_SSI2 11
  25. #define MX31_INT_SSI1 12
  26. #define MXC_INT_MBX 16
  27. #define MXC_INT_CSPI3 17
  28. #define MXC_INT_SIM2 20
  29. #define MXC_INT_SIM1 21
  30. #define MXC_INT_CCM_DVFS 31
  31. #define MXC_INT_USB1 35
  32. #define MXC_INT_USB2 36
  33. #define MXC_INT_USB3 37
  34. #define MXC_INT_USB4 38
  35. #define MXC_INT_MSHC2 40
  36. #define MXC_INT_UART4 46
  37. #define MXC_INT_UART5 47
  38. #define MXC_INT_CCM 53
  39. #define MXC_INT_PCMCIA 54