regs-clkctrl.h 2.6 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788
  1. /*
  2. * stmp378x: CLKCTRL register definitions
  3. *
  4. * Copyright (c) 2008 Freescale Semiconductor
  5. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #ifndef _MACH_REGS_CLKCTRL
  22. #define _MACH_REGS_CLKCTRL
  23. #define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
  24. #define REGS_CLKCTRL_PHYS 0x80040000
  25. #define REGS_CLKCTRL_SIZE 0x2000
  26. #define HW_CLKCTRL_PLLCTRL0 0x0
  27. #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
  28. #define HW_CLKCTRL_CPU 0x20
  29. #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
  30. #define BP_CLKCTRL_CPU_DIV_CPU 0
  31. #define HW_CLKCTRL_HBUS 0x30
  32. #define BM_CLKCTRL_HBUS_DIV 0x0000001F
  33. #define BP_CLKCTRL_HBUS_DIV 0
  34. #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
  35. #define HW_CLKCTRL_XBUS 0x40
  36. #define HW_CLKCTRL_XTAL 0x50
  37. #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
  38. #define HW_CLKCTRL_PIX 0x60
  39. #define BM_CLKCTRL_PIX_DIV 0x00000FFF
  40. #define BP_CLKCTRL_PIX_DIV 0
  41. #define BM_CLKCTRL_PIX_CLKGATE 0x80000000
  42. #define HW_CLKCTRL_SSP 0x70
  43. #define HW_CLKCTRL_GPMI 0x80
  44. #define HW_CLKCTRL_SPDIF 0x90
  45. #define HW_CLKCTRL_EMI 0xA0
  46. #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
  47. #define BP_CLKCTRL_EMI_DIV_EMI 0
  48. #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
  49. #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
  50. #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
  51. #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
  52. #define HW_CLKCTRL_IR 0xB0
  53. #define HW_CLKCTRL_SAIF 0xC0
  54. #define HW_CLKCTRL_TV 0xD0
  55. #define HW_CLKCTRL_ETM 0xE0
  56. #define HW_CLKCTRL_FRAC 0xF0
  57. #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
  58. #define BP_CLKCTRL_FRAC_EMIFRAC 8
  59. #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
  60. #define BP_CLKCTRL_FRAC_PIXFRAC 16
  61. #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
  62. #define HW_CLKCTRL_FRAC1 0x100
  63. #define HW_CLKCTRL_CLKSEQ 0x110
  64. #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
  65. #define HW_CLKCTRL_RESET 0x120
  66. #define BM_CLKCTRL_RESET_DIG 0x00000001
  67. #define BP_CLKCTRL_RESET_DIG 0
  68. #endif