mach-qt2410.c 8.0 KB

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  1. /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
  2. *
  3. * Copyright (C) 2006 by OpenMoko, Inc.
  4. * Author: Harald Welte <laforge@openmoko.org>
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/types.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/list.h>
  27. #include <linux/timer.h>
  28. #include <linux/init.h>
  29. #include <linux/gpio.h>
  30. #include <linux/sysdev.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/serial_core.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/spi/spi_bitbang.h>
  35. #include <linux/io.h>
  36. #include <linux/mtd/mtd.h>
  37. #include <linux/mtd/nand.h>
  38. #include <linux/mtd/nand_ecc.h>
  39. #include <linux/mtd/partitions.h>
  40. #include <asm/mach/arch.h>
  41. #include <asm/mach/map.h>
  42. #include <asm/mach/irq.h>
  43. #include <mach/hardware.h>
  44. #include <asm/irq.h>
  45. #include <asm/mach-types.h>
  46. #include <mach/regs-gpio.h>
  47. #include <mach/leds-gpio.h>
  48. #include <plat/regs-serial.h>
  49. #include <mach/fb.h>
  50. #include <plat/nand.h>
  51. #include <plat/udc.h>
  52. #include <mach/spi.h>
  53. #include <mach/spi-gpio.h>
  54. #include <plat/iic.h>
  55. #include <plat/common-smdk.h>
  56. #include <plat/devs.h>
  57. #include <plat/cpu.h>
  58. #include <plat/pm.h>
  59. static struct map_desc qt2410_iodesc[] __initdata = {
  60. { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  61. };
  62. #define UCON S3C2410_UCON_DEFAULT
  63. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  64. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  65. static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  66. [0] = {
  67. .hwport = 0,
  68. .flags = 0,
  69. .ucon = UCON,
  70. .ulcon = ULCON,
  71. .ufcon = UFCON,
  72. },
  73. [1] = {
  74. .hwport = 1,
  75. .flags = 0,
  76. .ucon = UCON,
  77. .ulcon = ULCON,
  78. .ufcon = UFCON,
  79. },
  80. [2] = {
  81. .hwport = 2,
  82. .flags = 0,
  83. .ucon = UCON,
  84. .ulcon = ULCON,
  85. .ufcon = UFCON,
  86. }
  87. };
  88. /* LCD driver info */
  89. static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  90. {
  91. /* Configuration for 640x480 SHARP LQ080V3DG01 */
  92. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  93. S3C2410_LCDCON5_INVVLINE |
  94. S3C2410_LCDCON5_INVVFRAME |
  95. S3C2410_LCDCON5_PWREN |
  96. S3C2410_LCDCON5_HWSWP,
  97. .type = S3C2410_LCDCON1_TFT,
  98. .width = 640,
  99. .height = 480,
  100. .pixclock = 40000, /* HCLK/4 */
  101. .xres = 640,
  102. .yres = 480,
  103. .bpp = 16,
  104. .left_margin = 44,
  105. .right_margin = 116,
  106. .hsync_len = 96,
  107. .upper_margin = 19,
  108. .lower_margin = 11,
  109. .vsync_len = 15,
  110. },
  111. {
  112. /* Configuration for 480x640 toppoly TD028TTEC1 */
  113. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  114. S3C2410_LCDCON5_INVVLINE |
  115. S3C2410_LCDCON5_INVVFRAME |
  116. S3C2410_LCDCON5_PWREN |
  117. S3C2410_LCDCON5_HWSWP,
  118. .type = S3C2410_LCDCON1_TFT,
  119. .width = 480,
  120. .height = 640,
  121. .pixclock = 40000, /* HCLK/4 */
  122. .xres = 480,
  123. .yres = 640,
  124. .bpp = 16,
  125. .left_margin = 8,
  126. .right_margin = 24,
  127. .hsync_len = 8,
  128. .upper_margin = 2,
  129. .lower_margin = 4,
  130. .vsync_len = 2,
  131. },
  132. {
  133. /* Config for 240x320 LCD */
  134. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  135. S3C2410_LCDCON5_INVVLINE |
  136. S3C2410_LCDCON5_INVVFRAME |
  137. S3C2410_LCDCON5_PWREN |
  138. S3C2410_LCDCON5_HWSWP,
  139. .type = S3C2410_LCDCON1_TFT,
  140. .width = 240,
  141. .height = 320,
  142. .pixclock = 100000, /* HCLK/10 */
  143. .xres = 240,
  144. .yres = 320,
  145. .bpp = 16,
  146. .left_margin = 13,
  147. .right_margin = 8,
  148. .hsync_len = 4,
  149. .upper_margin = 2,
  150. .lower_margin = 7,
  151. .vsync_len = 4,
  152. },
  153. };
  154. static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
  155. .displays = qt2410_lcd_cfg,
  156. .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
  157. .default_display = 0,
  158. .lpcsel = ((0xCE6) & ~7) | 1<<4,
  159. };
  160. /* CS8900 */
  161. static struct resource qt2410_cs89x0_resources[] = {
  162. [0] = {
  163. .start = 0x19000000,
  164. .end = 0x19000000 + 16,
  165. .flags = IORESOURCE_MEM,
  166. },
  167. [1] = {
  168. .start = IRQ_EINT9,
  169. .end = IRQ_EINT9,
  170. .flags = IORESOURCE_IRQ,
  171. },
  172. };
  173. static struct platform_device qt2410_cs89x0 = {
  174. .name = "cirrus-cs89x0",
  175. .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
  176. .resource = qt2410_cs89x0_resources,
  177. };
  178. /* LED */
  179. static struct s3c24xx_led_platdata qt2410_pdata_led = {
  180. .gpio = S3C2410_GPB(0),
  181. .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
  182. .name = "led",
  183. .def_trigger = "timer",
  184. };
  185. static struct platform_device qt2410_led = {
  186. .name = "s3c24xx_led",
  187. .id = 0,
  188. .dev = {
  189. .platform_data = &qt2410_pdata_led,
  190. },
  191. };
  192. /* SPI */
  193. static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
  194. {
  195. switch (cs) {
  196. case BITBANG_CS_ACTIVE:
  197. s3c2410_gpio_setpin(S3C2410_GPB(5), 0);
  198. break;
  199. case BITBANG_CS_INACTIVE:
  200. s3c2410_gpio_setpin(S3C2410_GPB(5), 1);
  201. break;
  202. }
  203. }
  204. static struct s3c2410_spigpio_info spi_gpio_cfg = {
  205. .pin_clk = S3C2410_GPG(7),
  206. .pin_mosi = S3C2410_GPG(6),
  207. .pin_miso = S3C2410_GPG(5),
  208. .chip_select = &spi_gpio_cs,
  209. };
  210. static struct platform_device qt2410_spi = {
  211. .name = "s3c24xx-spi-gpio",
  212. .id = 1,
  213. .dev = {
  214. .platform_data = &spi_gpio_cfg,
  215. },
  216. };
  217. /* Board devices */
  218. static struct platform_device *qt2410_devices[] __initdata = {
  219. &s3c_device_usb,
  220. &s3c_device_lcd,
  221. &s3c_device_wdt,
  222. &s3c_device_i2c0,
  223. &s3c_device_iis,
  224. &s3c_device_sdi,
  225. &s3c_device_usbgadget,
  226. &qt2410_spi,
  227. &qt2410_cs89x0,
  228. &qt2410_led,
  229. };
  230. static struct mtd_partition qt2410_nand_part[] = {
  231. [0] = {
  232. .name = "U-Boot",
  233. .size = 0x30000,
  234. .offset = 0,
  235. },
  236. [1] = {
  237. .name = "U-Boot environment",
  238. .offset = 0x30000,
  239. .size = 0x4000,
  240. },
  241. [2] = {
  242. .name = "kernel",
  243. .offset = 0x34000,
  244. .size = SZ_2M,
  245. },
  246. [3] = {
  247. .name = "initrd",
  248. .offset = 0x234000,
  249. .size = SZ_4M,
  250. },
  251. [4] = {
  252. .name = "jffs2",
  253. .offset = 0x634000,
  254. .size = 0x39cc000,
  255. },
  256. };
  257. static struct s3c2410_nand_set qt2410_nand_sets[] = {
  258. [0] = {
  259. .name = "NAND",
  260. .nr_chips = 1,
  261. .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
  262. .partitions = qt2410_nand_part,
  263. },
  264. };
  265. /* choose a set of timings which should suit most 512Mbit
  266. * chips and beyond.
  267. */
  268. static struct s3c2410_platform_nand qt2410_nand_info = {
  269. .tacls = 20,
  270. .twrph0 = 60,
  271. .twrph1 = 20,
  272. .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
  273. .sets = qt2410_nand_sets,
  274. };
  275. /* UDC */
  276. static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
  277. };
  278. static char tft_type = 's';
  279. static int __init qt2410_tft_setup(char *str)
  280. {
  281. tft_type = str[0];
  282. return 1;
  283. }
  284. __setup("tft=", qt2410_tft_setup);
  285. static void __init qt2410_map_io(void)
  286. {
  287. s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
  288. s3c24xx_init_clocks(12*1000*1000);
  289. s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
  290. }
  291. static void __init qt2410_machine_init(void)
  292. {
  293. s3c_device_nand.dev.platform_data = &qt2410_nand_info;
  294. switch (tft_type) {
  295. case 'p': /* production */
  296. qt2410_fb_info.default_display = 1;
  297. break;
  298. case 'b': /* big */
  299. qt2410_fb_info.default_display = 0;
  300. break;
  301. case 's': /* small */
  302. default:
  303. qt2410_fb_info.default_display = 2;
  304. break;
  305. }
  306. s3c24xx_fb_set_platdata(&qt2410_fb_info);
  307. s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
  308. s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
  309. s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
  310. s3c_i2c0_set_platdata(NULL);
  311. s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT);
  312. platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
  313. s3c_pm_init();
  314. }
  315. MACHINE_START(QT2410, "QT2410")
  316. .phys_io = S3C2410_PA_UART,
  317. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  318. .boot_params = S3C2410_SDRAM_PA + 0x100,
  319. .map_io = qt2410_map_io,
  320. .init_irq = s3c24xx_init_irq,
  321. .init_machine = qt2410_machine_init,
  322. .timer = &s3c24xx_timer,
  323. MACHINE_END