Home Explore Help
Register Sign In
phyus
/
linux-vybrid_public
8
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: d461d26dde
Branches Tags
linux-vybrid_pu...
/
arch
/
arm
/
mach-s3c2410
/
include
/
mach
/
regs-mem.h

regs-mem.h 7.5 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230 
  1. /* arch/arm/mach-s3c2410/include/mach/regs-mem.h
    2. 

  2.  *
    3. 

  3.  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
    4. 

  4.  *		http://www.simtec.co.uk/products/SWLINUX/
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  *
    10. 

  10.  * S3C2410 Memory Control register definitions
    11. 

  11. */
    12. 

  12. 

  13. #ifndef __ASM_ARM_MEMREGS_H
    14. 

  14. #define __ASM_ARM_MEMREGS_H
    15. 

  15. 

  16. #ifndef S3C2410_MEMREG
    17. 

  17. #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
    18. 

  18. #endif
    19. 

  19. 

  20. /* bus width, and wait state control */
    21. 

  21. #define S3C2410_BWSCON			S3C2410_MEMREG(0x0000)
    22. 

  22. 

  23. /* bank zero config - note, pinstrapped from OM pins! */
    24. 

  24. #define S3C2410_BWSCON_DW0_16		(1<<1)
    25. 

  25. #define S3C2410_BWSCON_DW0_32		(2<<1)
    26. 

  26. 

  27. /* bank one configs */
    28. 

  28. #define S3C2410_BWSCON_DW1_8		(0<<4)
    29. 

  29. #define S3C2410_BWSCON_DW1_16		(1<<4)
    30. 

  30. #define S3C2410_BWSCON_DW1_32		(2<<4)
    31. 

  31. #define S3C2410_BWSCON_WS1		(1<<6)
    32. 

  32. #define S3C2410_BWSCON_ST1		(1<<7)
    33. 

  33. 

  34. /* bank 2 configurations */
    35. 

  35. #define S3C2410_BWSCON_DW2_8		(0<<8)
    36. 

  36. #define S3C2410_BWSCON_DW2_16		(1<<8)
    37. 

  37. #define S3C2410_BWSCON_DW2_32		(2<<8)
    38. 

  38. #define S3C2410_BWSCON_WS2		(1<<10)
    39. 

  39. #define S3C2410_BWSCON_ST2		(1<<11)
    40. 

  40. 

  41. /* bank 3 configurations */
    42. 

  42. #define S3C2410_BWSCON_DW3_8		(0<<12)
    43. 

  43. #define S3C2410_BWSCON_DW3_16		(1<<12)
    44. 

  44. #define S3C2410_BWSCON_DW3_32		(2<<12)
    45. 

  45. #define S3C2410_BWSCON_WS3		(1<<14)
    46. 

  46. #define S3C2410_BWSCON_ST3		(1<<15)
    47. 

  47. 

  48. /* bank 4 configurations */
    49. 

  49. #define S3C2410_BWSCON_DW4_8		(0<<16)
    50. 

  50. #define S3C2410_BWSCON_DW4_16		(1<<16)
    51. 

  51. #define S3C2410_BWSCON_DW4_32		(2<<16)
    52. 

  52. #define S3C2410_BWSCON_WS4		(1<<18)
    53. 

  53. #define S3C2410_BWSCON_ST4		(1<<19)
    54. 

  54. 

  55. /* bank 5 configurations */
    56. 

  56. #define S3C2410_BWSCON_DW5_8		(0<<20)
    57. 

  57. #define S3C2410_BWSCON_DW5_16		(1<<20)
    58. 

  58. #define S3C2410_BWSCON_DW5_32		(2<<20)
    59. 

  59. #define S3C2410_BWSCON_WS5		(1<<22)
    60. 

  60. #define S3C2410_BWSCON_ST5		(1<<23)
    61. 

  61. 

  62. /* bank 6 configurations */
    63. 

  63. #define S3C2410_BWSCON_DW6_8		(0<<24)
    64. 

  64. #define S3C2410_BWSCON_DW6_16		(1<<24)
    65. 

  65. #define S3C2410_BWSCON_DW6_32		(2<<24)
    66. 

  66. #define S3C2410_BWSCON_WS6		(1<<26)
    67. 

  67. #define S3C2410_BWSCON_ST6		(1<<27)
    68. 

  68. 

  69. /* bank 7 configurations */
    70. 

  70. #define S3C2410_BWSCON_DW7_8		(0<<28)
    71. 

  71. #define S3C2410_BWSCON_DW7_16		(1<<28)
    72. 

  72. #define S3C2410_BWSCON_DW7_32		(2<<28)
    73. 

  73. #define S3C2410_BWSCON_WS7		(1<<30)
    74. 

  74. #define S3C2410_BWSCON_ST7		(1<<31)
    75. 

  75. 

  76. /* accesor functions for getting BANK(n) configuration. (n != 0) */
    77. 

  77. 

  78. #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
    79. 

  79. 

  80. #define S3C2410_BWSCON_DW8		(0)
    81. 

  81. #define S3C2410_BWSCON_DW16		(1)
    82. 

  82. #define S3C2410_BWSCON_DW32		(2)
    83. 

  83. #define S3C2410_BWSCON_WS		(1 << 2)
    84. 

  84. #define S3C2410_BWSCON_ST		(1 << 3)
    85. 

  85. 

  86. /* memory set (rom, ram) */
    87. 

  87. #define S3C2410_BANKCON0		S3C2410_MEMREG(0x0004)
    88. 

  88. #define S3C2410_BANKCON1		S3C2410_MEMREG(0x0008)
    89. 

  89. #define S3C2410_BANKCON2		S3C2410_MEMREG(0x000C)
    90. 

  90. #define S3C2410_BANKCON3		S3C2410_MEMREG(0x0010)
    91. 

  91. #define S3C2410_BANKCON4		S3C2410_MEMREG(0x0014)
    92. 

  92. #define S3C2410_BANKCON5		S3C2410_MEMREG(0x0018)
    93. 

  93. #define S3C2410_BANKCON6		S3C2410_MEMREG(0x001C)
    94. 

  94. #define S3C2410_BANKCON7		S3C2410_MEMREG(0x0020)
    95. 

  95. 

  96. /* bank configuration registers */
    97. 

  97. 

  98. #define S3C2410_BANKCON_PMCnorm		(0x00)
    99. 

  99. #define S3C2410_BANKCON_PMC4		(0x01)
    100. 

  100. #define S3C2410_BANKCON_PMC8		(0x02)
    101. 

  101. #define S3C2410_BANKCON_PMC16		(0x03)
    102. 

  102. 

  103. /* bank configurations for banks 0..7, note banks
    104. 

  104.  * 6 and 7 have differnt configurations depending on
    105. 

  105.  * the memory type bits */
    106. 

  106. 

  107. #define S3C2410_BANKCON_Tacp2		(0x0 << 2)
    108. 

  108. #define S3C2410_BANKCON_Tacp3		(0x1 << 2)
    109. 

  109. #define S3C2410_BANKCON_Tacp4		(0x2 << 2)
    110. 

  110. #define S3C2410_BANKCON_Tacp6		(0x3 << 2)
    111. 

  111. #define S3C2410_BANKCON_Tacp_SHIFT	(2)
    112. 

  112. 

  113. #define S3C2410_BANKCON_Tcah0		(0x0 << 4)
    114. 

  114. #define S3C2410_BANKCON_Tcah1		(0x1 << 4)
    115. 

  115. #define S3C2410_BANKCON_Tcah2		(0x2 << 4)
    116. 

  116. #define S3C2410_BANKCON_Tcah4		(0x3 << 4)
    117. 

  117. #define S3C2410_BANKCON_Tcah_SHIFT	(4)
    118. 

  118. 

  119. #define S3C2410_BANKCON_Tcoh0		(0x0 << 6)
    120. 

  120. #define S3C2410_BANKCON_Tcoh1		(0x1 << 6)
    121. 

  121. #define S3C2410_BANKCON_Tcoh2		(0x2 << 6)
    122. 

  122. #define S3C2410_BANKCON_Tcoh4		(0x3 << 6)
    123. 

  123. #define S3C2410_BANKCON_Tcoh_SHIFT	(6)
    124. 

  124. 

  125. #define S3C2410_BANKCON_Tacc1		(0x0 << 8)
    126. 

  126. #define S3C2410_BANKCON_Tacc2		(0x1 << 8)
    127. 

  127. #define S3C2410_BANKCON_Tacc3		(0x2 << 8)
    128. 

  128. #define S3C2410_BANKCON_Tacc4		(0x3 << 8)
    129. 

  129. #define S3C2410_BANKCON_Tacc6		(0x4 << 8)
    130. 

  130. #define S3C2410_BANKCON_Tacc8		(0x5 << 8)
    131. 

  131. #define S3C2410_BANKCON_Tacc10		(0x6 << 8)
    132. 

  132. #define S3C2410_BANKCON_Tacc14		(0x7 << 8)
    133. 

  133. #define S3C2410_BANKCON_Tacc_SHIFT	(8)
    134. 

  134. 

  135. #define S3C2410_BANKCON_Tcos0		(0x0 << 11)
    136. 

  136. #define S3C2410_BANKCON_Tcos1		(0x1 << 11)
    137. 

  137. #define S3C2410_BANKCON_Tcos2		(0x2 << 11)
    138. 

  138. #define S3C2410_BANKCON_Tcos4		(0x3 << 11)
    139. 

  139. #define S3C2410_BANKCON_Tcos_SHIFT	(11)
    140. 

  140. 

  141. #define S3C2410_BANKCON_Tacs0		(0x0 << 13)
    142. 

  142. #define S3C2410_BANKCON_Tacs1		(0x1 << 13)
    143. 

  143. #define S3C2410_BANKCON_Tacs2		(0x2 << 13)
    144. 

  144. #define S3C2410_BANKCON_Tacs4		(0x3 << 13)
    145. 

  145. #define S3C2410_BANKCON_Tacs_SHIFT	(13)
    146. 

  146. 

  147. #define S3C2410_BANKCON_SRAM		(0x0 << 15)
    148. 

  148. #define S3C2400_BANKCON_EDODRAM		(0x2 << 15)
    149. 

  149. #define S3C2410_BANKCON_SDRAM		(0x3 << 15)
    150. 

  150. 

  151. /* next bits only for EDO DRAM in 6,7 */
    152. 

  152. #define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
    153. 

  153. #define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
    154. 

  154. #define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
    155. 

  155. #define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)
    156. 

  156. 

  157. /* CAS pulse width */
    158. 

  158. #define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
    159. 

  159. #define S3C2400_BANKCON_EDO_PULSE2     (0x01 << 3)
    160. 

  160. 

  161. /* CAS pre-charge */
    162. 

  162. #define S3C2400_BANKCON_EDO_TCP1       (0x00 << 2)
    163. 

  163. #define S3C2400_BANKCON_EDO_TCP2       (0x01 << 2)
    164. 

  164. 

  165. /* control column address select */
    166. 

  166. #define S3C2400_BANKCON_EDO_SCANb8     (0x00 << 0)
    167. 

  167. #define S3C2400_BANKCON_EDO_SCANb9     (0x01 << 0)
    168. 

  168. #define S3C2400_BANKCON_EDO_SCANb10    (0x02 << 0)
    169. 

  169. #define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
    170. 

  170. 

  171. /* next bits only for SDRAM in 6,7 */
    172. 

  172. #define S3C2410_BANKCON_Trcd2		(0x00 << 2)
    173. 

  173. #define S3C2410_BANKCON_Trcd3		(0x01 << 2)
    174. 

  174. #define S3C2410_BANKCON_Trcd4		(0x02 << 2)
    175. 

  175. 

  176. /* control column address select */
    177. 

  177. #define S3C2410_BANKCON_SCANb8		(0x00 << 0)
    178. 

  178. #define S3C2410_BANKCON_SCANb9		(0x01 << 0)
    179. 

  179. #define S3C2410_BANKCON_SCANb10		(0x02 << 0)
    180. 

  180. 

  181. #define S3C2410_REFRESH			S3C2410_MEMREG(0x0024)
    182. 

  182. #define S3C2410_BANKSIZE		S3C2410_MEMREG(0x0028)
    183. 

  183. #define S3C2410_MRSRB6			S3C2410_MEMREG(0x002C)
    184. 

  184. #define S3C2410_MRSRB7			S3C2410_MEMREG(0x0030)
    185. 

  185. 

  186. /* refresh control */
    187. 

  187. 

  188. #define S3C2410_REFRESH_REFEN		(1<<23)
    189. 

  189. #define S3C2410_REFRESH_SELF		(1<<22)
    190. 

  190. #define S3C2410_REFRESH_REFCOUNTER	((1<<11)-1)
    191. 

  191. 

  192. #define S3C2410_REFRESH_TRP_MASK	(3<<20)
    193. 

  193. #define S3C2410_REFRESH_TRP_2clk	(0<<20)
    194. 

  194. #define S3C2410_REFRESH_TRP_3clk	(1<<20)
    195. 

  195. #define S3C2410_REFRESH_TRP_4clk	(2<<20)
    196. 

  196. 

  197. #define S3C2400_REFRESH_DRAM_TRP_MASK   (3<<20)
    198. 

  198. #define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
    199. 

  199. #define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
    200. 

  200. #define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
    201. 

  201. #define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
    202. 

  202. 

  203. #define S3C2410_REFRESH_TSRC_MASK	(3<<18)
    204. 

  204. #define S3C2410_REFRESH_TSRC_4clk	(0<<18)
    205. 

  205. #define S3C2410_REFRESH_TSRC_5clk	(1<<18)
    206. 

  206. #define S3C2410_REFRESH_TSRC_6clk	(2<<18)
    207. 

  207. #define S3C2410_REFRESH_TSRC_7clk	(3<<18)
    208. 

  208. 

  209. 

  210. /* mode select register(s) */
    211. 

  211. 

  212. #define  S3C2410_MRSRB_CL1		(0x00 << 4)
    213. 

  213. #define  S3C2410_MRSRB_CL2		(0x02 << 4)
    214. 

  214. #define  S3C2410_MRSRB_CL3		(0x03 << 4)
    215. 

  215. 

  216. /* bank size register */
    217. 

  217. #define S3C2410_BANKSIZE_128M		(0x2 << 0)
    218. 

  218. #define S3C2410_BANKSIZE_64M		(0x1 << 0)
    219. 

  219. #define S3C2410_BANKSIZE_32M		(0x0 << 0)
    220. 

  220. #define S3C2410_BANKSIZE_16M		(0x7 << 0)
    221. 

  221. #define S3C2410_BANKSIZE_8M		(0x6 << 0)
    222. 

  222. #define S3C2410_BANKSIZE_4M		(0x5 << 0)
    223. 

  223. #define S3C2410_BANKSIZE_2M		(0x4 << 0)
    224. 

  224. #define S3C2410_BANKSIZE_MASK		(0x7 << 0)
    225. 

  225. #define S3C2400_BANKSIZE_MASK           (0x4 << 0)
    226. 

  226. #define S3C2410_BANKSIZE_SCLK_EN	(1<<4)
    227. 

  227. #define S3C2410_BANKSIZE_SCKE_EN	(1<<5)
    228. 

  228. #define S3C2410_BANKSIZE_BURST		(1<<7)
    229. 

  229. 

  230. #endif /* __ASM_ARM_MEMREGS_H */
    231.