mainstone.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645
  1. /*
  2. * linux/arch/arm/mach-pxa/mainstone.c
  3. *
  4. * Support for the Intel HCDDBBVA0 Development Platform.
  5. * (go figure how they came up with such name...)
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/input.h>
  26. #include <linux/gpio_keys.h>
  27. #include <linux/pwm_backlight.h>
  28. #include <linux/smc91x.h>
  29. #include <asm/types.h>
  30. #include <asm/setup.h>
  31. #include <asm/memory.h>
  32. #include <asm/mach-types.h>
  33. #include <mach/hardware.h>
  34. #include <asm/irq.h>
  35. #include <asm/sizes.h>
  36. #include <asm/mach/arch.h>
  37. #include <asm/mach/map.h>
  38. #include <asm/mach/irq.h>
  39. #include <asm/mach/flash.h>
  40. #include <mach/pxa27x.h>
  41. #include <mach/gpio.h>
  42. #include <mach/mainstone.h>
  43. #include <mach/audio.h>
  44. #include <mach/pxafb.h>
  45. #include <plat/i2c.h>
  46. #include <mach/mmc.h>
  47. #include <mach/irda.h>
  48. #include <mach/ohci.h>
  49. #include <mach/pxa27x_keypad.h>
  50. #include "generic.h"
  51. #include "devices.h"
  52. static unsigned long mainstone_pin_config[] = {
  53. /* Chip Select */
  54. GPIO15_nCS_1,
  55. /* LCD - 16bpp Active TFT */
  56. GPIO58_LCD_LDD_0,
  57. GPIO59_LCD_LDD_1,
  58. GPIO60_LCD_LDD_2,
  59. GPIO61_LCD_LDD_3,
  60. GPIO62_LCD_LDD_4,
  61. GPIO63_LCD_LDD_5,
  62. GPIO64_LCD_LDD_6,
  63. GPIO65_LCD_LDD_7,
  64. GPIO66_LCD_LDD_8,
  65. GPIO67_LCD_LDD_9,
  66. GPIO68_LCD_LDD_10,
  67. GPIO69_LCD_LDD_11,
  68. GPIO70_LCD_LDD_12,
  69. GPIO71_LCD_LDD_13,
  70. GPIO72_LCD_LDD_14,
  71. GPIO73_LCD_LDD_15,
  72. GPIO74_LCD_FCLK,
  73. GPIO75_LCD_LCLK,
  74. GPIO76_LCD_PCLK,
  75. GPIO77_LCD_BIAS,
  76. GPIO16_PWM0_OUT, /* Backlight */
  77. /* MMC */
  78. GPIO32_MMC_CLK,
  79. GPIO112_MMC_CMD,
  80. GPIO92_MMC_DAT_0,
  81. GPIO109_MMC_DAT_1,
  82. GPIO110_MMC_DAT_2,
  83. GPIO111_MMC_DAT_3,
  84. /* USB Host Port 1 */
  85. GPIO88_USBH1_PWR,
  86. GPIO89_USBH1_PEN,
  87. /* PC Card */
  88. GPIO48_nPOE,
  89. GPIO49_nPWE,
  90. GPIO50_nPIOR,
  91. GPIO51_nPIOW,
  92. GPIO85_nPCE_1,
  93. GPIO54_nPCE_2,
  94. GPIO79_PSKTSEL,
  95. GPIO55_nPREG,
  96. GPIO56_nPWAIT,
  97. GPIO57_nIOIS16,
  98. /* AC97 */
  99. GPIO45_AC97_SYSCLK,
  100. /* Keypad */
  101. GPIO93_KP_DKIN_0,
  102. GPIO94_KP_DKIN_1,
  103. GPIO95_KP_DKIN_2,
  104. GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
  105. GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
  106. GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
  107. GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
  108. GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
  109. GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
  110. GPIO103_KP_MKOUT_0,
  111. GPIO104_KP_MKOUT_1,
  112. GPIO105_KP_MKOUT_2,
  113. GPIO106_KP_MKOUT_3,
  114. GPIO107_KP_MKOUT_4,
  115. GPIO108_KP_MKOUT_5,
  116. GPIO96_KP_MKOUT_6,
  117. /* I2C */
  118. GPIO117_I2C_SCL,
  119. GPIO118_I2C_SDA,
  120. /* GPIO */
  121. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  122. };
  123. static unsigned long mainstone_irq_enabled;
  124. static void mainstone_mask_irq(unsigned int irq)
  125. {
  126. int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  127. MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
  128. }
  129. static void mainstone_unmask_irq(unsigned int irq)
  130. {
  131. int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  132. /* the irq can be acknowledged only if deasserted, so it's done here */
  133. MST_INTSETCLR &= ~(1 << mainstone_irq);
  134. MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
  135. }
  136. static struct irq_chip mainstone_irq_chip = {
  137. .name = "FPGA",
  138. .ack = mainstone_mask_irq,
  139. .mask = mainstone_mask_irq,
  140. .unmask = mainstone_unmask_irq,
  141. };
  142. static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
  143. {
  144. unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
  145. do {
  146. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  147. if (likely(pending)) {
  148. irq = MAINSTONE_IRQ(0) + __ffs(pending);
  149. generic_handle_irq(irq);
  150. }
  151. pending = MST_INTSETCLR & mainstone_irq_enabled;
  152. } while (pending);
  153. }
  154. static void __init mainstone_init_irq(void)
  155. {
  156. int irq;
  157. pxa27x_init_irq();
  158. /* setup extra Mainstone irqs */
  159. for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
  160. set_irq_chip(irq, &mainstone_irq_chip);
  161. set_irq_handler(irq, handle_level_irq);
  162. if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
  163. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
  164. else
  165. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  166. }
  167. set_irq_flags(MAINSTONE_IRQ(8), 0);
  168. set_irq_flags(MAINSTONE_IRQ(12), 0);
  169. MST_INTMSKENA = 0;
  170. MST_INTSETCLR = 0;
  171. set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
  172. set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
  173. }
  174. #ifdef CONFIG_PM
  175. static int mainstone_irq_resume(struct sys_device *dev)
  176. {
  177. MST_INTMSKENA = mainstone_irq_enabled;
  178. return 0;
  179. }
  180. static struct sysdev_class mainstone_irq_sysclass = {
  181. .name = "cpld_irq",
  182. .resume = mainstone_irq_resume,
  183. };
  184. static struct sys_device mainstone_irq_device = {
  185. .cls = &mainstone_irq_sysclass,
  186. };
  187. static int __init mainstone_irq_device_init(void)
  188. {
  189. int ret = -ENODEV;
  190. if (machine_is_mainstone()) {
  191. ret = sysdev_class_register(&mainstone_irq_sysclass);
  192. if (ret == 0)
  193. ret = sysdev_register(&mainstone_irq_device);
  194. }
  195. return ret;
  196. }
  197. device_initcall(mainstone_irq_device_init);
  198. #endif
  199. static struct resource smc91x_resources[] = {
  200. [0] = {
  201. .start = (MST_ETH_PHYS + 0x300),
  202. .end = (MST_ETH_PHYS + 0xfffff),
  203. .flags = IORESOURCE_MEM,
  204. },
  205. [1] = {
  206. .start = MAINSTONE_IRQ(3),
  207. .end = MAINSTONE_IRQ(3),
  208. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  209. }
  210. };
  211. static struct smc91x_platdata mainstone_smc91x_info = {
  212. .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
  213. SMC91X_NOWAIT | SMC91X_USE_DMA,
  214. };
  215. static struct platform_device smc91x_device = {
  216. .name = "smc91x",
  217. .id = 0,
  218. .num_resources = ARRAY_SIZE(smc91x_resources),
  219. .resource = smc91x_resources,
  220. .dev = {
  221. .platform_data = &mainstone_smc91x_info,
  222. },
  223. };
  224. static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
  225. {
  226. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  227. MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
  228. return 0;
  229. }
  230. static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
  231. {
  232. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  233. MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
  234. }
  235. static long mst_audio_suspend_mask;
  236. static void mst_audio_suspend(void *priv)
  237. {
  238. mst_audio_suspend_mask = MST_MSCWR2;
  239. MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
  240. }
  241. static void mst_audio_resume(void *priv)
  242. {
  243. MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
  244. }
  245. static pxa2xx_audio_ops_t mst_audio_ops = {
  246. .startup = mst_audio_startup,
  247. .shutdown = mst_audio_shutdown,
  248. .suspend = mst_audio_suspend,
  249. .resume = mst_audio_resume,
  250. };
  251. static struct resource flash_resources[] = {
  252. [0] = {
  253. .start = PXA_CS0_PHYS,
  254. .end = PXA_CS0_PHYS + SZ_64M - 1,
  255. .flags = IORESOURCE_MEM,
  256. },
  257. [1] = {
  258. .start = PXA_CS1_PHYS,
  259. .end = PXA_CS1_PHYS + SZ_64M - 1,
  260. .flags = IORESOURCE_MEM,
  261. },
  262. };
  263. static struct mtd_partition mainstoneflash0_partitions[] = {
  264. {
  265. .name = "Bootloader",
  266. .size = 0x00040000,
  267. .offset = 0,
  268. .mask_flags = MTD_WRITEABLE /* force read-only */
  269. },{
  270. .name = "Kernel",
  271. .size = 0x00400000,
  272. .offset = 0x00040000,
  273. },{
  274. .name = "Filesystem",
  275. .size = MTDPART_SIZ_FULL,
  276. .offset = 0x00440000
  277. }
  278. };
  279. static struct flash_platform_data mst_flash_data[2] = {
  280. {
  281. .map_name = "cfi_probe",
  282. .parts = mainstoneflash0_partitions,
  283. .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
  284. }, {
  285. .map_name = "cfi_probe",
  286. .parts = NULL,
  287. .nr_parts = 0,
  288. }
  289. };
  290. static struct platform_device mst_flash_device[2] = {
  291. {
  292. .name = "pxa2xx-flash",
  293. .id = 0,
  294. .dev = {
  295. .platform_data = &mst_flash_data[0],
  296. },
  297. .resource = &flash_resources[0],
  298. .num_resources = 1,
  299. },
  300. {
  301. .name = "pxa2xx-flash",
  302. .id = 1,
  303. .dev = {
  304. .platform_data = &mst_flash_data[1],
  305. },
  306. .resource = &flash_resources[1],
  307. .num_resources = 1,
  308. },
  309. };
  310. #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
  311. static struct platform_pwm_backlight_data mainstone_backlight_data = {
  312. .pwm_id = 0,
  313. .max_brightness = 1023,
  314. .dft_brightness = 1023,
  315. .pwm_period_ns = 78770,
  316. };
  317. static struct platform_device mainstone_backlight_device = {
  318. .name = "pwm-backlight",
  319. .dev = {
  320. .parent = &pxa27x_device_pwm0.dev,
  321. .platform_data = &mainstone_backlight_data,
  322. },
  323. };
  324. static void __init mainstone_backlight_register(void)
  325. {
  326. int ret = platform_device_register(&mainstone_backlight_device);
  327. if (ret)
  328. printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
  329. }
  330. #else
  331. #define mainstone_backlight_register() do { } while (0)
  332. #endif
  333. static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
  334. .pixclock = 50000,
  335. .xres = 640,
  336. .yres = 480,
  337. .bpp = 16,
  338. .hsync_len = 1,
  339. .left_margin = 0x9f,
  340. .right_margin = 1,
  341. .vsync_len = 44,
  342. .upper_margin = 0,
  343. .lower_margin = 0,
  344. .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  345. };
  346. static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
  347. .pixclock = 110000,
  348. .xres = 240,
  349. .yres = 320,
  350. .bpp = 16,
  351. .hsync_len = 4,
  352. .left_margin = 8,
  353. .right_margin = 20,
  354. .vsync_len = 3,
  355. .upper_margin = 1,
  356. .lower_margin = 10,
  357. .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  358. };
  359. static struct pxafb_mach_info mainstone_pxafb_info = {
  360. .num_modes = 1,
  361. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
  362. };
  363. static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
  364. {
  365. int err;
  366. /* make sure SD/Memory Stick multiplexer's signals
  367. * are routed to MMC controller
  368. */
  369. MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
  370. err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
  371. "MMC card detect", data);
  372. if (err)
  373. printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
  374. return err;
  375. }
  376. static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
  377. {
  378. struct pxamci_platform_data* p_d = dev->platform_data;
  379. if (( 1 << vdd) & p_d->ocr_mask) {
  380. printk(KERN_DEBUG "%s: on\n", __func__);
  381. MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
  382. MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
  383. } else {
  384. printk(KERN_DEBUG "%s: off\n", __func__);
  385. MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
  386. }
  387. }
  388. static void mainstone_mci_exit(struct device *dev, void *data)
  389. {
  390. free_irq(MAINSTONE_MMC_IRQ, data);
  391. }
  392. static struct pxamci_platform_data mainstone_mci_platform_data = {
  393. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  394. .init = mainstone_mci_init,
  395. .setpower = mainstone_mci_setpower,
  396. .exit = mainstone_mci_exit,
  397. .gpio_card_detect = -1,
  398. .gpio_card_ro = -1,
  399. .gpio_power = -1,
  400. };
  401. static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
  402. {
  403. unsigned long flags;
  404. local_irq_save(flags);
  405. if (mode & IR_SIRMODE) {
  406. MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
  407. } else if (mode & IR_FIRMODE) {
  408. MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
  409. }
  410. pxa2xx_transceiver_mode(dev, mode);
  411. if (mode & IR_OFF) {
  412. MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
  413. } else {
  414. MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
  415. }
  416. local_irq_restore(flags);
  417. }
  418. static struct pxaficp_platform_data mainstone_ficp_platform_data = {
  419. .gpio_pwdown = -1,
  420. .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
  421. .transceiver_mode = mainstone_irda_transceiver_mode,
  422. };
  423. static struct gpio_keys_button gpio_keys_button[] = {
  424. [0] = {
  425. .desc = "wakeup",
  426. .code = KEY_SUSPEND,
  427. .type = EV_KEY,
  428. .gpio = 1,
  429. .wakeup = 1,
  430. },
  431. };
  432. static struct gpio_keys_platform_data mainstone_gpio_keys = {
  433. .buttons = gpio_keys_button,
  434. .nbuttons = 1,
  435. };
  436. static struct platform_device mst_gpio_keys_device = {
  437. .name = "gpio-keys",
  438. .id = -1,
  439. .dev = {
  440. .platform_data = &mainstone_gpio_keys,
  441. },
  442. };
  443. static struct platform_device *platform_devices[] __initdata = {
  444. &smc91x_device,
  445. &mst_flash_device[0],
  446. &mst_flash_device[1],
  447. &mst_gpio_keys_device,
  448. };
  449. static struct pxaohci_platform_data mainstone_ohci_platform_data = {
  450. .port_mode = PMM_PERPORT_MODE,
  451. .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
  452. };
  453. #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
  454. static unsigned int mainstone_matrix_keys[] = {
  455. KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
  456. KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
  457. KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
  458. KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
  459. KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
  460. KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
  461. KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
  462. KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
  463. KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
  464. KEY(0, 4, KEY_DOT), /* . */
  465. KEY(1, 4, KEY_CLOSE), /* @ */
  466. KEY(4, 4, KEY_SLASH),
  467. KEY(5, 4, KEY_BACKSLASH),
  468. KEY(0, 5, KEY_HOME),
  469. KEY(1, 5, KEY_LEFTSHIFT),
  470. KEY(2, 5, KEY_SPACE),
  471. KEY(3, 5, KEY_SPACE),
  472. KEY(4, 5, KEY_ENTER),
  473. KEY(5, 5, KEY_BACKSPACE),
  474. KEY(0, 6, KEY_UP),
  475. KEY(1, 6, KEY_DOWN),
  476. KEY(2, 6, KEY_LEFT),
  477. KEY(3, 6, KEY_RIGHT),
  478. KEY(4, 6, KEY_SELECT),
  479. };
  480. struct pxa27x_keypad_platform_data mainstone_keypad_info = {
  481. .matrix_key_rows = 6,
  482. .matrix_key_cols = 7,
  483. .matrix_key_map = mainstone_matrix_keys,
  484. .matrix_key_map_size = ARRAY_SIZE(mainstone_matrix_keys),
  485. .enable_rotary0 = 1,
  486. .rotary0_up_key = KEY_UP,
  487. .rotary0_down_key = KEY_DOWN,
  488. .debounce_interval = 30,
  489. };
  490. static void __init mainstone_init_keypad(void)
  491. {
  492. pxa_set_keypad_info(&mainstone_keypad_info);
  493. }
  494. #else
  495. static inline void mainstone_init_keypad(void) {}
  496. #endif
  497. static void __init mainstone_init(void)
  498. {
  499. int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
  500. pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
  501. mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  502. mst_flash_data[1].width = 4;
  503. /* Compensate for SW7 which swaps the flash banks */
  504. mst_flash_data[SW7].name = "processor-flash";
  505. mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
  506. printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
  507. mst_flash_data[0].name);
  508. /* system bus arbiter setting
  509. * - Core_Park
  510. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  511. */
  512. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  513. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  514. /* reading Mainstone's "Virtual Configuration Register"
  515. might be handy to select LCD type here */
  516. if (0)
  517. mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
  518. else
  519. mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
  520. set_pxa_fb_info(&mainstone_pxafb_info);
  521. mainstone_backlight_register();
  522. pxa_set_mci_info(&mainstone_mci_platform_data);
  523. pxa_set_ficp_info(&mainstone_ficp_platform_data);
  524. pxa_set_ohci_info(&mainstone_ohci_platform_data);
  525. pxa_set_i2c_info(NULL);
  526. pxa_set_ac97_info(&mst_audio_ops);
  527. mainstone_init_keypad();
  528. }
  529. static struct map_desc mainstone_io_desc[] __initdata = {
  530. { /* CPLD */
  531. .virtual = MST_FPGA_VIRT,
  532. .pfn = __phys_to_pfn(MST_FPGA_PHYS),
  533. .length = 0x00100000,
  534. .type = MT_DEVICE
  535. }
  536. };
  537. static void __init mainstone_map_io(void)
  538. {
  539. pxa_map_io();
  540. iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
  541. /* for use I SRAM as framebuffer. */
  542. PSLR |= 0xF04;
  543. PCFR = 0x66;
  544. }
  545. MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
  546. /* Maintainer: MontaVista Software Inc. */
  547. .phys_io = 0x40000000,
  548. .boot_params = 0xa0000100, /* BLOB boot parameter setting */
  549. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  550. .map_io = mainstone_map_io,
  551. .init_irq = mainstone_init_irq,
  552. .timer = &pxa_timer,
  553. .init_machine = mainstone_init,
  554. MACHINE_END