irq.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203
  1. /*
  2. * linux/arch/arm/mach-pxa/irq.c
  3. *
  4. * Generic PXA IRQ handling
  5. *
  6. * Author: Nicolas Pitre
  7. * Created: Jun 15, 2001
  8. * Copyright: MontaVista Software Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/sysdev.h>
  18. #include <mach/hardware.h>
  19. #include <asm/irq.h>
  20. #include <asm/mach/irq.h>
  21. #include <mach/gpio.h>
  22. #include <mach/regs-intc.h>
  23. #include "generic.h"
  24. #define MAX_INTERNAL_IRQS 128
  25. #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
  26. #define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
  27. #define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
  28. /*
  29. * This is for peripheral IRQs internal to the PXA chip.
  30. */
  31. static int pxa_internal_irq_nr;
  32. static void pxa_mask_irq(unsigned int irq)
  33. {
  34. _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
  35. }
  36. static void pxa_unmask_irq(unsigned int irq)
  37. {
  38. _ICMR(irq) |= 1 << IRQ_BIT(irq);
  39. }
  40. static struct irq_chip pxa_internal_irq_chip = {
  41. .name = "SC",
  42. .ack = pxa_mask_irq,
  43. .mask = pxa_mask_irq,
  44. .unmask = pxa_unmask_irq,
  45. };
  46. /*
  47. * GPIO IRQs for GPIO 0 and 1
  48. */
  49. static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
  50. {
  51. int gpio = irq - IRQ_GPIO0;
  52. if (__gpio_is_occupied(gpio)) {
  53. pr_err("%s failed: GPIO is configured\n", __func__);
  54. return -EINVAL;
  55. }
  56. if (type & IRQ_TYPE_EDGE_RISING)
  57. GRER0 |= GPIO_bit(gpio);
  58. else
  59. GRER0 &= ~GPIO_bit(gpio);
  60. if (type & IRQ_TYPE_EDGE_FALLING)
  61. GFER0 |= GPIO_bit(gpio);
  62. else
  63. GFER0 &= ~GPIO_bit(gpio);
  64. return 0;
  65. }
  66. static void pxa_ack_low_gpio(unsigned int irq)
  67. {
  68. GEDR0 = (1 << (irq - IRQ_GPIO0));
  69. }
  70. static void pxa_mask_low_gpio(unsigned int irq)
  71. {
  72. ICMR &= ~(1 << (irq - PXA_IRQ(0)));
  73. }
  74. static void pxa_unmask_low_gpio(unsigned int irq)
  75. {
  76. ICMR |= 1 << (irq - PXA_IRQ(0));
  77. }
  78. static struct irq_chip pxa_low_gpio_chip = {
  79. .name = "GPIO-l",
  80. .ack = pxa_ack_low_gpio,
  81. .mask = pxa_mask_low_gpio,
  82. .unmask = pxa_unmask_low_gpio,
  83. .set_type = pxa_set_low_gpio_type,
  84. };
  85. static void __init pxa_init_low_gpio_irq(set_wake_t fn)
  86. {
  87. int irq;
  88. /* clear edge detection on GPIO 0 and 1 */
  89. GFER0 &= ~0x3;
  90. GRER0 &= ~0x3;
  91. GEDR0 = 0x3;
  92. for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
  93. set_irq_chip(irq, &pxa_low_gpio_chip);
  94. set_irq_handler(irq, handle_edge_irq);
  95. set_irq_flags(irq, IRQF_VALID);
  96. }
  97. pxa_low_gpio_chip.set_wake = fn;
  98. }
  99. void __init pxa_init_irq(int irq_nr, set_wake_t fn)
  100. {
  101. int irq, i;
  102. BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
  103. pxa_internal_irq_nr = irq_nr;
  104. for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
  105. _ICMR(irq) = 0; /* disable all IRQs */
  106. _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
  107. }
  108. /* initialize interrupt priority */
  109. if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
  110. for (i = 0; i < irq_nr; i++)
  111. IPR(i) = i | (1 << 31);
  112. }
  113. /* only unmasked interrupts kick us out of idle */
  114. ICCR = 1;
  115. for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
  116. set_irq_chip(irq, &pxa_internal_irq_chip);
  117. set_irq_handler(irq, handle_level_irq);
  118. set_irq_flags(irq, IRQF_VALID);
  119. }
  120. pxa_internal_irq_chip.set_wake = fn;
  121. pxa_init_low_gpio_irq(fn);
  122. }
  123. #ifdef CONFIG_PM
  124. static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
  125. static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
  126. static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
  127. {
  128. int i, irq = PXA_IRQ(0);
  129. for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
  130. saved_icmr[i] = _ICMR(irq);
  131. _ICMR(irq) = 0;
  132. }
  133. for (i = 0; i < pxa_internal_irq_nr; i++)
  134. saved_ipr[i] = IPR(i);
  135. return 0;
  136. }
  137. static int pxa_irq_resume(struct sys_device *dev)
  138. {
  139. int i, irq = PXA_IRQ(0);
  140. for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
  141. _ICMR(irq) = saved_icmr[i];
  142. _ICLR(irq) = 0;
  143. }
  144. for (i = 0; i < pxa_internal_irq_nr; i++)
  145. IPR(i) = saved_ipr[i];
  146. ICCR = 1;
  147. return 0;
  148. }
  149. #else
  150. #define pxa_irq_suspend NULL
  151. #define pxa_irq_resume NULL
  152. #endif
  153. struct sysdev_class pxa_irq_sysclass = {
  154. .name = "irq",
  155. .suspend = pxa_irq_suspend,
  156. .resume = pxa_irq_resume,
  157. };
  158. static int __init pxa_irq_init(void)
  159. {
  160. return sysdev_class_register(&pxa_irq_sysclass);
  161. }
  162. core_initcall(pxa_irq_init);