rd88f5181l-fxo-setup.c 5.0 KB

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  1. /*
  2. * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
  3. *
  4. * Marvell Orion-VoIP FXO Reference Design Setup
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pci.h>
  14. #include <linux/irq.h>
  15. #include <linux/mtd/physmap.h>
  16. #include <linux/mv643xx_eth.h>
  17. #include <linux/ethtool.h>
  18. #include <net/dsa.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/gpio.h>
  21. #include <asm/leds.h>
  22. #include <asm/mach/arch.h>
  23. #include <asm/mach/pci.h>
  24. #include <mach/orion5x.h>
  25. #include "common.h"
  26. #include "mpp.h"
  27. /*****************************************************************************
  28. * RD-88F5181L FXO Info
  29. ****************************************************************************/
  30. /*
  31. * 8M NOR flash Device bus boot chip select
  32. */
  33. #define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000
  34. #define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M
  35. /*****************************************************************************
  36. * 8M NOR Flash on Device bus Boot chip select
  37. ****************************************************************************/
  38. static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = {
  39. .width = 1,
  40. };
  41. static struct resource rd88f5181l_fxo_nor_boot_flash_resource = {
  42. .flags = IORESOURCE_MEM,
  43. .start = RD88F5181L_FXO_NOR_BOOT_BASE,
  44. .end = RD88F5181L_FXO_NOR_BOOT_BASE +
  45. RD88F5181L_FXO_NOR_BOOT_SIZE - 1,
  46. };
  47. static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
  48. .name = "physmap-flash",
  49. .id = 0,
  50. .dev = {
  51. .platform_data = &rd88f5181l_fxo_nor_boot_flash_data,
  52. },
  53. .num_resources = 1,
  54. .resource = &rd88f5181l_fxo_nor_boot_flash_resource,
  55. };
  56. /*****************************************************************************
  57. * General Setup
  58. ****************************************************************************/
  59. static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
  60. { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */
  61. { 1, MPP_GPIO }, /* PCI_intA */
  62. { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/
  63. { 3, MPP_GPIO }, /* FXS or DAA select */
  64. { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */
  65. { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */
  66. { 6, MPP_PCI_CLK }, /* CPU PCI refclk */
  67. { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
  68. { 8, MPP_GPIO }, /* CardBus reset */
  69. { 9, MPP_GPIO }, /* GE_RXERR */
  70. { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */
  71. { 11, MPP_GPIO }, /* Lifeline control */
  72. { 12, MPP_GIGE }, /* GE_TXD[4] */
  73. { 13, MPP_GIGE }, /* GE_TXD[5] */
  74. { 14, MPP_GIGE }, /* GE_TXD[6] */
  75. { 15, MPP_GIGE }, /* GE_TXD[7] */
  76. { 16, MPP_GIGE }, /* GE_RXD[4] */
  77. { 17, MPP_GIGE }, /* GE_RXD[5] */
  78. { 18, MPP_GIGE }, /* GE_RXD[6] */
  79. { 19, MPP_GIGE }, /* GE_RXD[7] */
  80. { -1 },
  81. };
  82. static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
  83. .phy_addr = MV643XX_ETH_PHY_NONE,
  84. .speed = SPEED_1000,
  85. .duplex = DUPLEX_FULL,
  86. };
  87. static struct dsa_chip_data rd88f5181l_fxo_switch_chip_data = {
  88. .port_names[0] = "lan2",
  89. .port_names[1] = "lan1",
  90. .port_names[2] = "wan",
  91. .port_names[3] = "cpu",
  92. .port_names[5] = "lan4",
  93. .port_names[7] = "lan3",
  94. };
  95. static struct dsa_platform_data rd88f5181l_fxo_switch_plat_data = {
  96. .nr_chips = 1,
  97. .chip = &rd88f5181l_fxo_switch_chip_data,
  98. };
  99. static void __init rd88f5181l_fxo_init(void)
  100. {
  101. /*
  102. * Setup basic Orion functions. Need to be called early.
  103. */
  104. orion5x_init();
  105. orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes);
  106. /*
  107. * Configure peripherals.
  108. */
  109. orion5x_ehci0_init();
  110. orion5x_eth_init(&rd88f5181l_fxo_eth_data);
  111. orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
  112. orion5x_uart0_init();
  113. orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
  114. RD88F5181L_FXO_NOR_BOOT_SIZE);
  115. platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
  116. }
  117. static int __init
  118. rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  119. {
  120. int irq;
  121. /*
  122. * Check for devices with hard-wired IRQs.
  123. */
  124. irq = orion5x_pci_map_irq(dev, slot, pin);
  125. if (irq != -1)
  126. return irq;
  127. /*
  128. * Mini-PCI / Cardbus slot.
  129. */
  130. return gpio_to_irq(1);
  131. }
  132. static struct hw_pci rd88f5181l_fxo_pci __initdata = {
  133. .nr_controllers = 2,
  134. .swizzle = pci_std_swizzle,
  135. .setup = orion5x_pci_sys_setup,
  136. .scan = orion5x_pci_sys_scan_bus,
  137. .map_irq = rd88f5181l_fxo_pci_map_irq,
  138. };
  139. static int __init rd88f5181l_fxo_pci_init(void)
  140. {
  141. if (machine_is_rd88f5181l_fxo()) {
  142. orion5x_pci_set_cardbus_mode();
  143. pci_common_init(&rd88f5181l_fxo_pci);
  144. }
  145. return 0;
  146. }
  147. subsys_initcall(rd88f5181l_fxo_pci_init);
  148. MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
  149. /* Maintainer: Nicolas Pitre <nico@marvell.com> */
  150. .phys_io = ORION5X_REGS_PHYS_BASE,
  151. .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
  152. .boot_params = 0x00000100,
  153. .init_machine = rd88f5181l_fxo_init,
  154. .map_io = orion5x_map_io,
  155. .init_irq = orion5x_init_irq,
  156. .timer = &orion5x_timer,
  157. .fixup = tag_fixup_mem32,
  158. MACHINE_END