gpmc-smc91x.c 4.9 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/gpmc-smc91x.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Contact: Tony Lindgren
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/gpio.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/smc91x.h>
  18. #include <mach/board.h>
  19. #include <mach/gpmc.h>
  20. #include <mach/gpmc-smc91x.h>
  21. static struct omap_smc91x_platform_data *gpmc_cfg;
  22. static struct resource gpmc_smc91x_resources[] = {
  23. [0] = {
  24. .flags = IORESOURCE_MEM,
  25. },
  26. [1] = {
  27. .flags = IORESOURCE_IRQ,
  28. },
  29. };
  30. static struct smc91x_platdata gpmc_smc91x_info = {
  31. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
  32. };
  33. static struct platform_device gpmc_smc91x_device = {
  34. .name = "smc91x",
  35. .id = -1,
  36. .num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
  37. .resource = gpmc_smc91x_resources,
  38. .dev = {
  39. .platform_data = &gpmc_smc91x_info,
  40. },
  41. };
  42. /*
  43. * Set the gpmc timings for smc91c96. The timings are taken
  44. * from the data sheet available at:
  45. * http://www.smsc.com/main/catalog/lan91c96.html
  46. * REVISIT: Level shifters can add at least to the access latency.
  47. */
  48. static int smc91c96_gpmc_retime(void)
  49. {
  50. struct gpmc_timings t;
  51. const int t3 = 10; /* Figure 12.2 read and 12.4 write */
  52. const int t4_r = 20; /* Figure 12.2 read */
  53. const int t4_w = 5; /* Figure 12.4 write */
  54. const int t5 = 25; /* Figure 12.2 read */
  55. const int t6 = 15; /* Figure 12.2 read */
  56. const int t7 = 5; /* Figure 12.4 write */
  57. const int t8 = 5; /* Figure 12.4 write */
  58. const int t20 = 185; /* Figure 12.2 read and 12.4 write */
  59. u32 l;
  60. memset(&t, 0, sizeof(t));
  61. /* Read timings */
  62. t.cs_on = 0;
  63. t.adv_on = t.cs_on;
  64. t.oe_on = t.adv_on + t3;
  65. t.access = t.oe_on + t5;
  66. t.oe_off = t.access;
  67. t.adv_rd_off = t.oe_off + max(t4_r, t6);
  68. t.cs_rd_off = t.oe_off;
  69. t.rd_cycle = t20 - t.oe_on;
  70. /* Write timings */
  71. t.we_on = t.adv_on + t3;
  72. if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {
  73. t.wr_data_mux_bus = t.we_on;
  74. t.we_off = t.wr_data_mux_bus + t7;
  75. } else
  76. t.we_off = t.we_on + t7;
  77. if (cpu_is_omap34xx())
  78. t.wr_access = t.we_off;
  79. t.adv_wr_off = t.we_off + max(t4_w, t8);
  80. t.cs_wr_off = t.we_off + t4_w;
  81. t.wr_cycle = t20 - t.we_on;
  82. l = GPMC_CONFIG1_DEVICESIZE_16;
  83. if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
  84. l |= GPMC_CONFIG1_MUXADDDATA;
  85. if (gpmc_cfg->flags & GPMC_READ_MON)
  86. l |= GPMC_CONFIG1_WAIT_READ_MON;
  87. if (gpmc_cfg->flags & GPMC_WRITE_MON)
  88. l |= GPMC_CONFIG1_WAIT_WRITE_MON;
  89. if (gpmc_cfg->wait_pin)
  90. l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
  91. gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
  92. /*
  93. * FIXME: Calculate the address and data bus muxed timings.
  94. * Note that at least adv_rd_off needs to be changed according
  95. * to omap3430 TRM Figure 11-11. Are the sdp boards using the
  96. * FPGA in between smc91x and omap as the timings are different
  97. * from above?
  98. */
  99. if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
  100. return 0;
  101. return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
  102. }
  103. /*
  104. * Initialize smc91x device connected to the GPMC. Note that we
  105. * assume that pin multiplexing is done in the board-*.c file,
  106. * or in the bootloader.
  107. */
  108. void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
  109. {
  110. unsigned long cs_mem_base;
  111. int ret;
  112. gpmc_cfg = board_data;
  113. if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96)
  114. gpmc_cfg->retime = smc91c96_gpmc_retime;
  115. if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
  116. printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
  117. return;
  118. }
  119. gpmc_smc91x_resources[0].start = cs_mem_base + 0x300;
  120. gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
  121. gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
  122. if (gpmc_cfg->retime) {
  123. ret = gpmc_cfg->retime();
  124. if (ret != 0)
  125. goto free1;
  126. }
  127. if (gpio_request(gpmc_cfg->gpio_irq, "SMC91X irq") < 0)
  128. goto free1;
  129. gpio_direction_input(gpmc_cfg->gpio_irq);
  130. gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
  131. if (gpmc_cfg->gpio_pwrdwn) {
  132. ret = gpio_request(gpmc_cfg->gpio_pwrdwn, "SMC91X powerdown");
  133. if (ret)
  134. goto free2;
  135. gpio_direction_output(gpmc_cfg->gpio_pwrdwn, 0);
  136. }
  137. if (gpmc_cfg->gpio_reset) {
  138. ret = gpio_request(gpmc_cfg->gpio_reset, "SMC91X reset");
  139. if (ret)
  140. goto free3;
  141. gpio_direction_output(gpmc_cfg->gpio_reset, 0);
  142. gpio_set_value(gpmc_cfg->gpio_reset, 1);
  143. msleep(100);
  144. gpio_set_value(gpmc_cfg->gpio_reset, 0);
  145. }
  146. if (platform_device_register(&gpmc_smc91x_device) < 0) {
  147. printk(KERN_ERR "Unable to register smc91x device\n");
  148. gpio_free(gpmc_cfg->gpio_reset);
  149. goto free3;
  150. }
  151. return;
  152. free3:
  153. if (gpmc_cfg->gpio_pwrdwn)
  154. gpio_free(gpmc_cfg->gpio_pwrdwn);
  155. free2:
  156. gpio_free(gpmc_cfg->gpio_irq);
  157. free1:
  158. gpmc_cs_free(gpmc_cfg->cs);
  159. printk(KERN_ERR "Could not initialize smc91x\n");
  160. }