timer.c 4.2 KB

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  1. /*
  2. * linux/arch/arm/mach-nomadik/timer.c
  3. *
  4. * Copyright (C) 2008 STMicroelectronics
  5. * Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2, as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/io.h>
  15. #include <linux/clockchips.h>
  16. #include <linux/jiffies.h>
  17. #include <asm/mach/time.h>
  18. #include <mach/mtu.h>
  19. #define TIMER_CTRL 0x80 /* No divisor */
  20. #define TIMER_PERIODIC 0x40
  21. #define TIMER_SZ32BIT 0x02
  22. /* Initial value for SRC control register: all timers use MXTAL/8 source */
  23. #define SRC_CR_INIT_MASK 0x00007fff
  24. #define SRC_CR_INIT_VAL 0x2aaa8000
  25. static u32 nmdk_count; /* accumulated count */
  26. static u32 nmdk_cycle; /* write-once */
  27. static __iomem void *mtu_base;
  28. /*
  29. * clocksource: the MTU device is a decrementing counters, so we negate
  30. * the value being read.
  31. */
  32. static cycle_t nmdk_read_timer(struct clocksource *cs)
  33. {
  34. u32 count = readl(mtu_base + MTU_VAL(0));
  35. return nmdk_count + nmdk_cycle - count;
  36. }
  37. static struct clocksource nmdk_clksrc = {
  38. .name = "mtu_0",
  39. .rating = 120,
  40. .read = nmdk_read_timer,
  41. .shift = 20,
  42. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  43. };
  44. /*
  45. * Clockevent device: currently only periodic mode is supported
  46. */
  47. static void nmdk_clkevt_mode(enum clock_event_mode mode,
  48. struct clock_event_device *dev)
  49. {
  50. unsigned long flags;
  51. switch (mode) {
  52. case CLOCK_EVT_MODE_PERIODIC:
  53. /* enable interrupts -- and count current value? */
  54. raw_local_irq_save(flags);
  55. writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC);
  56. raw_local_irq_restore(flags);
  57. break;
  58. case CLOCK_EVT_MODE_ONESHOT:
  59. BUG(); /* Not supported, yet */
  60. /* FALLTHROUGH */
  61. case CLOCK_EVT_MODE_SHUTDOWN:
  62. case CLOCK_EVT_MODE_UNUSED:
  63. /* disable irq */
  64. raw_local_irq_save(flags);
  65. writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC);
  66. raw_local_irq_restore(flags);
  67. break;
  68. case CLOCK_EVT_MODE_RESUME:
  69. break;
  70. }
  71. }
  72. static struct clock_event_device nmdk_clkevt = {
  73. .name = "mtu_0",
  74. .features = CLOCK_EVT_FEAT_PERIODIC,
  75. .shift = 32,
  76. .rating = 100,
  77. .set_mode = nmdk_clkevt_mode,
  78. };
  79. /*
  80. * IRQ Handler for the timer 0 of the MTU block. The irq is not shared
  81. * as we are the only users of mtu0 by now.
  82. */
  83. static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
  84. {
  85. /* ack: "interrupt clear register" */
  86. writel( 1 << 0, mtu_base + MTU_ICR);
  87. /* we can't count lost ticks, unfortunately */
  88. nmdk_count += nmdk_cycle;
  89. nmdk_clkevt.event_handler(&nmdk_clkevt);
  90. return IRQ_HANDLED;
  91. }
  92. /*
  93. * Set up timer interrupt, and return the current time in seconds.
  94. */
  95. static struct irqaction nmdk_timer_irq = {
  96. .name = "Nomadik Timer Tick",
  97. .flags = IRQF_DISABLED | IRQF_TIMER,
  98. .handler = nmdk_timer_interrupt,
  99. };
  100. static void nmdk_timer_reset(void)
  101. {
  102. u32 cr;
  103. writel(0, mtu_base + MTU_CR(0)); /* off */
  104. /* configure load and background-load, and fire it up */
  105. writel(nmdk_cycle, mtu_base + MTU_LR(0));
  106. writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
  107. cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
  108. writel(cr, mtu_base + MTU_CR(0));
  109. writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
  110. }
  111. static void __init nmdk_timer_init(void)
  112. {
  113. u32 src_cr;
  114. unsigned long rate;
  115. int bits;
  116. rate = CLOCK_TICK_RATE; /* 2.4MHz */
  117. nmdk_cycle = (rate + HZ/2) / HZ;
  118. /* Configure timer sources in "system reset controller" ctrl reg */
  119. src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
  120. src_cr &= SRC_CR_INIT_MASK;
  121. src_cr |= SRC_CR_INIT_VAL;
  122. writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
  123. /* Save global pointer to mtu, used by functions above */
  124. mtu_base = io_p2v(NOMADIK_MTU0_BASE);
  125. /* Init the timer and register clocksource */
  126. nmdk_timer_reset();
  127. nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
  128. bits = 8*sizeof(nmdk_count);
  129. nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits);
  130. clocksource_register(&nmdk_clksrc);
  131. /* Register irq and clockevents */
  132. setup_irq(IRQ_MTU0, &nmdk_timer_irq);
  133. nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
  134. nmdk_clkevt.cpumask = cpumask_of(0);
  135. clockevents_register_device(&nmdk_clkevt);
  136. }
  137. struct sys_timer nomadik_timer = {
  138. .init = nmdk_timer_init,
  139. };