irq-lh7a404.c 4.1 KB

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  1. /* arch/arm/mach-lh7a40x/irq-lh7a404.c
  2. *
  3. * Copyright (C) 2004 Logic Product Development
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * version 2 as published by the Free Software Foundation.
  8. *
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <mach/hardware.h>
  14. #include <asm/irq.h>
  15. #include <asm/mach/irq.h>
  16. #include <mach/irqs.h>
  17. #include "common.h"
  18. #define USE_PRIORITIES
  19. /* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
  20. * information on using the vectored interrupt controller's
  21. * prioritizing feature. */
  22. static unsigned char irq_pri_vic1[] = {
  23. #if defined (USE_PRIORITIES)
  24. IRQ_GPIO3INTR, /* CPLD */
  25. IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */
  26. #endif
  27. };
  28. static unsigned char irq_pri_vic2[] = {
  29. #if defined (USE_PRIORITIES)
  30. IRQ_T3UI, /* Timer */
  31. IRQ_GPIO7INTR, /* CPLD */
  32. IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
  33. IRQ_LCDINTR, /* LCD */
  34. IRQ_TSCINTR, /* ADC/Touchscreen */
  35. #endif
  36. };
  37. /* CPU IRQ handling */
  38. static void lh7a404_vic1_mask_irq (u32 irq)
  39. {
  40. VIC1_INTENCLR = (1 << irq);
  41. }
  42. static void lh7a404_vic1_unmask_irq (u32 irq)
  43. {
  44. VIC1_INTEN = (1 << irq);
  45. }
  46. static void lh7a404_vic2_mask_irq (u32 irq)
  47. {
  48. VIC2_INTENCLR = (1 << (irq - 32));
  49. }
  50. static void lh7a404_vic2_unmask_irq (u32 irq)
  51. {
  52. VIC2_INTEN = (1 << (irq - 32));
  53. }
  54. static void lh7a404_vic1_ack_gpio_irq (u32 irq)
  55. {
  56. GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  57. VIC1_INTENCLR = (1 << irq);
  58. }
  59. static void lh7a404_vic2_ack_gpio_irq (u32 irq)
  60. {
  61. GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
  62. VIC2_INTENCLR = (1 << irq);
  63. }
  64. static struct irq_chip lh7a404_vic1_chip = {
  65. .name = "VIC1",
  66. .ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
  67. .mask = lh7a404_vic1_mask_irq,
  68. .unmask = lh7a404_vic1_unmask_irq,
  69. };
  70. static struct irq_chip lh7a404_vic2_chip = {
  71. .name = "VIC2",
  72. .ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
  73. .mask = lh7a404_vic2_mask_irq,
  74. .unmask = lh7a404_vic2_unmask_irq,
  75. };
  76. static struct irq_chip lh7a404_gpio_vic1_chip = {
  77. .name = "GPIO-VIC1",
  78. .ack = lh7a404_vic1_ack_gpio_irq,
  79. .mask = lh7a404_vic1_mask_irq,
  80. .unmask = lh7a404_vic1_unmask_irq,
  81. };
  82. static struct irq_chip lh7a404_gpio_vic2_chip = {
  83. .name = "GPIO-VIC2",
  84. .ack = lh7a404_vic2_ack_gpio_irq,
  85. .mask = lh7a404_vic2_mask_irq,
  86. .unmask = lh7a404_vic2_unmask_irq,
  87. };
  88. /* IRQ initialization */
  89. #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  90. extern void* branch_irq_lh7a400;
  91. #endif
  92. void __init lh7a404_init_irq (void)
  93. {
  94. int irq;
  95. #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
  96. #define NOP 0xe1a00000 /* mov r0, r0 */
  97. branch_irq_lh7a400 = NOP;
  98. #endif
  99. VIC1_INTENCLR = 0xffffffff;
  100. VIC2_INTENCLR = 0xffffffff;
  101. VIC1_INTSEL = 0; /* All IRQs */
  102. VIC2_INTSEL = 0; /* All IRQs */
  103. VIC1_NVADDR = VA_VIC1DEFAULT;
  104. VIC2_NVADDR = VA_VIC2DEFAULT;
  105. VIC1_VECTADDR = 0;
  106. VIC2_VECTADDR = 0;
  107. GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
  108. barrier ();
  109. /* Install prioritized interrupts, if there are any. */
  110. /* The | 0x20*/
  111. for (irq = 0; irq < 16; ++irq) {
  112. (&VIC1_VAD0)[irq]
  113. = (irq < ARRAY_SIZE (irq_pri_vic1))
  114. ? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
  115. (&VIC1_VECTCNTL0)[irq]
  116. = (irq < ARRAY_SIZE (irq_pri_vic1))
  117. ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
  118. (&VIC2_VAD0)[irq]
  119. = (irq < ARRAY_SIZE (irq_pri_vic2))
  120. ? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
  121. (&VIC2_VECTCNTL0)[irq]
  122. = (irq < ARRAY_SIZE (irq_pri_vic2))
  123. ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
  124. }
  125. for (irq = 0; irq < NR_IRQS; ++irq) {
  126. switch (irq) {
  127. case IRQ_GPIO0INTR:
  128. case IRQ_GPIO1INTR:
  129. case IRQ_GPIO2INTR:
  130. case IRQ_GPIO3INTR:
  131. case IRQ_GPIO4INTR:
  132. case IRQ_GPIO5INTR:
  133. case IRQ_GPIO6INTR:
  134. case IRQ_GPIO7INTR:
  135. set_irq_chip (irq, irq < 32
  136. ? &lh7a404_gpio_vic1_chip
  137. : &lh7a404_gpio_vic2_chip);
  138. set_irq_handler (irq, handle_level_irq); /* OK default */
  139. break;
  140. default:
  141. set_irq_chip (irq, irq < 32
  142. ? &lh7a404_vic1_chip
  143. : &lh7a404_vic2_chip);
  144. set_irq_handler (irq, handle_level_irq);
  145. }
  146. set_irq_flags (irq, IRQF_VALID);
  147. }
  148. lh7a40x_init_board_irq ();
  149. }