ixdp2x00.c 8.6 KB

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  1. /*
  2. * arch/arm/mach-ixp2000/ixdp2x00.c
  3. *
  4. * Code common to IXDP2400 and IXDP2800 platforms.
  5. *
  6. * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
  7. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  8. *
  9. * Copyright (C) 2002 Intel Corp.
  10. * Copyright (C) 2003-2004 MontaVista Software, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/mm.h>
  20. #include <linux/sched.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/bitops.h>
  24. #include <linux/pci.h>
  25. #include <linux/ioport.h>
  26. #include <linux/slab.h>
  27. #include <linux/delay.h>
  28. #include <linux/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/pgtable.h>
  31. #include <asm/page.h>
  32. #include <asm/system.h>
  33. #include <mach/hardware.h>
  34. #include <asm/mach-types.h>
  35. #include <asm/mach/pci.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <asm/mach/time.h>
  39. #include <asm/mach/flash.h>
  40. #include <asm/mach/arch.h>
  41. #include <mach/gpio.h>
  42. /*************************************************************************
  43. * IXDP2x00 IRQ Initialization
  44. *************************************************************************/
  45. static volatile unsigned long *board_irq_mask;
  46. static volatile unsigned long *board_irq_stat;
  47. static unsigned long board_irq_count;
  48. #ifdef CONFIG_ARCH_IXDP2400
  49. /*
  50. * Slowport configuration for accessing CPLD registers on IXDP2x00
  51. */
  52. static struct slowport_cfg slowport_cpld_cfg = {
  53. .CCR = SLOWPORT_CCR_DIV_2,
  54. .WTC = 0x00000070,
  55. .RTC = 0x00000070,
  56. .PCR = SLOWPORT_MODE_FLASH,
  57. .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8
  58. };
  59. #endif
  60. static void ixdp2x00_irq_mask(unsigned int irq)
  61. {
  62. unsigned long dummy;
  63. static struct slowport_cfg old_cfg;
  64. /*
  65. * This is ugly in common code but really don't know
  66. * of a better way to handle it. :(
  67. */
  68. #ifdef CONFIG_ARCH_IXDP2400
  69. if (machine_is_ixdp2400())
  70. ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
  71. #endif
  72. dummy = *board_irq_mask;
  73. dummy |= IXP2000_BOARD_IRQ_MASK(irq);
  74. ixp2000_reg_wrb(board_irq_mask, dummy);
  75. #ifdef CONFIG_ARCH_IXDP2400
  76. if (machine_is_ixdp2400())
  77. ixp2000_release_slowport(&old_cfg);
  78. #endif
  79. }
  80. static void ixdp2x00_irq_unmask(unsigned int irq)
  81. {
  82. unsigned long dummy;
  83. static struct slowport_cfg old_cfg;
  84. #ifdef CONFIG_ARCH_IXDP2400
  85. if (machine_is_ixdp2400())
  86. ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
  87. #endif
  88. dummy = *board_irq_mask;
  89. dummy &= ~IXP2000_BOARD_IRQ_MASK(irq);
  90. ixp2000_reg_wrb(board_irq_mask, dummy);
  91. if (machine_is_ixdp2400())
  92. ixp2000_release_slowport(&old_cfg);
  93. }
  94. static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
  95. {
  96. volatile u32 ex_interrupt = 0;
  97. static struct slowport_cfg old_cfg;
  98. int i;
  99. desc->chip->mask(irq);
  100. #ifdef CONFIG_ARCH_IXDP2400
  101. if (machine_is_ixdp2400())
  102. ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
  103. #endif
  104. ex_interrupt = *board_irq_stat & 0xff;
  105. if (machine_is_ixdp2400())
  106. ixp2000_release_slowport(&old_cfg);
  107. if(!ex_interrupt) {
  108. printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n");
  109. return;
  110. }
  111. for(i = 0; i < board_irq_count; i++) {
  112. if(ex_interrupt & (1 << i)) {
  113. int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
  114. generic_handle_irq(cpld_irq);
  115. }
  116. }
  117. desc->chip->unmask(irq);
  118. }
  119. static struct irq_chip ixdp2x00_cpld_irq_chip = {
  120. .ack = ixdp2x00_irq_mask,
  121. .mask = ixdp2x00_irq_mask,
  122. .unmask = ixdp2x00_irq_unmask
  123. };
  124. void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
  125. {
  126. unsigned int irq;
  127. ixp2000_init_irq();
  128. if (!ixdp2x00_master_npu())
  129. return;
  130. board_irq_stat = stat_reg;
  131. board_irq_mask = mask_reg;
  132. board_irq_count = nr_of_irqs;
  133. *board_irq_mask = 0xffffffff;
  134. for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
  135. set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
  136. set_irq_handler(irq, handle_level_irq);
  137. set_irq_flags(irq, IRQF_VALID);
  138. }
  139. /* Hook into PCI interrupt */
  140. set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
  141. }
  142. /*************************************************************************
  143. * IXDP2x00 memory map
  144. *************************************************************************/
  145. static struct map_desc ixdp2x00_io_desc __initdata = {
  146. .virtual = IXDP2X00_VIRT_CPLD_BASE,
  147. .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE),
  148. .length = IXDP2X00_CPLD_SIZE,
  149. .type = MT_DEVICE
  150. };
  151. void __init ixdp2x00_map_io(void)
  152. {
  153. ixp2000_map_io();
  154. iotable_init(&ixdp2x00_io_desc, 1);
  155. }
  156. /*************************************************************************
  157. * IXDP2x00-common PCI init
  158. *
  159. * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board
  160. * contains two NPUs (ingress and egress) connected over PCI, both running
  161. * instances of the kernel. So far so good. Peers on the PCI bus running
  162. * Linux is a common design in telecom systems. The problem is that instead
  163. * of all the devices being controlled by a single host, different
  164. * devices are controlled by different NPUs on the same bus, leading to
  165. * multiple hosts on the bus. The exact bus layout looks like:
  166. *
  167. * Bus 0
  168. * Master NPU <-------------------+-------------------> Slave NPU
  169. * |
  170. * |
  171. * P2P
  172. * |
  173. *
  174. * Bus 1 |
  175. * <--+------+---------+---------+------+-->
  176. * | | | | |
  177. * | | | | |
  178. * ... Dev PMC Media Eth0 Eth1 ...
  179. *
  180. * The master controls all but Eth1, which is controlled by the
  181. * slave. What this means is that the both the master and the slave
  182. * have to scan the bus, but only one of them can enumerate the bus.
  183. * In addition, after the bus is scanned, each kernel must remove
  184. * the device(s) it does not control from the PCI dev list otherwise
  185. * a driver on each NPU will try to manage it and we will have horrible
  186. * conflicts. Oh..and the slave NPU needs to see the master NPU
  187. * for Intel's drivers to work properly. Closed source drivers...
  188. *
  189. * The way we deal with this is fairly simple but ugly:
  190. *
  191. * 1) Let master scan and enumerate the bus completely.
  192. * 2) Master deletes Eth1 from device list.
  193. * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave)
  194. * from device list.
  195. * 4) Find HW designers and LART them.
  196. *
  197. * The boards also do not do normal PCI IRQ routing, or any sort of
  198. * sensical swizzling, so we just need to check where on the bus a
  199. * device sits and figure out to which CPLD pin the interrupt is routed.
  200. * See ixdp2[48]00.c files.
  201. *
  202. *************************************************************************/
  203. void ixdp2x00_slave_pci_postinit(void)
  204. {
  205. struct pci_dev *dev;
  206. /*
  207. * Remove PMC device is there is one
  208. */
  209. if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
  210. pci_remove_bus_device(dev);
  211. pci_dev_put(dev);
  212. }
  213. dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
  214. pci_remove_bus_device(dev);
  215. pci_dev_put(dev);
  216. }
  217. /**************************************************************************
  218. * IXDP2x00 Machine Setup
  219. *************************************************************************/
  220. static struct flash_platform_data ixdp2x00_platform_data = {
  221. .map_name = "cfi_probe",
  222. .width = 1,
  223. };
  224. static struct ixp2000_flash_data ixdp2x00_flash_data = {
  225. .platform_data = &ixdp2x00_platform_data,
  226. .nr_banks = 1
  227. };
  228. static struct resource ixdp2x00_flash_resource = {
  229. .start = 0xc4000000,
  230. .end = 0xc4000000 + 0x00ffffff,
  231. .flags = IORESOURCE_MEM,
  232. };
  233. static struct platform_device ixdp2x00_flash = {
  234. .name = "IXP2000-Flash",
  235. .id = 0,
  236. .dev = {
  237. .platform_data = &ixdp2x00_flash_data,
  238. },
  239. .num_resources = 1,
  240. .resource = &ixdp2x00_flash_resource,
  241. };
  242. static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = {
  243. .sda_pin = IXDP2X00_GPIO_SDA,
  244. .scl_pin = IXDP2X00_GPIO_SCL,
  245. };
  246. static struct platform_device ixdp2x00_i2c_controller = {
  247. .name = "IXP2000-I2C",
  248. .id = 0,
  249. .dev = {
  250. .platform_data = &ixdp2x00_i2c_gpio_pins,
  251. },
  252. .num_resources = 0
  253. };
  254. static struct platform_device *ixdp2x00_devices[] __initdata = {
  255. &ixdp2x00_flash,
  256. &ixdp2x00_i2c_controller
  257. };
  258. void __init ixdp2x00_init_machine(void)
  259. {
  260. gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1);
  261. gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
  262. platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));
  263. ixp2000_uart_init();
  264. }