autcpu12.h 2.5 KB

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  1. /*
  2. * AUTCPU12 specific defines
  3. *
  4. * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #ifndef __ASM_ARCH_AUTCPU12_H
  21. #define __ASM_ARCH_AUTCPU12_H
  22. /*
  23. * The CS8900A ethernet chip has its I/O registers wired to chip select 2
  24. * (nCS2). This is the mapping for it.
  25. */
  26. #define AUTCPU12_PHYS_CS8900A CS2_PHYS_BASE /* physical */
  27. #define AUTCPU12_VIRT_CS8900A (0xfe000000) /* virtual */
  28. /*
  29. * The flash bank is wired to chip select 0
  30. */
  31. #define AUTCPU12_PHYS_FLASH CS0_PHYS_BASE /* physical */
  32. /* offset for device specific information structure */
  33. #define AUTCPU12_LCDINFO_OFFS (0x00010000)
  34. /*
  35. * Videomemory is the internal SRAM (CS 6)
  36. */
  37. #define AUTCPU12_PHYS_VIDEO CS6_PHYS_BASE
  38. #define AUTCPU12_VIRT_VIDEO (0xfd000000)
  39. /*
  40. * All special IO's are tied to CS1
  41. */
  42. #define AUTCPU12_PHYS_CHAR_LCD CS1_PHYS_BASE +0x00000000 /* physical */
  43. #define AUTCPU12_PHYS_NVRAM CS1_PHYS_BASE +0x02000000 /* physical */
  44. #define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
  45. #define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */
  46. #define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
  47. #define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
  48. #define AUTCPU12_PHYS_IO CS1_PHYS_BASE +0x0C000000 /* physical */
  49. #define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
  50. /*
  51. * defines for smartmedia card access
  52. */
  53. #define AUTCPU12_SMC_RDY (1<<2)
  54. #define AUTCPU12_SMC_ALE (1<<3)
  55. #define AUTCPU12_SMC_CLE (1<<4)
  56. #define AUTCPU12_SMC_PORT_OFFSET PBDR
  57. #define AUTCPU12_SMC_SELECT_OFFSET 0x10
  58. /*
  59. * defines for lcd contrast
  60. */
  61. #define AUTCPU12_DPOT_PORT_OFFSET PEDR
  62. #define AUTCPU12_DPOT_CS (1<<0)
  63. #define AUTCPU12_DPOT_CLK (1<<1)
  64. #define AUTCPU12_DPOT_UD (1<<2)
  65. #endif