cs4231_lib.c 57 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
  4. *
  5. * Bugs:
  6. * - sometimes record brokes playback with WSS portion of
  7. * Yamaha OPL3-SA3 chip
  8. * - CS4231 (GUS MAX) - still trouble with occasional noises
  9. * - broken initialization?
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/slab.h>
  32. #include <linux/ioport.h>
  33. #include <sound/core.h>
  34. #include <sound/cs4231.h>
  35. #include <sound/pcm_params.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h>
  38. #include <asm/irq.h>
  39. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  40. MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
  41. MODULE_LICENSE("GPL");
  42. #if 0
  43. #define SNDRV_DEBUG_MCE
  44. #endif
  45. /*
  46. * Some variables
  47. */
  48. static unsigned char freq_bits[14] = {
  49. /* 5510 */ 0x00 | CS4231_XTAL2,
  50. /* 6620 */ 0x0E | CS4231_XTAL2,
  51. /* 8000 */ 0x00 | CS4231_XTAL1,
  52. /* 9600 */ 0x0E | CS4231_XTAL1,
  53. /* 11025 */ 0x02 | CS4231_XTAL2,
  54. /* 16000 */ 0x02 | CS4231_XTAL1,
  55. /* 18900 */ 0x04 | CS4231_XTAL2,
  56. /* 22050 */ 0x06 | CS4231_XTAL2,
  57. /* 27042 */ 0x04 | CS4231_XTAL1,
  58. /* 32000 */ 0x06 | CS4231_XTAL1,
  59. /* 33075 */ 0x0C | CS4231_XTAL2,
  60. /* 37800 */ 0x08 | CS4231_XTAL2,
  61. /* 44100 */ 0x0A | CS4231_XTAL2,
  62. /* 48000 */ 0x0C | CS4231_XTAL1
  63. };
  64. static unsigned int rates[14] = {
  65. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  66. 27042, 32000, 33075, 37800, 44100, 48000
  67. };
  68. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  69. .count = ARRAY_SIZE(rates),
  70. .list = rates,
  71. .mask = 0,
  72. };
  73. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  74. {
  75. return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  76. }
  77. static unsigned char snd_cs4231_original_image[32] =
  78. {
  79. 0x00, /* 00/00 - lic */
  80. 0x00, /* 01/01 - ric */
  81. 0x9f, /* 02/02 - la1ic */
  82. 0x9f, /* 03/03 - ra1ic */
  83. 0x9f, /* 04/04 - la2ic */
  84. 0x9f, /* 05/05 - ra2ic */
  85. 0xbf, /* 06/06 - loc */
  86. 0xbf, /* 07/07 - roc */
  87. 0x20, /* 08/08 - pdfr */
  88. CS4231_AUTOCALIB, /* 09/09 - ic */
  89. 0x00, /* 0a/10 - pc */
  90. 0x00, /* 0b/11 - ti */
  91. CS4231_MODE2, /* 0c/12 - mi */
  92. 0xfc, /* 0d/13 - lbc */
  93. 0x00, /* 0e/14 - pbru */
  94. 0x00, /* 0f/15 - pbrl */
  95. 0x80, /* 10/16 - afei */
  96. 0x01, /* 11/17 - afeii */
  97. 0x9f, /* 12/18 - llic */
  98. 0x9f, /* 13/19 - rlic */
  99. 0x00, /* 14/20 - tlb */
  100. 0x00, /* 15/21 - thb */
  101. 0x00, /* 16/22 - la3mic/reserved */
  102. 0x00, /* 17/23 - ra3mic/reserved */
  103. 0x00, /* 18/24 - afs */
  104. 0x00, /* 19/25 - lamoc/version */
  105. 0xcf, /* 1a/26 - mioc */
  106. 0x00, /* 1b/27 - ramoc/reserved */
  107. 0x20, /* 1c/28 - cdfr */
  108. 0x00, /* 1d/29 - res4 */
  109. 0x00, /* 1e/30 - cbru */
  110. 0x00, /* 1f/31 - cbrl */
  111. };
  112. /*
  113. * Basic I/O functions
  114. */
  115. static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val)
  116. {
  117. outb(val, chip->port + offset);
  118. }
  119. static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset)
  120. {
  121. return inb(chip->port + offset);
  122. }
  123. static void snd_cs4231_wait(struct snd_cs4231 *chip)
  124. {
  125. int timeout;
  126. for (timeout = 250;
  127. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  128. timeout--)
  129. udelay(100);
  130. }
  131. static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  132. unsigned char mask, unsigned char value)
  133. {
  134. unsigned char tmp = (chip->image[reg] & mask) | value;
  135. snd_cs4231_wait(chip);
  136. #ifdef CONFIG_SND_DEBUG
  137. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  138. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  139. #endif
  140. chip->image[reg] = tmp;
  141. if (!chip->calibrate_mute) {
  142. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  143. wmb();
  144. cs4231_outb(chip, CS4231P(REG), tmp);
  145. mb();
  146. }
  147. }
  148. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  149. {
  150. int timeout;
  151. for (timeout = 250;
  152. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  153. timeout--)
  154. udelay(10);
  155. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  156. cs4231_outb(chip, CS4231P(REG), value);
  157. mb();
  158. }
  159. void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  160. {
  161. snd_cs4231_wait(chip);
  162. #ifdef CONFIG_SND_DEBUG
  163. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  164. snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  165. #endif
  166. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  167. cs4231_outb(chip, CS4231P(REG), value);
  168. chip->image[reg] = value;
  169. mb();
  170. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  171. chip->mce_bit | reg, value);
  172. }
  173. unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  174. {
  175. snd_cs4231_wait(chip);
  176. #ifdef CONFIG_SND_DEBUG
  177. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  178. snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
  179. #endif
  180. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  181. mb();
  182. return cs4231_inb(chip, CS4231P(REG));
  183. }
  184. void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val)
  185. {
  186. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  187. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  188. cs4231_outb(chip, CS4231P(REG), val);
  189. chip->eimage[CS4236_REG(reg)] = val;
  190. #if 0
  191. printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
  192. #endif
  193. }
  194. unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg)
  195. {
  196. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  197. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  198. #if 1
  199. return cs4231_inb(chip, CS4231P(REG));
  200. #else
  201. {
  202. unsigned char res;
  203. res = cs4231_inb(chip, CS4231P(REG));
  204. printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
  205. return res;
  206. }
  207. #endif
  208. }
  209. #if 0
  210. static void snd_cs4231_debug(struct snd_cs4231 *chip)
  211. {
  212. printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
  213. printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
  214. printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
  215. printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
  216. printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
  217. printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
  218. printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
  219. printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
  220. printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
  221. printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
  222. printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
  223. printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
  224. printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
  225. printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
  226. printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
  227. printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
  228. printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
  229. printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
  230. printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
  231. printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
  232. printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
  233. printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
  234. printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
  235. printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
  236. printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
  237. printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
  238. printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
  239. printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
  240. printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
  241. printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
  242. printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
  243. printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
  244. printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
  245. printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
  246. }
  247. #endif
  248. /*
  249. * CS4231 detection / MCE routines
  250. */
  251. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  252. {
  253. int timeout;
  254. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  255. for (timeout = 5; timeout > 0; timeout--)
  256. cs4231_inb(chip, CS4231P(REGSEL));
  257. /* end of cleanup sequence */
  258. for (timeout = 250;
  259. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  260. timeout--)
  261. udelay(10);
  262. }
  263. void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  264. {
  265. unsigned long flags;
  266. int timeout;
  267. snd_cs4231_wait(chip);
  268. #ifdef CONFIG_SND_DEBUG
  269. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  270. snd_printk("mce_up - auto calibration time out (0)\n");
  271. #endif
  272. spin_lock_irqsave(&chip->reg_lock, flags);
  273. chip->mce_bit |= CS4231_MCE;
  274. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  275. if (timeout == 0x80)
  276. snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  277. if (!(timeout & CS4231_MCE))
  278. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  279. spin_unlock_irqrestore(&chip->reg_lock, flags);
  280. }
  281. void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  282. {
  283. unsigned long flags;
  284. int timeout;
  285. snd_cs4231_busy_wait(chip);
  286. #ifdef CONFIG_SND_DEBUG
  287. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  288. snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
  289. #endif
  290. spin_lock_irqsave(&chip->reg_lock, flags);
  291. chip->mce_bit &= ~CS4231_MCE;
  292. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  293. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  294. spin_unlock_irqrestore(&chip->reg_lock, flags);
  295. if (timeout == 0x80)
  296. snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  297. if ((timeout & CS4231_MCE) == 0 ||
  298. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  299. return;
  300. }
  301. snd_cs4231_busy_wait(chip);
  302. /*
  303. * Wait for (possible -- during init auto-calibration may not be set)
  304. * calibration process to start. Needs upto 5 sample periods on AD1848
  305. * which at the slowest possible rate of 5.5125 kHz means 907 us.
  306. */
  307. msleep(1);
  308. snd_printdd("(1) jiffies = %lu\n", jiffies);
  309. /* in 10 ms increments, check condition, up to 250 ms */
  310. timeout = 25;
  311. while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
  312. if (--timeout < 0) {
  313. snd_printk("mce_down - auto calibration time out (2)\n");
  314. return;
  315. }
  316. msleep(10);
  317. }
  318. snd_printdd("(2) jiffies = %lu\n", jiffies);
  319. /* in 10 ms increments, check condition, up to 100 ms */
  320. timeout = 10;
  321. while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  322. if (--timeout < 0) {
  323. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  324. return;
  325. }
  326. msleep(10);
  327. }
  328. snd_printdd("(3) jiffies = %lu\n", jiffies);
  329. snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
  330. }
  331. static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
  332. {
  333. switch (format & 0xe0) {
  334. case CS4231_LINEAR_16:
  335. case CS4231_LINEAR_16_BIG:
  336. size >>= 1;
  337. break;
  338. case CS4231_ADPCM_16:
  339. return size >> 2;
  340. }
  341. if (format & CS4231_STEREO)
  342. size >>= 1;
  343. return size;
  344. }
  345. static int snd_cs4231_trigger(struct snd_pcm_substream *substream,
  346. int cmd)
  347. {
  348. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  349. int result = 0;
  350. unsigned int what;
  351. struct snd_pcm_substream *s;
  352. int do_start;
  353. #if 0
  354. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
  355. #endif
  356. switch (cmd) {
  357. case SNDRV_PCM_TRIGGER_START:
  358. case SNDRV_PCM_TRIGGER_RESUME:
  359. do_start = 1; break;
  360. case SNDRV_PCM_TRIGGER_STOP:
  361. case SNDRV_PCM_TRIGGER_SUSPEND:
  362. do_start = 0; break;
  363. default:
  364. return -EINVAL;
  365. }
  366. what = 0;
  367. snd_pcm_group_for_each_entry(s, substream) {
  368. if (s == chip->playback_substream) {
  369. what |= CS4231_PLAYBACK_ENABLE;
  370. snd_pcm_trigger_done(s, substream);
  371. } else if (s == chip->capture_substream) {
  372. what |= CS4231_RECORD_ENABLE;
  373. snd_pcm_trigger_done(s, substream);
  374. }
  375. }
  376. spin_lock(&chip->reg_lock);
  377. if (do_start) {
  378. chip->image[CS4231_IFACE_CTRL] |= what;
  379. if (chip->trigger)
  380. chip->trigger(chip, what, 1);
  381. } else {
  382. chip->image[CS4231_IFACE_CTRL] &= ~what;
  383. if (chip->trigger)
  384. chip->trigger(chip, what, 0);
  385. }
  386. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  387. spin_unlock(&chip->reg_lock);
  388. #if 0
  389. snd_cs4231_debug(chip);
  390. #endif
  391. return result;
  392. }
  393. /*
  394. * CODEC I/O
  395. */
  396. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  397. {
  398. int i;
  399. for (i = 0; i < ARRAY_SIZE(rates); i++)
  400. if (rate == rates[i])
  401. return freq_bits[i];
  402. // snd_BUG();
  403. return freq_bits[ARRAY_SIZE(rates) - 1];
  404. }
  405. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip,
  406. int format,
  407. int channels)
  408. {
  409. unsigned char rformat;
  410. rformat = CS4231_LINEAR_8;
  411. switch (format) {
  412. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  413. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  414. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  415. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  416. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  417. }
  418. if (channels > 1)
  419. rformat |= CS4231_STEREO;
  420. #if 0
  421. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  422. #endif
  423. return rformat;
  424. }
  425. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  426. {
  427. unsigned long flags;
  428. mute = mute ? 1 : 0;
  429. spin_lock_irqsave(&chip->reg_lock, flags);
  430. if (chip->calibrate_mute == mute) {
  431. spin_unlock_irqrestore(&chip->reg_lock, flags);
  432. return;
  433. }
  434. if (!mute) {
  435. snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
  436. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
  437. snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
  438. }
  439. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  440. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  441. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  442. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  443. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  444. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  445. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  446. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  447. snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  448. if (chip->hardware == CS4231_HW_INTERWAVE) {
  449. snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
  450. snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
  451. snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
  452. snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
  453. }
  454. chip->calibrate_mute = mute;
  455. spin_unlock_irqrestore(&chip->reg_lock, flags);
  456. }
  457. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  458. struct snd_pcm_hw_params *params,
  459. unsigned char pdfr)
  460. {
  461. unsigned long flags;
  462. int full_calib = 1;
  463. mutex_lock(&chip->mce_mutex);
  464. snd_cs4231_calibrate_mute(chip, 1);
  465. if (chip->hardware == CS4231_HW_CS4231A ||
  466. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  467. spin_lock_irqsave(&chip->reg_lock, flags);
  468. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
  469. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
  470. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  471. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
  472. udelay(100); /* Fixes audible clicks at least on GUS MAX */
  473. full_calib = 0;
  474. }
  475. spin_unlock_irqrestore(&chip->reg_lock, flags);
  476. }
  477. if (full_calib) {
  478. snd_cs4231_mce_up(chip);
  479. spin_lock_irqsave(&chip->reg_lock, flags);
  480. if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
  481. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  482. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  483. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  484. pdfr);
  485. } else {
  486. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  487. }
  488. spin_unlock_irqrestore(&chip->reg_lock, flags);
  489. if (chip->hardware == CS4231_HW_OPL3SA2)
  490. udelay(100); /* this seems to help */
  491. snd_cs4231_mce_down(chip);
  492. }
  493. snd_cs4231_calibrate_mute(chip, 0);
  494. mutex_unlock(&chip->mce_mutex);
  495. }
  496. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  497. struct snd_pcm_hw_params *params,
  498. unsigned char cdfr)
  499. {
  500. unsigned long flags;
  501. int full_calib = 1;
  502. mutex_lock(&chip->mce_mutex);
  503. snd_cs4231_calibrate_mute(chip, 1);
  504. if (chip->hardware == CS4231_HW_CS4231A ||
  505. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  506. spin_lock_irqsave(&chip->reg_lock, flags);
  507. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
  508. (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  509. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
  510. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
  511. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
  512. full_calib = 0;
  513. }
  514. spin_unlock_irqrestore(&chip->reg_lock, flags);
  515. }
  516. if (full_calib) {
  517. snd_cs4231_mce_up(chip);
  518. spin_lock_irqsave(&chip->reg_lock, flags);
  519. if (chip->hardware != CS4231_HW_INTERWAVE) {
  520. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  521. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  522. ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  523. (cdfr & 0x0f));
  524. spin_unlock_irqrestore(&chip->reg_lock, flags);
  525. snd_cs4231_mce_down(chip);
  526. snd_cs4231_mce_up(chip);
  527. spin_lock_irqsave(&chip->reg_lock, flags);
  528. }
  529. }
  530. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  531. spin_unlock_irqrestore(&chip->reg_lock, flags);
  532. snd_cs4231_mce_down(chip);
  533. }
  534. snd_cs4231_calibrate_mute(chip, 0);
  535. mutex_unlock(&chip->mce_mutex);
  536. }
  537. /*
  538. * Timer interface
  539. */
  540. static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer)
  541. {
  542. struct snd_cs4231 *chip = snd_timer_chip(timer);
  543. if (chip->hardware & CS4231_HW_CS4236B_MASK)
  544. return 14467;
  545. else
  546. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  547. }
  548. static int snd_cs4231_timer_start(struct snd_timer * timer)
  549. {
  550. unsigned long flags;
  551. unsigned int ticks;
  552. struct snd_cs4231 *chip = snd_timer_chip(timer);
  553. spin_lock_irqsave(&chip->reg_lock, flags);
  554. ticks = timer->sticks;
  555. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  556. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  557. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  558. snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
  559. snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
  560. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  561. }
  562. spin_unlock_irqrestore(&chip->reg_lock, flags);
  563. return 0;
  564. }
  565. static int snd_cs4231_timer_stop(struct snd_timer * timer)
  566. {
  567. unsigned long flags;
  568. struct snd_cs4231 *chip = snd_timer_chip(timer);
  569. spin_lock_irqsave(&chip->reg_lock, flags);
  570. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  571. spin_unlock_irqrestore(&chip->reg_lock, flags);
  572. return 0;
  573. }
  574. static void snd_cs4231_init(struct snd_cs4231 *chip)
  575. {
  576. unsigned long flags;
  577. snd_cs4231_mce_down(chip);
  578. #ifdef SNDRV_DEBUG_MCE
  579. snd_printk("init: (1)\n");
  580. #endif
  581. snd_cs4231_mce_up(chip);
  582. spin_lock_irqsave(&chip->reg_lock, flags);
  583. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  584. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  585. CS4231_CALIB_MODE);
  586. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  587. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  588. spin_unlock_irqrestore(&chip->reg_lock, flags);
  589. snd_cs4231_mce_down(chip);
  590. #ifdef SNDRV_DEBUG_MCE
  591. snd_printk("init: (2)\n");
  592. #endif
  593. snd_cs4231_mce_up(chip);
  594. spin_lock_irqsave(&chip->reg_lock, flags);
  595. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  596. spin_unlock_irqrestore(&chip->reg_lock, flags);
  597. snd_cs4231_mce_down(chip);
  598. #ifdef SNDRV_DEBUG_MCE
  599. snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  600. #endif
  601. spin_lock_irqsave(&chip->reg_lock, flags);
  602. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  603. spin_unlock_irqrestore(&chip->reg_lock, flags);
  604. snd_cs4231_mce_up(chip);
  605. spin_lock_irqsave(&chip->reg_lock, flags);
  606. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  607. spin_unlock_irqrestore(&chip->reg_lock, flags);
  608. snd_cs4231_mce_down(chip);
  609. #ifdef SNDRV_DEBUG_MCE
  610. snd_printk("init: (4)\n");
  611. #endif
  612. snd_cs4231_mce_up(chip);
  613. spin_lock_irqsave(&chip->reg_lock, flags);
  614. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  615. spin_unlock_irqrestore(&chip->reg_lock, flags);
  616. snd_cs4231_mce_down(chip);
  617. #ifdef SNDRV_DEBUG_MCE
  618. snd_printk("init: (5)\n");
  619. #endif
  620. }
  621. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  622. {
  623. unsigned long flags;
  624. mutex_lock(&chip->open_mutex);
  625. if ((chip->mode & mode) ||
  626. ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
  627. mutex_unlock(&chip->open_mutex);
  628. return -EAGAIN;
  629. }
  630. if (chip->mode & CS4231_MODE_OPEN) {
  631. chip->mode |= mode;
  632. mutex_unlock(&chip->open_mutex);
  633. return 0;
  634. }
  635. /* ok. now enable and ack CODEC IRQ */
  636. spin_lock_irqsave(&chip->reg_lock, flags);
  637. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  638. CS4231_RECORD_IRQ |
  639. CS4231_TIMER_IRQ);
  640. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  641. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  642. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  643. chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
  644. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  645. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  646. CS4231_RECORD_IRQ |
  647. CS4231_TIMER_IRQ);
  648. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  649. spin_unlock_irqrestore(&chip->reg_lock, flags);
  650. chip->mode = mode;
  651. mutex_unlock(&chip->open_mutex);
  652. return 0;
  653. }
  654. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  655. {
  656. unsigned long flags;
  657. mutex_lock(&chip->open_mutex);
  658. chip->mode &= ~mode;
  659. if (chip->mode & CS4231_MODE_OPEN) {
  660. mutex_unlock(&chip->open_mutex);
  661. return;
  662. }
  663. snd_cs4231_calibrate_mute(chip, 1);
  664. /* disable IRQ */
  665. spin_lock_irqsave(&chip->reg_lock, flags);
  666. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  667. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  668. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  669. chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
  670. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  671. /* now disable record & playback */
  672. if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  673. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  674. spin_unlock_irqrestore(&chip->reg_lock, flags);
  675. snd_cs4231_mce_up(chip);
  676. spin_lock_irqsave(&chip->reg_lock, flags);
  677. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  678. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  679. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  680. spin_unlock_irqrestore(&chip->reg_lock, flags);
  681. snd_cs4231_mce_down(chip);
  682. spin_lock_irqsave(&chip->reg_lock, flags);
  683. }
  684. /* clear IRQ again */
  685. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  686. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  687. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  688. spin_unlock_irqrestore(&chip->reg_lock, flags);
  689. snd_cs4231_calibrate_mute(chip, 0);
  690. chip->mode = 0;
  691. mutex_unlock(&chip->open_mutex);
  692. }
  693. /*
  694. * timer open/close
  695. */
  696. static int snd_cs4231_timer_open(struct snd_timer * timer)
  697. {
  698. struct snd_cs4231 *chip = snd_timer_chip(timer);
  699. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  700. return 0;
  701. }
  702. static int snd_cs4231_timer_close(struct snd_timer * timer)
  703. {
  704. struct snd_cs4231 *chip = snd_timer_chip(timer);
  705. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  706. return 0;
  707. }
  708. static struct snd_timer_hardware snd_cs4231_timer_table =
  709. {
  710. .flags = SNDRV_TIMER_HW_AUTO,
  711. .resolution = 9945,
  712. .ticks = 65535,
  713. .open = snd_cs4231_timer_open,
  714. .close = snd_cs4231_timer_close,
  715. .c_resolution = snd_cs4231_timer_resolution,
  716. .start = snd_cs4231_timer_start,
  717. .stop = snd_cs4231_timer_stop,
  718. };
  719. /*
  720. * ok.. exported functions..
  721. */
  722. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  723. struct snd_pcm_hw_params *hw_params)
  724. {
  725. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  726. unsigned char new_pdfr;
  727. int err;
  728. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  729. return err;
  730. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  731. snd_cs4231_get_rate(params_rate(hw_params));
  732. chip->set_playback_format(chip, hw_params, new_pdfr);
  733. return 0;
  734. }
  735. static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
  736. {
  737. return snd_pcm_lib_free_pages(substream);
  738. }
  739. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  740. {
  741. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  742. struct snd_pcm_runtime *runtime = substream->runtime;
  743. unsigned long flags;
  744. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  745. unsigned int count = snd_pcm_lib_period_bytes(substream);
  746. spin_lock_irqsave(&chip->reg_lock, flags);
  747. chip->p_dma_size = size;
  748. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
  749. snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  750. count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
  751. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  752. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  753. spin_unlock_irqrestore(&chip->reg_lock, flags);
  754. #if 0
  755. snd_cs4231_debug(chip);
  756. #endif
  757. return 0;
  758. }
  759. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  760. struct snd_pcm_hw_params *hw_params)
  761. {
  762. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  763. unsigned char new_cdfr;
  764. int err;
  765. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  766. return err;
  767. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  768. snd_cs4231_get_rate(params_rate(hw_params));
  769. chip->set_capture_format(chip, hw_params, new_cdfr);
  770. return 0;
  771. }
  772. static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
  773. {
  774. return snd_pcm_lib_free_pages(substream);
  775. }
  776. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  777. {
  778. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  779. struct snd_pcm_runtime *runtime = substream->runtime;
  780. unsigned long flags;
  781. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  782. unsigned int count = snd_pcm_lib_period_bytes(substream);
  783. spin_lock_irqsave(&chip->reg_lock, flags);
  784. chip->c_dma_size = size;
  785. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  786. snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  787. count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
  788. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  789. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  790. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  791. } else {
  792. snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
  793. snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
  794. }
  795. spin_unlock_irqrestore(&chip->reg_lock, flags);
  796. return 0;
  797. }
  798. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  799. {
  800. unsigned long flags;
  801. unsigned char res;
  802. spin_lock_irqsave(&chip->reg_lock, flags);
  803. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  804. spin_unlock_irqrestore(&chip->reg_lock, flags);
  805. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  806. chip->capture_substream->runtime->overrange++;
  807. }
  808. irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id)
  809. {
  810. struct snd_cs4231 *chip = dev_id;
  811. unsigned char status;
  812. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  813. if (status & CS4231_TIMER_IRQ) {
  814. if (chip->timer)
  815. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  816. }
  817. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  818. if (status & CS4231_PLAYBACK_IRQ) {
  819. if (chip->mode & CS4231_MODE_PLAY) {
  820. if (chip->playback_substream)
  821. snd_pcm_period_elapsed(chip->playback_substream);
  822. }
  823. if (chip->mode & CS4231_MODE_RECORD) {
  824. if (chip->capture_substream) {
  825. snd_cs4231_overrange(chip);
  826. snd_pcm_period_elapsed(chip->capture_substream);
  827. }
  828. }
  829. }
  830. } else {
  831. if (status & CS4231_PLAYBACK_IRQ) {
  832. if (chip->playback_substream)
  833. snd_pcm_period_elapsed(chip->playback_substream);
  834. }
  835. if (status & CS4231_RECORD_IRQ) {
  836. if (chip->capture_substream) {
  837. snd_cs4231_overrange(chip);
  838. snd_pcm_period_elapsed(chip->capture_substream);
  839. }
  840. }
  841. }
  842. spin_lock(&chip->reg_lock);
  843. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  844. spin_unlock(&chip->reg_lock);
  845. return IRQ_HANDLED;
  846. }
  847. static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
  848. {
  849. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  850. size_t ptr;
  851. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  852. return 0;
  853. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  854. return bytes_to_frames(substream->runtime, ptr);
  855. }
  856. static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
  857. {
  858. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  859. size_t ptr;
  860. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  861. return 0;
  862. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  863. return bytes_to_frames(substream->runtime, ptr);
  864. }
  865. /*
  866. */
  867. static int snd_cs4231_probe(struct snd_cs4231 *chip)
  868. {
  869. unsigned long flags;
  870. int i, id, rev;
  871. unsigned char *ptr;
  872. unsigned int hw;
  873. #if 0
  874. snd_cs4231_debug(chip);
  875. #endif
  876. id = 0;
  877. for (i = 0; i < 50; i++) {
  878. mb();
  879. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  880. udelay(2000);
  881. else {
  882. spin_lock_irqsave(&chip->reg_lock, flags);
  883. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  884. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  885. spin_unlock_irqrestore(&chip->reg_lock, flags);
  886. if (id == 0x0a)
  887. break; /* this is valid value */
  888. }
  889. }
  890. snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
  891. if (id != 0x0a)
  892. return -ENODEV; /* no valid device found */
  893. if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  894. rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
  895. snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
  896. if (rev == 0x80) {
  897. unsigned char tmp = snd_cs4231_in(chip, 23);
  898. snd_cs4231_out(chip, 23, ~tmp);
  899. if (snd_cs4231_in(chip, 23) != tmp)
  900. chip->hardware = CS4231_HW_AD1845;
  901. else
  902. chip->hardware = CS4231_HW_CS4231;
  903. } else if (rev == 0xa0) {
  904. chip->hardware = CS4231_HW_CS4231A;
  905. } else if (rev == 0xa2) {
  906. chip->hardware = CS4231_HW_CS4232;
  907. } else if (rev == 0xb2) {
  908. chip->hardware = CS4231_HW_CS4232A;
  909. } else if (rev == 0x83) {
  910. chip->hardware = CS4231_HW_CS4236;
  911. } else if (rev == 0x03) {
  912. chip->hardware = CS4231_HW_CS4236B;
  913. } else {
  914. snd_printk("unknown CS chip with version 0x%x\n", rev);
  915. return -ENODEV; /* unknown CS4231 chip? */
  916. }
  917. }
  918. spin_lock_irqsave(&chip->reg_lock, flags);
  919. cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
  920. cs4231_outb(chip, CS4231P(STATUS), 0);
  921. mb();
  922. spin_unlock_irqrestore(&chip->reg_lock, flags);
  923. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  924. switch (chip->hardware) {
  925. case CS4231_HW_INTERWAVE:
  926. chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
  927. break;
  928. case CS4231_HW_CS4235:
  929. case CS4231_HW_CS4236B:
  930. case CS4231_HW_CS4237B:
  931. case CS4231_HW_CS4238B:
  932. case CS4231_HW_CS4239:
  933. if (hw == CS4231_HW_DETECT3)
  934. chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
  935. else
  936. chip->hardware = CS4231_HW_CS4236;
  937. break;
  938. }
  939. chip->image[CS4231_IFACE_CTRL] =
  940. (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
  941. (chip->single_dma ? CS4231_SINGLE_DMA : 0);
  942. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  943. chip->image[CS4231_ALT_FEATURE_2] = chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
  944. ptr = (unsigned char *) &chip->image;
  945. snd_cs4231_mce_down(chip);
  946. spin_lock_irqsave(&chip->reg_lock, flags);
  947. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  948. snd_cs4231_out(chip, i, *ptr++);
  949. spin_unlock_irqrestore(&chip->reg_lock, flags);
  950. snd_cs4231_mce_up(chip);
  951. snd_cs4231_mce_down(chip);
  952. mdelay(2);
  953. /* ok.. try check hardware version for CS4236+ chips */
  954. if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  955. if (chip->hardware == CS4231_HW_CS4236B) {
  956. rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
  957. snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
  958. id = snd_cs4236_ext_in(chip, CS4236_VERSION);
  959. snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
  960. snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
  961. if ((id & 0x1f) == 0x1d) { /* CS4235 */
  962. chip->hardware = CS4231_HW_CS4235;
  963. switch (id >> 5) {
  964. case 4:
  965. case 5:
  966. case 6:
  967. break;
  968. default:
  969. snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
  970. }
  971. } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
  972. switch (id >> 5) {
  973. case 4:
  974. case 5:
  975. case 6:
  976. case 7:
  977. chip->hardware = CS4231_HW_CS4236B;
  978. break;
  979. default:
  980. snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
  981. }
  982. } else if ((id & 0x1f) == 0x08) { /* CS4237B */
  983. chip->hardware = CS4231_HW_CS4237B;
  984. switch (id >> 5) {
  985. case 4:
  986. case 5:
  987. case 6:
  988. case 7:
  989. break;
  990. default:
  991. snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
  992. }
  993. } else if ((id & 0x1f) == 0x09) { /* CS4238B */
  994. chip->hardware = CS4231_HW_CS4238B;
  995. switch (id >> 5) {
  996. case 5:
  997. case 6:
  998. case 7:
  999. break;
  1000. default:
  1001. snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
  1002. }
  1003. } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
  1004. chip->hardware = CS4231_HW_CS4239;
  1005. switch (id >> 5) {
  1006. case 4:
  1007. case 5:
  1008. case 6:
  1009. break;
  1010. default:
  1011. snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
  1012. }
  1013. } else {
  1014. snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
  1015. }
  1016. }
  1017. }
  1018. return 0; /* all things are ok.. */
  1019. }
  1020. /*
  1021. */
  1022. static struct snd_pcm_hardware snd_cs4231_playback =
  1023. {
  1024. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1025. SNDRV_PCM_INFO_MMAP_VALID |
  1026. SNDRV_PCM_INFO_RESUME |
  1027. SNDRV_PCM_INFO_SYNC_START),
  1028. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1029. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1030. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1031. .rate_min = 5510,
  1032. .rate_max = 48000,
  1033. .channels_min = 1,
  1034. .channels_max = 2,
  1035. .buffer_bytes_max = (128*1024),
  1036. .period_bytes_min = 64,
  1037. .period_bytes_max = (128*1024),
  1038. .periods_min = 1,
  1039. .periods_max = 1024,
  1040. .fifo_size = 0,
  1041. };
  1042. static struct snd_pcm_hardware snd_cs4231_capture =
  1043. {
  1044. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1045. SNDRV_PCM_INFO_MMAP_VALID |
  1046. SNDRV_PCM_INFO_RESUME |
  1047. SNDRV_PCM_INFO_SYNC_START),
  1048. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1049. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1050. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1051. .rate_min = 5510,
  1052. .rate_max = 48000,
  1053. .channels_min = 1,
  1054. .channels_max = 2,
  1055. .buffer_bytes_max = (128*1024),
  1056. .period_bytes_min = 64,
  1057. .period_bytes_max = (128*1024),
  1058. .periods_min = 1,
  1059. .periods_max = 1024,
  1060. .fifo_size = 0,
  1061. };
  1062. /*
  1063. */
  1064. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  1065. {
  1066. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1067. struct snd_pcm_runtime *runtime = substream->runtime;
  1068. int err;
  1069. runtime->hw = snd_cs4231_playback;
  1070. /* hardware bug in InterWave chipset */
  1071. if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
  1072. runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
  1073. /* hardware limitation of cheap chips */
  1074. if (chip->hardware == CS4231_HW_CS4235 ||
  1075. chip->hardware == CS4231_HW_CS4239)
  1076. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1077. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  1078. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  1079. if (chip->claim_dma) {
  1080. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
  1081. return err;
  1082. }
  1083. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1084. if (chip->release_dma)
  1085. chip->release_dma(chip, chip->dma_private_data, chip->dma1);
  1086. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1087. return err;
  1088. }
  1089. chip->playback_substream = substream;
  1090. snd_pcm_set_sync(substream);
  1091. chip->rate_constraint(runtime);
  1092. return 0;
  1093. }
  1094. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  1095. {
  1096. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1097. struct snd_pcm_runtime *runtime = substream->runtime;
  1098. int err;
  1099. runtime->hw = snd_cs4231_capture;
  1100. /* hardware limitation of cheap chips */
  1101. if (chip->hardware == CS4231_HW_CS4235 ||
  1102. chip->hardware == CS4231_HW_CS4239)
  1103. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1104. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  1105. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  1106. if (chip->claim_dma) {
  1107. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
  1108. return err;
  1109. }
  1110. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1111. if (chip->release_dma)
  1112. chip->release_dma(chip, chip->dma_private_data, chip->dma2);
  1113. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1114. return err;
  1115. }
  1116. chip->capture_substream = substream;
  1117. snd_pcm_set_sync(substream);
  1118. chip->rate_constraint(runtime);
  1119. return 0;
  1120. }
  1121. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1122. {
  1123. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1124. chip->playback_substream = NULL;
  1125. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1126. return 0;
  1127. }
  1128. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1129. {
  1130. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1131. chip->capture_substream = NULL;
  1132. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1133. return 0;
  1134. }
  1135. #ifdef CONFIG_PM
  1136. /* lowlevel suspend callback for CS4231 */
  1137. static void snd_cs4231_suspend(struct snd_cs4231 *chip)
  1138. {
  1139. int reg;
  1140. unsigned long flags;
  1141. snd_pcm_suspend_all(chip->pcm);
  1142. spin_lock_irqsave(&chip->reg_lock, flags);
  1143. for (reg = 0; reg < 32; reg++)
  1144. chip->image[reg] = snd_cs4231_in(chip, reg);
  1145. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1146. }
  1147. /* lowlevel resume callback for CS4231 */
  1148. static void snd_cs4231_resume(struct snd_cs4231 *chip)
  1149. {
  1150. int reg;
  1151. unsigned long flags;
  1152. /* int timeout; */
  1153. snd_cs4231_mce_up(chip);
  1154. spin_lock_irqsave(&chip->reg_lock, flags);
  1155. for (reg = 0; reg < 32; reg++) {
  1156. switch (reg) {
  1157. case CS4231_VERSION:
  1158. break;
  1159. default:
  1160. snd_cs4231_out(chip, reg, chip->image[reg]);
  1161. break;
  1162. }
  1163. }
  1164. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1165. #if 1
  1166. snd_cs4231_mce_down(chip);
  1167. #else
  1168. /* The following is a workaround to avoid freeze after resume on TP600E.
  1169. This is the first half of copy of snd_cs4231_mce_down(), but doesn't
  1170. include rescheduling. -- iwai
  1171. */
  1172. snd_cs4231_busy_wait(chip);
  1173. spin_lock_irqsave(&chip->reg_lock, flags);
  1174. chip->mce_bit &= ~CS4231_MCE;
  1175. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  1176. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  1177. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1178. if (timeout == 0x80)
  1179. snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  1180. if ((timeout & CS4231_MCE) == 0 ||
  1181. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  1182. return;
  1183. }
  1184. snd_cs4231_busy_wait(chip);
  1185. #endif
  1186. }
  1187. #endif /* CONFIG_PM */
  1188. static int snd_cs4231_free(struct snd_cs4231 *chip)
  1189. {
  1190. release_and_free_resource(chip->res_port);
  1191. release_and_free_resource(chip->res_cport);
  1192. if (chip->irq >= 0) {
  1193. disable_irq(chip->irq);
  1194. if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
  1195. free_irq(chip->irq, (void *) chip);
  1196. }
  1197. if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
  1198. snd_dma_disable(chip->dma1);
  1199. free_dma(chip->dma1);
  1200. }
  1201. if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
  1202. snd_dma_disable(chip->dma2);
  1203. free_dma(chip->dma2);
  1204. }
  1205. if (chip->timer)
  1206. snd_device_free(chip->card, chip->timer);
  1207. kfree(chip);
  1208. return 0;
  1209. }
  1210. static int snd_cs4231_dev_free(struct snd_device *device)
  1211. {
  1212. struct snd_cs4231 *chip = device->device_data;
  1213. return snd_cs4231_free(chip);
  1214. }
  1215. const char *snd_cs4231_chip_id(struct snd_cs4231 *chip)
  1216. {
  1217. switch (chip->hardware) {
  1218. case CS4231_HW_CS4231: return "CS4231";
  1219. case CS4231_HW_CS4231A: return "CS4231A";
  1220. case CS4231_HW_CS4232: return "CS4232";
  1221. case CS4231_HW_CS4232A: return "CS4232A";
  1222. case CS4231_HW_CS4235: return "CS4235";
  1223. case CS4231_HW_CS4236: return "CS4236";
  1224. case CS4231_HW_CS4236B: return "CS4236B";
  1225. case CS4231_HW_CS4237B: return "CS4237B";
  1226. case CS4231_HW_CS4238B: return "CS4238B";
  1227. case CS4231_HW_CS4239: return "CS4239";
  1228. case CS4231_HW_INTERWAVE: return "AMD InterWave";
  1229. case CS4231_HW_OPL3SA2: return chip->card->shortname;
  1230. case CS4231_HW_AD1845: return "AD1845";
  1231. default: return "???";
  1232. }
  1233. }
  1234. static int snd_cs4231_new(struct snd_card *card,
  1235. unsigned short hardware,
  1236. unsigned short hwshare,
  1237. struct snd_cs4231 ** rchip)
  1238. {
  1239. struct snd_cs4231 *chip;
  1240. *rchip = NULL;
  1241. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1242. if (chip == NULL)
  1243. return -ENOMEM;
  1244. chip->hardware = hardware;
  1245. chip->hwshare = hwshare;
  1246. spin_lock_init(&chip->reg_lock);
  1247. mutex_init(&chip->mce_mutex);
  1248. mutex_init(&chip->open_mutex);
  1249. chip->card = card;
  1250. chip->rate_constraint = snd_cs4231_xrate;
  1251. chip->set_playback_format = snd_cs4231_playback_format;
  1252. chip->set_capture_format = snd_cs4231_capture_format;
  1253. memcpy(&chip->image, &snd_cs4231_original_image, sizeof(snd_cs4231_original_image));
  1254. *rchip = chip;
  1255. return 0;
  1256. }
  1257. int snd_cs4231_create(struct snd_card *card,
  1258. unsigned long port,
  1259. unsigned long cport,
  1260. int irq, int dma1, int dma2,
  1261. unsigned short hardware,
  1262. unsigned short hwshare,
  1263. struct snd_cs4231 ** rchip)
  1264. {
  1265. static struct snd_device_ops ops = {
  1266. .dev_free = snd_cs4231_dev_free,
  1267. };
  1268. struct snd_cs4231 *chip;
  1269. int err;
  1270. err = snd_cs4231_new(card, hardware, hwshare, &chip);
  1271. if (err < 0)
  1272. return err;
  1273. chip->irq = -1;
  1274. chip->dma1 = -1;
  1275. chip->dma2 = -1;
  1276. if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
  1277. snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
  1278. snd_cs4231_free(chip);
  1279. return -EBUSY;
  1280. }
  1281. chip->port = port;
  1282. if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
  1283. snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
  1284. snd_cs4231_free(chip);
  1285. return -ENODEV;
  1286. }
  1287. chip->cport = cport;
  1288. if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) {
  1289. snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
  1290. snd_cs4231_free(chip);
  1291. return -EBUSY;
  1292. }
  1293. chip->irq = irq;
  1294. if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
  1295. snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
  1296. snd_cs4231_free(chip);
  1297. return -EBUSY;
  1298. }
  1299. chip->dma1 = dma1;
  1300. if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
  1301. snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
  1302. snd_cs4231_free(chip);
  1303. return -EBUSY;
  1304. }
  1305. if (dma1 == dma2 || dma2 < 0) {
  1306. chip->single_dma = 1;
  1307. chip->dma2 = chip->dma1;
  1308. } else
  1309. chip->dma2 = dma2;
  1310. /* global setup */
  1311. if (snd_cs4231_probe(chip) < 0) {
  1312. snd_cs4231_free(chip);
  1313. return -ENODEV;
  1314. }
  1315. snd_cs4231_init(chip);
  1316. #if 0
  1317. if (chip->hardware & CS4231_HW_CS4232_MASK) {
  1318. if (chip->res_cport == NULL)
  1319. snd_printk("CS4232 control port features are not accessible\n");
  1320. }
  1321. #endif
  1322. /* Register device */
  1323. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1324. snd_cs4231_free(chip);
  1325. return err;
  1326. }
  1327. #ifdef CONFIG_PM
  1328. /* Power Management */
  1329. chip->suspend = snd_cs4231_suspend;
  1330. chip->resume = snd_cs4231_resume;
  1331. #endif
  1332. *rchip = chip;
  1333. return 0;
  1334. }
  1335. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1336. .open = snd_cs4231_playback_open,
  1337. .close = snd_cs4231_playback_close,
  1338. .ioctl = snd_pcm_lib_ioctl,
  1339. .hw_params = snd_cs4231_playback_hw_params,
  1340. .hw_free = snd_cs4231_playback_hw_free,
  1341. .prepare = snd_cs4231_playback_prepare,
  1342. .trigger = snd_cs4231_trigger,
  1343. .pointer = snd_cs4231_playback_pointer,
  1344. };
  1345. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1346. .open = snd_cs4231_capture_open,
  1347. .close = snd_cs4231_capture_close,
  1348. .ioctl = snd_pcm_lib_ioctl,
  1349. .hw_params = snd_cs4231_capture_hw_params,
  1350. .hw_free = snd_cs4231_capture_hw_free,
  1351. .prepare = snd_cs4231_capture_prepare,
  1352. .trigger = snd_cs4231_trigger,
  1353. .pointer = snd_cs4231_capture_pointer,
  1354. };
  1355. int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm)
  1356. {
  1357. struct snd_pcm *pcm;
  1358. int err;
  1359. if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
  1360. return err;
  1361. spin_lock_init(&chip->reg_lock);
  1362. mutex_init(&chip->mce_mutex);
  1363. mutex_init(&chip->open_mutex);
  1364. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1365. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1366. /* global setup */
  1367. pcm->private_data = chip;
  1368. pcm->info_flags = 0;
  1369. if (chip->single_dma)
  1370. pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
  1371. if (chip->hardware != CS4231_HW_INTERWAVE)
  1372. pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
  1373. strcpy(pcm->name, snd_cs4231_chip_id(chip));
  1374. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1375. snd_dma_isa_data(),
  1376. 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
  1377. chip->pcm = pcm;
  1378. if (rpcm)
  1379. *rpcm = pcm;
  1380. return 0;
  1381. }
  1382. static void snd_cs4231_timer_free(struct snd_timer *timer)
  1383. {
  1384. struct snd_cs4231 *chip = timer->private_data;
  1385. chip->timer = NULL;
  1386. }
  1387. int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer)
  1388. {
  1389. struct snd_timer *timer;
  1390. struct snd_timer_id tid;
  1391. int err;
  1392. /* Timer initialization */
  1393. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1394. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1395. tid.card = chip->card->number;
  1396. tid.device = device;
  1397. tid.subdevice = 0;
  1398. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1399. return err;
  1400. strcpy(timer->name, snd_cs4231_chip_id(chip));
  1401. timer->private_data = chip;
  1402. timer->private_free = snd_cs4231_timer_free;
  1403. timer->hw = snd_cs4231_timer_table;
  1404. chip->timer = timer;
  1405. if (rtimer)
  1406. *rtimer = timer;
  1407. return 0;
  1408. }
  1409. /*
  1410. * MIXER part
  1411. */
  1412. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1413. {
  1414. static char *texts[4] = {
  1415. "Line", "Aux", "Mic", "Mix"
  1416. };
  1417. static char *opl3sa_texts[4] = {
  1418. "Line", "CD", "Mic", "Mix"
  1419. };
  1420. static char *gusmax_texts[4] = {
  1421. "Line", "Synth", "Mic", "Mix"
  1422. };
  1423. char **ptexts = texts;
  1424. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1425. snd_assert(chip->card != NULL, return -EINVAL);
  1426. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1427. uinfo->count = 2;
  1428. uinfo->value.enumerated.items = 4;
  1429. if (uinfo->value.enumerated.item > 3)
  1430. uinfo->value.enumerated.item = 3;
  1431. if (!strcmp(chip->card->driver, "GUS MAX"))
  1432. ptexts = gusmax_texts;
  1433. switch (chip->hardware) {
  1434. case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
  1435. case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
  1436. }
  1437. strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
  1438. return 0;
  1439. }
  1440. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1441. {
  1442. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1443. unsigned long flags;
  1444. spin_lock_irqsave(&chip->reg_lock, flags);
  1445. ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1446. ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1447. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1448. return 0;
  1449. }
  1450. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1451. {
  1452. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1453. unsigned long flags;
  1454. unsigned short left, right;
  1455. int change;
  1456. if (ucontrol->value.enumerated.item[0] > 3 ||
  1457. ucontrol->value.enumerated.item[1] > 3)
  1458. return -EINVAL;
  1459. left = ucontrol->value.enumerated.item[0] << 6;
  1460. right = ucontrol->value.enumerated.item[1] << 6;
  1461. spin_lock_irqsave(&chip->reg_lock, flags);
  1462. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1463. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1464. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1465. right != chip->image[CS4231_RIGHT_INPUT];
  1466. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1467. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1468. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1469. return change;
  1470. }
  1471. int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1472. {
  1473. int mask = (kcontrol->private_value >> 16) & 0xff;
  1474. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1475. uinfo->count = 1;
  1476. uinfo->value.integer.min = 0;
  1477. uinfo->value.integer.max = mask;
  1478. return 0;
  1479. }
  1480. int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1481. {
  1482. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1483. unsigned long flags;
  1484. int reg = kcontrol->private_value & 0xff;
  1485. int shift = (kcontrol->private_value >> 8) & 0xff;
  1486. int mask = (kcontrol->private_value >> 16) & 0xff;
  1487. int invert = (kcontrol->private_value >> 24) & 0xff;
  1488. spin_lock_irqsave(&chip->reg_lock, flags);
  1489. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1490. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1491. if (invert)
  1492. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1493. return 0;
  1494. }
  1495. int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1496. {
  1497. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1498. unsigned long flags;
  1499. int reg = kcontrol->private_value & 0xff;
  1500. int shift = (kcontrol->private_value >> 8) & 0xff;
  1501. int mask = (kcontrol->private_value >> 16) & 0xff;
  1502. int invert = (kcontrol->private_value >> 24) & 0xff;
  1503. int change;
  1504. unsigned short val;
  1505. val = (ucontrol->value.integer.value[0] & mask);
  1506. if (invert)
  1507. val = mask - val;
  1508. val <<= shift;
  1509. spin_lock_irqsave(&chip->reg_lock, flags);
  1510. val = (chip->image[reg] & ~(mask << shift)) | val;
  1511. change = val != chip->image[reg];
  1512. snd_cs4231_out(chip, reg, val);
  1513. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1514. return change;
  1515. }
  1516. int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1517. {
  1518. int mask = (kcontrol->private_value >> 24) & 0xff;
  1519. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1520. uinfo->count = 2;
  1521. uinfo->value.integer.min = 0;
  1522. uinfo->value.integer.max = mask;
  1523. return 0;
  1524. }
  1525. int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1526. {
  1527. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1528. unsigned long flags;
  1529. int left_reg = kcontrol->private_value & 0xff;
  1530. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1531. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1532. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1533. int mask = (kcontrol->private_value >> 24) & 0xff;
  1534. int invert = (kcontrol->private_value >> 22) & 1;
  1535. spin_lock_irqsave(&chip->reg_lock, flags);
  1536. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1537. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1538. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1539. if (invert) {
  1540. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1541. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1542. }
  1543. return 0;
  1544. }
  1545. int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1548. unsigned long flags;
  1549. int left_reg = kcontrol->private_value & 0xff;
  1550. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1551. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1552. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1553. int mask = (kcontrol->private_value >> 24) & 0xff;
  1554. int invert = (kcontrol->private_value >> 22) & 1;
  1555. int change;
  1556. unsigned short val1, val2;
  1557. val1 = ucontrol->value.integer.value[0] & mask;
  1558. val2 = ucontrol->value.integer.value[1] & mask;
  1559. if (invert) {
  1560. val1 = mask - val1;
  1561. val2 = mask - val2;
  1562. }
  1563. val1 <<= shift_left;
  1564. val2 <<= shift_right;
  1565. spin_lock_irqsave(&chip->reg_lock, flags);
  1566. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1567. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1568. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1569. snd_cs4231_out(chip, left_reg, val1);
  1570. snd_cs4231_out(chip, right_reg, val2);
  1571. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1572. return change;
  1573. }
  1574. static struct snd_kcontrol_new snd_cs4231_controls[] = {
  1575. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1576. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1577. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1578. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1579. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1580. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1581. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1582. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1583. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1584. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1585. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1586. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1587. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1588. {
  1589. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1590. .name = "Capture Source",
  1591. .info = snd_cs4231_info_mux,
  1592. .get = snd_cs4231_get_mux,
  1593. .put = snd_cs4231_put_mux,
  1594. },
  1595. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1596. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1597. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
  1598. };
  1599. int snd_cs4231_mixer(struct snd_cs4231 *chip)
  1600. {
  1601. struct snd_card *card;
  1602. unsigned int idx;
  1603. int err;
  1604. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1605. card = chip->card;
  1606. strcpy(card->mixername, chip->pcm->name);
  1607. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1608. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4231_controls[idx], chip))) < 0)
  1609. return err;
  1610. }
  1611. return 0;
  1612. }
  1613. EXPORT_SYMBOL(snd_cs4231_out);
  1614. EXPORT_SYMBOL(snd_cs4231_in);
  1615. EXPORT_SYMBOL(snd_cs4236_ext_out);
  1616. EXPORT_SYMBOL(snd_cs4236_ext_in);
  1617. EXPORT_SYMBOL(snd_cs4231_mce_up);
  1618. EXPORT_SYMBOL(snd_cs4231_mce_down);
  1619. EXPORT_SYMBOL(snd_cs4231_interrupt);
  1620. EXPORT_SYMBOL(snd_cs4231_chip_id);
  1621. EXPORT_SYMBOL(snd_cs4231_create);
  1622. EXPORT_SYMBOL(snd_cs4231_pcm);
  1623. EXPORT_SYMBOL(snd_cs4231_mixer);
  1624. EXPORT_SYMBOL(snd_cs4231_timer);
  1625. EXPORT_SYMBOL(snd_cs4231_info_single);
  1626. EXPORT_SYMBOL(snd_cs4231_get_single);
  1627. EXPORT_SYMBOL(snd_cs4231_put_single);
  1628. EXPORT_SYMBOL(snd_cs4231_info_double);
  1629. EXPORT_SYMBOL(snd_cs4231_get_double);
  1630. EXPORT_SYMBOL(snd_cs4231_put_double);
  1631. /*
  1632. * INIT part
  1633. */
  1634. static int __init alsa_cs4231_init(void)
  1635. {
  1636. return 0;
  1637. }
  1638. static void __exit alsa_cs4231_exit(void)
  1639. {
  1640. }
  1641. module_init(alsa_cs4231_init)
  1642. module_exit(alsa_cs4231_exit)