be_main.c 154 KB

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  1. /**
  2. * Copyright (C) 2005 - 2013 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
  145. DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
  146. DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
  147. DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
  148. beiscsi_active_session_disp, NULL);
  149. DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
  150. beiscsi_free_session_disp, NULL);
  151. struct device_attribute *beiscsi_attrs[] = {
  152. &dev_attr_beiscsi_log_enable,
  153. &dev_attr_beiscsi_drvr_ver,
  154. &dev_attr_beiscsi_adapter_family,
  155. &dev_attr_beiscsi_fw_ver,
  156. &dev_attr_beiscsi_active_session_count,
  157. &dev_attr_beiscsi_free_session_count,
  158. &dev_attr_beiscsi_phys_port,
  159. NULL,
  160. };
  161. static char const *cqe_desc[] = {
  162. "RESERVED_DESC",
  163. "SOL_CMD_COMPLETE",
  164. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  165. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  166. "CXN_KILLED_BURST_LEN_MISMATCH",
  167. "CXN_KILLED_AHS_RCVD",
  168. "CXN_KILLED_HDR_DIGEST_ERR",
  169. "CXN_KILLED_UNKNOWN_HDR",
  170. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  171. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  172. "CXN_KILLED_RST_RCVD",
  173. "CXN_KILLED_TIMED_OUT",
  174. "CXN_KILLED_RST_SENT",
  175. "CXN_KILLED_FIN_RCVD",
  176. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  177. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  178. "CXN_KILLED_OVER_RUN_RESIDUAL",
  179. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  180. "CMD_KILLED_INVALID_STATSN_RCVD",
  181. "CMD_KILLED_INVALID_R2T_RCVD",
  182. "CMD_CXN_KILLED_LUN_INVALID",
  183. "CMD_CXN_KILLED_ICD_INVALID",
  184. "CMD_CXN_KILLED_ITT_INVALID",
  185. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  186. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  187. "CXN_INVALIDATE_NOTIFY",
  188. "CXN_INVALIDATE_INDEX_NOTIFY",
  189. "CMD_INVALIDATED_NOTIFY",
  190. "UNSOL_HDR_NOTIFY",
  191. "UNSOL_DATA_NOTIFY",
  192. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  193. "DRIVERMSG_NOTIFY",
  194. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  195. "SOL_CMD_KILLED_DIF_ERR",
  196. "CXN_KILLED_SYN_RCVD",
  197. "CXN_KILLED_IMM_DATA_RCVD"
  198. };
  199. static int beiscsi_slave_configure(struct scsi_device *sdev)
  200. {
  201. blk_queue_max_segment_size(sdev->request_queue, 65536);
  202. return 0;
  203. }
  204. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  205. {
  206. struct iscsi_cls_session *cls_session;
  207. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  208. struct beiscsi_io_task *aborted_io_task;
  209. struct iscsi_conn *conn;
  210. struct beiscsi_conn *beiscsi_conn;
  211. struct beiscsi_hba *phba;
  212. struct iscsi_session *session;
  213. struct invalidate_command_table *inv_tbl;
  214. struct be_dma_mem nonemb_cmd;
  215. unsigned int cid, tag, num_invalidate;
  216. cls_session = starget_to_session(scsi_target(sc->device));
  217. session = cls_session->dd_data;
  218. spin_lock_bh(&session->lock);
  219. if (!aborted_task || !aborted_task->sc) {
  220. /* we raced */
  221. spin_unlock_bh(&session->lock);
  222. return SUCCESS;
  223. }
  224. aborted_io_task = aborted_task->dd_data;
  225. if (!aborted_io_task->scsi_cmnd) {
  226. /* raced or invalid command */
  227. spin_unlock_bh(&session->lock);
  228. return SUCCESS;
  229. }
  230. spin_unlock_bh(&session->lock);
  231. conn = aborted_task->conn;
  232. beiscsi_conn = conn->dd_data;
  233. phba = beiscsi_conn->phba;
  234. /* invalidate iocb */
  235. cid = beiscsi_conn->beiscsi_conn_cid;
  236. inv_tbl = phba->inv_tbl;
  237. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  238. inv_tbl->cid = cid;
  239. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  240. num_invalidate = 1;
  241. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  242. sizeof(struct invalidate_commands_params_in),
  243. &nonemb_cmd.dma);
  244. if (nonemb_cmd.va == NULL) {
  245. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  246. "BM_%d : Failed to allocate memory for"
  247. "mgmt_invalidate_icds\n");
  248. return FAILED;
  249. }
  250. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  251. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  252. cid, &nonemb_cmd);
  253. if (!tag) {
  254. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  255. "BM_%d : mgmt_invalidate_icds could not be"
  256. "submitted\n");
  257. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  258. nonemb_cmd.va, nonemb_cmd.dma);
  259. return FAILED;
  260. }
  261. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  262. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  263. nonemb_cmd.va, nonemb_cmd.dma);
  264. return iscsi_eh_abort(sc);
  265. }
  266. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  267. {
  268. struct iscsi_task *abrt_task;
  269. struct beiscsi_io_task *abrt_io_task;
  270. struct iscsi_conn *conn;
  271. struct beiscsi_conn *beiscsi_conn;
  272. struct beiscsi_hba *phba;
  273. struct iscsi_session *session;
  274. struct iscsi_cls_session *cls_session;
  275. struct invalidate_command_table *inv_tbl;
  276. struct be_dma_mem nonemb_cmd;
  277. unsigned int cid, tag, i, num_invalidate;
  278. /* invalidate iocbs */
  279. cls_session = starget_to_session(scsi_target(sc->device));
  280. session = cls_session->dd_data;
  281. spin_lock_bh(&session->lock);
  282. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  283. spin_unlock_bh(&session->lock);
  284. return FAILED;
  285. }
  286. conn = session->leadconn;
  287. beiscsi_conn = conn->dd_data;
  288. phba = beiscsi_conn->phba;
  289. cid = beiscsi_conn->beiscsi_conn_cid;
  290. inv_tbl = phba->inv_tbl;
  291. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  292. num_invalidate = 0;
  293. for (i = 0; i < conn->session->cmds_max; i++) {
  294. abrt_task = conn->session->cmds[i];
  295. abrt_io_task = abrt_task->dd_data;
  296. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  297. continue;
  298. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  299. continue;
  300. inv_tbl->cid = cid;
  301. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  302. num_invalidate++;
  303. inv_tbl++;
  304. }
  305. spin_unlock_bh(&session->lock);
  306. inv_tbl = phba->inv_tbl;
  307. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  308. sizeof(struct invalidate_commands_params_in),
  309. &nonemb_cmd.dma);
  310. if (nonemb_cmd.va == NULL) {
  311. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  312. "BM_%d : Failed to allocate memory for"
  313. "mgmt_invalidate_icds\n");
  314. return FAILED;
  315. }
  316. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  317. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  318. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  319. cid, &nonemb_cmd);
  320. if (!tag) {
  321. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  322. "BM_%d : mgmt_invalidate_icds could not be"
  323. " submitted\n");
  324. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  325. nonemb_cmd.va, nonemb_cmd.dma);
  326. return FAILED;
  327. }
  328. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  329. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  330. nonemb_cmd.va, nonemb_cmd.dma);
  331. return iscsi_eh_device_reset(sc);
  332. }
  333. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  334. {
  335. struct beiscsi_hba *phba = data;
  336. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  337. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  338. char *str = buf;
  339. int rc;
  340. switch (type) {
  341. case ISCSI_BOOT_TGT_NAME:
  342. rc = sprintf(buf, "%.*s\n",
  343. (int)strlen(boot_sess->target_name),
  344. (char *)&boot_sess->target_name);
  345. break;
  346. case ISCSI_BOOT_TGT_IP_ADDR:
  347. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  348. rc = sprintf(buf, "%pI4\n",
  349. (char *)&boot_conn->dest_ipaddr.addr);
  350. else
  351. rc = sprintf(str, "%pI6\n",
  352. (char *)&boot_conn->dest_ipaddr.addr);
  353. break;
  354. case ISCSI_BOOT_TGT_PORT:
  355. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  356. break;
  357. case ISCSI_BOOT_TGT_CHAP_NAME:
  358. rc = sprintf(str, "%.*s\n",
  359. boot_conn->negotiated_login_options.auth_data.chap.
  360. target_chap_name_length,
  361. (char *)&boot_conn->negotiated_login_options.
  362. auth_data.chap.target_chap_name);
  363. break;
  364. case ISCSI_BOOT_TGT_CHAP_SECRET:
  365. rc = sprintf(str, "%.*s\n",
  366. boot_conn->negotiated_login_options.auth_data.chap.
  367. target_secret_length,
  368. (char *)&boot_conn->negotiated_login_options.
  369. auth_data.chap.target_secret);
  370. break;
  371. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  372. rc = sprintf(str, "%.*s\n",
  373. boot_conn->negotiated_login_options.auth_data.chap.
  374. intr_chap_name_length,
  375. (char *)&boot_conn->negotiated_login_options.
  376. auth_data.chap.intr_chap_name);
  377. break;
  378. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  379. rc = sprintf(str, "%.*s\n",
  380. boot_conn->negotiated_login_options.auth_data.chap.
  381. intr_secret_length,
  382. (char *)&boot_conn->negotiated_login_options.
  383. auth_data.chap.intr_secret);
  384. break;
  385. case ISCSI_BOOT_TGT_FLAGS:
  386. rc = sprintf(str, "2\n");
  387. break;
  388. case ISCSI_BOOT_TGT_NIC_ASSOC:
  389. rc = sprintf(str, "0\n");
  390. break;
  391. default:
  392. rc = -ENOSYS;
  393. break;
  394. }
  395. return rc;
  396. }
  397. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  398. {
  399. struct beiscsi_hba *phba = data;
  400. char *str = buf;
  401. int rc;
  402. switch (type) {
  403. case ISCSI_BOOT_INI_INITIATOR_NAME:
  404. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  405. break;
  406. default:
  407. rc = -ENOSYS;
  408. break;
  409. }
  410. return rc;
  411. }
  412. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  413. {
  414. struct beiscsi_hba *phba = data;
  415. char *str = buf;
  416. int rc;
  417. switch (type) {
  418. case ISCSI_BOOT_ETH_FLAGS:
  419. rc = sprintf(str, "2\n");
  420. break;
  421. case ISCSI_BOOT_ETH_INDEX:
  422. rc = sprintf(str, "0\n");
  423. break;
  424. case ISCSI_BOOT_ETH_MAC:
  425. rc = beiscsi_get_macaddr(str, phba);
  426. break;
  427. default:
  428. rc = -ENOSYS;
  429. break;
  430. }
  431. return rc;
  432. }
  433. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  434. {
  435. umode_t rc;
  436. switch (type) {
  437. case ISCSI_BOOT_TGT_NAME:
  438. case ISCSI_BOOT_TGT_IP_ADDR:
  439. case ISCSI_BOOT_TGT_PORT:
  440. case ISCSI_BOOT_TGT_CHAP_NAME:
  441. case ISCSI_BOOT_TGT_CHAP_SECRET:
  442. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  443. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  444. case ISCSI_BOOT_TGT_NIC_ASSOC:
  445. case ISCSI_BOOT_TGT_FLAGS:
  446. rc = S_IRUGO;
  447. break;
  448. default:
  449. rc = 0;
  450. break;
  451. }
  452. return rc;
  453. }
  454. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  455. {
  456. umode_t rc;
  457. switch (type) {
  458. case ISCSI_BOOT_INI_INITIATOR_NAME:
  459. rc = S_IRUGO;
  460. break;
  461. default:
  462. rc = 0;
  463. break;
  464. }
  465. return rc;
  466. }
  467. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  468. {
  469. umode_t rc;
  470. switch (type) {
  471. case ISCSI_BOOT_ETH_FLAGS:
  472. case ISCSI_BOOT_ETH_MAC:
  473. case ISCSI_BOOT_ETH_INDEX:
  474. rc = S_IRUGO;
  475. break;
  476. default:
  477. rc = 0;
  478. break;
  479. }
  480. return rc;
  481. }
  482. /*------------------- PCI Driver operations and data ----------------- */
  483. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  484. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  485. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  486. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  487. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  488. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  489. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  490. { 0 }
  491. };
  492. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  493. static struct scsi_host_template beiscsi_sht = {
  494. .module = THIS_MODULE,
  495. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  496. .proc_name = DRV_NAME,
  497. .queuecommand = iscsi_queuecommand,
  498. .change_queue_depth = iscsi_change_queue_depth,
  499. .slave_configure = beiscsi_slave_configure,
  500. .target_alloc = iscsi_target_alloc,
  501. .eh_abort_handler = beiscsi_eh_abort,
  502. .eh_device_reset_handler = beiscsi_eh_device_reset,
  503. .eh_target_reset_handler = iscsi_eh_session_reset,
  504. .shost_attrs = beiscsi_attrs,
  505. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  506. .can_queue = BE2_IO_DEPTH,
  507. .this_id = -1,
  508. .max_sectors = BEISCSI_MAX_SECTORS,
  509. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  510. .use_clustering = ENABLE_CLUSTERING,
  511. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  512. };
  513. static struct scsi_transport_template *beiscsi_scsi_transport;
  514. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  515. {
  516. struct beiscsi_hba *phba;
  517. struct Scsi_Host *shost;
  518. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  519. if (!shost) {
  520. dev_err(&pcidev->dev,
  521. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  522. return NULL;
  523. }
  524. shost->dma_boundary = pcidev->dma_mask;
  525. shost->max_id = BE2_MAX_SESSIONS;
  526. shost->max_channel = 0;
  527. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  528. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  529. shost->transportt = beiscsi_scsi_transport;
  530. phba = iscsi_host_priv(shost);
  531. memset(phba, 0, sizeof(*phba));
  532. phba->shost = shost;
  533. phba->pcidev = pci_dev_get(pcidev);
  534. pci_set_drvdata(pcidev, phba);
  535. phba->interface_handle = 0xFFFFFFFF;
  536. if (iscsi_host_add(shost, &phba->pcidev->dev))
  537. goto free_devices;
  538. return phba;
  539. free_devices:
  540. pci_dev_put(phba->pcidev);
  541. iscsi_host_free(phba->shost);
  542. return NULL;
  543. }
  544. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  545. {
  546. if (phba->csr_va) {
  547. iounmap(phba->csr_va);
  548. phba->csr_va = NULL;
  549. }
  550. if (phba->db_va) {
  551. iounmap(phba->db_va);
  552. phba->db_va = NULL;
  553. }
  554. if (phba->pci_va) {
  555. iounmap(phba->pci_va);
  556. phba->pci_va = NULL;
  557. }
  558. }
  559. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  560. struct pci_dev *pcidev)
  561. {
  562. u8 __iomem *addr;
  563. int pcicfg_reg;
  564. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  565. pci_resource_len(pcidev, 2));
  566. if (addr == NULL)
  567. return -ENOMEM;
  568. phba->ctrl.csr = addr;
  569. phba->csr_va = addr;
  570. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  571. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  572. if (addr == NULL)
  573. goto pci_map_err;
  574. phba->ctrl.db = addr;
  575. phba->db_va = addr;
  576. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  577. if (phba->generation == BE_GEN2)
  578. pcicfg_reg = 1;
  579. else
  580. pcicfg_reg = 0;
  581. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  582. pci_resource_len(pcidev, pcicfg_reg));
  583. if (addr == NULL)
  584. goto pci_map_err;
  585. phba->ctrl.pcicfg = addr;
  586. phba->pci_va = addr;
  587. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  588. return 0;
  589. pci_map_err:
  590. beiscsi_unmap_pci_function(phba);
  591. return -ENOMEM;
  592. }
  593. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  594. {
  595. int ret;
  596. ret = pci_enable_device(pcidev);
  597. if (ret) {
  598. dev_err(&pcidev->dev,
  599. "beiscsi_enable_pci - enable device failed\n");
  600. return ret;
  601. }
  602. pci_set_master(pcidev);
  603. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  604. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  605. if (ret) {
  606. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  607. pci_disable_device(pcidev);
  608. return ret;
  609. }
  610. }
  611. return 0;
  612. }
  613. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  614. {
  615. struct be_ctrl_info *ctrl = &phba->ctrl;
  616. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  617. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  618. int status = 0;
  619. ctrl->pdev = pdev;
  620. status = beiscsi_map_pci_bars(phba, pdev);
  621. if (status)
  622. return status;
  623. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  624. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  625. mbox_mem_alloc->size,
  626. &mbox_mem_alloc->dma);
  627. if (!mbox_mem_alloc->va) {
  628. beiscsi_unmap_pci_function(phba);
  629. return -ENOMEM;
  630. }
  631. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  632. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  633. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  634. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  635. spin_lock_init(&ctrl->mbox_lock);
  636. spin_lock_init(&phba->ctrl.mcc_lock);
  637. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  638. return status;
  639. }
  640. /**
  641. * beiscsi_get_params()- Set the config paramters
  642. * @phba: ptr device priv structure
  643. **/
  644. static void beiscsi_get_params(struct beiscsi_hba *phba)
  645. {
  646. uint32_t total_cid_count = 0;
  647. uint32_t total_icd_count = 0;
  648. uint8_t ulp_num = 0;
  649. total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
  650. BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
  651. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
  652. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  653. total_icd_count = phba->fw_config.
  654. iscsi_icd_count[ulp_num];
  655. break;
  656. }
  657. phba->params.ios_per_ctrl = (total_icd_count -
  658. (total_cid_count +
  659. BE2_TMFS + BE2_NOPOUT_REQ));
  660. phba->params.cxns_per_ctrl = total_cid_count;
  661. phba->params.asyncpdus_per_ctrl = total_cid_count;
  662. phba->params.icds_per_ctrl = total_icd_count;
  663. phba->params.num_sge_per_io = BE2_SGE;
  664. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  665. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  666. phba->params.eq_timer = 64;
  667. phba->params.num_eq_entries = 1024;
  668. phba->params.num_cq_entries = 1024;
  669. phba->params.wrbs_per_cxn = 256;
  670. }
  671. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  672. unsigned int id, unsigned int clr_interrupt,
  673. unsigned int num_processed,
  674. unsigned char rearm, unsigned char event)
  675. {
  676. u32 val = 0;
  677. val |= id & DB_EQ_RING_ID_MASK;
  678. if (rearm)
  679. val |= 1 << DB_EQ_REARM_SHIFT;
  680. if (clr_interrupt)
  681. val |= 1 << DB_EQ_CLR_SHIFT;
  682. if (event)
  683. val |= 1 << DB_EQ_EVNT_SHIFT;
  684. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  685. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  686. }
  687. /**
  688. * be_isr_mcc - The isr routine of the driver.
  689. * @irq: Not used
  690. * @dev_id: Pointer to host adapter structure
  691. */
  692. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  693. {
  694. struct beiscsi_hba *phba;
  695. struct be_eq_entry *eqe = NULL;
  696. struct be_queue_info *eq;
  697. struct be_queue_info *mcc;
  698. unsigned int num_eq_processed;
  699. struct be_eq_obj *pbe_eq;
  700. unsigned long flags;
  701. pbe_eq = dev_id;
  702. eq = &pbe_eq->q;
  703. phba = pbe_eq->phba;
  704. mcc = &phba->ctrl.mcc_obj.cq;
  705. eqe = queue_tail_node(eq);
  706. num_eq_processed = 0;
  707. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  708. & EQE_VALID_MASK) {
  709. if (((eqe->dw[offsetof(struct amap_eq_entry,
  710. resource_id) / 32] &
  711. EQE_RESID_MASK) >> 16) == mcc->id) {
  712. spin_lock_irqsave(&phba->isr_lock, flags);
  713. pbe_eq->todo_mcc_cq = true;
  714. spin_unlock_irqrestore(&phba->isr_lock, flags);
  715. }
  716. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  717. queue_tail_inc(eq);
  718. eqe = queue_tail_node(eq);
  719. num_eq_processed++;
  720. }
  721. if (pbe_eq->todo_mcc_cq)
  722. queue_work(phba->wq, &pbe_eq->work_cqs);
  723. if (num_eq_processed)
  724. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  725. return IRQ_HANDLED;
  726. }
  727. /**
  728. * be_isr_msix - The isr routine of the driver.
  729. * @irq: Not used
  730. * @dev_id: Pointer to host adapter structure
  731. */
  732. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  733. {
  734. struct beiscsi_hba *phba;
  735. struct be_eq_entry *eqe = NULL;
  736. struct be_queue_info *eq;
  737. struct be_queue_info *cq;
  738. unsigned int num_eq_processed;
  739. struct be_eq_obj *pbe_eq;
  740. unsigned long flags;
  741. pbe_eq = dev_id;
  742. eq = &pbe_eq->q;
  743. cq = pbe_eq->cq;
  744. eqe = queue_tail_node(eq);
  745. phba = pbe_eq->phba;
  746. num_eq_processed = 0;
  747. if (blk_iopoll_enabled) {
  748. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  749. & EQE_VALID_MASK) {
  750. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  751. blk_iopoll_sched(&pbe_eq->iopoll);
  752. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  753. queue_tail_inc(eq);
  754. eqe = queue_tail_node(eq);
  755. num_eq_processed++;
  756. }
  757. } else {
  758. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  759. & EQE_VALID_MASK) {
  760. spin_lock_irqsave(&phba->isr_lock, flags);
  761. pbe_eq->todo_cq = true;
  762. spin_unlock_irqrestore(&phba->isr_lock, flags);
  763. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  764. queue_tail_inc(eq);
  765. eqe = queue_tail_node(eq);
  766. num_eq_processed++;
  767. }
  768. if (pbe_eq->todo_cq)
  769. queue_work(phba->wq, &pbe_eq->work_cqs);
  770. }
  771. if (num_eq_processed)
  772. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  773. return IRQ_HANDLED;
  774. }
  775. /**
  776. * be_isr - The isr routine of the driver.
  777. * @irq: Not used
  778. * @dev_id: Pointer to host adapter structure
  779. */
  780. static irqreturn_t be_isr(int irq, void *dev_id)
  781. {
  782. struct beiscsi_hba *phba;
  783. struct hwi_controller *phwi_ctrlr;
  784. struct hwi_context_memory *phwi_context;
  785. struct be_eq_entry *eqe = NULL;
  786. struct be_queue_info *eq;
  787. struct be_queue_info *cq;
  788. struct be_queue_info *mcc;
  789. unsigned long flags, index;
  790. unsigned int num_mcceq_processed, num_ioeq_processed;
  791. struct be_ctrl_info *ctrl;
  792. struct be_eq_obj *pbe_eq;
  793. int isr;
  794. phba = dev_id;
  795. ctrl = &phba->ctrl;
  796. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  797. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  798. if (!isr)
  799. return IRQ_NONE;
  800. phwi_ctrlr = phba->phwi_ctrlr;
  801. phwi_context = phwi_ctrlr->phwi_ctxt;
  802. pbe_eq = &phwi_context->be_eq[0];
  803. eq = &phwi_context->be_eq[0].q;
  804. mcc = &phba->ctrl.mcc_obj.cq;
  805. index = 0;
  806. eqe = queue_tail_node(eq);
  807. num_ioeq_processed = 0;
  808. num_mcceq_processed = 0;
  809. if (blk_iopoll_enabled) {
  810. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  811. & EQE_VALID_MASK) {
  812. if (((eqe->dw[offsetof(struct amap_eq_entry,
  813. resource_id) / 32] &
  814. EQE_RESID_MASK) >> 16) == mcc->id) {
  815. spin_lock_irqsave(&phba->isr_lock, flags);
  816. pbe_eq->todo_mcc_cq = true;
  817. spin_unlock_irqrestore(&phba->isr_lock, flags);
  818. num_mcceq_processed++;
  819. } else {
  820. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  821. blk_iopoll_sched(&pbe_eq->iopoll);
  822. num_ioeq_processed++;
  823. }
  824. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  825. queue_tail_inc(eq);
  826. eqe = queue_tail_node(eq);
  827. }
  828. if (num_ioeq_processed || num_mcceq_processed) {
  829. if (pbe_eq->todo_mcc_cq)
  830. queue_work(phba->wq, &pbe_eq->work_cqs);
  831. if ((num_mcceq_processed) && (!num_ioeq_processed))
  832. hwi_ring_eq_db(phba, eq->id, 0,
  833. (num_ioeq_processed +
  834. num_mcceq_processed) , 1, 1);
  835. else
  836. hwi_ring_eq_db(phba, eq->id, 0,
  837. (num_ioeq_processed +
  838. num_mcceq_processed), 0, 1);
  839. return IRQ_HANDLED;
  840. } else
  841. return IRQ_NONE;
  842. } else {
  843. cq = &phwi_context->be_cq[0];
  844. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  845. & EQE_VALID_MASK) {
  846. if (((eqe->dw[offsetof(struct amap_eq_entry,
  847. resource_id) / 32] &
  848. EQE_RESID_MASK) >> 16) != cq->id) {
  849. spin_lock_irqsave(&phba->isr_lock, flags);
  850. pbe_eq->todo_mcc_cq = true;
  851. spin_unlock_irqrestore(&phba->isr_lock, flags);
  852. } else {
  853. spin_lock_irqsave(&phba->isr_lock, flags);
  854. pbe_eq->todo_cq = true;
  855. spin_unlock_irqrestore(&phba->isr_lock, flags);
  856. }
  857. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  858. queue_tail_inc(eq);
  859. eqe = queue_tail_node(eq);
  860. num_ioeq_processed++;
  861. }
  862. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  863. queue_work(phba->wq, &pbe_eq->work_cqs);
  864. if (num_ioeq_processed) {
  865. hwi_ring_eq_db(phba, eq->id, 0,
  866. num_ioeq_processed, 1, 1);
  867. return IRQ_HANDLED;
  868. } else
  869. return IRQ_NONE;
  870. }
  871. }
  872. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  873. {
  874. struct pci_dev *pcidev = phba->pcidev;
  875. struct hwi_controller *phwi_ctrlr;
  876. struct hwi_context_memory *phwi_context;
  877. int ret, msix_vec, i, j;
  878. phwi_ctrlr = phba->phwi_ctrlr;
  879. phwi_context = phwi_ctrlr->phwi_ctxt;
  880. if (phba->msix_enabled) {
  881. for (i = 0; i < phba->num_cpus; i++) {
  882. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  883. GFP_KERNEL);
  884. if (!phba->msi_name[i]) {
  885. ret = -ENOMEM;
  886. goto free_msix_irqs;
  887. }
  888. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  889. phba->shost->host_no, i);
  890. msix_vec = phba->msix_entries[i].vector;
  891. ret = request_irq(msix_vec, be_isr_msix, 0,
  892. phba->msi_name[i],
  893. &phwi_context->be_eq[i]);
  894. if (ret) {
  895. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  896. "BM_%d : beiscsi_init_irqs-Failed to"
  897. "register msix for i = %d\n",
  898. i);
  899. kfree(phba->msi_name[i]);
  900. goto free_msix_irqs;
  901. }
  902. }
  903. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  904. if (!phba->msi_name[i]) {
  905. ret = -ENOMEM;
  906. goto free_msix_irqs;
  907. }
  908. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  909. phba->shost->host_no);
  910. msix_vec = phba->msix_entries[i].vector;
  911. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  912. &phwi_context->be_eq[i]);
  913. if (ret) {
  914. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  915. "BM_%d : beiscsi_init_irqs-"
  916. "Failed to register beiscsi_msix_mcc\n");
  917. kfree(phba->msi_name[i]);
  918. goto free_msix_irqs;
  919. }
  920. } else {
  921. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  922. "beiscsi", phba);
  923. if (ret) {
  924. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  925. "BM_%d : beiscsi_init_irqs-"
  926. "Failed to register irq\\n");
  927. return ret;
  928. }
  929. }
  930. return 0;
  931. free_msix_irqs:
  932. for (j = i - 1; j >= 0; j--) {
  933. kfree(phba->msi_name[j]);
  934. msix_vec = phba->msix_entries[j].vector;
  935. free_irq(msix_vec, &phwi_context->be_eq[j]);
  936. }
  937. return ret;
  938. }
  939. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  940. unsigned int id, unsigned int num_processed,
  941. unsigned char rearm, unsigned char event)
  942. {
  943. u32 val = 0;
  944. val |= id & DB_CQ_RING_ID_MASK;
  945. if (rearm)
  946. val |= 1 << DB_CQ_REARM_SHIFT;
  947. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  948. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  949. }
  950. static unsigned int
  951. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  952. struct beiscsi_hba *phba,
  953. struct pdu_base *ppdu,
  954. unsigned long pdu_len,
  955. void *pbuffer, unsigned long buf_len)
  956. {
  957. struct iscsi_conn *conn = beiscsi_conn->conn;
  958. struct iscsi_session *session = conn->session;
  959. struct iscsi_task *task;
  960. struct beiscsi_io_task *io_task;
  961. struct iscsi_hdr *login_hdr;
  962. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  963. PDUBASE_OPCODE_MASK) {
  964. case ISCSI_OP_NOOP_IN:
  965. pbuffer = NULL;
  966. buf_len = 0;
  967. break;
  968. case ISCSI_OP_ASYNC_EVENT:
  969. break;
  970. case ISCSI_OP_REJECT:
  971. WARN_ON(!pbuffer);
  972. WARN_ON(!(buf_len == 48));
  973. beiscsi_log(phba, KERN_ERR,
  974. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  975. "BM_%d : In ISCSI_OP_REJECT\n");
  976. break;
  977. case ISCSI_OP_LOGIN_RSP:
  978. case ISCSI_OP_TEXT_RSP:
  979. task = conn->login_task;
  980. io_task = task->dd_data;
  981. login_hdr = (struct iscsi_hdr *)ppdu;
  982. login_hdr->itt = io_task->libiscsi_itt;
  983. break;
  984. default:
  985. beiscsi_log(phba, KERN_WARNING,
  986. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  987. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  988. (ppdu->
  989. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  990. & PDUBASE_OPCODE_MASK));
  991. return 1;
  992. }
  993. spin_lock_bh(&session->lock);
  994. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  995. spin_unlock_bh(&session->lock);
  996. return 0;
  997. }
  998. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  999. {
  1000. struct sgl_handle *psgl_handle;
  1001. if (phba->io_sgl_hndl_avbl) {
  1002. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1003. "BM_%d : In alloc_io_sgl_handle,"
  1004. " io_sgl_alloc_index=%d\n",
  1005. phba->io_sgl_alloc_index);
  1006. psgl_handle = phba->io_sgl_hndl_base[phba->
  1007. io_sgl_alloc_index];
  1008. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  1009. phba->io_sgl_hndl_avbl--;
  1010. if (phba->io_sgl_alloc_index == (phba->params.
  1011. ios_per_ctrl - 1))
  1012. phba->io_sgl_alloc_index = 0;
  1013. else
  1014. phba->io_sgl_alloc_index++;
  1015. } else
  1016. psgl_handle = NULL;
  1017. return psgl_handle;
  1018. }
  1019. static void
  1020. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1021. {
  1022. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1023. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1024. phba->io_sgl_free_index);
  1025. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1026. /*
  1027. * this can happen if clean_task is called on a task that
  1028. * failed in xmit_task or alloc_pdu.
  1029. */
  1030. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1031. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1032. "value there=%p\n", phba->io_sgl_free_index,
  1033. phba->io_sgl_hndl_base
  1034. [phba->io_sgl_free_index]);
  1035. return;
  1036. }
  1037. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1038. phba->io_sgl_hndl_avbl++;
  1039. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1040. phba->io_sgl_free_index = 0;
  1041. else
  1042. phba->io_sgl_free_index++;
  1043. }
  1044. /**
  1045. * alloc_wrb_handle - To allocate a wrb handle
  1046. * @phba: The hba pointer
  1047. * @cid: The cid to use for allocation
  1048. *
  1049. * This happens under session_lock until submission to chip
  1050. */
  1051. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1052. {
  1053. struct hwi_wrb_context *pwrb_context;
  1054. struct hwi_controller *phwi_ctrlr;
  1055. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1056. uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
  1057. phwi_ctrlr = phba->phwi_ctrlr;
  1058. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1059. if (pwrb_context->wrb_handles_available >= 2) {
  1060. pwrb_handle = pwrb_context->pwrb_handle_base[
  1061. pwrb_context->alloc_index];
  1062. pwrb_context->wrb_handles_available--;
  1063. if (pwrb_context->alloc_index ==
  1064. (phba->params.wrbs_per_cxn - 1))
  1065. pwrb_context->alloc_index = 0;
  1066. else
  1067. pwrb_context->alloc_index++;
  1068. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1069. pwrb_context->alloc_index];
  1070. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1071. } else
  1072. pwrb_handle = NULL;
  1073. return pwrb_handle;
  1074. }
  1075. /**
  1076. * free_wrb_handle - To free the wrb handle back to pool
  1077. * @phba: The hba pointer
  1078. * @pwrb_context: The context to free from
  1079. * @pwrb_handle: The wrb_handle to free
  1080. *
  1081. * This happens under session_lock until submission to chip
  1082. */
  1083. static void
  1084. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1085. struct wrb_handle *pwrb_handle)
  1086. {
  1087. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1088. pwrb_context->wrb_handles_available++;
  1089. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1090. pwrb_context->free_index = 0;
  1091. else
  1092. pwrb_context->free_index++;
  1093. beiscsi_log(phba, KERN_INFO,
  1094. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1095. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1096. "wrb_handles_available=%d\n",
  1097. pwrb_handle, pwrb_context->free_index,
  1098. pwrb_context->wrb_handles_available);
  1099. }
  1100. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1101. {
  1102. struct sgl_handle *psgl_handle;
  1103. if (phba->eh_sgl_hndl_avbl) {
  1104. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1105. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1106. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1107. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1108. phba->eh_sgl_alloc_index,
  1109. phba->eh_sgl_alloc_index);
  1110. phba->eh_sgl_hndl_avbl--;
  1111. if (phba->eh_sgl_alloc_index ==
  1112. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1113. 1))
  1114. phba->eh_sgl_alloc_index = 0;
  1115. else
  1116. phba->eh_sgl_alloc_index++;
  1117. } else
  1118. psgl_handle = NULL;
  1119. return psgl_handle;
  1120. }
  1121. void
  1122. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1123. {
  1124. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1125. "BM_%d : In free_mgmt_sgl_handle,"
  1126. "eh_sgl_free_index=%d\n",
  1127. phba->eh_sgl_free_index);
  1128. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1129. /*
  1130. * this can happen if clean_task is called on a task that
  1131. * failed in xmit_task or alloc_pdu.
  1132. */
  1133. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1134. "BM_%d : Double Free in eh SGL ,"
  1135. "eh_sgl_free_index=%d\n",
  1136. phba->eh_sgl_free_index);
  1137. return;
  1138. }
  1139. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1140. phba->eh_sgl_hndl_avbl++;
  1141. if (phba->eh_sgl_free_index ==
  1142. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1143. phba->eh_sgl_free_index = 0;
  1144. else
  1145. phba->eh_sgl_free_index++;
  1146. }
  1147. static void
  1148. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1149. struct iscsi_task *task,
  1150. struct common_sol_cqe *csol_cqe)
  1151. {
  1152. struct beiscsi_io_task *io_task = task->dd_data;
  1153. struct be_status_bhs *sts_bhs =
  1154. (struct be_status_bhs *)io_task->cmd_bhs;
  1155. struct iscsi_conn *conn = beiscsi_conn->conn;
  1156. unsigned char *sense;
  1157. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1158. u8 rsp, status, flags;
  1159. exp_cmdsn = csol_cqe->exp_cmdsn;
  1160. max_cmdsn = (csol_cqe->exp_cmdsn +
  1161. csol_cqe->cmd_wnd - 1);
  1162. rsp = csol_cqe->i_resp;
  1163. status = csol_cqe->i_sts;
  1164. flags = csol_cqe->i_flags;
  1165. resid = csol_cqe->res_cnt;
  1166. if (!task->sc) {
  1167. if (io_task->scsi_cmnd)
  1168. scsi_dma_unmap(io_task->scsi_cmnd);
  1169. return;
  1170. }
  1171. task->sc->result = (DID_OK << 16) | status;
  1172. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1173. task->sc->result = DID_ERROR << 16;
  1174. goto unmap;
  1175. }
  1176. /* bidi not initially supported */
  1177. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1178. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1179. task->sc->result = DID_ERROR << 16;
  1180. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1181. scsi_set_resid(task->sc, resid);
  1182. if (!status && (scsi_bufflen(task->sc) - resid <
  1183. task->sc->underflow))
  1184. task->sc->result = DID_ERROR << 16;
  1185. }
  1186. }
  1187. if (status == SAM_STAT_CHECK_CONDITION) {
  1188. u16 sense_len;
  1189. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1190. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1191. sense_len = be16_to_cpu(*slen);
  1192. memcpy(task->sc->sense_buffer, sense,
  1193. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1194. }
  1195. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1196. conn->rxdata_octets += resid;
  1197. unmap:
  1198. scsi_dma_unmap(io_task->scsi_cmnd);
  1199. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1200. }
  1201. static void
  1202. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1203. struct iscsi_task *task,
  1204. struct common_sol_cqe *csol_cqe)
  1205. {
  1206. struct iscsi_logout_rsp *hdr;
  1207. struct beiscsi_io_task *io_task = task->dd_data;
  1208. struct iscsi_conn *conn = beiscsi_conn->conn;
  1209. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1210. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1211. hdr->t2wait = 5;
  1212. hdr->t2retain = 0;
  1213. hdr->flags = csol_cqe->i_flags;
  1214. hdr->response = csol_cqe->i_resp;
  1215. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1216. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1217. csol_cqe->cmd_wnd - 1);
  1218. hdr->dlength[0] = 0;
  1219. hdr->dlength[1] = 0;
  1220. hdr->dlength[2] = 0;
  1221. hdr->hlength = 0;
  1222. hdr->itt = io_task->libiscsi_itt;
  1223. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1224. }
  1225. static void
  1226. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1227. struct iscsi_task *task,
  1228. struct common_sol_cqe *csol_cqe)
  1229. {
  1230. struct iscsi_tm_rsp *hdr;
  1231. struct iscsi_conn *conn = beiscsi_conn->conn;
  1232. struct beiscsi_io_task *io_task = task->dd_data;
  1233. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1234. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1235. hdr->flags = csol_cqe->i_flags;
  1236. hdr->response = csol_cqe->i_resp;
  1237. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1238. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1239. csol_cqe->cmd_wnd - 1);
  1240. hdr->itt = io_task->libiscsi_itt;
  1241. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1242. }
  1243. static void
  1244. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1245. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1246. {
  1247. struct hwi_wrb_context *pwrb_context;
  1248. struct wrb_handle *pwrb_handle = NULL;
  1249. struct hwi_controller *phwi_ctrlr;
  1250. struct iscsi_task *task;
  1251. struct beiscsi_io_task *io_task;
  1252. uint16_t wrb_index, cid, cri_index;
  1253. phwi_ctrlr = phba->phwi_ctrlr;
  1254. if (is_chip_be2_be3r(phba)) {
  1255. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1256. wrb_idx, psol);
  1257. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1258. cid, psol);
  1259. } else {
  1260. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1261. wrb_idx, psol);
  1262. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1263. cid, psol);
  1264. }
  1265. cri_index = BE_GET_CRI_FROM_CID(cid);
  1266. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1267. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1268. task = pwrb_handle->pio_handle;
  1269. io_task = task->dd_data;
  1270. memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
  1271. iscsi_put_task(task);
  1272. }
  1273. static void
  1274. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1275. struct iscsi_task *task,
  1276. struct common_sol_cqe *csol_cqe)
  1277. {
  1278. struct iscsi_nopin *hdr;
  1279. struct iscsi_conn *conn = beiscsi_conn->conn;
  1280. struct beiscsi_io_task *io_task = task->dd_data;
  1281. hdr = (struct iscsi_nopin *)task->hdr;
  1282. hdr->flags = csol_cqe->i_flags;
  1283. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1284. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1285. csol_cqe->cmd_wnd - 1);
  1286. hdr->opcode = ISCSI_OP_NOOP_IN;
  1287. hdr->itt = io_task->libiscsi_itt;
  1288. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1289. }
  1290. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1291. struct sol_cqe *psol,
  1292. struct common_sol_cqe *csol_cqe)
  1293. {
  1294. if (is_chip_be2_be3r(phba)) {
  1295. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1296. i_exp_cmd_sn, psol);
  1297. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1298. i_res_cnt, psol);
  1299. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1300. i_cmd_wnd, psol);
  1301. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1302. wrb_index, psol);
  1303. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1304. cid, psol);
  1305. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1306. hw_sts, psol);
  1307. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1308. i_resp, psol);
  1309. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1310. i_sts, psol);
  1311. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1312. i_flags, psol);
  1313. } else {
  1314. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1315. i_exp_cmd_sn, psol);
  1316. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1317. i_res_cnt, psol);
  1318. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1319. wrb_index, psol);
  1320. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1321. cid, psol);
  1322. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1323. hw_sts, psol);
  1324. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1325. i_cmd_wnd, psol);
  1326. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1327. cmd_cmpl, psol))
  1328. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1329. i_sts, psol);
  1330. else
  1331. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1332. i_sts, psol);
  1333. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1334. u, psol))
  1335. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1336. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1337. o, psol))
  1338. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1339. }
  1340. }
  1341. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1342. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1343. {
  1344. struct hwi_wrb_context *pwrb_context;
  1345. struct wrb_handle *pwrb_handle;
  1346. struct iscsi_wrb *pwrb = NULL;
  1347. struct hwi_controller *phwi_ctrlr;
  1348. struct iscsi_task *task;
  1349. unsigned int type;
  1350. struct iscsi_conn *conn = beiscsi_conn->conn;
  1351. struct iscsi_session *session = conn->session;
  1352. struct common_sol_cqe csol_cqe = {0};
  1353. uint16_t cri_index = 0;
  1354. phwi_ctrlr = phba->phwi_ctrlr;
  1355. /* Copy the elements to a common structure */
  1356. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1357. cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
  1358. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1359. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1360. csol_cqe.wrb_index];
  1361. task = pwrb_handle->pio_handle;
  1362. pwrb = pwrb_handle->pwrb;
  1363. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1364. spin_lock_bh(&session->lock);
  1365. switch (type) {
  1366. case HWH_TYPE_IO:
  1367. case HWH_TYPE_IO_RD:
  1368. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1369. ISCSI_OP_NOOP_OUT)
  1370. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1371. else
  1372. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1373. break;
  1374. case HWH_TYPE_LOGOUT:
  1375. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1376. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1377. else
  1378. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1379. break;
  1380. case HWH_TYPE_LOGIN:
  1381. beiscsi_log(phba, KERN_ERR,
  1382. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1383. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1384. " hwi_complete_cmd- Solicited path\n");
  1385. break;
  1386. case HWH_TYPE_NOP:
  1387. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1388. break;
  1389. default:
  1390. beiscsi_log(phba, KERN_WARNING,
  1391. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1392. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1393. "wrb_index 0x%x CID 0x%x\n", type,
  1394. csol_cqe.wrb_index,
  1395. csol_cqe.cid);
  1396. break;
  1397. }
  1398. spin_unlock_bh(&session->lock);
  1399. }
  1400. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1401. *pasync_ctx, unsigned int is_header,
  1402. unsigned int host_write_ptr)
  1403. {
  1404. if (is_header)
  1405. return &pasync_ctx->async_entry[host_write_ptr].
  1406. header_busy_list;
  1407. else
  1408. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1409. }
  1410. static struct async_pdu_handle *
  1411. hwi_get_async_handle(struct beiscsi_hba *phba,
  1412. struct beiscsi_conn *beiscsi_conn,
  1413. struct hwi_async_pdu_context *pasync_ctx,
  1414. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1415. {
  1416. struct be_bus_address phys_addr;
  1417. struct list_head *pbusy_list;
  1418. struct async_pdu_handle *pasync_handle = NULL;
  1419. unsigned char is_header = 0;
  1420. unsigned int index, dpl;
  1421. if (is_chip_be2_be3r(phba)) {
  1422. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1423. dpl, pdpdu_cqe);
  1424. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1425. index, pdpdu_cqe);
  1426. } else {
  1427. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1428. dpl, pdpdu_cqe);
  1429. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1430. index, pdpdu_cqe);
  1431. }
  1432. phys_addr.u.a32.address_lo =
  1433. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1434. db_addr_lo) / 32] - dpl);
  1435. phys_addr.u.a32.address_hi =
  1436. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1437. db_addr_hi) / 32];
  1438. phys_addr.u.a64.address =
  1439. *((unsigned long long *)(&phys_addr.u.a64.address));
  1440. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1441. & PDUCQE_CODE_MASK) {
  1442. case UNSOL_HDR_NOTIFY:
  1443. is_header = 1;
  1444. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1445. is_header, index);
  1446. break;
  1447. case UNSOL_DATA_NOTIFY:
  1448. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1449. is_header, index);
  1450. break;
  1451. default:
  1452. pbusy_list = NULL;
  1453. beiscsi_log(phba, KERN_WARNING,
  1454. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1455. "BM_%d : Unexpected code=%d\n",
  1456. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1457. code) / 32] & PDUCQE_CODE_MASK);
  1458. return NULL;
  1459. }
  1460. WARN_ON(list_empty(pbusy_list));
  1461. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1462. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1463. break;
  1464. }
  1465. WARN_ON(!pasync_handle);
  1466. pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(
  1467. beiscsi_conn->beiscsi_conn_cid);
  1468. pasync_handle->is_header = is_header;
  1469. pasync_handle->buffer_len = dpl;
  1470. *pcq_index = index;
  1471. return pasync_handle;
  1472. }
  1473. static unsigned int
  1474. hwi_update_async_writables(struct beiscsi_hba *phba,
  1475. struct hwi_async_pdu_context *pasync_ctx,
  1476. unsigned int is_header, unsigned int cq_index)
  1477. {
  1478. struct list_head *pbusy_list;
  1479. struct async_pdu_handle *pasync_handle;
  1480. unsigned int num_entries, writables = 0;
  1481. unsigned int *pep_read_ptr, *pwritables;
  1482. num_entries = pasync_ctx->num_entries;
  1483. if (is_header) {
  1484. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1485. pwritables = &pasync_ctx->async_header.writables;
  1486. } else {
  1487. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1488. pwritables = &pasync_ctx->async_data.writables;
  1489. }
  1490. while ((*pep_read_ptr) != cq_index) {
  1491. (*pep_read_ptr)++;
  1492. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1493. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1494. *pep_read_ptr);
  1495. if (writables == 0)
  1496. WARN_ON(list_empty(pbusy_list));
  1497. if (!list_empty(pbusy_list)) {
  1498. pasync_handle = list_entry(pbusy_list->next,
  1499. struct async_pdu_handle,
  1500. link);
  1501. WARN_ON(!pasync_handle);
  1502. pasync_handle->consumed = 1;
  1503. }
  1504. writables++;
  1505. }
  1506. if (!writables) {
  1507. beiscsi_log(phba, KERN_ERR,
  1508. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1509. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1510. cq_index);
  1511. WARN_ON(1);
  1512. }
  1513. *pwritables = *pwritables + writables;
  1514. return 0;
  1515. }
  1516. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1517. struct hwi_async_pdu_context *pasync_ctx,
  1518. unsigned int cri)
  1519. {
  1520. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1521. struct list_head *plist;
  1522. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1523. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1524. list_del(&pasync_handle->link);
  1525. if (pasync_handle->is_header) {
  1526. list_add_tail(&pasync_handle->link,
  1527. &pasync_ctx->async_header.free_list);
  1528. pasync_ctx->async_header.free_entries++;
  1529. } else {
  1530. list_add_tail(&pasync_handle->link,
  1531. &pasync_ctx->async_data.free_list);
  1532. pasync_ctx->async_data.free_entries++;
  1533. }
  1534. }
  1535. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1536. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1537. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1538. }
  1539. static struct phys_addr *
  1540. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1541. unsigned int is_header, unsigned int host_write_ptr)
  1542. {
  1543. struct phys_addr *pasync_sge = NULL;
  1544. if (is_header)
  1545. pasync_sge = pasync_ctx->async_header.ring_base;
  1546. else
  1547. pasync_sge = pasync_ctx->async_data.ring_base;
  1548. return pasync_sge + host_write_ptr;
  1549. }
  1550. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1551. unsigned int is_header, uint8_t ulp_num)
  1552. {
  1553. struct hwi_controller *phwi_ctrlr;
  1554. struct hwi_async_pdu_context *pasync_ctx;
  1555. struct async_pdu_handle *pasync_handle;
  1556. struct list_head *pfree_link, *pbusy_list;
  1557. struct phys_addr *pasync_sge;
  1558. unsigned int ring_id, num_entries;
  1559. unsigned int host_write_num, doorbell_offset;
  1560. unsigned int writables;
  1561. unsigned int i = 0;
  1562. u32 doorbell = 0;
  1563. phwi_ctrlr = phba->phwi_ctrlr;
  1564. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
  1565. num_entries = pasync_ctx->num_entries;
  1566. if (is_header) {
  1567. writables = min(pasync_ctx->async_header.writables,
  1568. pasync_ctx->async_header.free_entries);
  1569. pfree_link = pasync_ctx->async_header.free_list.next;
  1570. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1571. ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
  1572. doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
  1573. doorbell_offset;
  1574. } else {
  1575. writables = min(pasync_ctx->async_data.writables,
  1576. pasync_ctx->async_data.free_entries);
  1577. pfree_link = pasync_ctx->async_data.free_list.next;
  1578. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1579. ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
  1580. doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
  1581. doorbell_offset;
  1582. }
  1583. writables = (writables / 8) * 8;
  1584. if (writables) {
  1585. for (i = 0; i < writables; i++) {
  1586. pbusy_list =
  1587. hwi_get_async_busy_list(pasync_ctx, is_header,
  1588. host_write_num);
  1589. pasync_handle =
  1590. list_entry(pfree_link, struct async_pdu_handle,
  1591. link);
  1592. WARN_ON(!pasync_handle);
  1593. pasync_handle->consumed = 0;
  1594. pfree_link = pfree_link->next;
  1595. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1596. is_header, host_write_num);
  1597. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1598. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1599. list_move(&pasync_handle->link, pbusy_list);
  1600. host_write_num++;
  1601. host_write_num = host_write_num % num_entries;
  1602. }
  1603. if (is_header) {
  1604. pasync_ctx->async_header.host_write_ptr =
  1605. host_write_num;
  1606. pasync_ctx->async_header.free_entries -= writables;
  1607. pasync_ctx->async_header.writables -= writables;
  1608. pasync_ctx->async_header.busy_entries += writables;
  1609. } else {
  1610. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1611. pasync_ctx->async_data.free_entries -= writables;
  1612. pasync_ctx->async_data.writables -= writables;
  1613. pasync_ctx->async_data.busy_entries += writables;
  1614. }
  1615. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1616. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1617. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1618. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1619. << DB_DEF_PDU_CQPROC_SHIFT;
  1620. iowrite32(doorbell, phba->db_va + doorbell_offset);
  1621. }
  1622. }
  1623. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1624. struct beiscsi_conn *beiscsi_conn,
  1625. struct i_t_dpdu_cqe *pdpdu_cqe)
  1626. {
  1627. struct hwi_controller *phwi_ctrlr;
  1628. struct hwi_async_pdu_context *pasync_ctx;
  1629. struct async_pdu_handle *pasync_handle = NULL;
  1630. unsigned int cq_index = -1;
  1631. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  1632. beiscsi_conn->beiscsi_conn_cid);
  1633. phwi_ctrlr = phba->phwi_ctrlr;
  1634. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
  1635. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1636. cri_index));
  1637. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1638. pdpdu_cqe, &cq_index);
  1639. BUG_ON(pasync_handle->is_header != 0);
  1640. if (pasync_handle->consumed == 0)
  1641. hwi_update_async_writables(phba, pasync_ctx,
  1642. pasync_handle->is_header, cq_index);
  1643. hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri);
  1644. hwi_post_async_buffers(phba, pasync_handle->is_header,
  1645. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1646. cri_index));
  1647. }
  1648. static unsigned int
  1649. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1650. struct beiscsi_hba *phba,
  1651. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1652. {
  1653. struct list_head *plist;
  1654. struct async_pdu_handle *pasync_handle;
  1655. void *phdr = NULL;
  1656. unsigned int hdr_len = 0, buf_len = 0;
  1657. unsigned int status, index = 0, offset = 0;
  1658. void *pfirst_buffer = NULL;
  1659. unsigned int num_buf = 0;
  1660. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1661. list_for_each_entry(pasync_handle, plist, link) {
  1662. if (index == 0) {
  1663. phdr = pasync_handle->pbuffer;
  1664. hdr_len = pasync_handle->buffer_len;
  1665. } else {
  1666. buf_len = pasync_handle->buffer_len;
  1667. if (!num_buf) {
  1668. pfirst_buffer = pasync_handle->pbuffer;
  1669. num_buf++;
  1670. }
  1671. memcpy(pfirst_buffer + offset,
  1672. pasync_handle->pbuffer, buf_len);
  1673. offset += buf_len;
  1674. }
  1675. index++;
  1676. }
  1677. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1678. phdr, hdr_len, pfirst_buffer,
  1679. offset);
  1680. hwi_free_async_msg(phba, pasync_ctx, cri);
  1681. return 0;
  1682. }
  1683. static unsigned int
  1684. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1685. struct beiscsi_hba *phba,
  1686. struct async_pdu_handle *pasync_handle)
  1687. {
  1688. struct hwi_async_pdu_context *pasync_ctx;
  1689. struct hwi_controller *phwi_ctrlr;
  1690. unsigned int bytes_needed = 0, status = 0;
  1691. unsigned short cri = pasync_handle->cri;
  1692. struct pdu_base *ppdu;
  1693. phwi_ctrlr = phba->phwi_ctrlr;
  1694. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
  1695. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1696. BE_GET_CRI_FROM_CID(beiscsi_conn->
  1697. beiscsi_conn_cid)));
  1698. list_del(&pasync_handle->link);
  1699. if (pasync_handle->is_header) {
  1700. pasync_ctx->async_header.busy_entries--;
  1701. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1702. hwi_free_async_msg(phba, pasync_ctx, cri);
  1703. BUG();
  1704. }
  1705. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1706. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1707. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1708. (unsigned short)pasync_handle->buffer_len;
  1709. list_add_tail(&pasync_handle->link,
  1710. &pasync_ctx->async_entry[cri].wait_queue.list);
  1711. ppdu = pasync_handle->pbuffer;
  1712. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1713. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1714. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1715. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1716. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1717. if (status == 0) {
  1718. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1719. bytes_needed;
  1720. if (bytes_needed == 0)
  1721. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1722. pasync_ctx, cri);
  1723. }
  1724. } else {
  1725. pasync_ctx->async_data.busy_entries--;
  1726. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1727. list_add_tail(&pasync_handle->link,
  1728. &pasync_ctx->async_entry[cri].wait_queue.
  1729. list);
  1730. pasync_ctx->async_entry[cri].wait_queue.
  1731. bytes_received +=
  1732. (unsigned short)pasync_handle->buffer_len;
  1733. if (pasync_ctx->async_entry[cri].wait_queue.
  1734. bytes_received >=
  1735. pasync_ctx->async_entry[cri].wait_queue.
  1736. bytes_needed)
  1737. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1738. pasync_ctx, cri);
  1739. }
  1740. }
  1741. return status;
  1742. }
  1743. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1744. struct beiscsi_hba *phba,
  1745. struct i_t_dpdu_cqe *pdpdu_cqe)
  1746. {
  1747. struct hwi_controller *phwi_ctrlr;
  1748. struct hwi_async_pdu_context *pasync_ctx;
  1749. struct async_pdu_handle *pasync_handle = NULL;
  1750. unsigned int cq_index = -1;
  1751. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  1752. beiscsi_conn->beiscsi_conn_cid);
  1753. phwi_ctrlr = phba->phwi_ctrlr;
  1754. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
  1755. BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
  1756. cri_index));
  1757. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1758. pdpdu_cqe, &cq_index);
  1759. if (pasync_handle->consumed == 0)
  1760. hwi_update_async_writables(phba, pasync_ctx,
  1761. pasync_handle->is_header, cq_index);
  1762. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1763. hwi_post_async_buffers(phba, pasync_handle->is_header,
  1764. BEISCSI_GET_ULP_FROM_CRI(
  1765. phwi_ctrlr, cri_index));
  1766. }
  1767. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1768. {
  1769. struct be_queue_info *mcc_cq;
  1770. struct be_mcc_compl *mcc_compl;
  1771. unsigned int num_processed = 0;
  1772. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1773. mcc_compl = queue_tail_node(mcc_cq);
  1774. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1775. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1776. if (num_processed >= 32) {
  1777. hwi_ring_cq_db(phba, mcc_cq->id,
  1778. num_processed, 0, 0);
  1779. num_processed = 0;
  1780. }
  1781. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1782. /* Interpret flags as an async trailer */
  1783. if (is_link_state_evt(mcc_compl->flags))
  1784. /* Interpret compl as a async link evt */
  1785. beiscsi_async_link_state_process(phba,
  1786. (struct be_async_event_link_state *) mcc_compl);
  1787. else
  1788. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1789. "BM_%d : Unsupported Async Event, flags"
  1790. " = 0x%08x\n",
  1791. mcc_compl->flags);
  1792. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1793. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1794. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1795. }
  1796. mcc_compl->flags = 0;
  1797. queue_tail_inc(mcc_cq);
  1798. mcc_compl = queue_tail_node(mcc_cq);
  1799. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1800. num_processed++;
  1801. }
  1802. if (num_processed > 0)
  1803. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1804. }
  1805. /**
  1806. * beiscsi_process_cq()- Process the Completion Queue
  1807. * @pbe_eq: Event Q on which the Completion has come
  1808. *
  1809. * return
  1810. * Number of Completion Entries processed.
  1811. **/
  1812. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1813. {
  1814. struct be_queue_info *cq;
  1815. struct sol_cqe *sol;
  1816. struct dmsg_cqe *dmsg;
  1817. unsigned int num_processed = 0;
  1818. unsigned int tot_nump = 0;
  1819. unsigned short code = 0, cid = 0;
  1820. uint16_t cri_index = 0;
  1821. struct beiscsi_conn *beiscsi_conn;
  1822. struct beiscsi_endpoint *beiscsi_ep;
  1823. struct iscsi_endpoint *ep;
  1824. struct beiscsi_hba *phba;
  1825. cq = pbe_eq->cq;
  1826. sol = queue_tail_node(cq);
  1827. phba = pbe_eq->phba;
  1828. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1829. CQE_VALID_MASK) {
  1830. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1831. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1832. 32] & CQE_CODE_MASK);
  1833. /* Get the CID */
  1834. if (is_chip_be2_be3r(phba)) {
  1835. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1836. } else {
  1837. if ((code == DRIVERMSG_NOTIFY) ||
  1838. (code == UNSOL_HDR_NOTIFY) ||
  1839. (code == UNSOL_DATA_NOTIFY))
  1840. cid = AMAP_GET_BITS(
  1841. struct amap_i_t_dpdu_cqe_v2,
  1842. cid, sol);
  1843. else
  1844. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1845. cid, sol);
  1846. }
  1847. cri_index = BE_GET_CRI_FROM_CID(cid);
  1848. ep = phba->ep_array[cri_index];
  1849. beiscsi_ep = ep->dd_data;
  1850. beiscsi_conn = beiscsi_ep->conn;
  1851. if (num_processed >= 32) {
  1852. hwi_ring_cq_db(phba, cq->id,
  1853. num_processed, 0, 0);
  1854. tot_nump += num_processed;
  1855. num_processed = 0;
  1856. }
  1857. switch (code) {
  1858. case SOL_CMD_COMPLETE:
  1859. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1860. break;
  1861. case DRIVERMSG_NOTIFY:
  1862. beiscsi_log(phba, KERN_INFO,
  1863. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1864. "BM_%d : Received %s[%d] on CID : %d\n",
  1865. cqe_desc[code], code, cid);
  1866. dmsg = (struct dmsg_cqe *)sol;
  1867. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1868. break;
  1869. case UNSOL_HDR_NOTIFY:
  1870. beiscsi_log(phba, KERN_INFO,
  1871. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1872. "BM_%d : Received %s[%d] on CID : %d\n",
  1873. cqe_desc[code], code, cid);
  1874. spin_lock_bh(&phba->async_pdu_lock);
  1875. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1876. (struct i_t_dpdu_cqe *)sol);
  1877. spin_unlock_bh(&phba->async_pdu_lock);
  1878. break;
  1879. case UNSOL_DATA_NOTIFY:
  1880. beiscsi_log(phba, KERN_INFO,
  1881. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1882. "BM_%d : Received %s[%d] on CID : %d\n",
  1883. cqe_desc[code], code, cid);
  1884. spin_lock_bh(&phba->async_pdu_lock);
  1885. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1886. (struct i_t_dpdu_cqe *)sol);
  1887. spin_unlock_bh(&phba->async_pdu_lock);
  1888. break;
  1889. case CXN_INVALIDATE_INDEX_NOTIFY:
  1890. case CMD_INVALIDATED_NOTIFY:
  1891. case CXN_INVALIDATE_NOTIFY:
  1892. beiscsi_log(phba, KERN_ERR,
  1893. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1894. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1895. cqe_desc[code], code, cid);
  1896. break;
  1897. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1898. case CMD_KILLED_INVALID_STATSN_RCVD:
  1899. case CMD_KILLED_INVALID_R2T_RCVD:
  1900. case CMD_CXN_KILLED_LUN_INVALID:
  1901. case CMD_CXN_KILLED_ICD_INVALID:
  1902. case CMD_CXN_KILLED_ITT_INVALID:
  1903. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1904. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1905. beiscsi_log(phba, KERN_ERR,
  1906. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1907. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1908. cqe_desc[code], code, cid);
  1909. break;
  1910. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1911. beiscsi_log(phba, KERN_ERR,
  1912. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1913. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1914. cqe_desc[code], code, cid);
  1915. spin_lock_bh(&phba->async_pdu_lock);
  1916. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1917. (struct i_t_dpdu_cqe *) sol);
  1918. spin_unlock_bh(&phba->async_pdu_lock);
  1919. break;
  1920. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1921. case CXN_KILLED_BURST_LEN_MISMATCH:
  1922. case CXN_KILLED_AHS_RCVD:
  1923. case CXN_KILLED_HDR_DIGEST_ERR:
  1924. case CXN_KILLED_UNKNOWN_HDR:
  1925. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1926. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1927. case CXN_KILLED_TIMED_OUT:
  1928. case CXN_KILLED_FIN_RCVD:
  1929. case CXN_KILLED_RST_SENT:
  1930. case CXN_KILLED_RST_RCVD:
  1931. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1932. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1933. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1934. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1935. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1936. beiscsi_log(phba, KERN_ERR,
  1937. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1938. "BM_%d : Event %s[%d] received on CID : %d\n",
  1939. cqe_desc[code], code, cid);
  1940. if (beiscsi_conn)
  1941. iscsi_conn_failure(beiscsi_conn->conn,
  1942. ISCSI_ERR_CONN_FAILED);
  1943. break;
  1944. default:
  1945. beiscsi_log(phba, KERN_ERR,
  1946. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1947. "BM_%d : Invalid CQE Event Received Code : %d"
  1948. "CID 0x%x...\n",
  1949. code, cid);
  1950. break;
  1951. }
  1952. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1953. queue_tail_inc(cq);
  1954. sol = queue_tail_node(cq);
  1955. num_processed++;
  1956. }
  1957. if (num_processed > 0) {
  1958. tot_nump += num_processed;
  1959. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1960. }
  1961. return tot_nump;
  1962. }
  1963. void beiscsi_process_all_cqs(struct work_struct *work)
  1964. {
  1965. unsigned long flags;
  1966. struct hwi_controller *phwi_ctrlr;
  1967. struct hwi_context_memory *phwi_context;
  1968. struct beiscsi_hba *phba;
  1969. struct be_eq_obj *pbe_eq =
  1970. container_of(work, struct be_eq_obj, work_cqs);
  1971. phba = pbe_eq->phba;
  1972. phwi_ctrlr = phba->phwi_ctrlr;
  1973. phwi_context = phwi_ctrlr->phwi_ctxt;
  1974. if (pbe_eq->todo_mcc_cq) {
  1975. spin_lock_irqsave(&phba->isr_lock, flags);
  1976. pbe_eq->todo_mcc_cq = false;
  1977. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1978. beiscsi_process_mcc_isr(phba);
  1979. }
  1980. if (pbe_eq->todo_cq) {
  1981. spin_lock_irqsave(&phba->isr_lock, flags);
  1982. pbe_eq->todo_cq = false;
  1983. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1984. beiscsi_process_cq(pbe_eq);
  1985. }
  1986. /* rearm EQ for further interrupts */
  1987. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1988. }
  1989. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1990. {
  1991. unsigned int ret;
  1992. struct beiscsi_hba *phba;
  1993. struct be_eq_obj *pbe_eq;
  1994. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1995. ret = beiscsi_process_cq(pbe_eq);
  1996. if (ret < budget) {
  1997. phba = pbe_eq->phba;
  1998. blk_iopoll_complete(iop);
  1999. beiscsi_log(phba, KERN_INFO,
  2000. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  2001. "BM_%d : rearm pbe_eq->q.id =%d\n",
  2002. pbe_eq->q.id);
  2003. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  2004. }
  2005. return ret;
  2006. }
  2007. static void
  2008. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2009. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2010. {
  2011. struct iscsi_sge *psgl;
  2012. unsigned int sg_len, index;
  2013. unsigned int sge_len = 0;
  2014. unsigned long long addr;
  2015. struct scatterlist *l_sg;
  2016. unsigned int offset;
  2017. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  2018. io_task->bhs_pa.u.a32.address_lo);
  2019. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  2020. io_task->bhs_pa.u.a32.address_hi);
  2021. l_sg = sg;
  2022. for (index = 0; (index < num_sg) && (index < 2); index++,
  2023. sg = sg_next(sg)) {
  2024. if (index == 0) {
  2025. sg_len = sg_dma_len(sg);
  2026. addr = (u64) sg_dma_address(sg);
  2027. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2028. sge0_addr_lo, pwrb,
  2029. lower_32_bits(addr));
  2030. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2031. sge0_addr_hi, pwrb,
  2032. upper_32_bits(addr));
  2033. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2034. sge0_len, pwrb,
  2035. sg_len);
  2036. sge_len = sg_len;
  2037. } else {
  2038. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2039. pwrb, sge_len);
  2040. sg_len = sg_dma_len(sg);
  2041. addr = (u64) sg_dma_address(sg);
  2042. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2043. sge1_addr_lo, pwrb,
  2044. lower_32_bits(addr));
  2045. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2046. sge1_addr_hi, pwrb,
  2047. upper_32_bits(addr));
  2048. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2049. sge1_len, pwrb,
  2050. sg_len);
  2051. }
  2052. }
  2053. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2054. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2056. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2057. io_task->bhs_pa.u.a32.address_hi);
  2058. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2059. io_task->bhs_pa.u.a32.address_lo);
  2060. if (num_sg == 1) {
  2061. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2062. 1);
  2063. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2064. 0);
  2065. } else if (num_sg == 2) {
  2066. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2067. 0);
  2068. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2069. 1);
  2070. } else {
  2071. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2072. 0);
  2073. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2074. 0);
  2075. }
  2076. sg = l_sg;
  2077. psgl++;
  2078. psgl++;
  2079. offset = 0;
  2080. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2081. sg_len = sg_dma_len(sg);
  2082. addr = (u64) sg_dma_address(sg);
  2083. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2084. lower_32_bits(addr));
  2085. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2086. upper_32_bits(addr));
  2087. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2088. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2089. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2090. offset += sg_len;
  2091. }
  2092. psgl--;
  2093. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2094. }
  2095. static void
  2096. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2097. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2098. {
  2099. struct iscsi_sge *psgl;
  2100. unsigned int sg_len, index;
  2101. unsigned int sge_len = 0;
  2102. unsigned long long addr;
  2103. struct scatterlist *l_sg;
  2104. unsigned int offset;
  2105. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2106. io_task->bhs_pa.u.a32.address_lo);
  2107. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2108. io_task->bhs_pa.u.a32.address_hi);
  2109. l_sg = sg;
  2110. for (index = 0; (index < num_sg) && (index < 2); index++,
  2111. sg = sg_next(sg)) {
  2112. if (index == 0) {
  2113. sg_len = sg_dma_len(sg);
  2114. addr = (u64) sg_dma_address(sg);
  2115. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2116. ((u32)(addr & 0xFFFFFFFF)));
  2117. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2118. ((u32)(addr >> 32)));
  2119. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2120. sg_len);
  2121. sge_len = sg_len;
  2122. } else {
  2123. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2124. pwrb, sge_len);
  2125. sg_len = sg_dma_len(sg);
  2126. addr = (u64) sg_dma_address(sg);
  2127. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2128. ((u32)(addr & 0xFFFFFFFF)));
  2129. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2130. ((u32)(addr >> 32)));
  2131. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2132. sg_len);
  2133. }
  2134. }
  2135. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2136. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2137. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2138. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2139. io_task->bhs_pa.u.a32.address_hi);
  2140. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2141. io_task->bhs_pa.u.a32.address_lo);
  2142. if (num_sg == 1) {
  2143. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2144. 1);
  2145. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2146. 0);
  2147. } else if (num_sg == 2) {
  2148. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2149. 0);
  2150. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2151. 1);
  2152. } else {
  2153. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2154. 0);
  2155. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2156. 0);
  2157. }
  2158. sg = l_sg;
  2159. psgl++;
  2160. psgl++;
  2161. offset = 0;
  2162. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2163. sg_len = sg_dma_len(sg);
  2164. addr = (u64) sg_dma_address(sg);
  2165. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2166. (addr & 0xFFFFFFFF));
  2167. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2168. (addr >> 32));
  2169. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2170. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2171. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2172. offset += sg_len;
  2173. }
  2174. psgl--;
  2175. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2176. }
  2177. /**
  2178. * hwi_write_buffer()- Populate the WRB with task info
  2179. * @pwrb: ptr to the WRB entry
  2180. * @task: iscsi task which is to be executed
  2181. **/
  2182. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2183. {
  2184. struct iscsi_sge *psgl;
  2185. struct beiscsi_io_task *io_task = task->dd_data;
  2186. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2187. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2188. uint8_t dsp_value = 0;
  2189. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2190. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2191. io_task->bhs_pa.u.a32.address_lo);
  2192. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2193. io_task->bhs_pa.u.a32.address_hi);
  2194. if (task->data) {
  2195. /* Check for the data_count */
  2196. dsp_value = (task->data_count) ? 1 : 0;
  2197. if (is_chip_be2_be3r(phba))
  2198. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2199. pwrb, dsp_value);
  2200. else
  2201. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2202. pwrb, dsp_value);
  2203. /* Map addr only if there is data_count */
  2204. if (dsp_value) {
  2205. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2206. task->data,
  2207. task->data_count,
  2208. PCI_DMA_TODEVICE);
  2209. io_task->mtask_data_count = task->data_count;
  2210. } else
  2211. io_task->mtask_addr = 0;
  2212. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2213. lower_32_bits(io_task->mtask_addr));
  2214. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2215. upper_32_bits(io_task->mtask_addr));
  2216. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2217. task->data_count);
  2218. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2219. } else {
  2220. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2221. io_task->mtask_addr = 0;
  2222. }
  2223. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2224. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2225. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2226. io_task->bhs_pa.u.a32.address_hi);
  2227. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2228. io_task->bhs_pa.u.a32.address_lo);
  2229. if (task->data) {
  2230. psgl++;
  2231. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2232. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2233. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2234. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2235. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2236. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2237. psgl++;
  2238. if (task->data) {
  2239. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2240. lower_32_bits(io_task->mtask_addr));
  2241. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2242. upper_32_bits(io_task->mtask_addr));
  2243. }
  2244. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2245. }
  2246. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2247. }
  2248. /**
  2249. * beiscsi_find_mem_req()- Find mem needed
  2250. * @phba: ptr to HBA struct
  2251. **/
  2252. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2253. {
  2254. uint8_t mem_descr_index, ulp_num;
  2255. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2256. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2257. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2258. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2259. sizeof(struct sol_cqe));
  2260. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2261. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2262. BE_ISCSI_PDU_HEADER_SIZE;
  2263. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2264. sizeof(struct hwi_context_memory);
  2265. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2266. * (phba->params.wrbs_per_cxn)
  2267. * phba->params.cxns_per_ctrl;
  2268. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2269. (phba->params.wrbs_per_cxn);
  2270. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2271. phba->params.cxns_per_ctrl);
  2272. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2273. phba->params.icds_per_ctrl;
  2274. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2275. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2276. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  2277. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  2278. num_async_pdu_buf_sgl_pages =
  2279. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2280. phba, ulp_num) *
  2281. sizeof(struct phys_addr));
  2282. num_async_pdu_buf_pages =
  2283. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2284. phba, ulp_num) *
  2285. phba->params.defpdu_hdr_sz);
  2286. num_async_pdu_data_pages =
  2287. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2288. phba, ulp_num) *
  2289. phba->params.defpdu_data_sz);
  2290. num_async_pdu_data_sgl_pages =
  2291. PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
  2292. phba, ulp_num) *
  2293. sizeof(struct phys_addr));
  2294. mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
  2295. (ulp_num * MEM_DESCR_OFFSET));
  2296. phba->mem_req[mem_descr_index] =
  2297. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2298. BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
  2299. mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
  2300. (ulp_num * MEM_DESCR_OFFSET));
  2301. phba->mem_req[mem_descr_index] =
  2302. num_async_pdu_buf_pages *
  2303. PAGE_SIZE;
  2304. mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
  2305. (ulp_num * MEM_DESCR_OFFSET));
  2306. phba->mem_req[mem_descr_index] =
  2307. num_async_pdu_data_pages *
  2308. PAGE_SIZE;
  2309. mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
  2310. (ulp_num * MEM_DESCR_OFFSET));
  2311. phba->mem_req[mem_descr_index] =
  2312. num_async_pdu_buf_sgl_pages *
  2313. PAGE_SIZE;
  2314. mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
  2315. (ulp_num * MEM_DESCR_OFFSET));
  2316. phba->mem_req[mem_descr_index] =
  2317. num_async_pdu_data_sgl_pages *
  2318. PAGE_SIZE;
  2319. mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
  2320. (ulp_num * MEM_DESCR_OFFSET));
  2321. phba->mem_req[mem_descr_index] =
  2322. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2323. sizeof(struct async_pdu_handle);
  2324. mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
  2325. (ulp_num * MEM_DESCR_OFFSET));
  2326. phba->mem_req[mem_descr_index] =
  2327. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2328. sizeof(struct async_pdu_handle);
  2329. mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
  2330. (ulp_num * MEM_DESCR_OFFSET));
  2331. phba->mem_req[mem_descr_index] =
  2332. sizeof(struct hwi_async_pdu_context) +
  2333. (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  2334. sizeof(struct hwi_async_entry));
  2335. }
  2336. }
  2337. }
  2338. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2339. {
  2340. dma_addr_t bus_add;
  2341. struct hwi_controller *phwi_ctrlr;
  2342. struct be_mem_descriptor *mem_descr;
  2343. struct mem_array *mem_arr, *mem_arr_orig;
  2344. unsigned int i, j, alloc_size, curr_alloc_size;
  2345. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2346. if (!phba->phwi_ctrlr)
  2347. return -ENOMEM;
  2348. /* Allocate memory for wrb_context */
  2349. phwi_ctrlr = phba->phwi_ctrlr;
  2350. phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
  2351. phba->params.cxns_per_ctrl,
  2352. GFP_KERNEL);
  2353. if (!phwi_ctrlr->wrb_context)
  2354. return -ENOMEM;
  2355. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2356. GFP_KERNEL);
  2357. if (!phba->init_mem) {
  2358. kfree(phwi_ctrlr->wrb_context);
  2359. kfree(phba->phwi_ctrlr);
  2360. return -ENOMEM;
  2361. }
  2362. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2363. GFP_KERNEL);
  2364. if (!mem_arr_orig) {
  2365. kfree(phba->init_mem);
  2366. kfree(phwi_ctrlr->wrb_context);
  2367. kfree(phba->phwi_ctrlr);
  2368. return -ENOMEM;
  2369. }
  2370. mem_descr = phba->init_mem;
  2371. for (i = 0; i < SE_MEM_MAX; i++) {
  2372. if (!phba->mem_req[i]) {
  2373. mem_descr->mem_array = NULL;
  2374. mem_descr++;
  2375. continue;
  2376. }
  2377. j = 0;
  2378. mem_arr = mem_arr_orig;
  2379. alloc_size = phba->mem_req[i];
  2380. memset(mem_arr, 0, sizeof(struct mem_array) *
  2381. BEISCSI_MAX_FRAGS_INIT);
  2382. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2383. do {
  2384. mem_arr->virtual_address = pci_alloc_consistent(
  2385. phba->pcidev,
  2386. curr_alloc_size,
  2387. &bus_add);
  2388. if (!mem_arr->virtual_address) {
  2389. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2390. goto free_mem;
  2391. if (curr_alloc_size -
  2392. rounddown_pow_of_two(curr_alloc_size))
  2393. curr_alloc_size = rounddown_pow_of_two
  2394. (curr_alloc_size);
  2395. else
  2396. curr_alloc_size = curr_alloc_size / 2;
  2397. } else {
  2398. mem_arr->bus_address.u.
  2399. a64.address = (__u64) bus_add;
  2400. mem_arr->size = curr_alloc_size;
  2401. alloc_size -= curr_alloc_size;
  2402. curr_alloc_size = min(be_max_phys_size *
  2403. 1024, alloc_size);
  2404. j++;
  2405. mem_arr++;
  2406. }
  2407. } while (alloc_size);
  2408. mem_descr->num_elements = j;
  2409. mem_descr->size_in_bytes = phba->mem_req[i];
  2410. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2411. GFP_KERNEL);
  2412. if (!mem_descr->mem_array)
  2413. goto free_mem;
  2414. memcpy(mem_descr->mem_array, mem_arr_orig,
  2415. sizeof(struct mem_array) * j);
  2416. mem_descr++;
  2417. }
  2418. kfree(mem_arr_orig);
  2419. return 0;
  2420. free_mem:
  2421. mem_descr->num_elements = j;
  2422. while ((i) || (j)) {
  2423. for (j = mem_descr->num_elements; j > 0; j--) {
  2424. pci_free_consistent(phba->pcidev,
  2425. mem_descr->mem_array[j - 1].size,
  2426. mem_descr->mem_array[j - 1].
  2427. virtual_address,
  2428. (unsigned long)mem_descr->
  2429. mem_array[j - 1].
  2430. bus_address.u.a64.address);
  2431. }
  2432. if (i) {
  2433. i--;
  2434. kfree(mem_descr->mem_array);
  2435. mem_descr--;
  2436. }
  2437. }
  2438. kfree(mem_arr_orig);
  2439. kfree(phba->init_mem);
  2440. kfree(phba->phwi_ctrlr->wrb_context);
  2441. kfree(phba->phwi_ctrlr);
  2442. return -ENOMEM;
  2443. }
  2444. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2445. {
  2446. beiscsi_find_mem_req(phba);
  2447. return beiscsi_alloc_mem(phba);
  2448. }
  2449. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2450. {
  2451. struct pdu_data_out *pdata_out;
  2452. struct pdu_nop_out *pnop_out;
  2453. struct be_mem_descriptor *mem_descr;
  2454. mem_descr = phba->init_mem;
  2455. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2456. pdata_out =
  2457. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2458. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2459. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2460. IIOC_SCSI_DATA);
  2461. pnop_out =
  2462. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2463. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2464. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2465. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2466. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2467. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2468. }
  2469. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2470. {
  2471. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2472. struct hwi_context_memory *phwi_ctxt;
  2473. struct wrb_handle *pwrb_handle = NULL;
  2474. struct hwi_controller *phwi_ctrlr;
  2475. struct hwi_wrb_context *pwrb_context;
  2476. struct iscsi_wrb *pwrb = NULL;
  2477. unsigned int num_cxn_wrbh = 0;
  2478. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2479. mem_descr_wrbh = phba->init_mem;
  2480. mem_descr_wrbh += HWI_MEM_WRBH;
  2481. mem_descr_wrb = phba->init_mem;
  2482. mem_descr_wrb += HWI_MEM_WRB;
  2483. phwi_ctrlr = phba->phwi_ctrlr;
  2484. /* Allocate memory for WRBQ */
  2485. phwi_ctxt = phwi_ctrlr->phwi_ctxt;
  2486. phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
  2487. phba->params.cxns_per_ctrl,
  2488. GFP_KERNEL);
  2489. if (!phwi_ctxt->be_wrbq) {
  2490. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2491. "BM_%d : WRBQ Mem Alloc Failed\n");
  2492. return -ENOMEM;
  2493. }
  2494. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2495. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2496. pwrb_context->pwrb_handle_base =
  2497. kzalloc(sizeof(struct wrb_handle *) *
  2498. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2499. if (!pwrb_context->pwrb_handle_base) {
  2500. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2501. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2502. goto init_wrb_hndl_failed;
  2503. }
  2504. pwrb_context->pwrb_handle_basestd =
  2505. kzalloc(sizeof(struct wrb_handle *) *
  2506. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2507. if (!pwrb_context->pwrb_handle_basestd) {
  2508. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2509. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2510. goto init_wrb_hndl_failed;
  2511. }
  2512. if (!num_cxn_wrbh) {
  2513. pwrb_handle =
  2514. mem_descr_wrbh->mem_array[idx].virtual_address;
  2515. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2516. ((sizeof(struct wrb_handle)) *
  2517. phba->params.wrbs_per_cxn));
  2518. idx++;
  2519. }
  2520. pwrb_context->alloc_index = 0;
  2521. pwrb_context->wrb_handles_available = 0;
  2522. pwrb_context->free_index = 0;
  2523. if (num_cxn_wrbh) {
  2524. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2525. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2526. pwrb_context->pwrb_handle_basestd[j] =
  2527. pwrb_handle;
  2528. pwrb_context->wrb_handles_available++;
  2529. pwrb_handle->wrb_index = j;
  2530. pwrb_handle++;
  2531. }
  2532. num_cxn_wrbh--;
  2533. }
  2534. }
  2535. idx = 0;
  2536. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2537. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2538. if (!num_cxn_wrb) {
  2539. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2540. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2541. ((sizeof(struct iscsi_wrb) *
  2542. phba->params.wrbs_per_cxn));
  2543. idx++;
  2544. }
  2545. if (num_cxn_wrb) {
  2546. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2547. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2548. pwrb_handle->pwrb = pwrb;
  2549. pwrb++;
  2550. }
  2551. num_cxn_wrb--;
  2552. }
  2553. }
  2554. return 0;
  2555. init_wrb_hndl_failed:
  2556. for (j = index; j > 0; j--) {
  2557. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2558. kfree(pwrb_context->pwrb_handle_base);
  2559. kfree(pwrb_context->pwrb_handle_basestd);
  2560. }
  2561. return -ENOMEM;
  2562. }
  2563. static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2564. {
  2565. uint8_t ulp_num;
  2566. struct hwi_controller *phwi_ctrlr;
  2567. struct hba_parameters *p = &phba->params;
  2568. struct hwi_async_pdu_context *pasync_ctx;
  2569. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2570. unsigned int index, idx, num_per_mem, num_async_data;
  2571. struct be_mem_descriptor *mem_descr;
  2572. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  2573. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  2574. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2575. mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
  2576. (ulp_num * MEM_DESCR_OFFSET));
  2577. phwi_ctrlr = phba->phwi_ctrlr;
  2578. phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
  2579. (struct hwi_async_pdu_context *)
  2580. mem_descr->mem_array[0].virtual_address;
  2581. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
  2582. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2583. pasync_ctx->async_entry =
  2584. (struct hwi_async_entry *)
  2585. ((long unsigned int)pasync_ctx +
  2586. sizeof(struct hwi_async_pdu_context));
  2587. pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
  2588. ulp_num);
  2589. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2590. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2591. mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
  2592. (ulp_num * MEM_DESCR_OFFSET);
  2593. if (mem_descr->mem_array[0].virtual_address) {
  2594. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2595. "BM_%d : hwi_init_async_pdu_ctx"
  2596. " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
  2597. ulp_num,
  2598. mem_descr->mem_array[0].
  2599. virtual_address);
  2600. } else
  2601. beiscsi_log(phba, KERN_WARNING,
  2602. BEISCSI_LOG_INIT,
  2603. "BM_%d : No Virtual address for ULP : %d\n",
  2604. ulp_num);
  2605. pasync_ctx->async_header.va_base =
  2606. mem_descr->mem_array[0].virtual_address;
  2607. pasync_ctx->async_header.pa_base.u.a64.address =
  2608. mem_descr->mem_array[0].
  2609. bus_address.u.a64.address;
  2610. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2611. mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
  2612. (ulp_num * MEM_DESCR_OFFSET);
  2613. if (mem_descr->mem_array[0].virtual_address) {
  2614. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2615. "BM_%d : hwi_init_async_pdu_ctx"
  2616. " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
  2617. ulp_num,
  2618. mem_descr->mem_array[0].
  2619. virtual_address);
  2620. } else
  2621. beiscsi_log(phba, KERN_WARNING,
  2622. BEISCSI_LOG_INIT,
  2623. "BM_%d : No Virtual address for ULP : %d\n",
  2624. ulp_num);
  2625. pasync_ctx->async_header.ring_base =
  2626. mem_descr->mem_array[0].virtual_address;
  2627. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2628. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
  2629. (ulp_num * MEM_DESCR_OFFSET);
  2630. if (mem_descr->mem_array[0].virtual_address) {
  2631. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2632. "BM_%d : hwi_init_async_pdu_ctx"
  2633. " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
  2634. ulp_num,
  2635. mem_descr->mem_array[0].
  2636. virtual_address);
  2637. } else
  2638. beiscsi_log(phba, KERN_WARNING,
  2639. BEISCSI_LOG_INIT,
  2640. "BM_%d : No Virtual address for ULP : %d\n",
  2641. ulp_num);
  2642. pasync_ctx->async_header.handle_base =
  2643. mem_descr->mem_array[0].virtual_address;
  2644. pasync_ctx->async_header.writables = 0;
  2645. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2646. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2647. mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
  2648. (ulp_num * MEM_DESCR_OFFSET);
  2649. if (mem_descr->mem_array[0].virtual_address) {
  2650. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2651. "BM_%d : hwi_init_async_pdu_ctx"
  2652. " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
  2653. ulp_num,
  2654. mem_descr->mem_array[0].
  2655. virtual_address);
  2656. } else
  2657. beiscsi_log(phba, KERN_WARNING,
  2658. BEISCSI_LOG_INIT,
  2659. "BM_%d : No Virtual address for ULP : %d\n",
  2660. ulp_num);
  2661. pasync_ctx->async_data.ring_base =
  2662. mem_descr->mem_array[0].virtual_address;
  2663. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2664. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
  2665. (ulp_num * MEM_DESCR_OFFSET);
  2666. if (!mem_descr->mem_array[0].virtual_address)
  2667. beiscsi_log(phba, KERN_WARNING,
  2668. BEISCSI_LOG_INIT,
  2669. "BM_%d : No Virtual address for ULP : %d\n",
  2670. ulp_num);
  2671. pasync_ctx->async_data.handle_base =
  2672. mem_descr->mem_array[0].virtual_address;
  2673. pasync_ctx->async_data.writables = 0;
  2674. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2675. pasync_header_h =
  2676. (struct async_pdu_handle *)
  2677. pasync_ctx->async_header.handle_base;
  2678. pasync_data_h =
  2679. (struct async_pdu_handle *)
  2680. pasync_ctx->async_data.handle_base;
  2681. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2682. mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
  2683. (ulp_num * MEM_DESCR_OFFSET);
  2684. if (mem_descr->mem_array[0].virtual_address) {
  2685. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2686. "BM_%d : hwi_init_async_pdu_ctx"
  2687. " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
  2688. ulp_num,
  2689. mem_descr->mem_array[0].
  2690. virtual_address);
  2691. } else
  2692. beiscsi_log(phba, KERN_WARNING,
  2693. BEISCSI_LOG_INIT,
  2694. "BM_%d : No Virtual address for ULP : %d\n",
  2695. ulp_num);
  2696. idx = 0;
  2697. pasync_ctx->async_data.va_base =
  2698. mem_descr->mem_array[idx].virtual_address;
  2699. pasync_ctx->async_data.pa_base.u.a64.address =
  2700. mem_descr->mem_array[idx].
  2701. bus_address.u.a64.address;
  2702. num_async_data = ((mem_descr->mem_array[idx].size) /
  2703. phba->params.defpdu_data_sz);
  2704. num_per_mem = 0;
  2705. for (index = 0; index < BEISCSI_GET_CID_COUNT
  2706. (phba, ulp_num); index++) {
  2707. pasync_header_h->cri = -1;
  2708. pasync_header_h->index = (char)index;
  2709. INIT_LIST_HEAD(&pasync_header_h->link);
  2710. pasync_header_h->pbuffer =
  2711. (void *)((unsigned long)
  2712. (pasync_ctx->
  2713. async_header.va_base) +
  2714. (p->defpdu_hdr_sz * index));
  2715. pasync_header_h->pa.u.a64.address =
  2716. pasync_ctx->async_header.pa_base.u.a64.
  2717. address + (p->defpdu_hdr_sz * index);
  2718. list_add_tail(&pasync_header_h->link,
  2719. &pasync_ctx->async_header.
  2720. free_list);
  2721. pasync_header_h++;
  2722. pasync_ctx->async_header.free_entries++;
  2723. pasync_ctx->async_header.writables++;
  2724. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2725. wait_queue.list);
  2726. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2727. header_busy_list);
  2728. pasync_data_h->cri = -1;
  2729. pasync_data_h->index = (char)index;
  2730. INIT_LIST_HEAD(&pasync_data_h->link);
  2731. if (!num_async_data) {
  2732. num_per_mem = 0;
  2733. idx++;
  2734. pasync_ctx->async_data.va_base =
  2735. mem_descr->mem_array[idx].
  2736. virtual_address;
  2737. pasync_ctx->async_data.pa_base.u.
  2738. a64.address =
  2739. mem_descr->mem_array[idx].
  2740. bus_address.u.a64.address;
  2741. num_async_data =
  2742. ((mem_descr->mem_array[idx].
  2743. size) /
  2744. phba->params.defpdu_data_sz);
  2745. }
  2746. pasync_data_h->pbuffer =
  2747. (void *)((unsigned long)
  2748. (pasync_ctx->async_data.va_base) +
  2749. (p->defpdu_data_sz * num_per_mem));
  2750. pasync_data_h->pa.u.a64.address =
  2751. pasync_ctx->async_data.pa_base.u.a64.
  2752. address + (p->defpdu_data_sz *
  2753. num_per_mem);
  2754. num_per_mem++;
  2755. num_async_data--;
  2756. list_add_tail(&pasync_data_h->link,
  2757. &pasync_ctx->async_data.
  2758. free_list);
  2759. pasync_data_h++;
  2760. pasync_ctx->async_data.free_entries++;
  2761. pasync_ctx->async_data.writables++;
  2762. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2763. data_busy_list);
  2764. }
  2765. pasync_ctx->async_header.host_write_ptr = 0;
  2766. pasync_ctx->async_header.ep_read_ptr = -1;
  2767. pasync_ctx->async_data.host_write_ptr = 0;
  2768. pasync_ctx->async_data.ep_read_ptr = -1;
  2769. }
  2770. }
  2771. return 0;
  2772. }
  2773. static int
  2774. be_sgl_create_contiguous(void *virtual_address,
  2775. u64 physical_address, u32 length,
  2776. struct be_dma_mem *sgl)
  2777. {
  2778. WARN_ON(!virtual_address);
  2779. WARN_ON(!physical_address);
  2780. WARN_ON(!length > 0);
  2781. WARN_ON(!sgl);
  2782. sgl->va = virtual_address;
  2783. sgl->dma = (unsigned long)physical_address;
  2784. sgl->size = length;
  2785. return 0;
  2786. }
  2787. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2788. {
  2789. memset(sgl, 0, sizeof(*sgl));
  2790. }
  2791. static void
  2792. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2793. struct mem_array *pmem, struct be_dma_mem *sgl)
  2794. {
  2795. if (sgl->va)
  2796. be_sgl_destroy_contiguous(sgl);
  2797. be_sgl_create_contiguous(pmem->virtual_address,
  2798. pmem->bus_address.u.a64.address,
  2799. pmem->size, sgl);
  2800. }
  2801. static void
  2802. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2803. struct mem_array *pmem, struct be_dma_mem *sgl)
  2804. {
  2805. if (sgl->va)
  2806. be_sgl_destroy_contiguous(sgl);
  2807. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2808. pmem->bus_address.u.a64.address,
  2809. pmem->size, sgl);
  2810. }
  2811. static int be_fill_queue(struct be_queue_info *q,
  2812. u16 len, u16 entry_size, void *vaddress)
  2813. {
  2814. struct be_dma_mem *mem = &q->dma_mem;
  2815. memset(q, 0, sizeof(*q));
  2816. q->len = len;
  2817. q->entry_size = entry_size;
  2818. mem->size = len * entry_size;
  2819. mem->va = vaddress;
  2820. if (!mem->va)
  2821. return -ENOMEM;
  2822. memset(mem->va, 0, mem->size);
  2823. return 0;
  2824. }
  2825. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2826. struct hwi_context_memory *phwi_context)
  2827. {
  2828. unsigned int i, num_eq_pages;
  2829. int ret = 0, eq_for_mcc;
  2830. struct be_queue_info *eq;
  2831. struct be_dma_mem *mem;
  2832. void *eq_vaddress;
  2833. dma_addr_t paddr;
  2834. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2835. sizeof(struct be_eq_entry));
  2836. if (phba->msix_enabled)
  2837. eq_for_mcc = 1;
  2838. else
  2839. eq_for_mcc = 0;
  2840. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2841. eq = &phwi_context->be_eq[i].q;
  2842. mem = &eq->dma_mem;
  2843. phwi_context->be_eq[i].phba = phba;
  2844. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2845. num_eq_pages * PAGE_SIZE,
  2846. &paddr);
  2847. if (!eq_vaddress)
  2848. goto create_eq_error;
  2849. mem->va = eq_vaddress;
  2850. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2851. sizeof(struct be_eq_entry), eq_vaddress);
  2852. if (ret) {
  2853. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2854. "BM_%d : be_fill_queue Failed for EQ\n");
  2855. goto create_eq_error;
  2856. }
  2857. mem->dma = paddr;
  2858. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2859. phwi_context->cur_eqd);
  2860. if (ret) {
  2861. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2862. "BM_%d : beiscsi_cmd_eq_create"
  2863. "Failed for EQ\n");
  2864. goto create_eq_error;
  2865. }
  2866. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2867. "BM_%d : eqid = %d\n",
  2868. phwi_context->be_eq[i].q.id);
  2869. }
  2870. return 0;
  2871. create_eq_error:
  2872. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2873. eq = &phwi_context->be_eq[i].q;
  2874. mem = &eq->dma_mem;
  2875. if (mem->va)
  2876. pci_free_consistent(phba->pcidev, num_eq_pages
  2877. * PAGE_SIZE,
  2878. mem->va, mem->dma);
  2879. }
  2880. return ret;
  2881. }
  2882. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2883. struct hwi_context_memory *phwi_context)
  2884. {
  2885. unsigned int i, num_cq_pages;
  2886. int ret = 0;
  2887. struct be_queue_info *cq, *eq;
  2888. struct be_dma_mem *mem;
  2889. struct be_eq_obj *pbe_eq;
  2890. void *cq_vaddress;
  2891. dma_addr_t paddr;
  2892. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2893. sizeof(struct sol_cqe));
  2894. for (i = 0; i < phba->num_cpus; i++) {
  2895. cq = &phwi_context->be_cq[i];
  2896. eq = &phwi_context->be_eq[i].q;
  2897. pbe_eq = &phwi_context->be_eq[i];
  2898. pbe_eq->cq = cq;
  2899. pbe_eq->phba = phba;
  2900. mem = &cq->dma_mem;
  2901. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2902. num_cq_pages * PAGE_SIZE,
  2903. &paddr);
  2904. if (!cq_vaddress)
  2905. goto create_cq_error;
  2906. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2907. sizeof(struct sol_cqe), cq_vaddress);
  2908. if (ret) {
  2909. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2910. "BM_%d : be_fill_queue Failed "
  2911. "for ISCSI CQ\n");
  2912. goto create_cq_error;
  2913. }
  2914. mem->dma = paddr;
  2915. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2916. false, 0);
  2917. if (ret) {
  2918. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2919. "BM_%d : beiscsi_cmd_eq_create"
  2920. "Failed for ISCSI CQ\n");
  2921. goto create_cq_error;
  2922. }
  2923. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2924. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2925. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2926. }
  2927. return 0;
  2928. create_cq_error:
  2929. for (i = 0; i < phba->num_cpus; i++) {
  2930. cq = &phwi_context->be_cq[i];
  2931. mem = &cq->dma_mem;
  2932. if (mem->va)
  2933. pci_free_consistent(phba->pcidev, num_cq_pages
  2934. * PAGE_SIZE,
  2935. mem->va, mem->dma);
  2936. }
  2937. return ret;
  2938. }
  2939. static int
  2940. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2941. struct hwi_context_memory *phwi_context,
  2942. struct hwi_controller *phwi_ctrlr,
  2943. unsigned int def_pdu_ring_sz, uint8_t ulp_num)
  2944. {
  2945. unsigned int idx;
  2946. int ret;
  2947. struct be_queue_info *dq, *cq;
  2948. struct be_dma_mem *mem;
  2949. struct be_mem_descriptor *mem_descr;
  2950. void *dq_vaddress;
  2951. idx = 0;
  2952. dq = &phwi_context->be_def_hdrq[ulp_num];
  2953. cq = &phwi_context->be_cq[0];
  2954. mem = &dq->dma_mem;
  2955. mem_descr = phba->init_mem;
  2956. mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
  2957. (ulp_num * MEM_DESCR_OFFSET);
  2958. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2959. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2960. sizeof(struct phys_addr),
  2961. sizeof(struct phys_addr), dq_vaddress);
  2962. if (ret) {
  2963. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2964. "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
  2965. ulp_num);
  2966. return ret;
  2967. }
  2968. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2969. bus_address.u.a64.address;
  2970. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2971. def_pdu_ring_sz,
  2972. phba->params.defpdu_hdr_sz,
  2973. BEISCSI_DEFQ_HDR, ulp_num);
  2974. if (ret) {
  2975. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2976. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
  2977. ulp_num);
  2978. return ret;
  2979. }
  2980. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2981. "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
  2982. ulp_num,
  2983. phwi_context->be_def_hdrq[ulp_num].id);
  2984. hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num);
  2985. return 0;
  2986. }
  2987. static int
  2988. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2989. struct hwi_context_memory *phwi_context,
  2990. struct hwi_controller *phwi_ctrlr,
  2991. unsigned int def_pdu_ring_sz, uint8_t ulp_num)
  2992. {
  2993. unsigned int idx;
  2994. int ret;
  2995. struct be_queue_info *dataq, *cq;
  2996. struct be_dma_mem *mem;
  2997. struct be_mem_descriptor *mem_descr;
  2998. void *dq_vaddress;
  2999. idx = 0;
  3000. dataq = &phwi_context->be_def_dataq[ulp_num];
  3001. cq = &phwi_context->be_cq[0];
  3002. mem = &dataq->dma_mem;
  3003. mem_descr = phba->init_mem;
  3004. mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
  3005. (ulp_num * MEM_DESCR_OFFSET);
  3006. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  3007. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  3008. sizeof(struct phys_addr),
  3009. sizeof(struct phys_addr), dq_vaddress);
  3010. if (ret) {
  3011. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3012. "BM_%d : be_fill_queue Failed for DEF PDU "
  3013. "DATA on ULP : %d\n",
  3014. ulp_num);
  3015. return ret;
  3016. }
  3017. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  3018. bus_address.u.a64.address;
  3019. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  3020. def_pdu_ring_sz,
  3021. phba->params.defpdu_data_sz,
  3022. BEISCSI_DEFQ_DATA, ulp_num);
  3023. if (ret) {
  3024. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3025. "BM_%d be_cmd_create_default_pdu_queue"
  3026. " Failed for DEF PDU DATA on ULP : %d\n",
  3027. ulp_num);
  3028. return ret;
  3029. }
  3030. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3031. "BM_%d : iscsi def data id on ULP : %d is %d\n",
  3032. ulp_num,
  3033. phwi_context->be_def_dataq[ulp_num].id);
  3034. hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num);
  3035. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3036. "BM_%d : DEFAULT PDU DATA RING CREATED"
  3037. "on ULP : %d\n", ulp_num);
  3038. return 0;
  3039. }
  3040. static int
  3041. beiscsi_post_template_hdr(struct beiscsi_hba *phba)
  3042. {
  3043. struct be_mem_descriptor *mem_descr;
  3044. struct mem_array *pm_arr;
  3045. struct be_dma_mem sgl;
  3046. int status, ulp_num;
  3047. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3048. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3049. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  3050. mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
  3051. (ulp_num * MEM_DESCR_OFFSET);
  3052. pm_arr = mem_descr->mem_array;
  3053. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  3054. status = be_cmd_iscsi_post_template_hdr(
  3055. &phba->ctrl, &sgl);
  3056. if (status != 0) {
  3057. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3058. "BM_%d : Post Template HDR Failed for"
  3059. "ULP_%d\n", ulp_num);
  3060. return status;
  3061. }
  3062. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3063. "BM_%d : Template HDR Pages Posted for"
  3064. "ULP_%d\n", ulp_num);
  3065. }
  3066. }
  3067. return 0;
  3068. }
  3069. static int
  3070. beiscsi_post_pages(struct beiscsi_hba *phba)
  3071. {
  3072. struct be_mem_descriptor *mem_descr;
  3073. struct mem_array *pm_arr;
  3074. unsigned int page_offset, i;
  3075. struct be_dma_mem sgl;
  3076. int status, ulp_num = 0;
  3077. mem_descr = phba->init_mem;
  3078. mem_descr += HWI_MEM_SGE;
  3079. pm_arr = mem_descr->mem_array;
  3080. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
  3081. if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
  3082. break;
  3083. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  3084. phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
  3085. for (i = 0; i < mem_descr->num_elements; i++) {
  3086. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  3087. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  3088. page_offset,
  3089. (pm_arr->size / PAGE_SIZE));
  3090. page_offset += pm_arr->size / PAGE_SIZE;
  3091. if (status != 0) {
  3092. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3093. "BM_%d : post sgl failed.\n");
  3094. return status;
  3095. }
  3096. pm_arr++;
  3097. }
  3098. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3099. "BM_%d : POSTED PAGES\n");
  3100. return 0;
  3101. }
  3102. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  3103. {
  3104. struct be_dma_mem *mem = &q->dma_mem;
  3105. if (mem->va) {
  3106. pci_free_consistent(phba->pcidev, mem->size,
  3107. mem->va, mem->dma);
  3108. mem->va = NULL;
  3109. }
  3110. }
  3111. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  3112. u16 len, u16 entry_size)
  3113. {
  3114. struct be_dma_mem *mem = &q->dma_mem;
  3115. memset(q, 0, sizeof(*q));
  3116. q->len = len;
  3117. q->entry_size = entry_size;
  3118. mem->size = len * entry_size;
  3119. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  3120. if (!mem->va)
  3121. return -ENOMEM;
  3122. memset(mem->va, 0, mem->size);
  3123. return 0;
  3124. }
  3125. static int
  3126. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  3127. struct hwi_context_memory *phwi_context,
  3128. struct hwi_controller *phwi_ctrlr)
  3129. {
  3130. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  3131. u64 pa_addr_lo;
  3132. unsigned int idx, num, i, ulp_num;
  3133. struct mem_array *pwrb_arr;
  3134. void *wrb_vaddr;
  3135. struct be_dma_mem sgl;
  3136. struct be_mem_descriptor *mem_descr;
  3137. struct hwi_wrb_context *pwrb_context;
  3138. int status;
  3139. uint8_t ulp_count = 0, ulp_base_num = 0;
  3140. uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
  3141. idx = 0;
  3142. mem_descr = phba->init_mem;
  3143. mem_descr += HWI_MEM_WRB;
  3144. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  3145. GFP_KERNEL);
  3146. if (!pwrb_arr) {
  3147. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3148. "BM_%d : Memory alloc failed in create wrb ring.\n");
  3149. return -ENOMEM;
  3150. }
  3151. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3152. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  3153. num_wrb_rings = mem_descr->mem_array[idx].size /
  3154. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  3155. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  3156. if (num_wrb_rings) {
  3157. pwrb_arr[num].virtual_address = wrb_vaddr;
  3158. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  3159. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3160. sizeof(struct iscsi_wrb);
  3161. wrb_vaddr += pwrb_arr[num].size;
  3162. pa_addr_lo += pwrb_arr[num].size;
  3163. num_wrb_rings--;
  3164. } else {
  3165. idx++;
  3166. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3167. pa_addr_lo = mem_descr->mem_array[idx].\
  3168. bus_address.u.a64.address;
  3169. num_wrb_rings = mem_descr->mem_array[idx].size /
  3170. (phba->params.wrbs_per_cxn *
  3171. sizeof(struct iscsi_wrb));
  3172. pwrb_arr[num].virtual_address = wrb_vaddr;
  3173. pwrb_arr[num].bus_address.u.a64.address\
  3174. = pa_addr_lo;
  3175. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3176. sizeof(struct iscsi_wrb);
  3177. wrb_vaddr += pwrb_arr[num].size;
  3178. pa_addr_lo += pwrb_arr[num].size;
  3179. num_wrb_rings--;
  3180. }
  3181. }
  3182. /* Get the ULP Count */
  3183. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
  3184. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3185. ulp_count++;
  3186. ulp_base_num = ulp_num;
  3187. cid_count_ulp[ulp_num] =
  3188. BEISCSI_GET_CID_COUNT(phba, ulp_num);
  3189. }
  3190. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3191. wrb_mem_index = 0;
  3192. offset = 0;
  3193. size = 0;
  3194. if (ulp_count > 1) {
  3195. ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
  3196. if (!cid_count_ulp[ulp_base_num])
  3197. ulp_base_num = (ulp_base_num + 1) %
  3198. BEISCSI_ULP_COUNT;
  3199. cid_count_ulp[ulp_base_num]--;
  3200. }
  3201. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  3202. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  3203. &phwi_context->be_wrbq[i],
  3204. &phwi_ctrlr->wrb_context[i],
  3205. ulp_base_num);
  3206. if (status != 0) {
  3207. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3208. "BM_%d : wrbq create failed.");
  3209. kfree(pwrb_arr);
  3210. return status;
  3211. }
  3212. pwrb_context = &phwi_ctrlr->wrb_context[i];
  3213. BE_SET_CID_TO_CRI(i, pwrb_context->cid);
  3214. }
  3215. kfree(pwrb_arr);
  3216. return 0;
  3217. }
  3218. static void free_wrb_handles(struct beiscsi_hba *phba)
  3219. {
  3220. unsigned int index;
  3221. struct hwi_controller *phwi_ctrlr;
  3222. struct hwi_wrb_context *pwrb_context;
  3223. phwi_ctrlr = phba->phwi_ctrlr;
  3224. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  3225. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3226. kfree(pwrb_context->pwrb_handle_base);
  3227. kfree(pwrb_context->pwrb_handle_basestd);
  3228. }
  3229. }
  3230. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3231. {
  3232. struct be_queue_info *q;
  3233. struct be_ctrl_info *ctrl = &phba->ctrl;
  3234. q = &phba->ctrl.mcc_obj.q;
  3235. if (q->created)
  3236. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3237. be_queue_free(phba, q);
  3238. q = &phba->ctrl.mcc_obj.cq;
  3239. if (q->created)
  3240. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3241. be_queue_free(phba, q);
  3242. }
  3243. static void hwi_cleanup(struct beiscsi_hba *phba)
  3244. {
  3245. struct be_queue_info *q;
  3246. struct be_ctrl_info *ctrl = &phba->ctrl;
  3247. struct hwi_controller *phwi_ctrlr;
  3248. struct hwi_context_memory *phwi_context;
  3249. struct hwi_async_pdu_context *pasync_ctx;
  3250. int i, eq_num, ulp_num;
  3251. phwi_ctrlr = phba->phwi_ctrlr;
  3252. phwi_context = phwi_ctrlr->phwi_ctxt;
  3253. be_cmd_iscsi_remove_template_hdr(ctrl);
  3254. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3255. q = &phwi_context->be_wrbq[i];
  3256. if (q->created)
  3257. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3258. }
  3259. kfree(phwi_context->be_wrbq);
  3260. free_wrb_handles(phba);
  3261. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3262. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3263. q = &phwi_context->be_def_hdrq[ulp_num];
  3264. if (q->created)
  3265. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3266. q = &phwi_context->be_def_dataq[ulp_num];
  3267. if (q->created)
  3268. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3269. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
  3270. }
  3271. }
  3272. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3273. for (i = 0; i < (phba->num_cpus); i++) {
  3274. q = &phwi_context->be_cq[i];
  3275. if (q->created)
  3276. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3277. }
  3278. if (phba->msix_enabled)
  3279. eq_num = 1;
  3280. else
  3281. eq_num = 0;
  3282. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3283. q = &phwi_context->be_eq[i].q;
  3284. if (q->created)
  3285. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3286. }
  3287. be_mcc_queues_destroy(phba);
  3288. be_cmd_fw_uninit(ctrl);
  3289. }
  3290. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3291. struct hwi_context_memory *phwi_context)
  3292. {
  3293. struct be_queue_info *q, *cq;
  3294. struct be_ctrl_info *ctrl = &phba->ctrl;
  3295. /* Alloc MCC compl queue */
  3296. cq = &phba->ctrl.mcc_obj.cq;
  3297. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3298. sizeof(struct be_mcc_compl)))
  3299. goto err;
  3300. /* Ask BE to create MCC compl queue; */
  3301. if (phba->msix_enabled) {
  3302. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3303. [phba->num_cpus].q, false, true, 0))
  3304. goto mcc_cq_free;
  3305. } else {
  3306. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3307. false, true, 0))
  3308. goto mcc_cq_free;
  3309. }
  3310. /* Alloc MCC queue */
  3311. q = &phba->ctrl.mcc_obj.q;
  3312. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3313. goto mcc_cq_destroy;
  3314. /* Ask BE to create MCC queue */
  3315. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3316. goto mcc_q_free;
  3317. return 0;
  3318. mcc_q_free:
  3319. be_queue_free(phba, q);
  3320. mcc_cq_destroy:
  3321. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3322. mcc_cq_free:
  3323. be_queue_free(phba, cq);
  3324. err:
  3325. return -ENOMEM;
  3326. }
  3327. /**
  3328. * find_num_cpus()- Get the CPU online count
  3329. * @phba: ptr to priv structure
  3330. *
  3331. * CPU count is used for creating EQ.
  3332. **/
  3333. static void find_num_cpus(struct beiscsi_hba *phba)
  3334. {
  3335. int num_cpus = 0;
  3336. num_cpus = num_online_cpus();
  3337. switch (phba->generation) {
  3338. case BE_GEN2:
  3339. case BE_GEN3:
  3340. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3341. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3342. break;
  3343. case BE_GEN4:
  3344. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3345. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3346. break;
  3347. default:
  3348. phba->num_cpus = 1;
  3349. }
  3350. }
  3351. static int hwi_init_port(struct beiscsi_hba *phba)
  3352. {
  3353. struct hwi_controller *phwi_ctrlr;
  3354. struct hwi_context_memory *phwi_context;
  3355. unsigned int def_pdu_ring_sz;
  3356. struct be_ctrl_info *ctrl = &phba->ctrl;
  3357. int status, ulp_num;
  3358. phwi_ctrlr = phba->phwi_ctrlr;
  3359. phwi_context = phwi_ctrlr->phwi_ctxt;
  3360. phwi_context->max_eqd = 0;
  3361. phwi_context->min_eqd = 0;
  3362. phwi_context->cur_eqd = 64;
  3363. be_cmd_fw_initialize(&phba->ctrl);
  3364. status = beiscsi_create_eqs(phba, phwi_context);
  3365. if (status != 0) {
  3366. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3367. "BM_%d : EQ not created\n");
  3368. goto error;
  3369. }
  3370. status = be_mcc_queues_create(phba, phwi_context);
  3371. if (status != 0)
  3372. goto error;
  3373. status = mgmt_check_supported_fw(ctrl, phba);
  3374. if (status != 0) {
  3375. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3376. "BM_%d : Unsupported fw version\n");
  3377. goto error;
  3378. }
  3379. status = beiscsi_create_cqs(phba, phwi_context);
  3380. if (status != 0) {
  3381. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3382. "BM_%d : CQ not created\n");
  3383. goto error;
  3384. }
  3385. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3386. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3387. def_pdu_ring_sz =
  3388. BEISCSI_GET_CID_COUNT(phba, ulp_num) *
  3389. sizeof(struct phys_addr);
  3390. status = beiscsi_create_def_hdr(phba, phwi_context,
  3391. phwi_ctrlr,
  3392. def_pdu_ring_sz,
  3393. ulp_num);
  3394. if (status != 0) {
  3395. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3396. "BM_%d : Default Header not created for ULP : %d\n",
  3397. ulp_num);
  3398. goto error;
  3399. }
  3400. status = beiscsi_create_def_data(phba, phwi_context,
  3401. phwi_ctrlr,
  3402. def_pdu_ring_sz,
  3403. ulp_num);
  3404. if (status != 0) {
  3405. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3406. "BM_%d : Default Data not created for ULP : %d\n",
  3407. ulp_num);
  3408. goto error;
  3409. }
  3410. }
  3411. }
  3412. status = beiscsi_post_pages(phba);
  3413. if (status != 0) {
  3414. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3415. "BM_%d : Post SGL Pages Failed\n");
  3416. goto error;
  3417. }
  3418. status = beiscsi_post_template_hdr(phba);
  3419. if (status != 0) {
  3420. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3421. "BM_%d : Template HDR Posting for CXN Failed\n");
  3422. }
  3423. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3424. if (status != 0) {
  3425. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3426. "BM_%d : WRB Rings not created\n");
  3427. goto error;
  3428. }
  3429. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3430. uint16_t async_arr_idx = 0;
  3431. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  3432. uint16_t cri = 0;
  3433. struct hwi_async_pdu_context *pasync_ctx;
  3434. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
  3435. phwi_ctrlr, ulp_num);
  3436. for (cri = 0; cri <
  3437. phba->params.cxns_per_ctrl; cri++) {
  3438. if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
  3439. (phwi_ctrlr, cri))
  3440. pasync_ctx->cid_to_async_cri_map[
  3441. phwi_ctrlr->wrb_context[cri].cid] =
  3442. async_arr_idx++;
  3443. }
  3444. }
  3445. }
  3446. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3447. "BM_%d : hwi_init_port success\n");
  3448. return 0;
  3449. error:
  3450. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3451. "BM_%d : hwi_init_port failed");
  3452. hwi_cleanup(phba);
  3453. return status;
  3454. }
  3455. static int hwi_init_controller(struct beiscsi_hba *phba)
  3456. {
  3457. struct hwi_controller *phwi_ctrlr;
  3458. phwi_ctrlr = phba->phwi_ctrlr;
  3459. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3460. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3461. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3462. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3463. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3464. phwi_ctrlr->phwi_ctxt);
  3465. } else {
  3466. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3467. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3468. "than one element.Failing to load\n");
  3469. return -ENOMEM;
  3470. }
  3471. iscsi_init_global_templates(phba);
  3472. if (beiscsi_init_wrb_handle(phba))
  3473. return -ENOMEM;
  3474. if (hwi_init_async_pdu_ctx(phba)) {
  3475. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3476. "BM_%d : hwi_init_async_pdu_ctx failed\n");
  3477. return -ENOMEM;
  3478. }
  3479. if (hwi_init_port(phba) != 0) {
  3480. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3481. "BM_%d : hwi_init_controller failed\n");
  3482. return -ENOMEM;
  3483. }
  3484. return 0;
  3485. }
  3486. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3487. {
  3488. struct be_mem_descriptor *mem_descr;
  3489. int i, j;
  3490. mem_descr = phba->init_mem;
  3491. i = 0;
  3492. j = 0;
  3493. for (i = 0; i < SE_MEM_MAX; i++) {
  3494. for (j = mem_descr->num_elements; j > 0; j--) {
  3495. pci_free_consistent(phba->pcidev,
  3496. mem_descr->mem_array[j - 1].size,
  3497. mem_descr->mem_array[j - 1].virtual_address,
  3498. (unsigned long)mem_descr->mem_array[j - 1].
  3499. bus_address.u.a64.address);
  3500. }
  3501. kfree(mem_descr->mem_array);
  3502. mem_descr++;
  3503. }
  3504. kfree(phba->init_mem);
  3505. kfree(phba->phwi_ctrlr->wrb_context);
  3506. kfree(phba->phwi_ctrlr);
  3507. }
  3508. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3509. {
  3510. int ret = -ENOMEM;
  3511. ret = beiscsi_get_memory(phba);
  3512. if (ret < 0) {
  3513. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3514. "BM_%d : beiscsi_dev_probe -"
  3515. "Failed in beiscsi_alloc_memory\n");
  3516. return ret;
  3517. }
  3518. ret = hwi_init_controller(phba);
  3519. if (ret)
  3520. goto free_init;
  3521. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3522. "BM_%d : Return success from beiscsi_init_controller");
  3523. return 0;
  3524. free_init:
  3525. beiscsi_free_mem(phba);
  3526. return ret;
  3527. }
  3528. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3529. {
  3530. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3531. struct sgl_handle *psgl_handle;
  3532. struct iscsi_sge *pfrag;
  3533. unsigned int arr_index, i, idx;
  3534. unsigned int ulp_icd_start, ulp_num = 0;
  3535. phba->io_sgl_hndl_avbl = 0;
  3536. phba->eh_sgl_hndl_avbl = 0;
  3537. mem_descr_sglh = phba->init_mem;
  3538. mem_descr_sglh += HWI_MEM_SGLH;
  3539. if (1 == mem_descr_sglh->num_elements) {
  3540. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3541. phba->params.ios_per_ctrl,
  3542. GFP_KERNEL);
  3543. if (!phba->io_sgl_hndl_base) {
  3544. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3545. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3546. return -ENOMEM;
  3547. }
  3548. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3549. (phba->params.icds_per_ctrl -
  3550. phba->params.ios_per_ctrl),
  3551. GFP_KERNEL);
  3552. if (!phba->eh_sgl_hndl_base) {
  3553. kfree(phba->io_sgl_hndl_base);
  3554. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3555. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3556. return -ENOMEM;
  3557. }
  3558. } else {
  3559. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3560. "BM_%d : HWI_MEM_SGLH is more than one element."
  3561. "Failing to load\n");
  3562. return -ENOMEM;
  3563. }
  3564. arr_index = 0;
  3565. idx = 0;
  3566. while (idx < mem_descr_sglh->num_elements) {
  3567. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3568. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3569. sizeof(struct sgl_handle)); i++) {
  3570. if (arr_index < phba->params.ios_per_ctrl) {
  3571. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3572. phba->io_sgl_hndl_avbl++;
  3573. arr_index++;
  3574. } else {
  3575. phba->eh_sgl_hndl_base[arr_index -
  3576. phba->params.ios_per_ctrl] =
  3577. psgl_handle;
  3578. arr_index++;
  3579. phba->eh_sgl_hndl_avbl++;
  3580. }
  3581. psgl_handle++;
  3582. }
  3583. idx++;
  3584. }
  3585. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3586. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3587. "phba->eh_sgl_hndl_avbl=%d\n",
  3588. phba->io_sgl_hndl_avbl,
  3589. phba->eh_sgl_hndl_avbl);
  3590. mem_descr_sg = phba->init_mem;
  3591. mem_descr_sg += HWI_MEM_SGE;
  3592. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3593. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3594. mem_descr_sg->num_elements);
  3595. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
  3596. if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
  3597. break;
  3598. ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
  3599. arr_index = 0;
  3600. idx = 0;
  3601. while (idx < mem_descr_sg->num_elements) {
  3602. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3603. for (i = 0;
  3604. i < (mem_descr_sg->mem_array[idx].size) /
  3605. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3606. i++) {
  3607. if (arr_index < phba->params.ios_per_ctrl)
  3608. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3609. else
  3610. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3611. phba->params.ios_per_ctrl];
  3612. psgl_handle->pfrag = pfrag;
  3613. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3614. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3615. pfrag += phba->params.num_sge_per_io;
  3616. psgl_handle->sgl_index = ulp_icd_start + arr_index++;
  3617. }
  3618. idx++;
  3619. }
  3620. phba->io_sgl_free_index = 0;
  3621. phba->io_sgl_alloc_index = 0;
  3622. phba->eh_sgl_free_index = 0;
  3623. phba->eh_sgl_alloc_index = 0;
  3624. return 0;
  3625. }
  3626. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3627. {
  3628. int ret;
  3629. uint16_t i, ulp_num;
  3630. struct ulp_cid_info *ptr_cid_info = NULL;
  3631. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3632. if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
  3633. ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
  3634. GFP_KERNEL);
  3635. if (!ptr_cid_info) {
  3636. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3637. "BM_%d : Failed to allocate memory"
  3638. "for ULP_CID_INFO for ULP : %d\n",
  3639. ulp_num);
  3640. ret = -ENOMEM;
  3641. goto free_memory;
  3642. }
  3643. /* Allocate memory for CID array */
  3644. ptr_cid_info->cid_array = kzalloc(sizeof(void *) *
  3645. BEISCSI_GET_CID_COUNT(phba,
  3646. ulp_num), GFP_KERNEL);
  3647. if (!ptr_cid_info->cid_array) {
  3648. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3649. "BM_%d : Failed to allocate memory"
  3650. "for CID_ARRAY for ULP : %d\n",
  3651. ulp_num);
  3652. kfree(ptr_cid_info);
  3653. ptr_cid_info = NULL;
  3654. ret = -ENOMEM;
  3655. goto free_memory;
  3656. }
  3657. ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
  3658. phba, ulp_num);
  3659. /* Save the cid_info_array ptr */
  3660. phba->cid_array_info[ulp_num] = ptr_cid_info;
  3661. }
  3662. }
  3663. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3664. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3665. if (!phba->ep_array) {
  3666. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3667. "BM_%d : Failed to allocate memory in "
  3668. "hba_setup_cid_tbls\n");
  3669. ret = -ENOMEM;
  3670. goto free_memory;
  3671. }
  3672. phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
  3673. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3674. if (!phba->conn_table) {
  3675. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3676. "BM_%d : Failed to allocate memory in"
  3677. "hba_setup_cid_tbls\n");
  3678. kfree(phba->ep_array);
  3679. phba->ep_array = NULL;
  3680. ret = -ENOMEM;
  3681. }
  3682. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3683. ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
  3684. ptr_cid_info = phba->cid_array_info[ulp_num];
  3685. ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
  3686. phba->phwi_ctrlr->wrb_context[i].cid;
  3687. }
  3688. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3689. if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
  3690. ptr_cid_info = phba->cid_array_info[ulp_num];
  3691. ptr_cid_info->cid_alloc = 0;
  3692. ptr_cid_info->cid_free = 0;
  3693. }
  3694. }
  3695. return 0;
  3696. free_memory:
  3697. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3698. if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
  3699. ptr_cid_info = phba->cid_array_info[ulp_num];
  3700. if (ptr_cid_info) {
  3701. kfree(ptr_cid_info->cid_array);
  3702. kfree(ptr_cid_info);
  3703. phba->cid_array_info[ulp_num] = NULL;
  3704. }
  3705. }
  3706. }
  3707. return ret;
  3708. }
  3709. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3710. {
  3711. struct be_ctrl_info *ctrl = &phba->ctrl;
  3712. struct hwi_controller *phwi_ctrlr;
  3713. struct hwi_context_memory *phwi_context;
  3714. struct be_queue_info *eq;
  3715. u8 __iomem *addr;
  3716. u32 reg, i;
  3717. u32 enabled;
  3718. phwi_ctrlr = phba->phwi_ctrlr;
  3719. phwi_context = phwi_ctrlr->phwi_ctxt;
  3720. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3721. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3722. reg = ioread32(addr);
  3723. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3724. if (!enabled) {
  3725. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3726. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3727. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3728. iowrite32(reg, addr);
  3729. }
  3730. if (!phba->msix_enabled) {
  3731. eq = &phwi_context->be_eq[0].q;
  3732. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3733. "BM_%d : eq->id=%d\n", eq->id);
  3734. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3735. } else {
  3736. for (i = 0; i <= phba->num_cpus; i++) {
  3737. eq = &phwi_context->be_eq[i].q;
  3738. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3739. "BM_%d : eq->id=%d\n", eq->id);
  3740. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3741. }
  3742. }
  3743. }
  3744. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3745. {
  3746. struct be_ctrl_info *ctrl = &phba->ctrl;
  3747. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3748. u32 reg = ioread32(addr);
  3749. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3750. if (enabled) {
  3751. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3752. iowrite32(reg, addr);
  3753. } else
  3754. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3755. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3756. }
  3757. /**
  3758. * beiscsi_get_boot_info()- Get the boot session info
  3759. * @phba: The device priv structure instance
  3760. *
  3761. * Get the boot target info and store in driver priv structure
  3762. *
  3763. * return values
  3764. * Success: 0
  3765. * Failure: Non-Zero Value
  3766. **/
  3767. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3768. {
  3769. struct be_cmd_get_session_resp *session_resp;
  3770. struct be_dma_mem nonemb_cmd;
  3771. unsigned int tag;
  3772. unsigned int s_handle;
  3773. int ret = -ENOMEM;
  3774. /* Get the session handle of the boot target */
  3775. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3776. if (ret) {
  3777. beiscsi_log(phba, KERN_ERR,
  3778. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3779. "BM_%d : No boot session\n");
  3780. return ret;
  3781. }
  3782. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3783. sizeof(*session_resp),
  3784. &nonemb_cmd.dma);
  3785. if (nonemb_cmd.va == NULL) {
  3786. beiscsi_log(phba, KERN_ERR,
  3787. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3788. "BM_%d : Failed to allocate memory for"
  3789. "beiscsi_get_session_info\n");
  3790. return -ENOMEM;
  3791. }
  3792. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3793. tag = mgmt_get_session_info(phba, s_handle,
  3794. &nonemb_cmd);
  3795. if (!tag) {
  3796. beiscsi_log(phba, KERN_ERR,
  3797. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3798. "BM_%d : beiscsi_get_session_info"
  3799. " Failed\n");
  3800. goto boot_freemem;
  3801. }
  3802. ret = beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  3803. if (ret) {
  3804. beiscsi_log(phba, KERN_ERR,
  3805. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3806. "BM_%d : beiscsi_get_session_info Failed");
  3807. goto boot_freemem;
  3808. }
  3809. session_resp = nonemb_cmd.va ;
  3810. memcpy(&phba->boot_sess, &session_resp->session_info,
  3811. sizeof(struct mgmt_session_info));
  3812. ret = 0;
  3813. boot_freemem:
  3814. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3815. nonemb_cmd.va, nonemb_cmd.dma);
  3816. return ret;
  3817. }
  3818. static void beiscsi_boot_release(void *data)
  3819. {
  3820. struct beiscsi_hba *phba = data;
  3821. scsi_host_put(phba->shost);
  3822. }
  3823. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3824. {
  3825. struct iscsi_boot_kobj *boot_kobj;
  3826. /* get boot info using mgmt cmd */
  3827. if (beiscsi_get_boot_info(phba))
  3828. /* Try to see if we can carry on without this */
  3829. return 0;
  3830. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3831. if (!phba->boot_kset)
  3832. return -ENOMEM;
  3833. /* get a ref because the show function will ref the phba */
  3834. if (!scsi_host_get(phba->shost))
  3835. goto free_kset;
  3836. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3837. beiscsi_show_boot_tgt_info,
  3838. beiscsi_tgt_get_attr_visibility,
  3839. beiscsi_boot_release);
  3840. if (!boot_kobj)
  3841. goto put_shost;
  3842. if (!scsi_host_get(phba->shost))
  3843. goto free_kset;
  3844. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3845. beiscsi_show_boot_ini_info,
  3846. beiscsi_ini_get_attr_visibility,
  3847. beiscsi_boot_release);
  3848. if (!boot_kobj)
  3849. goto put_shost;
  3850. if (!scsi_host_get(phba->shost))
  3851. goto free_kset;
  3852. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3853. beiscsi_show_boot_eth_info,
  3854. beiscsi_eth_get_attr_visibility,
  3855. beiscsi_boot_release);
  3856. if (!boot_kobj)
  3857. goto put_shost;
  3858. return 0;
  3859. put_shost:
  3860. scsi_host_put(phba->shost);
  3861. free_kset:
  3862. iscsi_boot_destroy_kset(phba->boot_kset);
  3863. return -ENOMEM;
  3864. }
  3865. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3866. {
  3867. int ret;
  3868. ret = beiscsi_init_controller(phba);
  3869. if (ret < 0) {
  3870. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3871. "BM_%d : beiscsi_dev_probe - Failed in"
  3872. "beiscsi_init_controller\n");
  3873. return ret;
  3874. }
  3875. ret = beiscsi_init_sgl_handle(phba);
  3876. if (ret < 0) {
  3877. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3878. "BM_%d : beiscsi_dev_probe - Failed in"
  3879. "beiscsi_init_sgl_handle\n");
  3880. goto do_cleanup_ctrlr;
  3881. }
  3882. if (hba_setup_cid_tbls(phba)) {
  3883. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3884. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3885. kfree(phba->io_sgl_hndl_base);
  3886. kfree(phba->eh_sgl_hndl_base);
  3887. goto do_cleanup_ctrlr;
  3888. }
  3889. return ret;
  3890. do_cleanup_ctrlr:
  3891. hwi_cleanup(phba);
  3892. return ret;
  3893. }
  3894. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3895. {
  3896. struct hwi_controller *phwi_ctrlr;
  3897. struct hwi_context_memory *phwi_context;
  3898. struct be_queue_info *eq;
  3899. struct be_eq_entry *eqe = NULL;
  3900. int i, eq_msix;
  3901. unsigned int num_processed;
  3902. phwi_ctrlr = phba->phwi_ctrlr;
  3903. phwi_context = phwi_ctrlr->phwi_ctxt;
  3904. if (phba->msix_enabled)
  3905. eq_msix = 1;
  3906. else
  3907. eq_msix = 0;
  3908. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3909. eq = &phwi_context->be_eq[i].q;
  3910. eqe = queue_tail_node(eq);
  3911. num_processed = 0;
  3912. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3913. & EQE_VALID_MASK) {
  3914. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3915. queue_tail_inc(eq);
  3916. eqe = queue_tail_node(eq);
  3917. num_processed++;
  3918. }
  3919. if (num_processed)
  3920. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3921. }
  3922. }
  3923. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3924. {
  3925. int mgmt_status, ulp_num;
  3926. struct ulp_cid_info *ptr_cid_info = NULL;
  3927. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3928. if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
  3929. mgmt_status = mgmt_epfw_cleanup(phba, ulp_num);
  3930. if (mgmt_status)
  3931. beiscsi_log(phba, KERN_WARNING,
  3932. BEISCSI_LOG_INIT,
  3933. "BM_%d : mgmt_epfw_cleanup FAILED"
  3934. " for ULP_%d\n", ulp_num);
  3935. }
  3936. }
  3937. hwi_purge_eq(phba);
  3938. hwi_cleanup(phba);
  3939. kfree(phba->io_sgl_hndl_base);
  3940. kfree(phba->eh_sgl_hndl_base);
  3941. kfree(phba->ep_array);
  3942. kfree(phba->conn_table);
  3943. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
  3944. if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
  3945. ptr_cid_info = phba->cid_array_info[ulp_num];
  3946. if (ptr_cid_info) {
  3947. kfree(ptr_cid_info->cid_array);
  3948. kfree(ptr_cid_info);
  3949. phba->cid_array_info[ulp_num] = NULL;
  3950. }
  3951. }
  3952. }
  3953. }
  3954. /**
  3955. * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
  3956. * @beiscsi_conn: ptr to the conn to be cleaned up
  3957. * @task: ptr to iscsi_task resource to be freed.
  3958. *
  3959. * Free driver mgmt resources binded to CXN.
  3960. **/
  3961. void
  3962. beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
  3963. struct iscsi_task *task)
  3964. {
  3965. struct beiscsi_io_task *io_task;
  3966. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3967. struct hwi_wrb_context *pwrb_context;
  3968. struct hwi_controller *phwi_ctrlr;
  3969. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3970. beiscsi_conn->beiscsi_conn_cid);
  3971. phwi_ctrlr = phba->phwi_ctrlr;
  3972. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3973. io_task = task->dd_data;
  3974. if (io_task->pwrb_handle) {
  3975. memset(io_task->pwrb_handle->pwrb, 0,
  3976. sizeof(struct iscsi_wrb));
  3977. free_wrb_handle(phba, pwrb_context,
  3978. io_task->pwrb_handle);
  3979. io_task->pwrb_handle = NULL;
  3980. }
  3981. if (io_task->psgl_handle) {
  3982. spin_lock_bh(&phba->mgmt_sgl_lock);
  3983. free_mgmt_sgl_handle(phba,
  3984. io_task->psgl_handle);
  3985. io_task->psgl_handle = NULL;
  3986. spin_unlock_bh(&phba->mgmt_sgl_lock);
  3987. }
  3988. if (io_task->mtask_addr)
  3989. pci_unmap_single(phba->pcidev,
  3990. io_task->mtask_addr,
  3991. io_task->mtask_data_count,
  3992. PCI_DMA_TODEVICE);
  3993. }
  3994. /**
  3995. * beiscsi_cleanup_task()- Free driver resources of the task
  3996. * @task: ptr to the iscsi task
  3997. *
  3998. **/
  3999. static void beiscsi_cleanup_task(struct iscsi_task *task)
  4000. {
  4001. struct beiscsi_io_task *io_task = task->dd_data;
  4002. struct iscsi_conn *conn = task->conn;
  4003. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4004. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4005. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  4006. struct hwi_wrb_context *pwrb_context;
  4007. struct hwi_controller *phwi_ctrlr;
  4008. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  4009. beiscsi_conn->beiscsi_conn_cid);
  4010. phwi_ctrlr = phba->phwi_ctrlr;
  4011. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  4012. if (io_task->cmd_bhs) {
  4013. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  4014. io_task->bhs_pa.u.a64.address);
  4015. io_task->cmd_bhs = NULL;
  4016. }
  4017. if (task->sc) {
  4018. if (io_task->pwrb_handle) {
  4019. free_wrb_handle(phba, pwrb_context,
  4020. io_task->pwrb_handle);
  4021. io_task->pwrb_handle = NULL;
  4022. }
  4023. if (io_task->psgl_handle) {
  4024. spin_lock(&phba->io_sgl_lock);
  4025. free_io_sgl_handle(phba, io_task->psgl_handle);
  4026. spin_unlock(&phba->io_sgl_lock);
  4027. io_task->psgl_handle = NULL;
  4028. }
  4029. } else {
  4030. if (!beiscsi_conn->login_in_progress)
  4031. beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
  4032. }
  4033. }
  4034. void
  4035. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  4036. struct beiscsi_offload_params *params)
  4037. {
  4038. struct wrb_handle *pwrb_handle;
  4039. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4040. struct iscsi_task *task = beiscsi_conn->task;
  4041. struct iscsi_session *session = task->conn->session;
  4042. u32 doorbell = 0;
  4043. /*
  4044. * We can always use 0 here because it is reserved by libiscsi for
  4045. * login/startup related tasks.
  4046. */
  4047. beiscsi_conn->login_in_progress = 0;
  4048. spin_lock_bh(&session->lock);
  4049. beiscsi_cleanup_task(task);
  4050. spin_unlock_bh(&session->lock);
  4051. pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid);
  4052. /* Check for the adapter family */
  4053. if (is_chip_be2_be3r(phba))
  4054. beiscsi_offload_cxn_v0(params, pwrb_handle,
  4055. phba->init_mem);
  4056. else
  4057. beiscsi_offload_cxn_v2(params, pwrb_handle);
  4058. be_dws_le_to_cpu(pwrb_handle->pwrb,
  4059. sizeof(struct iscsi_target_context_update_wrb));
  4060. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4061. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  4062. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4063. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4064. iowrite32(doorbell, phba->db_va +
  4065. beiscsi_conn->doorbell_offset);
  4066. }
  4067. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  4068. int *index, int *age)
  4069. {
  4070. *index = (int)itt;
  4071. if (age)
  4072. *age = conn->session->age;
  4073. }
  4074. /**
  4075. * beiscsi_alloc_pdu - allocates pdu and related resources
  4076. * @task: libiscsi task
  4077. * @opcode: opcode of pdu for task
  4078. *
  4079. * This is called with the session lock held. It will allocate
  4080. * the wrb and sgl if needed for the command. And it will prep
  4081. * the pdu's itt. beiscsi_parse_pdu will later translate
  4082. * the pdu itt to the libiscsi task itt.
  4083. */
  4084. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  4085. {
  4086. struct beiscsi_io_task *io_task = task->dd_data;
  4087. struct iscsi_conn *conn = task->conn;
  4088. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4089. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4090. struct hwi_wrb_context *pwrb_context;
  4091. struct hwi_controller *phwi_ctrlr;
  4092. itt_t itt;
  4093. uint16_t cri_index = 0;
  4094. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  4095. dma_addr_t paddr;
  4096. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  4097. GFP_ATOMIC, &paddr);
  4098. if (!io_task->cmd_bhs)
  4099. return -ENOMEM;
  4100. io_task->bhs_pa.u.a64.address = paddr;
  4101. io_task->libiscsi_itt = (itt_t)task->itt;
  4102. io_task->conn = beiscsi_conn;
  4103. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  4104. task->hdr_max = sizeof(struct be_cmd_bhs);
  4105. io_task->psgl_handle = NULL;
  4106. io_task->pwrb_handle = NULL;
  4107. if (task->sc) {
  4108. spin_lock(&phba->io_sgl_lock);
  4109. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  4110. spin_unlock(&phba->io_sgl_lock);
  4111. if (!io_task->psgl_handle) {
  4112. beiscsi_log(phba, KERN_ERR,
  4113. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  4114. "BM_%d : Alloc of IO_SGL_ICD Failed"
  4115. "for the CID : %d\n",
  4116. beiscsi_conn->beiscsi_conn_cid);
  4117. goto free_hndls;
  4118. }
  4119. io_task->pwrb_handle = alloc_wrb_handle(phba,
  4120. beiscsi_conn->beiscsi_conn_cid);
  4121. if (!io_task->pwrb_handle) {
  4122. beiscsi_log(phba, KERN_ERR,
  4123. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  4124. "BM_%d : Alloc of WRB_HANDLE Failed"
  4125. "for the CID : %d\n",
  4126. beiscsi_conn->beiscsi_conn_cid);
  4127. goto free_io_hndls;
  4128. }
  4129. } else {
  4130. io_task->scsi_cmnd = NULL;
  4131. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  4132. beiscsi_conn->task = task;
  4133. if (!beiscsi_conn->login_in_progress) {
  4134. spin_lock(&phba->mgmt_sgl_lock);
  4135. io_task->psgl_handle = (struct sgl_handle *)
  4136. alloc_mgmt_sgl_handle(phba);
  4137. spin_unlock(&phba->mgmt_sgl_lock);
  4138. if (!io_task->psgl_handle) {
  4139. beiscsi_log(phba, KERN_ERR,
  4140. BEISCSI_LOG_IO |
  4141. BEISCSI_LOG_CONFIG,
  4142. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  4143. "for the CID : %d\n",
  4144. beiscsi_conn->
  4145. beiscsi_conn_cid);
  4146. goto free_hndls;
  4147. }
  4148. beiscsi_conn->login_in_progress = 1;
  4149. beiscsi_conn->plogin_sgl_handle =
  4150. io_task->psgl_handle;
  4151. io_task->pwrb_handle =
  4152. alloc_wrb_handle(phba,
  4153. beiscsi_conn->beiscsi_conn_cid);
  4154. if (!io_task->pwrb_handle) {
  4155. beiscsi_log(phba, KERN_ERR,
  4156. BEISCSI_LOG_IO |
  4157. BEISCSI_LOG_CONFIG,
  4158. "BM_%d : Alloc of WRB_HANDLE Failed"
  4159. "for the CID : %d\n",
  4160. beiscsi_conn->
  4161. beiscsi_conn_cid);
  4162. goto free_mgmt_hndls;
  4163. }
  4164. beiscsi_conn->plogin_wrb_handle =
  4165. io_task->pwrb_handle;
  4166. } else {
  4167. io_task->psgl_handle =
  4168. beiscsi_conn->plogin_sgl_handle;
  4169. io_task->pwrb_handle =
  4170. beiscsi_conn->plogin_wrb_handle;
  4171. }
  4172. } else {
  4173. spin_lock(&phba->mgmt_sgl_lock);
  4174. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  4175. spin_unlock(&phba->mgmt_sgl_lock);
  4176. if (!io_task->psgl_handle) {
  4177. beiscsi_log(phba, KERN_ERR,
  4178. BEISCSI_LOG_IO |
  4179. BEISCSI_LOG_CONFIG,
  4180. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  4181. "for the CID : %d\n",
  4182. beiscsi_conn->
  4183. beiscsi_conn_cid);
  4184. goto free_hndls;
  4185. }
  4186. io_task->pwrb_handle =
  4187. alloc_wrb_handle(phba,
  4188. beiscsi_conn->beiscsi_conn_cid);
  4189. if (!io_task->pwrb_handle) {
  4190. beiscsi_log(phba, KERN_ERR,
  4191. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  4192. "BM_%d : Alloc of WRB_HANDLE Failed"
  4193. "for the CID : %d\n",
  4194. beiscsi_conn->beiscsi_conn_cid);
  4195. goto free_mgmt_hndls;
  4196. }
  4197. }
  4198. }
  4199. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  4200. wrb_index << 16) | (unsigned int)
  4201. (io_task->psgl_handle->sgl_index));
  4202. io_task->pwrb_handle->pio_handle = task;
  4203. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  4204. return 0;
  4205. free_io_hndls:
  4206. spin_lock(&phba->io_sgl_lock);
  4207. free_io_sgl_handle(phba, io_task->psgl_handle);
  4208. spin_unlock(&phba->io_sgl_lock);
  4209. goto free_hndls;
  4210. free_mgmt_hndls:
  4211. spin_lock(&phba->mgmt_sgl_lock);
  4212. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  4213. io_task->psgl_handle = NULL;
  4214. spin_unlock(&phba->mgmt_sgl_lock);
  4215. free_hndls:
  4216. phwi_ctrlr = phba->phwi_ctrlr;
  4217. cri_index = BE_GET_CRI_FROM_CID(
  4218. beiscsi_conn->beiscsi_conn_cid);
  4219. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  4220. if (io_task->pwrb_handle)
  4221. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  4222. io_task->pwrb_handle = NULL;
  4223. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  4224. io_task->bhs_pa.u.a64.address);
  4225. io_task->cmd_bhs = NULL;
  4226. return -ENOMEM;
  4227. }
  4228. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  4229. unsigned int num_sg, unsigned int xferlen,
  4230. unsigned int writedir)
  4231. {
  4232. struct beiscsi_io_task *io_task = task->dd_data;
  4233. struct iscsi_conn *conn = task->conn;
  4234. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4235. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4236. struct iscsi_wrb *pwrb = NULL;
  4237. unsigned int doorbell = 0;
  4238. pwrb = io_task->pwrb_handle->pwrb;
  4239. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4240. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4241. if (writedir) {
  4242. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  4243. INI_WR_CMD);
  4244. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  4245. } else {
  4246. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  4247. INI_RD_CMD);
  4248. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  4249. }
  4250. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  4251. type, pwrb);
  4252. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  4253. cpu_to_be16(*(unsigned short *)
  4254. &io_task->cmd_bhs->iscsi_hdr.lun));
  4255. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  4256. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4257. io_task->pwrb_handle->wrb_index);
  4258. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4259. be32_to_cpu(task->cmdsn));
  4260. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4261. io_task->psgl_handle->sgl_index);
  4262. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  4263. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4264. io_task->pwrb_handle->nxt_wrb_index);
  4265. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4266. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4267. doorbell |= (io_task->pwrb_handle->wrb_index &
  4268. DB_DEF_PDU_WRB_INDEX_MASK) <<
  4269. DB_DEF_PDU_WRB_INDEX_SHIFT;
  4270. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4271. iowrite32(doorbell, phba->db_va +
  4272. beiscsi_conn->doorbell_offset);
  4273. return 0;
  4274. }
  4275. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  4276. unsigned int num_sg, unsigned int xferlen,
  4277. unsigned int writedir)
  4278. {
  4279. struct beiscsi_io_task *io_task = task->dd_data;
  4280. struct iscsi_conn *conn = task->conn;
  4281. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4282. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4283. struct iscsi_wrb *pwrb = NULL;
  4284. unsigned int doorbell = 0;
  4285. pwrb = io_task->pwrb_handle->pwrb;
  4286. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4287. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4288. if (writedir) {
  4289. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4290. INI_WR_CMD);
  4291. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  4292. } else {
  4293. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4294. INI_RD_CMD);
  4295. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  4296. }
  4297. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  4298. type, pwrb);
  4299. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  4300. cpu_to_be16(*(unsigned short *)
  4301. &io_task->cmd_bhs->iscsi_hdr.lun));
  4302. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  4303. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4304. io_task->pwrb_handle->wrb_index);
  4305. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4306. be32_to_cpu(task->cmdsn));
  4307. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4308. io_task->psgl_handle->sgl_index);
  4309. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  4310. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4311. io_task->pwrb_handle->nxt_wrb_index);
  4312. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4313. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4314. doorbell |= (io_task->pwrb_handle->wrb_index &
  4315. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4316. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4317. iowrite32(doorbell, phba->db_va +
  4318. beiscsi_conn->doorbell_offset);
  4319. return 0;
  4320. }
  4321. static int beiscsi_mtask(struct iscsi_task *task)
  4322. {
  4323. struct beiscsi_io_task *io_task = task->dd_data;
  4324. struct iscsi_conn *conn = task->conn;
  4325. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4326. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4327. struct iscsi_wrb *pwrb = NULL;
  4328. unsigned int doorbell = 0;
  4329. unsigned int cid;
  4330. unsigned int pwrb_typeoffset = 0;
  4331. cid = beiscsi_conn->beiscsi_conn_cid;
  4332. pwrb = io_task->pwrb_handle->pwrb;
  4333. memset(pwrb, 0, sizeof(*pwrb));
  4334. if (is_chip_be2_be3r(phba)) {
  4335. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4336. be32_to_cpu(task->cmdsn));
  4337. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4338. io_task->pwrb_handle->wrb_index);
  4339. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4340. io_task->psgl_handle->sgl_index);
  4341. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  4342. task->data_count);
  4343. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4344. io_task->pwrb_handle->nxt_wrb_index);
  4345. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  4346. } else {
  4347. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4348. be32_to_cpu(task->cmdsn));
  4349. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4350. io_task->pwrb_handle->wrb_index);
  4351. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4352. io_task->psgl_handle->sgl_index);
  4353. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  4354. task->data_count);
  4355. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4356. io_task->pwrb_handle->nxt_wrb_index);
  4357. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  4358. }
  4359. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  4360. case ISCSI_OP_LOGIN:
  4361. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4362. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4363. hwi_write_buffer(pwrb, task);
  4364. break;
  4365. case ISCSI_OP_NOOP_OUT:
  4366. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4367. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4368. if (is_chip_be2_be3r(phba))
  4369. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4370. dmsg, pwrb, 1);
  4371. else
  4372. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4373. dmsg, pwrb, 1);
  4374. } else {
  4375. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4376. if (is_chip_be2_be3r(phba))
  4377. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4378. dmsg, pwrb, 0);
  4379. else
  4380. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4381. dmsg, pwrb, 0);
  4382. }
  4383. hwi_write_buffer(pwrb, task);
  4384. break;
  4385. case ISCSI_OP_TEXT:
  4386. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4387. hwi_write_buffer(pwrb, task);
  4388. break;
  4389. case ISCSI_OP_SCSI_TMFUNC:
  4390. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4391. hwi_write_buffer(pwrb, task);
  4392. break;
  4393. case ISCSI_OP_LOGOUT:
  4394. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4395. hwi_write_buffer(pwrb, task);
  4396. break;
  4397. default:
  4398. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4399. "BM_%d : opcode =%d Not supported\n",
  4400. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4401. return -EINVAL;
  4402. }
  4403. /* Set the task type */
  4404. io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
  4405. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
  4406. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
  4407. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4408. doorbell |= (io_task->pwrb_handle->wrb_index &
  4409. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4410. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4411. iowrite32(doorbell, phba->db_va +
  4412. beiscsi_conn->doorbell_offset);
  4413. return 0;
  4414. }
  4415. static int beiscsi_task_xmit(struct iscsi_task *task)
  4416. {
  4417. struct beiscsi_io_task *io_task = task->dd_data;
  4418. struct scsi_cmnd *sc = task->sc;
  4419. struct beiscsi_hba *phba = NULL;
  4420. struct scatterlist *sg;
  4421. int num_sg;
  4422. unsigned int writedir = 0, xferlen = 0;
  4423. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4424. if (!sc)
  4425. return beiscsi_mtask(task);
  4426. io_task->scsi_cmnd = sc;
  4427. num_sg = scsi_dma_map(sc);
  4428. if (num_sg < 0) {
  4429. struct iscsi_conn *conn = task->conn;
  4430. struct beiscsi_hba *phba = NULL;
  4431. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4432. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4433. "BM_%d : scsi_dma_map Failed\n");
  4434. return num_sg;
  4435. }
  4436. xferlen = scsi_bufflen(sc);
  4437. sg = scsi_sglist(sc);
  4438. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4439. writedir = 1;
  4440. else
  4441. writedir = 0;
  4442. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4443. }
  4444. /**
  4445. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4446. * @job: job to handle
  4447. */
  4448. static int beiscsi_bsg_request(struct bsg_job *job)
  4449. {
  4450. struct Scsi_Host *shost;
  4451. struct beiscsi_hba *phba;
  4452. struct iscsi_bsg_request *bsg_req = job->request;
  4453. int rc = -EINVAL;
  4454. unsigned int tag;
  4455. struct be_dma_mem nonemb_cmd;
  4456. struct be_cmd_resp_hdr *resp;
  4457. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4458. unsigned short status, extd_status;
  4459. shost = iscsi_job_to_shost(job);
  4460. phba = iscsi_host_priv(shost);
  4461. switch (bsg_req->msgcode) {
  4462. case ISCSI_BSG_HST_VENDOR:
  4463. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4464. job->request_payload.payload_len,
  4465. &nonemb_cmd.dma);
  4466. if (nonemb_cmd.va == NULL) {
  4467. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4468. "BM_%d : Failed to allocate memory for "
  4469. "beiscsi_bsg_request\n");
  4470. return -ENOMEM;
  4471. }
  4472. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4473. &nonemb_cmd);
  4474. if (!tag) {
  4475. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4476. "BM_%d : MBX Tag Allocation Failed\n");
  4477. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4478. nonemb_cmd.va, nonemb_cmd.dma);
  4479. return -EAGAIN;
  4480. }
  4481. rc = wait_event_interruptible_timeout(
  4482. phba->ctrl.mcc_wait[tag],
  4483. phba->ctrl.mcc_numtag[tag],
  4484. msecs_to_jiffies(
  4485. BEISCSI_HOST_MBX_TIMEOUT));
  4486. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4487. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4488. free_mcc_tag(&phba->ctrl, tag);
  4489. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4490. sg_copy_from_buffer(job->reply_payload.sg_list,
  4491. job->reply_payload.sg_cnt,
  4492. nonemb_cmd.va, (resp->response_length
  4493. + sizeof(*resp)));
  4494. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4495. bsg_reply->result = status;
  4496. bsg_job_done(job, bsg_reply->result,
  4497. bsg_reply->reply_payload_rcv_len);
  4498. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4499. nonemb_cmd.va, nonemb_cmd.dma);
  4500. if (status || extd_status) {
  4501. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4502. "BM_%d : MBX Cmd Failed"
  4503. " status = %d extd_status = %d\n",
  4504. status, extd_status);
  4505. return -EIO;
  4506. } else {
  4507. rc = 0;
  4508. }
  4509. break;
  4510. default:
  4511. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4512. "BM_%d : Unsupported bsg command: 0x%x\n",
  4513. bsg_req->msgcode);
  4514. break;
  4515. }
  4516. return rc;
  4517. }
  4518. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4519. {
  4520. /* Set the logging parameter */
  4521. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4522. }
  4523. /*
  4524. * beiscsi_quiesce()- Cleanup Driver resources
  4525. * @phba: Instance Priv structure
  4526. *
  4527. * Free the OS and HW resources held by the driver
  4528. **/
  4529. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4530. {
  4531. struct hwi_controller *phwi_ctrlr;
  4532. struct hwi_context_memory *phwi_context;
  4533. struct be_eq_obj *pbe_eq;
  4534. unsigned int i, msix_vec;
  4535. phwi_ctrlr = phba->phwi_ctrlr;
  4536. phwi_context = phwi_ctrlr->phwi_ctxt;
  4537. hwi_disable_intr(phba);
  4538. if (phba->msix_enabled) {
  4539. for (i = 0; i <= phba->num_cpus; i++) {
  4540. msix_vec = phba->msix_entries[i].vector;
  4541. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4542. kfree(phba->msi_name[i]);
  4543. }
  4544. } else
  4545. if (phba->pcidev->irq)
  4546. free_irq(phba->pcidev->irq, phba);
  4547. pci_disable_msix(phba->pcidev);
  4548. destroy_workqueue(phba->wq);
  4549. if (blk_iopoll_enabled)
  4550. for (i = 0; i < phba->num_cpus; i++) {
  4551. pbe_eq = &phwi_context->be_eq[i];
  4552. blk_iopoll_disable(&pbe_eq->iopoll);
  4553. }
  4554. beiscsi_clean_port(phba);
  4555. beiscsi_free_mem(phba);
  4556. beiscsi_unmap_pci_function(phba);
  4557. pci_free_consistent(phba->pcidev,
  4558. phba->ctrl.mbox_mem_alloced.size,
  4559. phba->ctrl.mbox_mem_alloced.va,
  4560. phba->ctrl.mbox_mem_alloced.dma);
  4561. cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
  4562. }
  4563. static void beiscsi_remove(struct pci_dev *pcidev)
  4564. {
  4565. struct beiscsi_hba *phba = NULL;
  4566. phba = pci_get_drvdata(pcidev);
  4567. if (!phba) {
  4568. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4569. return;
  4570. }
  4571. beiscsi_destroy_def_ifaces(phba);
  4572. beiscsi_quiesce(phba);
  4573. iscsi_boot_destroy_kset(phba->boot_kset);
  4574. iscsi_host_remove(phba->shost);
  4575. pci_dev_put(phba->pcidev);
  4576. iscsi_host_free(phba->shost);
  4577. pci_disable_device(pcidev);
  4578. }
  4579. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4580. {
  4581. struct beiscsi_hba *phba = NULL;
  4582. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4583. if (!phba) {
  4584. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4585. return;
  4586. }
  4587. beiscsi_quiesce(phba);
  4588. pci_disable_device(pcidev);
  4589. }
  4590. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4591. {
  4592. int i, status;
  4593. for (i = 0; i <= phba->num_cpus; i++)
  4594. phba->msix_entries[i].entry = i;
  4595. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4596. (phba->num_cpus + 1));
  4597. if (!status)
  4598. phba->msix_enabled = true;
  4599. return;
  4600. }
  4601. /*
  4602. * beiscsi_hw_health_check()- Check adapter health
  4603. * @work: work item to check HW health
  4604. *
  4605. * Check if adapter in an unrecoverable state or not.
  4606. **/
  4607. static void
  4608. beiscsi_hw_health_check(struct work_struct *work)
  4609. {
  4610. struct beiscsi_hba *phba =
  4611. container_of(work, struct beiscsi_hba,
  4612. beiscsi_hw_check_task.work);
  4613. beiscsi_ue_detect(phba);
  4614. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4615. msecs_to_jiffies(1000));
  4616. }
  4617. static int beiscsi_dev_probe(struct pci_dev *pcidev,
  4618. const struct pci_device_id *id)
  4619. {
  4620. struct beiscsi_hba *phba = NULL;
  4621. struct hwi_controller *phwi_ctrlr;
  4622. struct hwi_context_memory *phwi_context;
  4623. struct be_eq_obj *pbe_eq;
  4624. int ret, i;
  4625. ret = beiscsi_enable_pci(pcidev);
  4626. if (ret < 0) {
  4627. dev_err(&pcidev->dev,
  4628. "beiscsi_dev_probe - Failed to enable pci device\n");
  4629. return ret;
  4630. }
  4631. phba = beiscsi_hba_alloc(pcidev);
  4632. if (!phba) {
  4633. dev_err(&pcidev->dev,
  4634. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4635. goto disable_pci;
  4636. }
  4637. /* Initialize Driver configuration Paramters */
  4638. beiscsi_hba_attrs_init(phba);
  4639. phba->fw_timeout = false;
  4640. phba->mac_addr_set = false;
  4641. switch (pcidev->device) {
  4642. case BE_DEVICE_ID1:
  4643. case OC_DEVICE_ID1:
  4644. case OC_DEVICE_ID2:
  4645. phba->generation = BE_GEN2;
  4646. phba->iotask_fn = beiscsi_iotask;
  4647. break;
  4648. case BE_DEVICE_ID2:
  4649. case OC_DEVICE_ID3:
  4650. phba->generation = BE_GEN3;
  4651. phba->iotask_fn = beiscsi_iotask;
  4652. break;
  4653. case OC_SKH_ID1:
  4654. phba->generation = BE_GEN4;
  4655. phba->iotask_fn = beiscsi_iotask_v2;
  4656. break;
  4657. default:
  4658. phba->generation = 0;
  4659. }
  4660. if (enable_msix)
  4661. find_num_cpus(phba);
  4662. else
  4663. phba->num_cpus = 1;
  4664. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4665. "BM_%d : num_cpus = %d\n",
  4666. phba->num_cpus);
  4667. if (enable_msix) {
  4668. beiscsi_msix_enable(phba);
  4669. if (!phba->msix_enabled)
  4670. phba->num_cpus = 1;
  4671. }
  4672. ret = be_ctrl_init(phba, pcidev);
  4673. if (ret) {
  4674. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4675. "BM_%d : beiscsi_dev_probe-"
  4676. "Failed in be_ctrl_init\n");
  4677. goto hba_free;
  4678. }
  4679. ret = beiscsi_cmd_reset_function(phba);
  4680. if (ret) {
  4681. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4682. "BM_%d : Reset Failed\n");
  4683. goto hba_free;
  4684. }
  4685. ret = be_chk_reset_complete(phba);
  4686. if (ret) {
  4687. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4688. "BM_%d : Failed to get out of reset.\n");
  4689. goto hba_free;
  4690. }
  4691. spin_lock_init(&phba->io_sgl_lock);
  4692. spin_lock_init(&phba->mgmt_sgl_lock);
  4693. spin_lock_init(&phba->isr_lock);
  4694. spin_lock_init(&phba->async_pdu_lock);
  4695. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4696. if (ret != 0) {
  4697. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4698. "BM_%d : Error getting fw config\n");
  4699. goto free_port;
  4700. }
  4701. phba->shost->max_id = phba->params.cxns_per_ctrl;
  4702. beiscsi_get_params(phba);
  4703. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4704. ret = beiscsi_init_port(phba);
  4705. if (ret < 0) {
  4706. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4707. "BM_%d : beiscsi_dev_probe-"
  4708. "Failed in beiscsi_init_port\n");
  4709. goto free_port;
  4710. }
  4711. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4712. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4713. phba->ctrl.mcc_tag[i] = i + 1;
  4714. phba->ctrl.mcc_numtag[i + 1] = 0;
  4715. phba->ctrl.mcc_tag_available++;
  4716. }
  4717. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4718. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4719. phba->shost->host_no);
  4720. phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
  4721. if (!phba->wq) {
  4722. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4723. "BM_%d : beiscsi_dev_probe-"
  4724. "Failed to allocate work queue\n");
  4725. goto free_twq;
  4726. }
  4727. INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
  4728. beiscsi_hw_health_check);
  4729. phwi_ctrlr = phba->phwi_ctrlr;
  4730. phwi_context = phwi_ctrlr->phwi_ctxt;
  4731. if (blk_iopoll_enabled) {
  4732. for (i = 0; i < phba->num_cpus; i++) {
  4733. pbe_eq = &phwi_context->be_eq[i];
  4734. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4735. be_iopoll);
  4736. blk_iopoll_enable(&pbe_eq->iopoll);
  4737. }
  4738. i = (phba->msix_enabled) ? i : 0;
  4739. /* Work item for MCC handling */
  4740. pbe_eq = &phwi_context->be_eq[i];
  4741. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4742. } else {
  4743. if (phba->msix_enabled) {
  4744. for (i = 0; i <= phba->num_cpus; i++) {
  4745. pbe_eq = &phwi_context->be_eq[i];
  4746. INIT_WORK(&pbe_eq->work_cqs,
  4747. beiscsi_process_all_cqs);
  4748. }
  4749. } else {
  4750. pbe_eq = &phwi_context->be_eq[0];
  4751. INIT_WORK(&pbe_eq->work_cqs,
  4752. beiscsi_process_all_cqs);
  4753. }
  4754. }
  4755. ret = beiscsi_init_irqs(phba);
  4756. if (ret < 0) {
  4757. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4758. "BM_%d : beiscsi_dev_probe-"
  4759. "Failed to beiscsi_init_irqs\n");
  4760. goto free_blkenbld;
  4761. }
  4762. hwi_enable_intr(phba);
  4763. if (beiscsi_setup_boot_info(phba))
  4764. /*
  4765. * log error but continue, because we may not be using
  4766. * iscsi boot.
  4767. */
  4768. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4769. "BM_%d : Could not set up "
  4770. "iSCSI boot info.\n");
  4771. beiscsi_create_def_ifaces(phba);
  4772. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4773. msecs_to_jiffies(1000));
  4774. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4775. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4776. return 0;
  4777. free_blkenbld:
  4778. destroy_workqueue(phba->wq);
  4779. if (blk_iopoll_enabled)
  4780. for (i = 0; i < phba->num_cpus; i++) {
  4781. pbe_eq = &phwi_context->be_eq[i];
  4782. blk_iopoll_disable(&pbe_eq->iopoll);
  4783. }
  4784. free_twq:
  4785. beiscsi_clean_port(phba);
  4786. beiscsi_free_mem(phba);
  4787. free_port:
  4788. pci_free_consistent(phba->pcidev,
  4789. phba->ctrl.mbox_mem_alloced.size,
  4790. phba->ctrl.mbox_mem_alloced.va,
  4791. phba->ctrl.mbox_mem_alloced.dma);
  4792. beiscsi_unmap_pci_function(phba);
  4793. hba_free:
  4794. if (phba->msix_enabled)
  4795. pci_disable_msix(phba->pcidev);
  4796. iscsi_host_remove(phba->shost);
  4797. pci_dev_put(phba->pcidev);
  4798. iscsi_host_free(phba->shost);
  4799. disable_pci:
  4800. pci_disable_device(pcidev);
  4801. return ret;
  4802. }
  4803. struct iscsi_transport beiscsi_iscsi_transport = {
  4804. .owner = THIS_MODULE,
  4805. .name = DRV_NAME,
  4806. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4807. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4808. .create_session = beiscsi_session_create,
  4809. .destroy_session = beiscsi_session_destroy,
  4810. .create_conn = beiscsi_conn_create,
  4811. .bind_conn = beiscsi_conn_bind,
  4812. .destroy_conn = iscsi_conn_teardown,
  4813. .attr_is_visible = be2iscsi_attr_is_visible,
  4814. .set_iface_param = be2iscsi_iface_set_param,
  4815. .get_iface_param = be2iscsi_iface_get_param,
  4816. .set_param = beiscsi_set_param,
  4817. .get_conn_param = iscsi_conn_get_param,
  4818. .get_session_param = iscsi_session_get_param,
  4819. .get_host_param = beiscsi_get_host_param,
  4820. .start_conn = beiscsi_conn_start,
  4821. .stop_conn = iscsi_conn_stop,
  4822. .send_pdu = iscsi_conn_send_pdu,
  4823. .xmit_task = beiscsi_task_xmit,
  4824. .cleanup_task = beiscsi_cleanup_task,
  4825. .alloc_pdu = beiscsi_alloc_pdu,
  4826. .parse_pdu_itt = beiscsi_parse_pdu,
  4827. .get_stats = beiscsi_conn_get_stats,
  4828. .get_ep_param = beiscsi_ep_get_param,
  4829. .ep_connect = beiscsi_ep_connect,
  4830. .ep_poll = beiscsi_ep_poll,
  4831. .ep_disconnect = beiscsi_ep_disconnect,
  4832. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4833. .bsg_request = beiscsi_bsg_request,
  4834. };
  4835. static struct pci_driver beiscsi_pci_driver = {
  4836. .name = DRV_NAME,
  4837. .probe = beiscsi_dev_probe,
  4838. .remove = beiscsi_remove,
  4839. .shutdown = beiscsi_shutdown,
  4840. .id_table = beiscsi_pci_id_table
  4841. };
  4842. static int __init beiscsi_module_init(void)
  4843. {
  4844. int ret;
  4845. beiscsi_scsi_transport =
  4846. iscsi_register_transport(&beiscsi_iscsi_transport);
  4847. if (!beiscsi_scsi_transport) {
  4848. printk(KERN_ERR
  4849. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4850. return -ENOMEM;
  4851. }
  4852. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4853. &beiscsi_iscsi_transport);
  4854. ret = pci_register_driver(&beiscsi_pci_driver);
  4855. if (ret) {
  4856. printk(KERN_ERR
  4857. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4858. goto unregister_iscsi_transport;
  4859. }
  4860. return 0;
  4861. unregister_iscsi_transport:
  4862. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4863. return ret;
  4864. }
  4865. static void __exit beiscsi_module_exit(void)
  4866. {
  4867. pci_unregister_driver(&beiscsi_pci_driver);
  4868. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4869. }
  4870. module_init(beiscsi_module_init);
  4871. module_exit(beiscsi_module_exit);