adg.c 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233
  1. /*
  2. * Helper routines for R-Car sound ADG.
  3. *
  4. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/sh_clk.h>
  11. #include "rsnd.h"
  12. #define CLKA 0
  13. #define CLKB 1
  14. #define CLKC 2
  15. #define CLKI 3
  16. #define CLKMAX 4
  17. struct rsnd_adg {
  18. struct clk *clk[CLKMAX];
  19. int rate_of_441khz_div_6;
  20. int rate_of_48khz_div_6;
  21. };
  22. #define for_each_rsnd_clk(pos, adg, i) \
  23. for (i = 0, (pos) = adg->clk[i]; \
  24. i < CLKMAX; \
  25. i++, (pos) = adg->clk[i])
  26. #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  27. static enum rsnd_reg rsnd_adg_ssi_reg_get(int id)
  28. {
  29. enum rsnd_reg reg;
  30. /*
  31. * SSI 8 is not connected to ADG.
  32. * it works with SSI 7
  33. */
  34. if (id == 8)
  35. return RSND_REG_MAX;
  36. if (0 <= id && id <= 3)
  37. reg = RSND_REG_AUDIO_CLK_SEL0;
  38. else if (4 <= id && id <= 7)
  39. reg = RSND_REG_AUDIO_CLK_SEL1;
  40. else
  41. reg = RSND_REG_AUDIO_CLK_SEL2;
  42. return reg;
  43. }
  44. int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
  45. {
  46. struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  47. enum rsnd_reg reg;
  48. int id;
  49. /*
  50. * "mod" = "ssi" here.
  51. * we can get "ssi id" from mod
  52. */
  53. id = rsnd_mod_id(mod);
  54. reg = rsnd_adg_ssi_reg_get(id);
  55. rsnd_write(priv, mod, reg, 0);
  56. return 0;
  57. }
  58. int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
  59. {
  60. struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  61. struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  62. struct device *dev = rsnd_priv_to_dev(priv);
  63. struct clk *clk;
  64. enum rsnd_reg reg;
  65. int id, shift, i;
  66. u32 data;
  67. int sel_table[] = {
  68. [CLKA] = 0x1,
  69. [CLKB] = 0x2,
  70. [CLKC] = 0x3,
  71. [CLKI] = 0x0,
  72. };
  73. dev_dbg(dev, "request clock = %d\n", rate);
  74. /*
  75. * find suitable clock from
  76. * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
  77. */
  78. data = 0;
  79. for_each_rsnd_clk(clk, adg, i) {
  80. if (rate == clk_get_rate(clk)) {
  81. data = sel_table[i];
  82. goto found_clock;
  83. }
  84. }
  85. /*
  86. * find 1/6 clock from BRGA/BRGB
  87. */
  88. if (rate == adg->rate_of_441khz_div_6) {
  89. data = 0x10;
  90. goto found_clock;
  91. }
  92. if (rate == adg->rate_of_48khz_div_6) {
  93. data = 0x20;
  94. goto found_clock;
  95. }
  96. return -EIO;
  97. found_clock:
  98. /*
  99. * This "mod" = "ssi" here.
  100. * we can get "ssi id" from mod
  101. */
  102. id = rsnd_mod_id(mod);
  103. reg = rsnd_adg_ssi_reg_get(id);
  104. dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", id, i, rate);
  105. /*
  106. * Enable SSIx clock
  107. */
  108. shift = (id % 4) * 8;
  109. rsnd_bset(priv, mod, reg,
  110. 0xFF << shift,
  111. data << shift);
  112. return 0;
  113. }
  114. static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
  115. {
  116. struct clk *clk;
  117. unsigned long rate;
  118. u32 ckr;
  119. int i;
  120. int brg_table[] = {
  121. [CLKA] = 0x0,
  122. [CLKB] = 0x1,
  123. [CLKC] = 0x4,
  124. [CLKI] = 0x2,
  125. };
  126. /*
  127. * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
  128. * have 44.1kHz or 48kHz base clocks for now.
  129. *
  130. * SSI itself can divide parent clock by 1/1 - 1/16
  131. * So, BRGA outputs 44.1kHz base parent clock 1/32,
  132. * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
  133. * see
  134. * rsnd_adg_ssi_clk_try_start()
  135. */
  136. ckr = 0;
  137. adg->rate_of_441khz_div_6 = 0;
  138. adg->rate_of_48khz_div_6 = 0;
  139. for_each_rsnd_clk(clk, adg, i) {
  140. rate = clk_get_rate(clk);
  141. if (0 == rate) /* not used */
  142. continue;
  143. /* RBGA */
  144. if (!adg->rate_of_441khz_div_6 && (0 == rate % 44100)) {
  145. adg->rate_of_441khz_div_6 = rate / 6;
  146. ckr |= brg_table[i] << 20;
  147. }
  148. /* RBGB */
  149. if (!adg->rate_of_48khz_div_6 && (0 == rate % 48000)) {
  150. adg->rate_of_48khz_div_6 = rate / 6;
  151. ckr |= brg_table[i] << 16;
  152. }
  153. }
  154. rsnd_priv_bset(priv, SSICKR, 0x00FF0000, ckr);
  155. rsnd_priv_write(priv, BRRA, 0x00000002); /* 1/6 */
  156. rsnd_priv_write(priv, BRRB, 0x00000002); /* 1/6 */
  157. }
  158. int rsnd_adg_probe(struct platform_device *pdev,
  159. struct rcar_snd_info *info,
  160. struct rsnd_priv *priv)
  161. {
  162. struct rsnd_adg *adg;
  163. struct device *dev = rsnd_priv_to_dev(priv);
  164. struct clk *clk;
  165. int i;
  166. adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
  167. if (!adg) {
  168. dev_err(dev, "ADG allocate failed\n");
  169. return -ENOMEM;
  170. }
  171. adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
  172. adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
  173. adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
  174. adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
  175. for_each_rsnd_clk(clk, adg, i) {
  176. if (IS_ERR(clk)) {
  177. dev_err(dev, "Audio clock failed\n");
  178. return -EIO;
  179. }
  180. }
  181. rsnd_adg_ssi_clk_init(priv, adg);
  182. priv->adg = adg;
  183. dev_dbg(dev, "adg probed\n");
  184. return 0;
  185. }
  186. void rsnd_adg_remove(struct platform_device *pdev,
  187. struct rsnd_priv *priv)
  188. {
  189. struct rsnd_adg *adg = priv->adg;
  190. struct clk *clk;
  191. int i;
  192. for_each_rsnd_clk(clk, adg, i)
  193. clk_put(clk);
  194. }