bcm11351.dtsi 2.7 KB

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  1. /*
  2. * Copyright (C) 2012-2013 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <dt-bindings/interrupt-controller/arm-gic.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include "skeleton.dtsi"
  16. / {
  17. model = "BCM11351 SoC";
  18. compatible = "brcm,bcm11351";
  19. interrupt-parent = <&gic>;
  20. chosen {
  21. bootargs = "console=ttyS0,115200n8";
  22. };
  23. gic: interrupt-controller@3ff00100 {
  24. compatible = "arm,cortex-a9-gic";
  25. #interrupt-cells = <3>;
  26. #address-cells = <0>;
  27. interrupt-controller;
  28. reg = <0x3ff01000 0x1000>,
  29. <0x3ff00100 0x100>;
  30. };
  31. smc@0x3404c000 {
  32. compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
  33. reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
  34. };
  35. uart@3e000000 {
  36. compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  37. status = "disabled";
  38. reg = <0x3e000000 0x1000>;
  39. clock-frequency = <13000000>;
  40. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  41. reg-shift = <2>;
  42. reg-io-width = <4>;
  43. };
  44. L2: l2-cache {
  45. compatible = "brcm,bcm11351-a2-pl310-cache";
  46. reg = <0x3ff20000 0x1000>;
  47. cache-unified;
  48. cache-level = <2>;
  49. };
  50. watchdog@35002f40 {
  51. compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
  52. reg = <0x35002f40 0x6c>;
  53. };
  54. timer@35006000 {
  55. compatible = "brcm,kona-timer";
  56. reg = <0x35006000 0x1000>;
  57. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  58. clock-frequency = <32768>;
  59. };
  60. gpio: gpio@35003000 {
  61. compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
  62. reg = <0x35003000 0x800>;
  63. interrupts =
  64. <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
  65. GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
  66. GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
  67. GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
  68. GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
  69. GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  70. #gpio-cells = <2>;
  71. #interrupt-cells = <2>;
  72. gpio-controller;
  73. interrupt-controller;
  74. };
  75. sdio1: sdio@3f180000 {
  76. compatible = "brcm,kona-sdhci";
  77. reg = <0x3f180000 0x10000>;
  78. interrupts = <0x0 77 0x4>;
  79. status = "disabled";
  80. };
  81. sdio2: sdio@3f190000 {
  82. compatible = "brcm,kona-sdhci";
  83. reg = <0x3f190000 0x10000>;
  84. interrupts = <0x0 76 0x4>;
  85. status = "disabled";
  86. };
  87. sdio3: sdio@3f1a0000 {
  88. compatible = "brcm,kona-sdhci";
  89. reg = <0x3f1a0000 0x10000>;
  90. interrupts = <0x0 74 0x4>;
  91. status = "disabled";
  92. };
  93. sdio4: sdio@3f1b0000 {
  94. compatible = "brcm,kona-sdhci";
  95. reg = <0x3f1b0000 0x10000>;
  96. interrupts = <0x0 73 0x4>;
  97. status = "disabled";
  98. };
  99. };