ps3vram.c 22 KB

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  1. /*
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright 2009 Sony Corporation
  5. *
  6. * Based on the MTD ps3vram driver, which is
  7. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  8. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  9. */
  10. #include <linux/blkdev.h>
  11. #include <linux/delay.h>
  12. #include <linux/proc_fs.h>
  13. #include <linux/seq_file.h>
  14. #include <asm/firmware.h>
  15. #include <asm/iommu.h>
  16. #include <asm/lv1call.h>
  17. #include <asm/ps3.h>
  18. #include <asm/ps3gpu.h>
  19. #define DEVICE_NAME "ps3vram"
  20. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  21. #define XDR_IOIF 0x0c000000
  22. #define FIFO_BASE XDR_IOIF
  23. #define FIFO_SIZE (64 * 1024)
  24. #define DMA_PAGE_SIZE (4 * 1024)
  25. #define CACHE_PAGE_SIZE (256 * 1024)
  26. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  27. #define CACHE_OFFSET CACHE_PAGE_SIZE
  28. #define FIFO_OFFSET 0
  29. #define CTRL_PUT 0x10
  30. #define CTRL_GET 0x11
  31. #define CTRL_TOP 0x15
  32. #define UPLOAD_SUBCH 1
  33. #define DOWNLOAD_SUBCH 2
  34. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  35. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  36. #define CACHE_PAGE_PRESENT 1
  37. #define CACHE_PAGE_DIRTY 2
  38. struct ps3vram_tag {
  39. unsigned int address;
  40. unsigned int flags;
  41. };
  42. struct ps3vram_cache {
  43. unsigned int page_count;
  44. unsigned int page_size;
  45. struct ps3vram_tag *tags;
  46. unsigned int hit;
  47. unsigned int miss;
  48. };
  49. struct ps3vram_priv {
  50. struct request_queue *queue;
  51. struct gendisk *gendisk;
  52. u64 size;
  53. u64 memory_handle;
  54. u64 context_handle;
  55. u32 *ctrl;
  56. u32 *reports;
  57. u8 __iomem *ddr_base;
  58. u8 *xdr_buf;
  59. u32 *fifo_base;
  60. u32 *fifo_ptr;
  61. struct ps3vram_cache cache;
  62. /* Used to serialize cache/DMA operations */
  63. struct mutex lock;
  64. };
  65. static int ps3vram_major;
  66. static struct block_device_operations ps3vram_fops = {
  67. .owner = THIS_MODULE,
  68. };
  69. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  70. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  71. #define DMA_NOTIFIER_SIZE 0x40
  72. #define NOTIFIER 7 /* notifier used for completion report */
  73. static char *size = "256M";
  74. module_param(size, charp, 0);
  75. MODULE_PARM_DESC(size, "memory size");
  76. static u32 *ps3vram_get_notifier(u32 *reports, int notifier)
  77. {
  78. return (void *)reports + DMA_NOTIFIER_OFFSET_BASE +
  79. DMA_NOTIFIER_SIZE * notifier;
  80. }
  81. static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
  82. {
  83. struct ps3vram_priv *priv = dev->core.driver_data;
  84. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  85. int i;
  86. for (i = 0; i < 4; i++)
  87. notify[i] = 0xffffffff;
  88. }
  89. static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
  90. unsigned int timeout_ms)
  91. {
  92. struct ps3vram_priv *priv = dev->core.driver_data;
  93. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  94. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  95. do {
  96. if (!notify[3])
  97. return 0;
  98. msleep(1);
  99. } while (time_before(jiffies, timeout));
  100. return -ETIMEDOUT;
  101. }
  102. static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
  103. {
  104. struct ps3vram_priv *priv = dev->core.driver_data;
  105. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  106. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  107. }
  108. static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
  109. unsigned int timeout_ms)
  110. {
  111. struct ps3vram_priv *priv = dev->core.driver_data;
  112. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  113. do {
  114. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  115. return 0;
  116. msleep(1);
  117. } while (time_before(jiffies, timeout));
  118. dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
  119. priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
  120. priv->ctrl[CTRL_TOP]);
  121. return -ETIMEDOUT;
  122. }
  123. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  124. {
  125. *(priv->fifo_ptr)++ = data;
  126. }
  127. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
  128. u32 size)
  129. {
  130. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  131. }
  132. static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
  133. {
  134. struct ps3vram_priv *priv = dev->core.driver_data;
  135. int status;
  136. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  137. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  138. /* asking the HV for a blit will kick the FIFO */
  139. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  140. if (status)
  141. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  142. __func__, status);
  143. priv->fifo_ptr = priv->fifo_base;
  144. }
  145. static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
  146. {
  147. struct ps3vram_priv *priv = dev->core.driver_data;
  148. int status;
  149. mutex_lock(&ps3_gpu_mutex);
  150. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  151. (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
  152. /* asking the HV for a blit will kick the FIFO */
  153. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  154. if (status)
  155. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  156. __func__, status);
  157. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  158. FIFO_SIZE - 1024) {
  159. dev_dbg(&dev->core, "FIFO full, rewinding\n");
  160. ps3vram_wait_ring(dev, 200);
  161. ps3vram_rewind_ring(dev);
  162. }
  163. mutex_unlock(&ps3_gpu_mutex);
  164. }
  165. static void ps3vram_bind(struct ps3_system_bus_device *dev)
  166. {
  167. struct ps3vram_priv *priv = dev->core.driver_data;
  168. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  169. ps3vram_out_ring(priv, 0x31337303);
  170. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  171. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  172. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  173. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  174. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  175. ps3vram_out_ring(priv, 0x3137c0de);
  176. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  177. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  178. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  179. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  180. ps3vram_fire_ring(dev);
  181. }
  182. static int ps3vram_upload(struct ps3_system_bus_device *dev,
  183. unsigned int src_offset, unsigned int dst_offset,
  184. int len, int count)
  185. {
  186. struct ps3vram_priv *priv = dev->core.driver_data;
  187. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  188. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  189. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  190. ps3vram_out_ring(priv, dst_offset);
  191. ps3vram_out_ring(priv, len);
  192. ps3vram_out_ring(priv, len);
  193. ps3vram_out_ring(priv, len);
  194. ps3vram_out_ring(priv, count);
  195. ps3vram_out_ring(priv, (1 << 8) | 1);
  196. ps3vram_out_ring(priv, 0);
  197. ps3vram_notifier_reset(dev);
  198. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  199. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  200. ps3vram_out_ring(priv, 0);
  201. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  202. ps3vram_out_ring(priv, 0);
  203. ps3vram_fire_ring(dev);
  204. if (ps3vram_notifier_wait(dev, 200) < 0) {
  205. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  206. return -1;
  207. }
  208. return 0;
  209. }
  210. static int ps3vram_download(struct ps3_system_bus_device *dev,
  211. unsigned int src_offset, unsigned int dst_offset,
  212. int len, int count)
  213. {
  214. struct ps3vram_priv *priv = dev->core.driver_data;
  215. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  216. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  217. ps3vram_out_ring(priv, src_offset);
  218. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  219. ps3vram_out_ring(priv, len);
  220. ps3vram_out_ring(priv, len);
  221. ps3vram_out_ring(priv, len);
  222. ps3vram_out_ring(priv, count);
  223. ps3vram_out_ring(priv, (1 << 8) | 1);
  224. ps3vram_out_ring(priv, 0);
  225. ps3vram_notifier_reset(dev);
  226. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  227. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  228. ps3vram_out_ring(priv, 0);
  229. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  230. ps3vram_out_ring(priv, 0);
  231. ps3vram_fire_ring(dev);
  232. if (ps3vram_notifier_wait(dev, 200) < 0) {
  233. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  234. return -1;
  235. }
  236. return 0;
  237. }
  238. static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
  239. {
  240. struct ps3vram_priv *priv = dev->core.driver_data;
  241. struct ps3vram_cache *cache = &priv->cache;
  242. if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
  243. return;
  244. dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
  245. cache->tags[entry].address);
  246. if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
  247. cache->tags[entry].address, DMA_PAGE_SIZE,
  248. cache->page_size / DMA_PAGE_SIZE) < 0) {
  249. dev_err(&dev->core,
  250. "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
  251. entry * cache->page_size, cache->tags[entry].address,
  252. cache->page_size);
  253. }
  254. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  255. }
  256. static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
  257. unsigned int address)
  258. {
  259. struct ps3vram_priv *priv = dev->core.driver_data;
  260. struct ps3vram_cache *cache = &priv->cache;
  261. dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
  262. if (ps3vram_download(dev, address,
  263. CACHE_OFFSET + entry * cache->page_size,
  264. DMA_PAGE_SIZE,
  265. cache->page_size / DMA_PAGE_SIZE) < 0) {
  266. dev_err(&dev->core,
  267. "Failed to download from 0x%x to 0x%x size 0x%x\n",
  268. address, entry * cache->page_size, cache->page_size);
  269. }
  270. cache->tags[entry].address = address;
  271. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  272. }
  273. static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
  274. {
  275. struct ps3vram_priv *priv = dev->core.driver_data;
  276. struct ps3vram_cache *cache = &priv->cache;
  277. int i;
  278. dev_dbg(&dev->core, "FLUSH\n");
  279. for (i = 0; i < cache->page_count; i++) {
  280. ps3vram_cache_evict(dev, i);
  281. cache->tags[i].flags = 0;
  282. }
  283. }
  284. static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
  285. loff_t address)
  286. {
  287. struct ps3vram_priv *priv = dev->core.driver_data;
  288. struct ps3vram_cache *cache = &priv->cache;
  289. unsigned int base;
  290. unsigned int offset;
  291. int i;
  292. static int counter;
  293. offset = (unsigned int) (address & (cache->page_size - 1));
  294. base = (unsigned int) (address - offset);
  295. /* fully associative check */
  296. for (i = 0; i < cache->page_count; i++) {
  297. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  298. cache->tags[i].address == base) {
  299. cache->hit++;
  300. dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
  301. cache->tags[i].address);
  302. return i;
  303. }
  304. }
  305. /* choose a random entry */
  306. i = (jiffies + (counter++)) % cache->page_count;
  307. dev_dbg(&dev->core, "Using entry %d\n", i);
  308. ps3vram_cache_evict(dev, i);
  309. ps3vram_cache_load(dev, i, base);
  310. cache->miss++;
  311. return i;
  312. }
  313. static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
  314. {
  315. struct ps3vram_priv *priv = dev->core.driver_data;
  316. priv->cache.page_count = CACHE_PAGE_COUNT;
  317. priv->cache.page_size = CACHE_PAGE_SIZE;
  318. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  319. CACHE_PAGE_COUNT, GFP_KERNEL);
  320. if (priv->cache.tags == NULL) {
  321. dev_err(&dev->core, "Could not allocate cache tags\n");
  322. return -ENOMEM;
  323. }
  324. dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
  325. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  326. return 0;
  327. }
  328. static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
  329. {
  330. struct ps3vram_priv *priv = dev->core.driver_data;
  331. ps3vram_cache_flush(dev);
  332. kfree(priv->cache.tags);
  333. }
  334. static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
  335. size_t len, size_t *retlen, u_char *buf)
  336. {
  337. struct ps3vram_priv *priv = dev->core.driver_data;
  338. unsigned int cached, count;
  339. dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
  340. (unsigned int)from, len);
  341. if (from >= priv->size)
  342. return -EIO;
  343. if (len > priv->size - from)
  344. len = priv->size - from;
  345. /* Copy from vram to buf */
  346. count = len;
  347. while (count) {
  348. unsigned int offset, avail;
  349. unsigned int entry;
  350. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  351. avail = priv->cache.page_size - offset;
  352. mutex_lock(&priv->lock);
  353. entry = ps3vram_cache_match(dev, from);
  354. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  355. dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
  356. "avail=%08x count=%08x\n", __func__,
  357. (unsigned int)from, cached, offset, avail, count);
  358. if (avail > count)
  359. avail = count;
  360. memcpy(buf, priv->xdr_buf + cached, avail);
  361. mutex_unlock(&priv->lock);
  362. buf += avail;
  363. count -= avail;
  364. from += avail;
  365. }
  366. *retlen = len;
  367. return 0;
  368. }
  369. static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
  370. size_t len, size_t *retlen, const u_char *buf)
  371. {
  372. struct ps3vram_priv *priv = dev->core.driver_data;
  373. unsigned int cached, count;
  374. if (to >= priv->size)
  375. return -EIO;
  376. if (len > priv->size - to)
  377. len = priv->size - to;
  378. /* Copy from buf to vram */
  379. count = len;
  380. while (count) {
  381. unsigned int offset, avail;
  382. unsigned int entry;
  383. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  384. avail = priv->cache.page_size - offset;
  385. mutex_lock(&priv->lock);
  386. entry = ps3vram_cache_match(dev, to);
  387. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  388. dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
  389. "avail=%08x count=%08x\n", __func__, (unsigned int)to,
  390. cached, offset, avail, count);
  391. if (avail > count)
  392. avail = count;
  393. memcpy(priv->xdr_buf + cached, buf, avail);
  394. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  395. mutex_unlock(&priv->lock);
  396. buf += avail;
  397. count -= avail;
  398. to += avail;
  399. }
  400. *retlen = len;
  401. return 0;
  402. }
  403. static int ps3vram_proc_show(struct seq_file *m, void *v)
  404. {
  405. struct ps3vram_priv *priv = m->private;
  406. seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
  407. return 0;
  408. }
  409. static int ps3vram_proc_open(struct inode *inode, struct file *file)
  410. {
  411. return single_open(file, ps3vram_proc_show, PDE(inode)->data);
  412. }
  413. static const struct file_operations ps3vram_proc_fops = {
  414. .owner = THIS_MODULE,
  415. .open = ps3vram_proc_open,
  416. .read = seq_read,
  417. .llseek = seq_lseek,
  418. .release = single_release,
  419. };
  420. static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev)
  421. {
  422. struct ps3vram_priv *priv = dev->core.driver_data;
  423. struct proc_dir_entry *pde;
  424. pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops,
  425. priv);
  426. if (!pde)
  427. dev_warn(&dev->core, "failed to create /proc entry\n");
  428. }
  429. static int ps3vram_make_request(struct request_queue *q, struct bio *bio)
  430. {
  431. struct ps3_system_bus_device *dev = q->queuedata;
  432. int write = bio_data_dir(bio) == WRITE;
  433. const char *op = write ? "write" : "read";
  434. loff_t offset = bio->bi_sector << 9;
  435. int error = 0;
  436. struct bio_vec *bvec;
  437. unsigned int i;
  438. dev_dbg(&dev->core, "%s\n", __func__);
  439. bio_for_each_segment(bvec, bio, i) {
  440. /* PS3 is ppc64, so we don't handle highmem */
  441. char *ptr = page_address(bvec->bv_page) + bvec->bv_offset;
  442. size_t len = bvec->bv_len, retlen;
  443. dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
  444. len, offset);
  445. if (write)
  446. error = ps3vram_write(dev, offset, len, &retlen, ptr);
  447. else
  448. error = ps3vram_read(dev, offset, len, &retlen, ptr);
  449. if (error) {
  450. dev_err(&dev->core, "%s failed\n", op);
  451. goto out;
  452. }
  453. if (retlen != len) {
  454. dev_err(&dev->core, "Short %s\n", op);
  455. error = -EIO;
  456. goto out;
  457. }
  458. offset += len;
  459. }
  460. dev_dbg(&dev->core, "%s completed\n", op);
  461. out:
  462. bio_endio(bio, error);
  463. return 0;
  464. }
  465. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  466. {
  467. struct ps3vram_priv *priv;
  468. int error, status;
  469. struct request_queue *queue;
  470. struct gendisk *gendisk;
  471. u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
  472. reports_size, xdr_lpar;
  473. char *rest;
  474. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  475. if (!priv) {
  476. error = -ENOMEM;
  477. goto fail;
  478. }
  479. mutex_init(&priv->lock);
  480. dev->core.driver_data = priv;
  481. priv = dev->core.driver_data;
  482. /* Allocate XDR buffer (1MiB aligned) */
  483. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  484. get_order(XDR_BUF_SIZE));
  485. if (priv->xdr_buf == NULL) {
  486. dev_err(&dev->core, "Could not allocate XDR buffer\n");
  487. error = -ENOMEM;
  488. goto fail_free_priv;
  489. }
  490. /* Put FIFO at begginning of XDR buffer */
  491. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  492. priv->fifo_ptr = priv->fifo_base;
  493. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  494. if (ps3_open_hv_device(dev)) {
  495. dev_err(&dev->core, "ps3_open_hv_device failed\n");
  496. error = -EAGAIN;
  497. goto out_free_xdr_buf;
  498. }
  499. /* Request memory */
  500. status = -1;
  501. ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
  502. if (!ddr_size) {
  503. dev_err(&dev->core, "Specified size is too small\n");
  504. error = -EINVAL;
  505. goto out_close_gpu;
  506. }
  507. while (ddr_size > 0) {
  508. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  509. &priv->memory_handle,
  510. &ddr_lpar);
  511. if (!status)
  512. break;
  513. ddr_size -= 1024*1024;
  514. }
  515. if (status) {
  516. dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
  517. status);
  518. error = -ENOMEM;
  519. goto out_close_gpu;
  520. }
  521. /* Request context */
  522. status = lv1_gpu_context_allocate(priv->memory_handle, 0,
  523. &priv->context_handle, &ctrl_lpar,
  524. &info_lpar, &reports_lpar,
  525. &reports_size);
  526. if (status) {
  527. dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
  528. status);
  529. error = -ENOMEM;
  530. goto out_free_memory;
  531. }
  532. /* Map XDR buffer to RSX */
  533. xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
  534. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  535. xdr_lpar, XDR_BUF_SIZE,
  536. CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
  537. CBE_IOPTE_M);
  538. if (status) {
  539. dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
  540. status);
  541. error = -ENOMEM;
  542. goto out_free_context;
  543. }
  544. priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE);
  545. if (!priv->ddr_base) {
  546. dev_err(&dev->core, "ioremap DDR failed\n");
  547. error = -ENOMEM;
  548. goto out_unmap_context;
  549. }
  550. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  551. if (!priv->ctrl) {
  552. dev_err(&dev->core, "ioremap CTRL failed\n");
  553. error = -ENOMEM;
  554. goto out_unmap_vram;
  555. }
  556. priv->reports = ioremap(reports_lpar, reports_size);
  557. if (!priv->reports) {
  558. dev_err(&dev->core, "ioremap REPORTS failed\n");
  559. error = -ENOMEM;
  560. goto out_unmap_ctrl;
  561. }
  562. mutex_lock(&ps3_gpu_mutex);
  563. ps3vram_init_ring(dev);
  564. mutex_unlock(&ps3_gpu_mutex);
  565. priv->size = ddr_size;
  566. ps3vram_bind(dev);
  567. mutex_lock(&ps3_gpu_mutex);
  568. error = ps3vram_wait_ring(dev, 100);
  569. mutex_unlock(&ps3_gpu_mutex);
  570. if (error < 0) {
  571. dev_err(&dev->core, "Failed to initialize channels\n");
  572. error = -ETIMEDOUT;
  573. goto out_unmap_reports;
  574. }
  575. ps3vram_cache_init(dev);
  576. ps3vram_proc_init(dev);
  577. queue = blk_alloc_queue(GFP_KERNEL);
  578. if (!queue) {
  579. dev_err(&dev->core, "blk_alloc_queue failed\n");
  580. error = -ENOMEM;
  581. goto out_cache_cleanup;
  582. }
  583. priv->queue = queue;
  584. queue->queuedata = dev;
  585. blk_queue_make_request(queue, ps3vram_make_request);
  586. blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS);
  587. blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS);
  588. blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE);
  589. blk_queue_max_sectors(queue, SAFE_MAX_SECTORS);
  590. gendisk = alloc_disk(1);
  591. if (!gendisk) {
  592. dev_err(&dev->core, "alloc_disk failed\n");
  593. error = -ENOMEM;
  594. goto fail_cleanup_queue;
  595. }
  596. priv->gendisk = gendisk;
  597. gendisk->major = ps3vram_major;
  598. gendisk->first_minor = 0;
  599. gendisk->fops = &ps3vram_fops;
  600. gendisk->queue = queue;
  601. gendisk->private_data = dev;
  602. gendisk->driverfs_dev = &dev->core;
  603. strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
  604. set_capacity(gendisk, priv->size >> 9);
  605. dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
  606. gendisk->disk_name, get_capacity(gendisk) >> 11);
  607. add_disk(gendisk);
  608. return 0;
  609. fail_cleanup_queue:
  610. blk_cleanup_queue(queue);
  611. out_cache_cleanup:
  612. remove_proc_entry(DEVICE_NAME, NULL);
  613. ps3vram_cache_cleanup(dev);
  614. out_unmap_reports:
  615. iounmap(priv->reports);
  616. out_unmap_ctrl:
  617. iounmap(priv->ctrl);
  618. out_unmap_vram:
  619. iounmap(priv->ddr_base);
  620. out_unmap_context:
  621. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
  622. XDR_BUF_SIZE, CBE_IOPTE_M);
  623. out_free_context:
  624. lv1_gpu_context_free(priv->context_handle);
  625. out_free_memory:
  626. lv1_gpu_memory_free(priv->memory_handle);
  627. out_close_gpu:
  628. ps3_close_hv_device(dev);
  629. out_free_xdr_buf:
  630. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  631. fail_free_priv:
  632. kfree(priv);
  633. dev->core.driver_data = NULL;
  634. fail:
  635. return error;
  636. }
  637. static int ps3vram_remove(struct ps3_system_bus_device *dev)
  638. {
  639. struct ps3vram_priv *priv = dev->core.driver_data;
  640. del_gendisk(priv->gendisk);
  641. put_disk(priv->gendisk);
  642. blk_cleanup_queue(priv->queue);
  643. remove_proc_entry(DEVICE_NAME, NULL);
  644. ps3vram_cache_cleanup(dev);
  645. iounmap(priv->reports);
  646. iounmap(priv->ctrl);
  647. iounmap(priv->ddr_base);
  648. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  649. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  650. XDR_BUF_SIZE, CBE_IOPTE_M);
  651. lv1_gpu_context_free(priv->context_handle);
  652. lv1_gpu_memory_free(priv->memory_handle);
  653. ps3_close_hv_device(dev);
  654. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  655. kfree(priv);
  656. dev->core.driver_data = NULL;
  657. return 0;
  658. }
  659. static struct ps3_system_bus_driver ps3vram = {
  660. .match_id = PS3_MATCH_ID_GPU,
  661. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  662. .core.name = DEVICE_NAME,
  663. .core.owner = THIS_MODULE,
  664. .probe = ps3vram_probe,
  665. .remove = ps3vram_remove,
  666. .shutdown = ps3vram_remove,
  667. };
  668. static int __init ps3vram_init(void)
  669. {
  670. int error;
  671. if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
  672. return -ENODEV;
  673. error = register_blkdev(0, DEVICE_NAME);
  674. if (error <= 0) {
  675. pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
  676. return error;
  677. }
  678. ps3vram_major = error;
  679. pr_info("%s: registered block device major %d\n", DEVICE_NAME,
  680. ps3vram_major);
  681. error = ps3_system_bus_driver_register(&ps3vram);
  682. if (error)
  683. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  684. return error;
  685. }
  686. static void __exit ps3vram_exit(void)
  687. {
  688. ps3_system_bus_driver_unregister(&ps3vram);
  689. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  690. }
  691. module_init(ps3vram_init);
  692. module_exit(ps3vram_exit);
  693. MODULE_LICENSE("GPL");
  694. MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
  695. MODULE_AUTHOR("Sony Corporation");
  696. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);