pxa2xx-i2s.c 7.6 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * lrg@slimlogic.co.uk
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <linux/platform_device.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc.h>
  23. #include <sound/pxa2xx-lib.h>
  24. #include <mach/hardware.h>
  25. #include <mach/pxa-regs.h>
  26. #include <mach/pxa2xx-gpio.h>
  27. #include <mach/audio.h>
  28. #include "pxa2xx-pcm.h"
  29. #include "pxa2xx-i2s.h"
  30. struct pxa2xx_gpio {
  31. u32 sys;
  32. u32 rx;
  33. u32 tx;
  34. u32 clk;
  35. u32 frm;
  36. };
  37. struct pxa_i2s_port {
  38. u32 sadiv;
  39. u32 sacr0;
  40. u32 sacr1;
  41. u32 saimr;
  42. int master;
  43. u32 fmt;
  44. };
  45. static struct pxa_i2s_port pxa_i2s;
  46. static struct clk *clk_i2s;
  47. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  48. .name = "I2S PCM Stereo out",
  49. .dev_addr = __PREG(SADR),
  50. .drcmr = &DRCMRTXSADR,
  51. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  52. DCMD_BURST32 | DCMD_WIDTH4,
  53. };
  54. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  55. .name = "I2S PCM Stereo in",
  56. .dev_addr = __PREG(SADR),
  57. .drcmr = &DRCMRRXSADR,
  58. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  59. DCMD_BURST32 | DCMD_WIDTH4,
  60. };
  61. static struct pxa2xx_gpio gpio_bus[] = {
  62. { /* I2S SoC Slave */
  63. .rx = GPIO29_SDATA_IN_I2S_MD,
  64. .tx = GPIO30_SDATA_OUT_I2S_MD,
  65. .clk = GPIO28_BITCLK_IN_I2S_MD,
  66. .frm = GPIO31_SYNC_I2S_MD,
  67. },
  68. { /* I2S SoC Master */
  69. .rx = GPIO29_SDATA_IN_I2S_MD,
  70. .tx = GPIO30_SDATA_OUT_I2S_MD,
  71. .clk = GPIO28_BITCLK_OUT_I2S_MD,
  72. .frm = GPIO31_SYNC_I2S_MD,
  73. },
  74. };
  75. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
  76. {
  77. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  78. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  79. if (IS_ERR(clk_i2s))
  80. return PTR_ERR(clk_i2s);
  81. if (!cpu_dai->active) {
  82. SACR0 |= SACR0_RST;
  83. SACR0 = 0;
  84. }
  85. return 0;
  86. }
  87. /* wait for I2S controller to be ready */
  88. static int pxa_i2s_wait(void)
  89. {
  90. int i;
  91. /* flush the Rx FIFO */
  92. for(i = 0; i < 16; i++)
  93. SADR;
  94. return 0;
  95. }
  96. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  97. unsigned int fmt)
  98. {
  99. /* interface format */
  100. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  101. case SND_SOC_DAIFMT_I2S:
  102. pxa_i2s.fmt = 0;
  103. break;
  104. case SND_SOC_DAIFMT_LEFT_J:
  105. pxa_i2s.fmt = SACR1_AMSL;
  106. break;
  107. }
  108. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  109. case SND_SOC_DAIFMT_CBS_CFS:
  110. pxa_i2s.master = 1;
  111. break;
  112. case SND_SOC_DAIFMT_CBM_CFS:
  113. pxa_i2s.master = 0;
  114. break;
  115. default:
  116. break;
  117. }
  118. return 0;
  119. }
  120. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  121. int clk_id, unsigned int freq, int dir)
  122. {
  123. if (clk_id != PXA2XX_I2S_SYSCLK)
  124. return -ENODEV;
  125. if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
  126. pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
  127. return 0;
  128. }
  129. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  130. struct snd_pcm_hw_params *params)
  131. {
  132. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  133. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  134. pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
  135. pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
  136. pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
  137. pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
  138. BUG_ON(IS_ERR(clk_i2s));
  139. clk_enable(clk_i2s);
  140. pxa_i2s_wait();
  141. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  142. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
  143. else
  144. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
  145. /* is port used by another stream */
  146. if (!(SACR0 & SACR0_ENB)) {
  147. SACR0 = 0;
  148. SACR1 = 0;
  149. if (pxa_i2s.master)
  150. SACR0 |= SACR0_BCKD;
  151. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  152. SACR1 |= pxa_i2s.fmt;
  153. }
  154. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  155. SAIMR |= SAIMR_TFS;
  156. else
  157. SAIMR |= SAIMR_RFS;
  158. switch (params_rate(params)) {
  159. case 8000:
  160. SADIV = 0x48;
  161. break;
  162. case 11025:
  163. SADIV = 0x34;
  164. break;
  165. case 16000:
  166. SADIV = 0x24;
  167. break;
  168. case 22050:
  169. SADIV = 0x1a;
  170. break;
  171. case 44100:
  172. SADIV = 0xd;
  173. break;
  174. case 48000:
  175. SADIV = 0xc;
  176. break;
  177. case 96000: /* not in manual and possibly slightly inaccurate */
  178. SADIV = 0x6;
  179. break;
  180. }
  181. return 0;
  182. }
  183. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  184. {
  185. int ret = 0;
  186. switch (cmd) {
  187. case SNDRV_PCM_TRIGGER_START:
  188. SACR0 |= SACR0_ENB;
  189. break;
  190. case SNDRV_PCM_TRIGGER_RESUME:
  191. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  192. case SNDRV_PCM_TRIGGER_STOP:
  193. case SNDRV_PCM_TRIGGER_SUSPEND:
  194. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  195. break;
  196. default:
  197. ret = -EINVAL;
  198. }
  199. return ret;
  200. }
  201. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
  202. {
  203. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  204. SACR1 |= SACR1_DRPL;
  205. SAIMR &= ~SAIMR_TFS;
  206. } else {
  207. SACR1 |= SACR1_DREC;
  208. SAIMR &= ~SAIMR_RFS;
  209. }
  210. if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
  211. SACR0 &= ~SACR0_ENB;
  212. pxa_i2s_wait();
  213. clk_disable(clk_i2s);
  214. }
  215. clk_put(clk_i2s);
  216. }
  217. #ifdef CONFIG_PM
  218. static int pxa2xx_i2s_suspend(struct platform_device *dev,
  219. struct snd_soc_dai *dai)
  220. {
  221. if (!dai->active)
  222. return 0;
  223. /* store registers */
  224. pxa_i2s.sacr0 = SACR0;
  225. pxa_i2s.sacr1 = SACR1;
  226. pxa_i2s.saimr = SAIMR;
  227. pxa_i2s.sadiv = SADIV;
  228. /* deactivate link */
  229. SACR0 &= ~SACR0_ENB;
  230. pxa_i2s_wait();
  231. return 0;
  232. }
  233. static int pxa2xx_i2s_resume(struct platform_device *pdev,
  234. struct snd_soc_dai *dai)
  235. {
  236. if (!dai->active)
  237. return 0;
  238. pxa_i2s_wait();
  239. SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
  240. SACR1 = pxa_i2s.sacr1;
  241. SAIMR = pxa_i2s.saimr;
  242. SADIV = pxa_i2s.sadiv;
  243. SACR0 |= SACR0_ENB;
  244. return 0;
  245. }
  246. #else
  247. #define pxa2xx_i2s_suspend NULL
  248. #define pxa2xx_i2s_resume NULL
  249. #endif
  250. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  251. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  252. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  253. struct snd_soc_dai pxa_i2s_dai = {
  254. .name = "pxa2xx-i2s",
  255. .id = 0,
  256. .type = SND_SOC_DAI_I2S,
  257. .suspend = pxa2xx_i2s_suspend,
  258. .resume = pxa2xx_i2s_resume,
  259. .playback = {
  260. .channels_min = 2,
  261. .channels_max = 2,
  262. .rates = PXA2XX_I2S_RATES,
  263. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  264. .capture = {
  265. .channels_min = 2,
  266. .channels_max = 2,
  267. .rates = PXA2XX_I2S_RATES,
  268. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  269. .ops = {
  270. .startup = pxa2xx_i2s_startup,
  271. .shutdown = pxa2xx_i2s_shutdown,
  272. .trigger = pxa2xx_i2s_trigger,
  273. .hw_params = pxa2xx_i2s_hw_params,},
  274. .dai_ops = {
  275. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  276. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  277. },
  278. };
  279. EXPORT_SYMBOL_GPL(pxa_i2s_dai);
  280. static int pxa2xx_i2s_probe(struct platform_device *dev)
  281. {
  282. clk_i2s = clk_get(&dev->dev, "I2SCLK");
  283. return IS_ERR(clk_i2s) ? PTR_ERR(clk_i2s) : 0;
  284. }
  285. static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
  286. {
  287. clk_put(clk_i2s);
  288. clk_i2s = ERR_PTR(-ENOENT);
  289. return 0;
  290. }
  291. static struct platform_driver pxa2xx_i2s_driver = {
  292. .probe = pxa2xx_i2s_probe,
  293. .remove = __devexit_p(pxa2xx_i2s_remove),
  294. .driver = {
  295. .name = "pxa2xx-i2s",
  296. .owner = THIS_MODULE,
  297. },
  298. };
  299. static int __init pxa2xx_i2s_init(void)
  300. {
  301. if (cpu_is_pxa27x())
  302. gpio_bus[1].sys = GPIO113_I2S_SYSCLK_MD;
  303. else
  304. gpio_bus[1].sys = GPIO32_SYSCLK_I2S_MD;
  305. clk_i2s = ERR_PTR(-ENOENT);
  306. return platform_driver_register(&pxa2xx_i2s_driver);
  307. }
  308. static void __exit pxa2xx_i2s_exit(void)
  309. {
  310. platform_driver_unregister(&pxa2xx_i2s_driver);
  311. }
  312. module_init(pxa2xx_i2s_init);
  313. module_exit(pxa2xx_i2s_exit);
  314. /* Module information */
  315. MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
  316. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  317. MODULE_LICENSE("GPL");