wm8962.c 53 KB

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  1. /*
  2. * wm8962.c -- WM8962 ALSA SoC Audio driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/gcd.h>
  19. #include <linux/i2c.h>
  20. #include <linux/input.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/slab.h>
  24. #include <linux/workqueue.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/soc.h>
  29. #include <sound/soc-dapm.h>
  30. #include <sound/initval.h>
  31. #include <sound/tlv.h>
  32. #include <sound/wm8962.h>
  33. #include "wm8962.h"
  34. #define WM8962_NUM_SUPPLIES 8
  35. static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
  36. "DCVDD",
  37. "DBVDD",
  38. "AVDD",
  39. "CPVDD",
  40. "MICVDD",
  41. "PLLVDD",
  42. "SPKVDD1",
  43. "SPKVDD2",
  44. };
  45. /* codec private data */
  46. struct wm8962_priv {
  47. struct snd_soc_codec *codec;
  48. u16 reg_cache[WM8962_MAX_REGISTER + 1];
  49. int sysclk;
  50. int sysclk_rate;
  51. int bclk; /* Desired BCLK */
  52. int lrclk;
  53. int fll_src;
  54. int fll_fref;
  55. int fll_fout;
  56. struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
  57. struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
  58. #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  59. struct input_dev *beep;
  60. struct work_struct beep_work;
  61. int beep_rate;
  62. #endif
  63. };
  64. /* We can't use the same notifier block for more than one supply and
  65. * there's no way I can see to get from a callback to the caller
  66. * except container_of().
  67. */
  68. #define WM8962_REGULATOR_EVENT(n) \
  69. static int wm8962_regulator_event_##n(struct notifier_block *nb, \
  70. unsigned long event, void *data) \
  71. { \
  72. struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
  73. disable_nb[n]); \
  74. if (event & REGULATOR_EVENT_DISABLE) { \
  75. wm8962->codec->cache_sync = 1; \
  76. } \
  77. return 0; \
  78. }
  79. WM8962_REGULATOR_EVENT(0)
  80. WM8962_REGULATOR_EVENT(1)
  81. WM8962_REGULATOR_EVENT(2)
  82. WM8962_REGULATOR_EVENT(3)
  83. WM8962_REGULATOR_EVENT(4)
  84. WM8962_REGULATOR_EVENT(5)
  85. WM8962_REGULATOR_EVENT(6)
  86. WM8962_REGULATOR_EVENT(7)
  87. static int wm8962_volatile_register(unsigned int reg)
  88. {
  89. if (wm8962_reg_access[reg].vol)
  90. return 1;
  91. else
  92. return 0;
  93. }
  94. static int wm8962_readable_register(unsigned int reg)
  95. {
  96. if (wm8962_reg_access[reg].read)
  97. return 1;
  98. else
  99. return 0;
  100. }
  101. static int wm8962_reset(struct snd_soc_codec *codec)
  102. {
  103. return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
  104. }
  105. static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
  106. static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
  107. static const unsigned int mixinpga_tlv[] = {
  108. TLV_DB_RANGE_HEAD(7),
  109. 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
  110. 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
  111. 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
  112. 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
  113. 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
  114. };
  115. static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
  116. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  117. static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
  118. static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
  119. static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
  120. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  121. static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
  122. static const unsigned int classd_tlv[] = {
  123. TLV_DB_RANGE_HEAD(7),
  124. 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
  125. 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
  126. };
  127. /* The VU bits for the headphones are in a different register to the mute
  128. * bits and only take effect on the PGA if it is actually powered.
  129. */
  130. static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
  131. struct snd_ctl_elem_value *ucontrol)
  132. {
  133. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  134. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  135. u16 *reg_cache = wm8962->reg_cache;
  136. int ret;
  137. /* Apply the update (if any) */
  138. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  139. if (ret == 0)
  140. return 0;
  141. /* If the left PGA is enabled hit that VU bit... */
  142. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
  143. return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
  144. reg_cache[WM8962_HPOUTL_VOLUME]);
  145. /* ...otherwise the right. The VU is stereo. */
  146. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
  147. return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
  148. reg_cache[WM8962_HPOUTR_VOLUME]);
  149. return 0;
  150. }
  151. /* The VU bits for the speakers are in a different register to the mute
  152. * bits and only take effect on the PGA if it is actually powered.
  153. */
  154. static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
  155. struct snd_ctl_elem_value *ucontrol)
  156. {
  157. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  158. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  159. u16 *reg_cache = wm8962->reg_cache;
  160. int ret;
  161. /* Apply the update (if any) */
  162. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  163. if (ret == 0)
  164. return 0;
  165. /* If the left PGA is enabled hit that VU bit... */
  166. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
  167. return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
  168. reg_cache[WM8962_SPKOUTL_VOLUME]);
  169. /* ...otherwise the right. The VU is stereo. */
  170. if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
  171. return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
  172. reg_cache[WM8962_SPKOUTR_VOLUME]);
  173. return 0;
  174. }
  175. static const struct snd_kcontrol_new wm8962_snd_controls[] = {
  176. SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
  177. SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
  178. mixin_tlv),
  179. SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
  180. mixinpga_tlv),
  181. SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
  182. mixin_tlv),
  183. SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
  184. mixin_tlv),
  185. SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
  186. mixinpga_tlv),
  187. SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
  188. mixin_tlv),
  189. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
  190. WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
  191. SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
  192. WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
  193. SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
  194. WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
  195. SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
  196. WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
  197. SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
  198. WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
  199. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
  200. WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
  201. SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
  202. SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
  203. 5, 1, 0),
  204. SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
  205. SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
  206. WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
  207. SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
  208. snd_soc_get_volsw, wm8962_put_hp_sw),
  209. SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
  210. 7, 1, 0),
  211. SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
  212. hp_tlv),
  213. SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
  214. WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
  215. SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
  216. 3, 7, 0, bypass_tlv),
  217. SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
  218. 0, 7, 0, bypass_tlv),
  219. SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
  220. 7, 1, 1, inmix_tlv),
  221. SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
  222. 6, 1, 1, inmix_tlv),
  223. SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
  224. 3, 7, 0, bypass_tlv),
  225. SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
  226. 0, 7, 0, bypass_tlv),
  227. SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
  228. 7, 1, 1, inmix_tlv),
  229. SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
  230. 6, 1, 1, inmix_tlv),
  231. SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
  232. classd_tlv),
  233. };
  234. static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
  235. SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
  236. SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
  237. snd_soc_get_volsw, wm8962_put_spk_sw),
  238. SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
  239. SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
  240. SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  241. 3, 7, 0, bypass_tlv),
  242. SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  243. 0, 7, 0, bypass_tlv),
  244. SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  245. 7, 1, 1, inmix_tlv),
  246. SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  247. 6, 1, 1, inmix_tlv),
  248. SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  249. 7, 1, 0, inmix_tlv),
  250. SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  251. 6, 1, 0, inmix_tlv),
  252. };
  253. static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
  254. SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
  255. WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
  256. SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
  257. snd_soc_get_volsw, wm8962_put_spk_sw),
  258. SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
  259. 7, 1, 0),
  260. SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
  261. WM8962_SPEAKER_MIXER_4, 8, 1, 1),
  262. SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
  263. 3, 7, 0, bypass_tlv),
  264. SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
  265. 0, 7, 0, bypass_tlv),
  266. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
  267. 7, 1, 1, inmix_tlv),
  268. SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
  269. 6, 1, 1, inmix_tlv),
  270. SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  271. 7, 1, 0, inmix_tlv),
  272. SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  273. 6, 1, 0, inmix_tlv),
  274. SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
  275. 3, 7, 0, bypass_tlv),
  276. SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
  277. 0, 7, 0, bypass_tlv),
  278. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
  279. 7, 1, 1, inmix_tlv),
  280. SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
  281. 6, 1, 1, inmix_tlv),
  282. SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
  283. 5, 1, 0, inmix_tlv),
  284. SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
  285. 4, 1, 0, inmix_tlv),
  286. };
  287. static int sysclk_event(struct snd_soc_dapm_widget *w,
  288. struct snd_kcontrol *kcontrol, int event)
  289. {
  290. struct snd_soc_codec *codec = w->codec;
  291. int src;
  292. int fll;
  293. src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
  294. switch (src) {
  295. case 0: /* MCLK */
  296. fll = 0;
  297. break;
  298. case 0x200: /* FLL */
  299. fll = 1;
  300. break;
  301. default:
  302. dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
  303. return -EINVAL;
  304. }
  305. switch (event) {
  306. case SND_SOC_DAPM_PRE_PMU:
  307. if (fll)
  308. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  309. WM8962_FLL_ENA, WM8962_FLL_ENA);
  310. break;
  311. case SND_SOC_DAPM_POST_PMD:
  312. if (fll)
  313. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  314. WM8962_FLL_ENA, 0);
  315. break;
  316. default:
  317. BUG();
  318. return -EINVAL;
  319. }
  320. return 0;
  321. }
  322. static int cp_event(struct snd_soc_dapm_widget *w,
  323. struct snd_kcontrol *kcontrol, int event)
  324. {
  325. switch (event) {
  326. case SND_SOC_DAPM_POST_PMU:
  327. msleep(5);
  328. break;
  329. default:
  330. BUG();
  331. return -EINVAL;
  332. }
  333. return 0;
  334. }
  335. static int hp_event(struct snd_soc_dapm_widget *w,
  336. struct snd_kcontrol *kcontrol, int event)
  337. {
  338. struct snd_soc_codec *codec = w->codec;
  339. int timeout;
  340. int reg;
  341. int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
  342. WM8962_DCS_STARTUP_DONE_HP1R);
  343. switch (event) {
  344. case SND_SOC_DAPM_POST_PMU:
  345. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  346. WM8962_HP1L_ENA | WM8962_HP1R_ENA,
  347. WM8962_HP1L_ENA | WM8962_HP1R_ENA);
  348. udelay(20);
  349. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  350. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
  351. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
  352. /* Start the DC servo */
  353. snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
  354. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  355. WM8962_HP1L_DCS_STARTUP |
  356. WM8962_HP1R_DCS_STARTUP,
  357. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  358. WM8962_HP1L_DCS_STARTUP |
  359. WM8962_HP1R_DCS_STARTUP);
  360. /* Wait for it to complete, should be well under 100ms */
  361. timeout = 0;
  362. do {
  363. msleep(1);
  364. reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
  365. if (reg < 0) {
  366. dev_err(codec->dev,
  367. "Failed to read DCS status: %d\n",
  368. reg);
  369. continue;
  370. }
  371. dev_dbg(codec->dev, "DCS status: %x\n", reg);
  372. } while (++timeout < 200 && (reg & expected) != expected);
  373. if ((reg & expected) != expected)
  374. dev_err(codec->dev, "DC servo timed out\n");
  375. else
  376. dev_dbg(codec->dev, "DC servo complete after %dms\n",
  377. timeout);
  378. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  379. WM8962_HP1L_ENA_OUTP |
  380. WM8962_HP1R_ENA_OUTP,
  381. WM8962_HP1L_ENA_OUTP |
  382. WM8962_HP1R_ENA_OUTP);
  383. udelay(20);
  384. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  385. WM8962_HP1L_RMV_SHORT |
  386. WM8962_HP1R_RMV_SHORT,
  387. WM8962_HP1L_RMV_SHORT |
  388. WM8962_HP1R_RMV_SHORT);
  389. break;
  390. case SND_SOC_DAPM_PRE_PMD:
  391. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  392. WM8962_HP1L_RMV_SHORT |
  393. WM8962_HP1R_RMV_SHORT, 0);
  394. udelay(20);
  395. snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
  396. WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
  397. WM8962_HP1L_DCS_STARTUP |
  398. WM8962_HP1R_DCS_STARTUP,
  399. 0);
  400. snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
  401. WM8962_HP1L_ENA | WM8962_HP1R_ENA |
  402. WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
  403. WM8962_HP1L_ENA_OUTP |
  404. WM8962_HP1R_ENA_OUTP, 0);
  405. break;
  406. default:
  407. BUG();
  408. return -EINVAL;
  409. }
  410. return 0;
  411. }
  412. /* VU bits for the output PGAs only take effect while the PGA is powered */
  413. static int out_pga_event(struct snd_soc_dapm_widget *w,
  414. struct snd_kcontrol *kcontrol, int event)
  415. {
  416. struct snd_soc_codec *codec = w->codec;
  417. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  418. u16 *reg_cache = wm8962->reg_cache;
  419. int reg;
  420. switch (w->shift) {
  421. case WM8962_HPOUTR_PGA_ENA_SHIFT:
  422. reg = WM8962_HPOUTR_VOLUME;
  423. break;
  424. case WM8962_HPOUTL_PGA_ENA_SHIFT:
  425. reg = WM8962_HPOUTL_VOLUME;
  426. break;
  427. case WM8962_SPKOUTR_PGA_ENA_SHIFT:
  428. reg = WM8962_SPKOUTR_VOLUME;
  429. break;
  430. case WM8962_SPKOUTL_PGA_ENA_SHIFT:
  431. reg = WM8962_SPKOUTL_VOLUME;
  432. break;
  433. default:
  434. BUG();
  435. return -EINVAL;
  436. }
  437. switch (event) {
  438. case SND_SOC_DAPM_POST_PMU:
  439. return snd_soc_write(codec, reg, reg_cache[reg]);
  440. default:
  441. BUG();
  442. return -EINVAL;
  443. }
  444. }
  445. static const char *st_text[] = { "None", "Right", "Left" };
  446. static const struct soc_enum str_enum =
  447. SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
  448. static const struct snd_kcontrol_new str_mux =
  449. SOC_DAPM_ENUM("Right Sidetone", str_enum);
  450. static const struct soc_enum stl_enum =
  451. SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
  452. static const struct snd_kcontrol_new stl_mux =
  453. SOC_DAPM_ENUM("Left Sidetone", stl_enum);
  454. static const char *outmux_text[] = { "DAC", "Mixer" };
  455. static const struct soc_enum spkoutr_enum =
  456. SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
  457. static const struct snd_kcontrol_new spkoutr_mux =
  458. SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
  459. static const struct soc_enum spkoutl_enum =
  460. SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
  461. static const struct snd_kcontrol_new spkoutl_mux =
  462. SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
  463. static const struct soc_enum hpoutr_enum =
  464. SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
  465. static const struct snd_kcontrol_new hpoutr_mux =
  466. SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
  467. static const struct soc_enum hpoutl_enum =
  468. SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
  469. static const struct snd_kcontrol_new hpoutl_mux =
  470. SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
  471. static const struct snd_kcontrol_new inpgal[] = {
  472. SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
  473. SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
  474. SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
  475. SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
  476. };
  477. static const struct snd_kcontrol_new inpgar[] = {
  478. SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
  479. SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
  480. SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
  481. SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
  482. };
  483. static const struct snd_kcontrol_new mixinl[] = {
  484. SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
  485. SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
  486. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
  487. };
  488. static const struct snd_kcontrol_new mixinr[] = {
  489. SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
  490. SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
  491. SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
  492. };
  493. static const struct snd_kcontrol_new hpmixl[] = {
  494. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
  495. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
  496. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
  497. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
  498. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
  499. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
  500. };
  501. static const struct snd_kcontrol_new hpmixr[] = {
  502. SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
  503. SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
  504. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
  505. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
  506. SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
  507. SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
  508. };
  509. static const struct snd_kcontrol_new spkmixl[] = {
  510. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
  511. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
  512. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
  513. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
  514. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
  515. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
  516. };
  517. static const struct snd_kcontrol_new spkmixr[] = {
  518. SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
  519. SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
  520. SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
  521. SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
  522. SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
  523. SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
  524. };
  525. static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
  526. SND_SOC_DAPM_INPUT("IN1L"),
  527. SND_SOC_DAPM_INPUT("IN1R"),
  528. SND_SOC_DAPM_INPUT("IN2L"),
  529. SND_SOC_DAPM_INPUT("IN2R"),
  530. SND_SOC_DAPM_INPUT("IN3L"),
  531. SND_SOC_DAPM_INPUT("IN3R"),
  532. SND_SOC_DAPM_INPUT("IN4L"),
  533. SND_SOC_DAPM_INPUT("IN4R"),
  534. SND_SOC_DAPM_INPUT("Beep"),
  535. SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
  536. SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
  537. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
  538. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  539. SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
  540. SND_SOC_DAPM_POST_PMU),
  541. SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
  542. SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
  543. inpgal, ARRAY_SIZE(inpgal)),
  544. SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
  545. inpgar, ARRAY_SIZE(inpgar)),
  546. SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
  547. mixinl, ARRAY_SIZE(mixinl)),
  548. SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
  549. mixinr, ARRAY_SIZE(mixinr)),
  550. SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
  551. SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
  552. SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
  553. SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
  554. SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
  555. SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
  556. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  557. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  558. SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
  559. hpmixl, ARRAY_SIZE(hpmixl)),
  560. SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
  561. hpmixr, ARRAY_SIZE(hpmixr)),
  562. SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
  563. out_pga_event, SND_SOC_DAPM_POST_PMU),
  564. SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
  565. out_pga_event, SND_SOC_DAPM_POST_PMU),
  566. SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
  567. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  568. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  569. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  570. };
  571. static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
  572. SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
  573. spkmixl, ARRAY_SIZE(spkmixl)),
  574. SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  575. out_pga_event, SND_SOC_DAPM_POST_PMU),
  576. SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  577. SND_SOC_DAPM_OUTPUT("SPKOUT"),
  578. };
  579. static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
  580. SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
  581. spkmixl, ARRAY_SIZE(spkmixl)),
  582. SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
  583. spkmixr, ARRAY_SIZE(spkmixr)),
  584. SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
  585. out_pga_event, SND_SOC_DAPM_POST_PMU),
  586. SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
  587. out_pga_event, SND_SOC_DAPM_POST_PMU),
  588. SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
  589. SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
  590. SND_SOC_DAPM_OUTPUT("SPKOUTL"),
  591. SND_SOC_DAPM_OUTPUT("SPKOUTR"),
  592. };
  593. static const struct snd_soc_dapm_route wm8962_intercon[] = {
  594. { "INPGAL", "IN1L Switch", "IN1L" },
  595. { "INPGAL", "IN2L Switch", "IN2L" },
  596. { "INPGAL", "IN3L Switch", "IN3L" },
  597. { "INPGAL", "IN4L Switch", "IN4L" },
  598. { "INPGAR", "IN1R Switch", "IN1R" },
  599. { "INPGAR", "IN2R Switch", "IN2R" },
  600. { "INPGAR", "IN3R Switch", "IN3R" },
  601. { "INPGAR", "IN4R Switch", "IN4R" },
  602. { "MIXINL", "IN2L Switch", "IN2L" },
  603. { "MIXINL", "IN3L Switch", "IN3L" },
  604. { "MIXINL", "PGA Switch", "INPGAL" },
  605. { "MIXINR", "IN2R Switch", "IN2R" },
  606. { "MIXINR", "IN3R Switch", "IN3R" },
  607. { "MIXINR", "PGA Switch", "INPGAR" },
  608. { "ADCL", NULL, "SYSCLK" },
  609. { "ADCL", NULL, "TOCLK" },
  610. { "ADCL", NULL, "MIXINL" },
  611. { "ADCR", NULL, "SYSCLK" },
  612. { "ADCR", NULL, "TOCLK" },
  613. { "ADCR", NULL, "MIXINR" },
  614. { "STL", "Left", "ADCL" },
  615. { "STL", "Right", "ADCR" },
  616. { "STR", "Left", "ADCL" },
  617. { "STR", "Right", "ADCR" },
  618. { "DACL", NULL, "SYSCLK" },
  619. { "DACL", NULL, "TOCLK" },
  620. { "DACL", NULL, "Beep" },
  621. { "DACL", NULL, "STL" },
  622. { "DACR", NULL, "SYSCLK" },
  623. { "DACR", NULL, "TOCLK" },
  624. { "DACR", NULL, "Beep" },
  625. { "DACR", NULL, "STR" },
  626. { "HPMIXL", "IN4L Switch", "IN4L" },
  627. { "HPMIXL", "IN4R Switch", "IN4R" },
  628. { "HPMIXL", "DACL Switch", "DACL" },
  629. { "HPMIXL", "DACR Switch", "DACR" },
  630. { "HPMIXL", "MIXINL Switch", "MIXINL" },
  631. { "HPMIXL", "MIXINR Switch", "MIXINR" },
  632. { "HPMIXR", "IN4L Switch", "IN4L" },
  633. { "HPMIXR", "IN4R Switch", "IN4R" },
  634. { "HPMIXR", "DACL Switch", "DACL" },
  635. { "HPMIXR", "DACR Switch", "DACR" },
  636. { "HPMIXR", "MIXINL Switch", "MIXINL" },
  637. { "HPMIXR", "MIXINR Switch", "MIXINR" },
  638. { "Left Bypass", NULL, "HPMIXL" },
  639. { "Left Bypass", NULL, "Class G" },
  640. { "Right Bypass", NULL, "HPMIXR" },
  641. { "Right Bypass", NULL, "Class G" },
  642. { "HPOUTL PGA", "Mixer", "Left Bypass" },
  643. { "HPOUTL PGA", "DAC", "DACL" },
  644. { "HPOUTR PGA", "Mixer", "Right Bypass" },
  645. { "HPOUTR PGA", "DAC", "DACR" },
  646. { "HPOUT", NULL, "HPOUTL PGA" },
  647. { "HPOUT", NULL, "HPOUTR PGA" },
  648. { "HPOUT", NULL, "Charge Pump" },
  649. { "HPOUT", NULL, "SYSCLK" },
  650. { "HPOUT", NULL, "TOCLK" },
  651. { "HPOUTL", NULL, "HPOUT" },
  652. { "HPOUTR", NULL, "HPOUT" },
  653. };
  654. static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
  655. { "Speaker Mixer", "IN4L Switch", "IN4L" },
  656. { "Speaker Mixer", "IN4R Switch", "IN4R" },
  657. { "Speaker Mixer", "DACL Switch", "DACL" },
  658. { "Speaker Mixer", "DACR Switch", "DACR" },
  659. { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
  660. { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
  661. { "Speaker PGA", "Mixer", "Speaker Mixer" },
  662. { "Speaker PGA", "DAC", "DACL" },
  663. { "Speaker Output", NULL, "Speaker PGA" },
  664. { "Speaker Output", NULL, "SYSCLK" },
  665. { "Speaker Output", NULL, "TOCLK" },
  666. { "SPKOUT", NULL, "Speaker Output" },
  667. };
  668. static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
  669. { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
  670. { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
  671. { "SPKOUTL Mixer", "DACL Switch", "DACL" },
  672. { "SPKOUTL Mixer", "DACR Switch", "DACR" },
  673. { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
  674. { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
  675. { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
  676. { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
  677. { "SPKOUTR Mixer", "DACL Switch", "DACL" },
  678. { "SPKOUTR Mixer", "DACR Switch", "DACR" },
  679. { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
  680. { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
  681. { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
  682. { "SPKOUTL PGA", "DAC", "DACL" },
  683. { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
  684. { "SPKOUTR PGA", "DAC", "DACR" },
  685. { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
  686. { "SPKOUTL Output", NULL, "SYSCLK" },
  687. { "SPKOUTL Output", NULL, "TOCLK" },
  688. { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
  689. { "SPKOUTR Output", NULL, "SYSCLK" },
  690. { "SPKOUTR Output", NULL, "TOCLK" },
  691. { "SPKOUTL", NULL, "SPKOUTL Output" },
  692. { "SPKOUTR", NULL, "SPKOUTR Output" },
  693. };
  694. static int wm8962_add_widgets(struct snd_soc_codec *codec)
  695. {
  696. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  697. snd_soc_add_controls(codec, wm8962_snd_controls,
  698. ARRAY_SIZE(wm8962_snd_controls));
  699. if (pdata && pdata->spk_mono)
  700. snd_soc_add_controls(codec, wm8962_spk_mono_controls,
  701. ARRAY_SIZE(wm8962_spk_mono_controls));
  702. else
  703. snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
  704. ARRAY_SIZE(wm8962_spk_stereo_controls));
  705. snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
  706. ARRAY_SIZE(wm8962_dapm_widgets));
  707. if (pdata && pdata->spk_mono)
  708. snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
  709. ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
  710. else
  711. snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
  712. ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
  713. snd_soc_dapm_add_routes(codec, wm8962_intercon,
  714. ARRAY_SIZE(wm8962_intercon));
  715. if (pdata && pdata->spk_mono)
  716. snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
  717. ARRAY_SIZE(wm8962_spk_mono_intercon));
  718. else
  719. snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
  720. ARRAY_SIZE(wm8962_spk_stereo_intercon));
  721. snd_soc_dapm_disable_pin(codec, "Beep");
  722. return 0;
  723. }
  724. static void wm8962_sync_cache(struct snd_soc_codec *codec)
  725. {
  726. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  727. int i;
  728. if (!codec->cache_sync)
  729. return;
  730. dev_dbg(codec->dev, "Syncing cache\n");
  731. codec->cache_only = 0;
  732. /* Sync back cached values if they're different from the
  733. * hardware default.
  734. */
  735. for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
  736. if (i == WM8962_SOFTWARE_RESET)
  737. continue;
  738. if (wm8962->reg_cache[i] == wm8962_reg[i])
  739. continue;
  740. snd_soc_write(codec, i, wm8962->reg_cache[i]);
  741. }
  742. codec->cache_sync = 0;
  743. }
  744. /* -1 for reserved values */
  745. static const int bclk_divs[] = {
  746. 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
  747. };
  748. static void wm8962_configure_bclk(struct snd_soc_codec *codec)
  749. {
  750. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  751. int dspclk, i;
  752. int clocking2 = 0;
  753. int aif2 = 0;
  754. if (!wm8962->bclk) {
  755. dev_dbg(codec->dev, "No BCLK rate configured\n");
  756. return;
  757. }
  758. dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
  759. if (dspclk < 0) {
  760. dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
  761. return;
  762. }
  763. dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
  764. switch (dspclk) {
  765. case 0:
  766. dspclk = wm8962->sysclk_rate;
  767. break;
  768. case 1:
  769. dspclk = wm8962->sysclk_rate / 2;
  770. break;
  771. case 2:
  772. dspclk = wm8962->sysclk_rate / 4;
  773. break;
  774. default:
  775. dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
  776. dspclk = wm8962->sysclk;
  777. }
  778. dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
  779. /* We're expecting an exact match */
  780. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  781. if (bclk_divs[i] < 0)
  782. continue;
  783. if (dspclk / bclk_divs[i] == wm8962->bclk) {
  784. dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
  785. bclk_divs[i], wm8962->bclk);
  786. clocking2 |= i;
  787. break;
  788. }
  789. }
  790. if (i == ARRAY_SIZE(bclk_divs)) {
  791. dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
  792. dspclk / wm8962->bclk);
  793. return;
  794. }
  795. aif2 |= wm8962->bclk / wm8962->lrclk;
  796. dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
  797. wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
  798. snd_soc_update_bits(codec, WM8962_CLOCKING2,
  799. WM8962_BCLK_DIV_MASK, clocking2);
  800. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
  801. WM8962_AIF_RATE_MASK, aif2);
  802. }
  803. static int wm8962_set_bias_level(struct snd_soc_codec *codec,
  804. enum snd_soc_bias_level level)
  805. {
  806. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  807. int ret;
  808. if (level == codec->bias_level)
  809. return 0;
  810. switch (level) {
  811. case SND_SOC_BIAS_ON:
  812. break;
  813. case SND_SOC_BIAS_PREPARE:
  814. /* VMID 2*50k */
  815. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  816. WM8962_VMID_SEL_MASK, 0x80);
  817. break;
  818. case SND_SOC_BIAS_STANDBY:
  819. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  820. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  821. wm8962->supplies);
  822. if (ret != 0) {
  823. dev_err(codec->dev,
  824. "Failed to enable supplies: %d\n",
  825. ret);
  826. return ret;
  827. }
  828. wm8962_sync_cache(codec);
  829. snd_soc_update_bits(codec, WM8962_ANTI_POP,
  830. WM8962_STARTUP_BIAS_ENA |
  831. WM8962_VMID_BUF_ENA,
  832. WM8962_STARTUP_BIAS_ENA |
  833. WM8962_VMID_BUF_ENA);
  834. /* Bias enable at 2*50k for ramp */
  835. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  836. WM8962_VMID_SEL_MASK |
  837. WM8962_BIAS_ENA,
  838. WM8962_BIAS_ENA | 0x180);
  839. msleep(5);
  840. snd_soc_update_bits(codec, WM8962_CLOCKING2,
  841. WM8962_CLKREG_OVD,
  842. WM8962_CLKREG_OVD);
  843. wm8962_configure_bclk(codec);
  844. }
  845. /* VMID 2*250k */
  846. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  847. WM8962_VMID_SEL_MASK, 0x100);
  848. break;
  849. case SND_SOC_BIAS_OFF:
  850. snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
  851. WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
  852. snd_soc_update_bits(codec, WM8962_ANTI_POP,
  853. WM8962_STARTUP_BIAS_ENA |
  854. WM8962_VMID_BUF_ENA, 0);
  855. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
  856. wm8962->supplies);
  857. break;
  858. }
  859. codec->bias_level = level;
  860. return 0;
  861. }
  862. static const struct {
  863. int rate;
  864. int reg;
  865. } sr_vals[] = {
  866. { 48000, 0 },
  867. { 44100, 0 },
  868. { 32000, 1 },
  869. { 22050, 2 },
  870. { 24000, 2 },
  871. { 16000, 3 },
  872. { 11025, 4 },
  873. { 12000, 4 },
  874. { 8000, 5 },
  875. { 88200, 6 },
  876. { 96000, 6 },
  877. };
  878. static const int sysclk_rates[] = {
  879. 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
  880. };
  881. static int wm8962_hw_params(struct snd_pcm_substream *substream,
  882. struct snd_pcm_hw_params *params,
  883. struct snd_soc_dai *dai)
  884. {
  885. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  886. struct snd_soc_codec *codec = rtd->codec;
  887. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  888. int rate = params_rate(params);
  889. int i;
  890. int aif0 = 0;
  891. int adctl3 = 0;
  892. int clocking4 = 0;
  893. wm8962->bclk = snd_soc_params_to_bclk(params);
  894. wm8962->lrclk = params_rate(params);
  895. for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
  896. if (sr_vals[i].rate == rate) {
  897. adctl3 |= sr_vals[i].reg;
  898. break;
  899. }
  900. }
  901. if (i == ARRAY_SIZE(sr_vals)) {
  902. dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
  903. return -EINVAL;
  904. }
  905. if (rate % 8000 == 0)
  906. adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
  907. for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
  908. if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
  909. clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
  910. break;
  911. }
  912. }
  913. if (i == ARRAY_SIZE(sysclk_rates)) {
  914. dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
  915. wm8962->sysclk_rate / rate);
  916. return -EINVAL;
  917. }
  918. switch (params_format(params)) {
  919. case SNDRV_PCM_FORMAT_S16_LE:
  920. break;
  921. case SNDRV_PCM_FORMAT_S20_3LE:
  922. aif0 |= 0x40;
  923. break;
  924. case SNDRV_PCM_FORMAT_S24_LE:
  925. aif0 |= 0x80;
  926. break;
  927. case SNDRV_PCM_FORMAT_S32_LE:
  928. aif0 |= 0xc0;
  929. break;
  930. default:
  931. return -EINVAL;
  932. }
  933. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
  934. WM8962_WL_MASK, aif0);
  935. snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
  936. WM8962_SAMPLE_RATE_INT_MODE |
  937. WM8962_SAMPLE_RATE_MASK, adctl3);
  938. snd_soc_update_bits(codec, WM8962_CLOCKING_4,
  939. WM8962_SYSCLK_RATE_MASK, clocking4);
  940. wm8962_configure_bclk(codec);
  941. return 0;
  942. }
  943. static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  944. unsigned int freq, int dir)
  945. {
  946. struct snd_soc_codec *codec = dai->codec;
  947. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  948. int src;
  949. switch (clk_id) {
  950. case WM8962_SYSCLK_MCLK:
  951. wm8962->sysclk = WM8962_SYSCLK_MCLK;
  952. src = 0;
  953. break;
  954. case WM8962_SYSCLK_FLL:
  955. wm8962->sysclk = WM8962_SYSCLK_FLL;
  956. src = 1 << WM8962_SYSCLK_SRC_SHIFT;
  957. WARN_ON(freq != wm8962->fll_fout);
  958. break;
  959. default:
  960. return -EINVAL;
  961. }
  962. snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
  963. src);
  964. wm8962->sysclk_rate = freq;
  965. return 0;
  966. }
  967. static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  968. {
  969. struct snd_soc_codec *codec = dai->codec;
  970. int aif0 = 0;
  971. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  972. case SND_SOC_DAIFMT_DSP_A:
  973. aif0 |= WM8962_LRCLK_INV;
  974. case SND_SOC_DAIFMT_DSP_B:
  975. aif0 |= 3;
  976. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  977. case SND_SOC_DAIFMT_NB_NF:
  978. case SND_SOC_DAIFMT_IB_NF:
  979. break;
  980. default:
  981. return -EINVAL;
  982. }
  983. break;
  984. case SND_SOC_DAIFMT_RIGHT_J:
  985. break;
  986. case SND_SOC_DAIFMT_LEFT_J:
  987. aif0 |= 1;
  988. break;
  989. case SND_SOC_DAIFMT_I2S:
  990. aif0 |= 2;
  991. break;
  992. default:
  993. return -EINVAL;
  994. }
  995. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  996. case SND_SOC_DAIFMT_NB_NF:
  997. break;
  998. case SND_SOC_DAIFMT_IB_NF:
  999. aif0 |= WM8962_BCLK_INV;
  1000. break;
  1001. case SND_SOC_DAIFMT_NB_IF:
  1002. aif0 |= WM8962_LRCLK_INV;
  1003. break;
  1004. case SND_SOC_DAIFMT_IB_IF:
  1005. aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
  1006. break;
  1007. default:
  1008. return -EINVAL;
  1009. }
  1010. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1011. case SND_SOC_DAIFMT_CBM_CFM:
  1012. aif0 |= WM8962_MSTR;
  1013. break;
  1014. case SND_SOC_DAIFMT_CBS_CFS:
  1015. break;
  1016. default:
  1017. return -EINVAL;
  1018. }
  1019. snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
  1020. WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
  1021. WM8962_LRCLK_INV, aif0);
  1022. return 0;
  1023. }
  1024. struct _fll_div {
  1025. u16 fll_fratio;
  1026. u16 fll_outdiv;
  1027. u16 fll_refclk_div;
  1028. u16 n;
  1029. u16 theta;
  1030. u16 lambda;
  1031. };
  1032. /* The size in bits of the FLL divide multiplied by 10
  1033. * to allow rounding later */
  1034. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1035. static struct {
  1036. unsigned int min;
  1037. unsigned int max;
  1038. u16 fll_fratio;
  1039. int ratio;
  1040. } fll_fratios[] = {
  1041. { 0, 64000, 4, 16 },
  1042. { 64000, 128000, 3, 8 },
  1043. { 128000, 256000, 2, 4 },
  1044. { 256000, 1000000, 1, 2 },
  1045. { 1000000, 13500000, 0, 1 },
  1046. };
  1047. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1048. unsigned int Fout)
  1049. {
  1050. unsigned int target;
  1051. unsigned int div;
  1052. unsigned int fratio, gcd_fll;
  1053. int i;
  1054. /* Fref must be <=13.5MHz */
  1055. div = 1;
  1056. fll_div->fll_refclk_div = 0;
  1057. while ((Fref / div) > 13500000) {
  1058. div *= 2;
  1059. fll_div->fll_refclk_div++;
  1060. if (div > 4) {
  1061. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1062. Fref);
  1063. return -EINVAL;
  1064. }
  1065. }
  1066. pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
  1067. /* Apply the division for our remaining calculations */
  1068. Fref /= div;
  1069. /* Fvco should be 90-100MHz; don't check the upper bound */
  1070. div = 2;
  1071. while (Fout * div < 90000000) {
  1072. div++;
  1073. if (div > 64) {
  1074. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1075. Fout);
  1076. return -EINVAL;
  1077. }
  1078. }
  1079. target = Fout * div;
  1080. fll_div->fll_outdiv = div - 1;
  1081. pr_debug("FLL Fvco=%dHz\n", target);
  1082. /* Find an appropraite FLL_FRATIO and factor it out of the target */
  1083. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1084. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1085. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1086. fratio = fll_fratios[i].ratio;
  1087. break;
  1088. }
  1089. }
  1090. if (i == ARRAY_SIZE(fll_fratios)) {
  1091. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1092. return -EINVAL;
  1093. }
  1094. fll_div->n = target / (fratio * Fref);
  1095. if (target % Fref == 0) {
  1096. fll_div->theta = 0;
  1097. fll_div->lambda = 0;
  1098. } else {
  1099. gcd_fll = gcd(target, fratio * Fref);
  1100. fll_div->theta = (target - (fll_div->n * fratio * Fref))
  1101. / gcd_fll;
  1102. fll_div->lambda = (fratio * Fref) / gcd_fll;
  1103. }
  1104. pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
  1105. fll_div->n, fll_div->theta, fll_div->lambda);
  1106. pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
  1107. fll_div->fll_fratio, fll_div->fll_outdiv,
  1108. fll_div->fll_refclk_div);
  1109. return 0;
  1110. }
  1111. static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  1112. unsigned int Fref, unsigned int Fout)
  1113. {
  1114. struct snd_soc_codec *codec = dai->codec;
  1115. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1116. struct _fll_div fll_div;
  1117. int ret;
  1118. int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
  1119. /* Any change? */
  1120. if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
  1121. Fout == wm8962->fll_fout)
  1122. return 0;
  1123. if (Fout == 0) {
  1124. dev_dbg(codec->dev, "FLL disabled\n");
  1125. wm8962->fll_fref = 0;
  1126. wm8962->fll_fout = 0;
  1127. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1128. WM8962_FLL_ENA, 0);
  1129. return 0;
  1130. }
  1131. ret = fll_factors(&fll_div, Fref, Fout);
  1132. if (ret != 0)
  1133. return ret;
  1134. switch (fll_id) {
  1135. case WM8962_FLL_MCLK:
  1136. case WM8962_FLL_BCLK:
  1137. case WM8962_FLL_OSC:
  1138. fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
  1139. break;
  1140. case WM8962_FLL_INT:
  1141. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1142. WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
  1143. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
  1144. WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
  1145. break;
  1146. default:
  1147. dev_err(codec->dev, "Unknown FLL source %d\n", ret);
  1148. return -EINVAL;
  1149. }
  1150. if (fll_div.theta || fll_div.lambda)
  1151. fll1 |= WM8962_FLL_FRAC;
  1152. /* Stop the FLL while we reconfigure */
  1153. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
  1154. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
  1155. WM8962_FLL_OUTDIV_MASK |
  1156. WM8962_FLL_REFCLK_DIV_MASK,
  1157. (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
  1158. (fll_div.fll_refclk_div));
  1159. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
  1160. WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
  1161. snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
  1162. snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
  1163. snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
  1164. snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
  1165. WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
  1166. WM8962_FLL_ENA, fll1);
  1167. dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1168. wm8962->fll_fref = Fref;
  1169. wm8962->fll_fout = Fout;
  1170. wm8962->fll_src = source;
  1171. return 0;
  1172. }
  1173. static int wm8962_mute(struct snd_soc_dai *dai, int mute)
  1174. {
  1175. struct snd_soc_codec *codec = dai->codec;
  1176. int val;
  1177. if (mute)
  1178. val = WM8962_DAC_MUTE;
  1179. else
  1180. val = 0;
  1181. return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
  1182. WM8962_DAC_MUTE, val);
  1183. }
  1184. #define WM8962_RATES SNDRV_PCM_RATE_8000_96000
  1185. #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1186. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1187. static struct snd_soc_dai_ops wm8962_dai_ops = {
  1188. .hw_params = wm8962_hw_params,
  1189. .set_sysclk = wm8962_set_dai_sysclk,
  1190. .set_fmt = wm8962_set_dai_fmt,
  1191. .set_pll = wm8962_set_fll,
  1192. .digital_mute = wm8962_mute,
  1193. };
  1194. static struct snd_soc_dai_driver wm8962_dai = {
  1195. .name = "wm8962",
  1196. .playback = {
  1197. .stream_name = "Playback",
  1198. .channels_min = 2,
  1199. .channels_max = 2,
  1200. .rates = WM8962_RATES,
  1201. .formats = WM8962_FORMATS,
  1202. },
  1203. .capture = {
  1204. .stream_name = "Capture",
  1205. .channels_min = 2,
  1206. .channels_max = 2,
  1207. .rates = WM8962_RATES,
  1208. .formats = WM8962_FORMATS,
  1209. },
  1210. .ops = &wm8962_dai_ops,
  1211. .symmetric_rates = 1,
  1212. };
  1213. static irqreturn_t wm8962_irq(int irq, void *data)
  1214. {
  1215. struct snd_soc_codec *codec = data;
  1216. int mask;
  1217. int active;
  1218. mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
  1219. active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
  1220. active &= ~mask;
  1221. if (active & WM8962_FIFOS_ERR_EINT)
  1222. dev_err(codec->dev, "FIFO error\n");
  1223. if (active & WM8962_TEMP_SHUT_EINT)
  1224. dev_crit(codec->dev, "Thermal shutdown\n");
  1225. /* Acknowledge the interrupts */
  1226. snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
  1227. return IRQ_HANDLED;
  1228. }
  1229. #ifdef CONFIG_PM
  1230. static int wm8962_resume(struct snd_soc_codec *codec)
  1231. {
  1232. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1233. u16 *reg_cache = codec->reg_cache;
  1234. int i;
  1235. /* Restore the registers */
  1236. for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
  1237. switch (i) {
  1238. case WM8962_SOFTWARE_RESET:
  1239. continue;
  1240. default:
  1241. break;
  1242. }
  1243. if (reg_cache[i] != wm8962_reg[i])
  1244. snd_soc_write(codec, i, reg_cache[i]);
  1245. }
  1246. return 0;
  1247. }
  1248. #else
  1249. #define wm8962_resume NULL
  1250. #endif
  1251. #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
  1252. static int beep_rates[] = {
  1253. 500, 1000, 2000, 4000,
  1254. };
  1255. static void wm8962_beep_work(struct work_struct *work)
  1256. {
  1257. struct wm8962_priv *wm8962 =
  1258. container_of(work, struct wm8962_priv, beep_work);
  1259. struct snd_soc_codec *codec = wm8962->codec;
  1260. int i;
  1261. int reg = 0;
  1262. int best = 0;
  1263. if (wm8962->beep_rate) {
  1264. for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
  1265. if (abs(wm8962->beep_rate - beep_rates[i]) <
  1266. abs(wm8962->beep_rate - beep_rates[best]))
  1267. best = i;
  1268. }
  1269. dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
  1270. beep_rates[best], wm8962->beep_rate);
  1271. reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
  1272. snd_soc_dapm_enable_pin(codec, "Beep");
  1273. } else {
  1274. dev_dbg(codec->dev, "Disabling beep\n");
  1275. snd_soc_dapm_disable_pin(codec, "Beep");
  1276. }
  1277. snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
  1278. WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
  1279. snd_soc_dapm_sync(codec);
  1280. }
  1281. /* For usability define a way of injecting beep events for the device -
  1282. * many systems will not have a keyboard.
  1283. */
  1284. static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
  1285. unsigned int code, int hz)
  1286. {
  1287. struct snd_soc_codec *codec = input_get_drvdata(dev);
  1288. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1289. dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
  1290. switch (code) {
  1291. case SND_BELL:
  1292. if (hz)
  1293. hz = 1000;
  1294. case SND_TONE:
  1295. break;
  1296. default:
  1297. return -1;
  1298. }
  1299. /* Kick the beep from a workqueue */
  1300. wm8962->beep_rate = hz;
  1301. schedule_work(&wm8962->beep_work);
  1302. return 0;
  1303. }
  1304. static ssize_t wm8962_beep_set(struct device *dev,
  1305. struct device_attribute *attr,
  1306. const char *buf, size_t count)
  1307. {
  1308. struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
  1309. long int time;
  1310. strict_strtol(buf, 10, &time);
  1311. input_event(wm8962->beep, EV_SND, SND_TONE, time);
  1312. return count;
  1313. }
  1314. static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
  1315. static void wm8962_init_beep(struct snd_soc_codec *codec)
  1316. {
  1317. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1318. int ret;
  1319. wm8962->beep = input_allocate_device();
  1320. if (!wm8962->beep) {
  1321. dev_err(codec->dev, "Failed to allocate beep device\n");
  1322. return;
  1323. }
  1324. INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
  1325. wm8962->beep_rate = 0;
  1326. wm8962->beep->name = "WM8962 Beep Generator";
  1327. wm8962->beep->phys = dev_name(codec->dev);
  1328. wm8962->beep->id.bustype = BUS_I2C;
  1329. wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
  1330. wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
  1331. wm8962->beep->event = wm8962_beep_event;
  1332. wm8962->beep->dev.parent = codec->dev;
  1333. input_set_drvdata(wm8962->beep, codec);
  1334. ret = input_register_device(wm8962->beep);
  1335. if (ret != 0) {
  1336. input_free_device(wm8962->beep);
  1337. wm8962->beep = NULL;
  1338. dev_err(codec->dev, "Failed to register beep device\n");
  1339. }
  1340. ret = device_create_file(codec->dev, &dev_attr_beep);
  1341. if (ret != 0) {
  1342. dev_err(codec->dev, "Failed to create keyclick file: %d\n",
  1343. ret);
  1344. }
  1345. }
  1346. static void wm8962_free_beep(struct snd_soc_codec *codec)
  1347. {
  1348. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1349. device_remove_file(codec->dev, &dev_attr_beep);
  1350. input_unregister_device(wm8962->beep);
  1351. cancel_work_sync(&wm8962->beep_work);
  1352. wm8962->beep = NULL;
  1353. snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
  1354. }
  1355. #else
  1356. static void wm8962_init_beep(struct snd_soc_codec *codec)
  1357. {
  1358. }
  1359. static void wm8962_free_beep(struct snd_soc_codec *codec)
  1360. {
  1361. }
  1362. #endif
  1363. static int wm8962_probe(struct snd_soc_codec *codec)
  1364. {
  1365. int ret;
  1366. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1367. struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
  1368. struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
  1369. dev);
  1370. int i, trigger, irq_pol;
  1371. wm8962->codec = codec;
  1372. codec->cache_sync = 1;
  1373. codec->idle_bias_off = 1;
  1374. ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
  1375. if (ret != 0) {
  1376. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1377. goto err;
  1378. }
  1379. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  1380. wm8962->supplies[i].supply = wm8962_supply_names[i];
  1381. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
  1382. wm8962->supplies);
  1383. if (ret != 0) {
  1384. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1385. goto err;
  1386. }
  1387. wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
  1388. wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
  1389. wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
  1390. wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
  1391. wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
  1392. wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
  1393. wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
  1394. wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
  1395. /* This should really be moved into the regulator core */
  1396. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
  1397. ret = regulator_register_notifier(wm8962->supplies[i].consumer,
  1398. &wm8962->disable_nb[i]);
  1399. if (ret != 0) {
  1400. dev_err(codec->dev,
  1401. "Failed to register regulator notifier: %d\n",
  1402. ret);
  1403. }
  1404. }
  1405. ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
  1406. wm8962->supplies);
  1407. if (ret != 0) {
  1408. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  1409. goto err_get;
  1410. }
  1411. ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
  1412. if (ret < 0) {
  1413. dev_err(codec->dev, "Failed to read ID register\n");
  1414. goto err_enable;
  1415. }
  1416. if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
  1417. dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
  1418. ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
  1419. ret = -EINVAL;
  1420. goto err_enable;
  1421. }
  1422. ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
  1423. if (ret < 0) {
  1424. dev_err(codec->dev, "Failed to read device revision: %d\n",
  1425. ret);
  1426. goto err_enable;
  1427. }
  1428. dev_info(codec->dev, "customer id %x revision %c\n",
  1429. (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
  1430. ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
  1431. + 'A');
  1432. ret = wm8962_reset(codec);
  1433. if (ret < 0) {
  1434. dev_err(codec->dev, "Failed to issue reset\n");
  1435. goto err_enable;
  1436. }
  1437. /* SYSCLK defaults to on; make sure it is off so we can safely
  1438. * write to registers if the device is declocked.
  1439. */
  1440. snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
  1441. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1442. if (pdata) {
  1443. /* Apply static configuration for GPIOs */
  1444. for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
  1445. if (pdata->gpio_init[i])
  1446. snd_soc_write(codec, 0x200 + i,
  1447. pdata->gpio_init[i] & 0xffff);
  1448. /* Put the speakers into mono mode? */
  1449. if (pdata->spk_mono)
  1450. wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
  1451. |= WM8962_SPK_MONO;
  1452. /* Micbias setup, detection enable and detection
  1453. * threasholds. */
  1454. if (pdata->mic_cfg)
  1455. snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
  1456. WM8962_MICDET_ENA |
  1457. WM8962_MICDET_THR_MASK |
  1458. WM8962_MICSHORT_THR_MASK |
  1459. WM8962_MICBIAS_LVL,
  1460. pdata->mic_cfg);
  1461. }
  1462. /* Latch volume update bits */
  1463. wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
  1464. wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
  1465. wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
  1466. wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
  1467. wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
  1468. wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
  1469. wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
  1470. wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
  1471. wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
  1472. wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
  1473. wm8962_add_widgets(codec);
  1474. wm8962_init_beep(codec);
  1475. if (i2c->irq) {
  1476. if (pdata && pdata->irq_active_low) {
  1477. trigger = IRQF_TRIGGER_LOW;
  1478. irq_pol = WM8962_IRQ_POL;
  1479. } else {
  1480. trigger = IRQF_TRIGGER_HIGH;
  1481. irq_pol = 0;
  1482. }
  1483. snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
  1484. WM8962_IRQ_POL, irq_pol);
  1485. ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq,
  1486. trigger | IRQF_ONESHOT,
  1487. "wm8962", codec);
  1488. if (ret != 0) {
  1489. dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
  1490. i2c->irq, ret);
  1491. /* Non-fatal */
  1492. } else {
  1493. /* Enable error reporting IRQs by default */
  1494. snd_soc_update_bits(codec,
  1495. WM8962_INTERRUPT_STATUS_2_MASK,
  1496. WM8962_TEMP_SHUT_EINT |
  1497. WM8962_FIFOS_ERR_EINT, 0);
  1498. }
  1499. }
  1500. return 0;
  1501. err_enable:
  1502. regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1503. err_get:
  1504. regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1505. err:
  1506. kfree(wm8962);
  1507. return ret;
  1508. }
  1509. static int wm8962_remove(struct snd_soc_codec *codec)
  1510. {
  1511. struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
  1512. struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
  1513. dev);
  1514. int i;
  1515. if (i2c->irq)
  1516. free_irq(i2c->irq, codec);
  1517. wm8962_free_beep(codec);
  1518. for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
  1519. regulator_unregister_notifier(wm8962->supplies[i].consumer,
  1520. &wm8962->disable_nb[i]);
  1521. regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
  1522. return 0;
  1523. }
  1524. static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
  1525. .probe = wm8962_probe,
  1526. .remove = wm8962_remove,
  1527. .resume = wm8962_resume,
  1528. .set_bias_level = wm8962_set_bias_level,
  1529. .reg_cache_size = WM8962_MAX_REGISTER + 1,
  1530. .reg_word_size = sizeof(u16),
  1531. .reg_cache_default = wm8962_reg,
  1532. .volatile_register = wm8962_volatile_register,
  1533. .readable_register = wm8962_readable_register,
  1534. };
  1535. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1536. static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
  1537. const struct i2c_device_id *id)
  1538. {
  1539. struct wm8962_priv *wm8962;
  1540. int ret;
  1541. wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
  1542. if (wm8962 == NULL)
  1543. return -ENOMEM;
  1544. i2c_set_clientdata(i2c, wm8962);
  1545. ret = snd_soc_register_codec(&i2c->dev,
  1546. &soc_codec_dev_wm8962, &wm8962_dai, 1);
  1547. if (ret < 0)
  1548. kfree(wm8962);
  1549. return ret;
  1550. }
  1551. static __devexit int wm8962_i2c_remove(struct i2c_client *client)
  1552. {
  1553. snd_soc_unregister_codec(&client->dev);
  1554. kfree(i2c_get_clientdata(client));
  1555. return 0;
  1556. }
  1557. static const struct i2c_device_id wm8962_i2c_id[] = {
  1558. { "wm8962", 0 },
  1559. { }
  1560. };
  1561. MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
  1562. static struct i2c_driver wm8962_i2c_driver = {
  1563. .driver = {
  1564. .name = "wm8962",
  1565. .owner = THIS_MODULE,
  1566. },
  1567. .probe = wm8962_i2c_probe,
  1568. .remove = __devexit_p(wm8962_i2c_remove),
  1569. .id_table = wm8962_i2c_id,
  1570. };
  1571. #endif
  1572. static int __init wm8962_modinit(void)
  1573. {
  1574. int ret;
  1575. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1576. ret = i2c_add_driver(&wm8962_i2c_driver);
  1577. if (ret != 0) {
  1578. printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
  1579. ret);
  1580. }
  1581. #endif
  1582. return 0;
  1583. }
  1584. module_init(wm8962_modinit);
  1585. static void __exit wm8962_exit(void)
  1586. {
  1587. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  1588. i2c_del_driver(&wm8962_i2c_driver);
  1589. #endif
  1590. }
  1591. module_exit(wm8962_exit);
  1592. MODULE_DESCRIPTION("ASoC WM8962 driver");
  1593. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  1594. MODULE_LICENSE("GPL");