ste-dbx5x0.dtsi 25 KB

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  1. /*
  2. * Copyright 2012 Linaro Ltd
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include <dt-bindings/mfd/dbx500-prcmu.h>
  13. #include "skeleton.dtsi"
  14. / {
  15. soc {
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. compatible = "stericsson,db8500";
  19. interrupt-parent = <&intc>;
  20. ranges;
  21. intc: interrupt-controller@a0411000 {
  22. compatible = "arm,cortex-a9-gic";
  23. #interrupt-cells = <3>;
  24. #address-cells = <1>;
  25. interrupt-controller;
  26. reg = <0xa0411000 0x1000>,
  27. <0xa0410100 0x100>;
  28. };
  29. L2: l2-cache {
  30. compatible = "arm,pl310-cache";
  31. reg = <0xa0412000 0x1000>;
  32. interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
  33. cache-unified;
  34. cache-level = <2>;
  35. };
  36. pmu {
  37. compatible = "arm,cortex-a9-pmu";
  38. interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
  39. };
  40. clocks {
  41. compatible = "stericsson,u8500-clks";
  42. prcmu_clk: prcmu-clock {
  43. #clock-cells = <1>;
  44. };
  45. prcc_pclk: prcc-periph-clock {
  46. #clock-cells = <2>;
  47. };
  48. prcc_kclk: prcc-kernel-clock {
  49. #clock-cells = <2>;
  50. };
  51. rtc_clk: rtc32k-clock {
  52. #clock-cells = <0>;
  53. };
  54. smp_twd_clk: smp-twd-clock {
  55. #clock-cells = <0>;
  56. };
  57. };
  58. mtu@a03c6000 {
  59. /* Nomadik System Timer */
  60. compatible = "st,nomadik-mtu";
  61. reg = <0xa03c6000 0x1000>;
  62. interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  63. clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
  64. clock-names = "timclk", "apb_pclk";
  65. };
  66. timer@a0410600 {
  67. compatible = "arm,cortex-a9-twd-timer";
  68. reg = <0xa0410600 0x20>;
  69. interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
  70. clocks = <&smp_twd_clk>;
  71. };
  72. rtc@80154000 {
  73. compatible = "arm,rtc-pl031", "arm,primecell";
  74. reg = <0x80154000 0x1000>;
  75. interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
  76. clocks = <&rtc_clk>;
  77. clock-names = "apb_pclk";
  78. };
  79. gpio0: gpio@8012e000 {
  80. compatible = "stericsson,db8500-gpio",
  81. "st,nomadik-gpio";
  82. reg = <0x8012e000 0x80>;
  83. interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
  84. interrupt-controller;
  85. #interrupt-cells = <2>;
  86. st,supports-sleepmode;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. gpio-bank = <0>;
  90. clocks = <&prcc_pclk 1 9>;
  91. };
  92. gpio1: gpio@8012e080 {
  93. compatible = "stericsson,db8500-gpio",
  94. "st,nomadik-gpio";
  95. reg = <0x8012e080 0x80>;
  96. interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
  97. interrupt-controller;
  98. #interrupt-cells = <2>;
  99. st,supports-sleepmode;
  100. gpio-controller;
  101. #gpio-cells = <2>;
  102. gpio-bank = <1>;
  103. clocks = <&prcc_pclk 1 9>;
  104. };
  105. gpio2: gpio@8000e000 {
  106. compatible = "stericsson,db8500-gpio",
  107. "st,nomadik-gpio";
  108. reg = <0x8000e000 0x80>;
  109. interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
  110. interrupt-controller;
  111. #interrupt-cells = <2>;
  112. st,supports-sleepmode;
  113. gpio-controller;
  114. #gpio-cells = <2>;
  115. gpio-bank = <2>;
  116. clocks = <&prcc_pclk 3 8>;
  117. };
  118. gpio3: gpio@8000e080 {
  119. compatible = "stericsson,db8500-gpio",
  120. "st,nomadik-gpio";
  121. reg = <0x8000e080 0x80>;
  122. interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
  123. interrupt-controller;
  124. #interrupt-cells = <2>;
  125. st,supports-sleepmode;
  126. gpio-controller;
  127. #gpio-cells = <2>;
  128. gpio-bank = <3>;
  129. clocks = <&prcc_pclk 3 8>;
  130. };
  131. gpio4: gpio@8000e100 {
  132. compatible = "stericsson,db8500-gpio",
  133. "st,nomadik-gpio";
  134. reg = <0x8000e100 0x80>;
  135. interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
  136. interrupt-controller;
  137. #interrupt-cells = <2>;
  138. st,supports-sleepmode;
  139. gpio-controller;
  140. #gpio-cells = <2>;
  141. gpio-bank = <4>;
  142. clocks = <&prcc_pclk 3 8>;
  143. };
  144. gpio5: gpio@8000e180 {
  145. compatible = "stericsson,db8500-gpio",
  146. "st,nomadik-gpio";
  147. reg = <0x8000e180 0x80>;
  148. interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
  149. interrupt-controller;
  150. #interrupt-cells = <2>;
  151. st,supports-sleepmode;
  152. gpio-controller;
  153. #gpio-cells = <2>;
  154. gpio-bank = <5>;
  155. clocks = <&prcc_pclk 3 8>;
  156. };
  157. gpio6: gpio@8011e000 {
  158. compatible = "stericsson,db8500-gpio",
  159. "st,nomadik-gpio";
  160. reg = <0x8011e000 0x80>;
  161. interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
  162. interrupt-controller;
  163. #interrupt-cells = <2>;
  164. st,supports-sleepmode;
  165. gpio-controller;
  166. #gpio-cells = <2>;
  167. gpio-bank = <6>;
  168. clocks = <&prcc_pclk 2 11>;
  169. };
  170. gpio7: gpio@8011e080 {
  171. compatible = "stericsson,db8500-gpio",
  172. "st,nomadik-gpio";
  173. reg = <0x8011e080 0x80>;
  174. interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
  175. interrupt-controller;
  176. #interrupt-cells = <2>;
  177. st,supports-sleepmode;
  178. gpio-controller;
  179. #gpio-cells = <2>;
  180. gpio-bank = <7>;
  181. clocks = <&prcc_pclk 2 11>;
  182. };
  183. gpio8: gpio@a03fe000 {
  184. compatible = "stericsson,db8500-gpio",
  185. "st,nomadik-gpio";
  186. reg = <0xa03fe000 0x80>;
  187. interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
  188. interrupt-controller;
  189. #interrupt-cells = <2>;
  190. st,supports-sleepmode;
  191. gpio-controller;
  192. #gpio-cells = <2>;
  193. gpio-bank = <8>;
  194. clocks = <&prcc_pclk 5 1>;
  195. };
  196. pinctrl {
  197. compatible = "stericsson,db8500-pinctrl";
  198. prcm = <&prcmu>;
  199. };
  200. usb_per5@a03e0000 {
  201. compatible = "stericsson,db8500-musb";
  202. reg = <0xa03e0000 0x10000>;
  203. interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
  204. interrupt-names = "mc";
  205. dr_mode = "otg";
  206. dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
  207. <&dma 38 0 0x0>, /* Logical - MemToDev */
  208. <&dma 37 0 0x2>, /* Logical - DevToMem */
  209. <&dma 37 0 0x0>, /* Logical - MemToDev */
  210. <&dma 36 0 0x2>, /* Logical - DevToMem */
  211. <&dma 36 0 0x0>, /* Logical - MemToDev */
  212. <&dma 19 0 0x2>, /* Logical - DevToMem */
  213. <&dma 19 0 0x0>, /* Logical - MemToDev */
  214. <&dma 18 0 0x2>, /* Logical - DevToMem */
  215. <&dma 18 0 0x0>, /* Logical - MemToDev */
  216. <&dma 17 0 0x2>, /* Logical - DevToMem */
  217. <&dma 17 0 0x0>, /* Logical - MemToDev */
  218. <&dma 16 0 0x2>, /* Logical - DevToMem */
  219. <&dma 16 0 0x0>, /* Logical - MemToDev */
  220. <&dma 39 0 0x2>, /* Logical - DevToMem */
  221. <&dma 39 0 0x0>; /* Logical - MemToDev */
  222. dma-names = "iep_1_9", "oep_1_9",
  223. "iep_2_10", "oep_2_10",
  224. "iep_3_11", "oep_3_11",
  225. "iep_4_12", "oep_4_12",
  226. "iep_5_13", "oep_5_13",
  227. "iep_6_14", "oep_6_14",
  228. "iep_7_15", "oep_7_15",
  229. "iep_8", "oep_8";
  230. clocks = <&prcc_pclk 5 0>;
  231. };
  232. dma: dma-controller@801C0000 {
  233. compatible = "stericsson,db8500-dma40", "stericsson,dma40";
  234. reg = <0x801C0000 0x1000 0x40010000 0x800>;
  235. reg-names = "base", "lcpa";
  236. interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
  237. #dma-cells = <3>;
  238. memcpy-channels = <56 57 58 59 60>;
  239. clocks = <&prcmu_clk PRCMU_DMACLK>;
  240. };
  241. prcmu: prcmu@80157000 {
  242. compatible = "stericsson,db8500-prcmu";
  243. reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
  244. reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
  245. interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
  246. #address-cells = <1>;
  247. #size-cells = <1>;
  248. interrupt-controller;
  249. #interrupt-cells = <2>;
  250. ranges;
  251. prcmu-timer-4@80157450 {
  252. compatible = "stericsson,db8500-prcmu-timer-4";
  253. reg = <0x80157450 0xC>;
  254. };
  255. cpufreq {
  256. compatible = "stericsson,cpufreq-ux500";
  257. clocks = <&prcmu_clk PRCMU_ARMSS>;
  258. clock-names = "armss";
  259. status = "disabled";
  260. };
  261. thermal@801573c0 {
  262. compatible = "stericsson,db8500-thermal";
  263. reg = <0x801573c0 0x40>;
  264. interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
  265. <22 IRQ_TYPE_LEVEL_HIGH>;
  266. interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
  267. status = "disabled";
  268. };
  269. db8500-prcmu-regulators {
  270. compatible = "stericsson,db8500-prcmu-regulator";
  271. // DB8500_REGULATOR_VAPE
  272. db8500_vape_reg: db8500_vape {
  273. regulator-compatible = "db8500_vape";
  274. regulator-always-on;
  275. };
  276. // DB8500_REGULATOR_VARM
  277. db8500_varm_reg: db8500_varm {
  278. regulator-compatible = "db8500_varm";
  279. };
  280. // DB8500_REGULATOR_VMODEM
  281. db8500_vmodem_reg: db8500_vmodem {
  282. regulator-compatible = "db8500_vmodem";
  283. };
  284. // DB8500_REGULATOR_VPLL
  285. db8500_vpll_reg: db8500_vpll {
  286. regulator-compatible = "db8500_vpll";
  287. };
  288. // DB8500_REGULATOR_VSMPS1
  289. db8500_vsmps1_reg: db8500_vsmps1 {
  290. regulator-compatible = "db8500_vsmps1";
  291. };
  292. // DB8500_REGULATOR_VSMPS2
  293. db8500_vsmps2_reg: db8500_vsmps2 {
  294. regulator-compatible = "db8500_vsmps2";
  295. };
  296. // DB8500_REGULATOR_VSMPS3
  297. db8500_vsmps3_reg: db8500_vsmps3 {
  298. regulator-compatible = "db8500_vsmps3";
  299. };
  300. // DB8500_REGULATOR_VRF1
  301. db8500_vrf1_reg: db8500_vrf1 {
  302. regulator-compatible = "db8500_vrf1";
  303. };
  304. // DB8500_REGULATOR_SWITCH_SVAMMDSP
  305. db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
  306. regulator-compatible = "db8500_sva_mmdsp";
  307. };
  308. // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
  309. db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
  310. regulator-compatible = "db8500_sva_mmdsp_ret";
  311. };
  312. // DB8500_REGULATOR_SWITCH_SVAPIPE
  313. db8500_sva_pipe_reg: db8500_sva_pipe {
  314. regulator-compatible = "db8500_sva_pipe";
  315. };
  316. // DB8500_REGULATOR_SWITCH_SIAMMDSP
  317. db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
  318. regulator-compatible = "db8500_sia_mmdsp";
  319. };
  320. // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
  321. db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
  322. };
  323. // DB8500_REGULATOR_SWITCH_SIAPIPE
  324. db8500_sia_pipe_reg: db8500_sia_pipe {
  325. regulator-compatible = "db8500_sia_pipe";
  326. };
  327. // DB8500_REGULATOR_SWITCH_SGA
  328. db8500_sga_reg: db8500_sga {
  329. regulator-compatible = "db8500_sga";
  330. vin-supply = <&db8500_vape_reg>;
  331. };
  332. // DB8500_REGULATOR_SWITCH_B2R2_MCDE
  333. db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
  334. regulator-compatible = "db8500_b2r2_mcde";
  335. vin-supply = <&db8500_vape_reg>;
  336. };
  337. // DB8500_REGULATOR_SWITCH_ESRAM12
  338. db8500_esram12_reg: db8500_esram12 {
  339. regulator-compatible = "db8500_esram12";
  340. };
  341. // DB8500_REGULATOR_SWITCH_ESRAM12RET
  342. db8500_esram12_ret_reg: db8500_esram12_ret {
  343. regulator-compatible = "db8500_esram12_ret";
  344. };
  345. // DB8500_REGULATOR_SWITCH_ESRAM34
  346. db8500_esram34_reg: db8500_esram34 {
  347. regulator-compatible = "db8500_esram34";
  348. };
  349. // DB8500_REGULATOR_SWITCH_ESRAM34RET
  350. db8500_esram34_ret_reg: db8500_esram34_ret {
  351. regulator-compatible = "db8500_esram34_ret";
  352. };
  353. };
  354. ab8500 {
  355. compatible = "stericsson,ab8500";
  356. interrupt-parent = <&intc>;
  357. interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
  358. interrupt-controller;
  359. #interrupt-cells = <2>;
  360. ab8500_gpio: ab8500-gpio {
  361. gpio-controller;
  362. #gpio-cells = <2>;
  363. };
  364. ab8500-rtc {
  365. compatible = "stericsson,ab8500-rtc";
  366. interrupts = <17 IRQ_TYPE_LEVEL_HIGH
  367. 18 IRQ_TYPE_LEVEL_HIGH>;
  368. interrupt-names = "60S", "ALARM";
  369. };
  370. ab8500-gpadc {
  371. compatible = "stericsson,ab8500-gpadc";
  372. interrupts = <32 IRQ_TYPE_LEVEL_HIGH
  373. 39 IRQ_TYPE_LEVEL_HIGH>;
  374. interrupt-names = "HW_CONV_END", "SW_CONV_END";
  375. vddadc-supply = <&ab8500_ldo_tvout_reg>;
  376. };
  377. ab8500_battery: ab8500_battery {
  378. stericsson,battery-type = "LIPO";
  379. thermistor-on-batctrl;
  380. };
  381. ab8500_fg {
  382. compatible = "stericsson,ab8500-fg";
  383. battery = <&ab8500_battery>;
  384. };
  385. ab8500_btemp {
  386. compatible = "stericsson,ab8500-btemp";
  387. battery = <&ab8500_battery>;
  388. };
  389. ab8500_charger {
  390. compatible = "stericsson,ab8500-charger";
  391. battery = <&ab8500_battery>;
  392. vddadc-supply = <&ab8500_ldo_tvout_reg>;
  393. };
  394. ab8500_chargalg {
  395. compatible = "stericsson,ab8500-chargalg";
  396. battery = <&ab8500_battery>;
  397. };
  398. ab8500_usb {
  399. compatible = "stericsson,ab8500-usb";
  400. interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
  401. 96 IRQ_TYPE_LEVEL_HIGH
  402. 14 IRQ_TYPE_LEVEL_HIGH
  403. 15 IRQ_TYPE_LEVEL_HIGH
  404. 79 IRQ_TYPE_LEVEL_HIGH
  405. 74 IRQ_TYPE_LEVEL_HIGH
  406. 75 IRQ_TYPE_LEVEL_HIGH>;
  407. interrupt-names = "ID_WAKEUP_R",
  408. "ID_WAKEUP_F",
  409. "VBUS_DET_F",
  410. "VBUS_DET_R",
  411. "USB_LINK_STATUS",
  412. "USB_ADP_PROBE_PLUG",
  413. "USB_ADP_PROBE_UNPLUG";
  414. vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
  415. v-ape-supply = <&db8500_vape_reg>;
  416. musb_1v8-supply = <&db8500_vsmps2_reg>;
  417. };
  418. ab8500-ponkey {
  419. compatible = "stericsson,ab8500-poweron-key";
  420. interrupts = <6 IRQ_TYPE_LEVEL_HIGH
  421. 7 IRQ_TYPE_LEVEL_HIGH>;
  422. interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
  423. };
  424. ab8500-sysctrl {
  425. compatible = "stericsson,ab8500-sysctrl";
  426. };
  427. ab8500-pwm {
  428. compatible = "stericsson,ab8500-pwm";
  429. };
  430. ab8500-debugfs {
  431. compatible = "stericsson,ab8500-debug";
  432. };
  433. codec: ab8500-codec {
  434. compatible = "stericsson,ab8500-codec";
  435. V-AUD-supply = <&ab8500_ldo_audio_reg>;
  436. V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
  437. V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
  438. V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
  439. stericsson,earpeice-cmv = <950>; /* Units in mV. */
  440. };
  441. ext_regulators: ab8500-ext-regulators {
  442. compatible = "stericsson,ab8500-ext-regulator";
  443. ab8500_ext1_reg: ab8500_ext1 {
  444. regulator-compatible = "ab8500_ext1";
  445. regulator-min-microvolt = <1800000>;
  446. regulator-max-microvolt = <1800000>;
  447. regulator-boot-on;
  448. regulator-always-on;
  449. };
  450. ab8500_ext2_reg: ab8500_ext2 {
  451. regulator-compatible = "ab8500_ext2";
  452. regulator-min-microvolt = <1360000>;
  453. regulator-max-microvolt = <1360000>;
  454. regulator-boot-on;
  455. regulator-always-on;
  456. };
  457. ab8500_ext3_reg: ab8500_ext3 {
  458. regulator-compatible = "ab8500_ext3";
  459. regulator-min-microvolt = <3400000>;
  460. regulator-max-microvolt = <3400000>;
  461. regulator-boot-on;
  462. };
  463. };
  464. ab8500-regulators {
  465. compatible = "stericsson,ab8500-regulator";
  466. vin-supply = <&ab8500_ext3_reg>;
  467. // supplies to the display/camera
  468. ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
  469. regulator-compatible = "ab8500_ldo_aux1";
  470. regulator-min-microvolt = <2500000>;
  471. regulator-max-microvolt = <2900000>;
  472. regulator-boot-on;
  473. /* BUG: If turned off MMC will be affected. */
  474. regulator-always-on;
  475. };
  476. // supplies to the on-board eMMC
  477. ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
  478. regulator-compatible = "ab8500_ldo_aux2";
  479. regulator-min-microvolt = <1100000>;
  480. regulator-max-microvolt = <3300000>;
  481. };
  482. // supply for VAUX3; SDcard slots
  483. ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
  484. regulator-compatible = "ab8500_ldo_aux3";
  485. regulator-min-microvolt = <1100000>;
  486. regulator-max-microvolt = <3300000>;
  487. };
  488. // supply for v-intcore12; VINTCORE12 LDO
  489. ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
  490. regulator-compatible = "ab8500_ldo_intcore";
  491. };
  492. // supply for tvout; gpadc; TVOUT LDO
  493. ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
  494. regulator-compatible = "ab8500_ldo_tvout";
  495. };
  496. // supply for ab8500-usb; USB LDO
  497. ab8500_ldo_usb_reg: ab8500_ldo_usb {
  498. regulator-compatible = "ab8500_ldo_usb";
  499. };
  500. // supply for ab8500-vaudio; VAUDIO LDO
  501. ab8500_ldo_audio_reg: ab8500_ldo_audio {
  502. regulator-compatible = "ab8500_ldo_audio";
  503. };
  504. // supply for v-anamic1 VAMIC1 LDO
  505. ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
  506. regulator-compatible = "ab8500_ldo_anamic1";
  507. };
  508. // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
  509. ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
  510. regulator-compatible = "ab8500_ldo_anamic2";
  511. };
  512. // supply for v-dmic; VDMIC LDO
  513. ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
  514. regulator-compatible = "ab8500_ldo_dmic";
  515. };
  516. // supply for U8500 CSI/DSI; VANA LDO
  517. ab8500_ldo_ana_reg: ab8500_ldo_ana {
  518. regulator-compatible = "ab8500_ldo_ana";
  519. };
  520. };
  521. };
  522. };
  523. i2c@80004000 {
  524. compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
  525. reg = <0x80004000 0x1000>;
  526. interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
  527. #address-cells = <1>;
  528. #size-cells = <0>;
  529. v-i2c-supply = <&db8500_vape_reg>;
  530. clock-frequency = <400000>;
  531. clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
  532. clock-names = "i2cclk", "apb_pclk";
  533. };
  534. i2c@80122000 {
  535. compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
  536. reg = <0x80122000 0x1000>;
  537. interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
  538. #address-cells = <1>;
  539. #size-cells = <0>;
  540. v-i2c-supply = <&db8500_vape_reg>;
  541. clock-frequency = <400000>;
  542. clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
  543. clock-names = "i2cclk", "apb_pclk";
  544. };
  545. i2c@80128000 {
  546. compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
  547. reg = <0x80128000 0x1000>;
  548. interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
  549. #address-cells = <1>;
  550. #size-cells = <0>;
  551. v-i2c-supply = <&db8500_vape_reg>;
  552. clock-frequency = <400000>;
  553. clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
  554. clock-names = "i2cclk", "apb_pclk";
  555. };
  556. i2c@80110000 {
  557. compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
  558. reg = <0x80110000 0x1000>;
  559. interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
  560. #address-cells = <1>;
  561. #size-cells = <0>;
  562. v-i2c-supply = <&db8500_vape_reg>;
  563. clock-frequency = <400000>;
  564. clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
  565. clock-names = "i2cclk", "apb_pclk";
  566. };
  567. i2c@8012a000 {
  568. compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
  569. reg = <0x8012a000 0x1000>;
  570. interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
  571. #address-cells = <1>;
  572. #size-cells = <0>;
  573. v-i2c-supply = <&db8500_vape_reg>;
  574. clock-frequency = <400000>;
  575. clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
  576. clock-names = "i2cclk", "apb_pclk";
  577. };
  578. ssp@80002000 {
  579. compatible = "arm,pl022", "arm,primecell";
  580. reg = <0x80002000 0x1000>;
  581. interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
  582. #address-cells = <1>;
  583. #size-cells = <0>;
  584. clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
  585. clock-names = "ssp0clk", "apb_pclk";
  586. dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
  587. <&dma 8 0 0x0>; /* Logical - MemToDev */
  588. dma-names = "rx", "tx";
  589. };
  590. ssp@80003000 {
  591. compatible = "arm,pl022", "arm,primecell";
  592. reg = <0x80003000 0x1000>;
  593. interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
  594. #address-cells = <1>;
  595. #size-cells = <0>;
  596. clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
  597. clock-names = "ssp1clk", "apb_pclk";
  598. dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
  599. <&dma 9 0 0x0>; /* Logical - MemToDev */
  600. dma-names = "rx", "tx";
  601. };
  602. spi@8011a000 {
  603. compatible = "arm,pl022", "arm,primecell";
  604. reg = <0x8011a000 0x1000>;
  605. interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
  606. #address-cells = <1>;
  607. #size-cells = <0>;
  608. /* Same clock wired to kernel and pclk */
  609. clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
  610. clock-names = "spi0clk", "apb_pclk";
  611. dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
  612. <&dma 0 0 0x0>; /* Logical - MemToDev */
  613. dma-names = "rx", "tx";
  614. };
  615. spi@80112000 {
  616. compatible = "arm,pl022", "arm,primecell";
  617. reg = <0x80112000 0x1000>;
  618. interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
  619. #address-cells = <1>;
  620. #size-cells = <0>;
  621. /* Same clock wired to kernel and pclk */
  622. clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
  623. clock-names = "spi1clk", "apb_pclk";
  624. dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
  625. <&dma 35 0 0x0>; /* Logical - MemToDev */
  626. dma-names = "rx", "tx";
  627. };
  628. spi@80111000 {
  629. compatible = "arm,pl022", "arm,primecell";
  630. reg = <0x80111000 0x1000>;
  631. interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  632. #address-cells = <1>;
  633. #size-cells = <0>;
  634. /* Same clock wired to kernel and pclk */
  635. clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
  636. clock-names = "spi2clk", "apb_pclk";
  637. dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
  638. <&dma 33 0 0x0>; /* Logical - MemToDev */
  639. dma-names = "rx", "tx";
  640. };
  641. spi@80129000 {
  642. compatible = "arm,pl022", "arm,primecell";
  643. reg = <0x80129000 0x1000>;
  644. interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
  645. #address-cells = <1>;
  646. #size-cells = <0>;
  647. /* Same clock wired to kernel and pclk */
  648. clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
  649. clock-names = "spi3clk", "apb_pclk";
  650. dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
  651. <&dma 40 0 0x0>; /* Logical - MemToDev */
  652. dma-names = "rx", "tx";
  653. };
  654. uart@80120000 {
  655. compatible = "arm,pl011", "arm,primecell";
  656. reg = <0x80120000 0x1000>;
  657. interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
  658. dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
  659. <&dma 13 0 0x0>; /* Logical - MemToDev */
  660. dma-names = "rx", "tx";
  661. clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
  662. clock-names = "uart", "apb_pclk";
  663. status = "disabled";
  664. };
  665. uart@80121000 {
  666. compatible = "arm,pl011", "arm,primecell";
  667. reg = <0x80121000 0x1000>;
  668. interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
  669. dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
  670. <&dma 12 0 0x0>; /* Logical - MemToDev */
  671. dma-names = "rx", "tx";
  672. clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
  673. clock-names = "uart", "apb_pclk";
  674. status = "disabled";
  675. };
  676. uart@80007000 {
  677. compatible = "arm,pl011", "arm,primecell";
  678. reg = <0x80007000 0x1000>;
  679. interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
  680. dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
  681. <&dma 11 0 0x0>; /* Logical - MemToDev */
  682. dma-names = "rx", "tx";
  683. clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
  684. clock-names = "uart", "apb_pclk";
  685. status = "disabled";
  686. };
  687. sdi0_per1@80126000 {
  688. compatible = "arm,pl18x", "arm,primecell";
  689. reg = <0x80126000 0x1000>;
  690. interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
  691. dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
  692. <&dma 29 0 0x0>; /* Logical - MemToDev */
  693. dma-names = "rx", "tx";
  694. clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
  695. clock-names = "sdi", "apb_pclk";
  696. status = "disabled";
  697. };
  698. sdi1_per2@80118000 {
  699. compatible = "arm,pl18x", "arm,primecell";
  700. reg = <0x80118000 0x1000>;
  701. interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
  702. dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
  703. <&dma 32 0 0x0>; /* Logical - MemToDev */
  704. dma-names = "rx", "tx";
  705. clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
  706. clock-names = "sdi", "apb_pclk";
  707. status = "disabled";
  708. };
  709. sdi2_per3@80005000 {
  710. compatible = "arm,pl18x", "arm,primecell";
  711. reg = <0x80005000 0x1000>;
  712. interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
  713. dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
  714. <&dma 28 0 0x0>; /* Logical - MemToDev */
  715. dma-names = "rx", "tx";
  716. clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
  717. clock-names = "sdi", "apb_pclk";
  718. status = "disabled";
  719. };
  720. sdi3_per2@80119000 {
  721. compatible = "arm,pl18x", "arm,primecell";
  722. reg = <0x80119000 0x1000>;
  723. interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
  724. clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
  725. clock-names = "sdi", "apb_pclk";
  726. status = "disabled";
  727. };
  728. sdi4_per2@80114000 {
  729. compatible = "arm,pl18x", "arm,primecell";
  730. reg = <0x80114000 0x1000>;
  731. interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
  732. dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
  733. <&dma 42 0 0x0>; /* Logical - MemToDev */
  734. dma-names = "rx", "tx";
  735. clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
  736. clock-names = "sdi", "apb_pclk";
  737. status = "disabled";
  738. };
  739. sdi5_per3@80008000 {
  740. compatible = "arm,pl18x", "arm,primecell";
  741. reg = <0x80008000 0x1000>;
  742. interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
  743. clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
  744. clock-names = "sdi", "apb_pclk";
  745. status = "disabled";
  746. };
  747. msp0: msp@80123000 {
  748. compatible = "stericsson,ux500-msp-i2s";
  749. reg = <0x80123000 0x1000>;
  750. interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
  751. v-ape-supply = <&db8500_vape_reg>;
  752. clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
  753. clock-names = "msp", "apb_pclk";
  754. status = "disabled";
  755. };
  756. msp1: msp@80124000 {
  757. compatible = "stericsson,ux500-msp-i2s";
  758. reg = <0x80124000 0x1000>;
  759. interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
  760. v-ape-supply = <&db8500_vape_reg>;
  761. clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
  762. clock-names = "msp", "apb_pclk";
  763. status = "disabled";
  764. };
  765. // HDMI sound
  766. msp2: msp@80117000 {
  767. compatible = "stericsson,ux500-msp-i2s";
  768. reg = <0x80117000 0x1000>;
  769. interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  770. v-ape-supply = <&db8500_vape_reg>;
  771. clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
  772. clock-names = "msp", "apb_pclk";
  773. status = "disabled";
  774. };
  775. msp3: msp@80125000 {
  776. compatible = "stericsson,ux500-msp-i2s";
  777. reg = <0x80125000 0x1000>;
  778. interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
  779. v-ape-supply = <&db8500_vape_reg>;
  780. clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
  781. clock-names = "msp", "apb_pclk";
  782. status = "disabled";
  783. };
  784. external-bus@50000000 {
  785. compatible = "simple-bus";
  786. reg = <0x50000000 0x4000000>;
  787. #address-cells = <1>;
  788. #size-cells = <1>;
  789. ranges = <0 0x50000000 0x4000000>;
  790. status = "disabled";
  791. };
  792. cpufreq-cooling {
  793. compatible = "stericsson,db8500-cpufreq-cooling";
  794. status = "disabled";
  795. };
  796. vmmci: regulator-gpio {
  797. compatible = "regulator-gpio";
  798. regulator-min-microvolt = <1800000>;
  799. regulator-max-microvolt = <2900000>;
  800. regulator-name = "mmci-reg";
  801. regulator-type = "voltage";
  802. startup-delay-us = <100>;
  803. enable-active-high;
  804. states = <1800000 0x1
  805. 2900000 0x0>;
  806. status = "disabled";
  807. };
  808. cryp@a03cb000 {
  809. compatible = "stericsson,ux500-cryp";
  810. reg = <0xa03cb000 0x1000>;
  811. interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
  812. v-ape-supply = <&db8500_vape_reg>;
  813. clocks = <&prcc_pclk 6 1>;
  814. };
  815. hash@a03c2000 {
  816. compatible = "stericsson,ux500-hash";
  817. reg = <0xa03c2000 0x1000>;
  818. v-ape-supply = <&db8500_vape_reg>;
  819. clocks = <&prcc_pclk 6 2>;
  820. };
  821. };
  822. };