sge.c 92 KB

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  1. /*
  2. * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/skbuff.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/if_vlan.h>
  36. #include <linux/ip.h>
  37. #include <linux/tcp.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/slab.h>
  40. #include <net/arp.h>
  41. #include "common.h"
  42. #include "regs.h"
  43. #include "sge_defs.h"
  44. #include "t3_cpl.h"
  45. #include "firmware_exports.h"
  46. #include "cxgb3_offload.h"
  47. #define USE_GTS 0
  48. #define SGE_RX_SM_BUF_SIZE 1536
  49. #define SGE_RX_COPY_THRES 256
  50. #define SGE_RX_PULL_LEN 128
  51. #define SGE_PG_RSVD SMP_CACHE_BYTES
  52. /*
  53. * Page chunk size for FL0 buffers if FL0 is to be populated with page chunks.
  54. * It must be a divisor of PAGE_SIZE. If set to 0 FL0 will use sk_buffs
  55. * directly.
  56. */
  57. #define FL0_PG_CHUNK_SIZE 2048
  58. #define FL0_PG_ORDER 0
  59. #define FL0_PG_ALLOC_SIZE (PAGE_SIZE << FL0_PG_ORDER)
  60. #define FL1_PG_CHUNK_SIZE (PAGE_SIZE > 8192 ? 16384 : 8192)
  61. #define FL1_PG_ORDER (PAGE_SIZE > 8192 ? 0 : 1)
  62. #define FL1_PG_ALLOC_SIZE (PAGE_SIZE << FL1_PG_ORDER)
  63. #define SGE_RX_DROP_THRES 16
  64. #define RX_RECLAIM_PERIOD (HZ/4)
  65. /*
  66. * Max number of Rx buffers we replenish at a time.
  67. */
  68. #define MAX_RX_REFILL 16U
  69. /*
  70. * Period of the Tx buffer reclaim timer. This timer does not need to run
  71. * frequently as Tx buffers are usually reclaimed by new Tx packets.
  72. */
  73. #define TX_RECLAIM_PERIOD (HZ / 4)
  74. #define TX_RECLAIM_TIMER_CHUNK 64U
  75. #define TX_RECLAIM_CHUNK 16U
  76. /* WR size in bytes */
  77. #define WR_LEN (WR_FLITS * 8)
  78. /*
  79. * Types of Tx queues in each queue set. Order here matters, do not change.
  80. */
  81. enum { TXQ_ETH, TXQ_OFLD, TXQ_CTRL };
  82. /* Values for sge_txq.flags */
  83. enum {
  84. TXQ_RUNNING = 1 << 0, /* fetch engine is running */
  85. TXQ_LAST_PKT_DB = 1 << 1, /* last packet rang the doorbell */
  86. };
  87. struct tx_desc {
  88. __be64 flit[TX_DESC_FLITS];
  89. };
  90. struct rx_desc {
  91. __be32 addr_lo;
  92. __be32 len_gen;
  93. __be32 gen2;
  94. __be32 addr_hi;
  95. };
  96. struct tx_sw_desc { /* SW state per Tx descriptor */
  97. struct sk_buff *skb;
  98. u8 eop; /* set if last descriptor for packet */
  99. u8 addr_idx; /* buffer index of first SGL entry in descriptor */
  100. u8 fragidx; /* first page fragment associated with descriptor */
  101. s8 sflit; /* start flit of first SGL entry in descriptor */
  102. };
  103. struct rx_sw_desc { /* SW state per Rx descriptor */
  104. union {
  105. struct sk_buff *skb;
  106. struct fl_pg_chunk pg_chunk;
  107. };
  108. DEFINE_DMA_UNMAP_ADDR(dma_addr);
  109. };
  110. struct rsp_desc { /* response queue descriptor */
  111. struct rss_header rss_hdr;
  112. __be32 flags;
  113. __be32 len_cq;
  114. u8 imm_data[47];
  115. u8 intr_gen;
  116. };
  117. /*
  118. * Holds unmapping information for Tx packets that need deferred unmapping.
  119. * This structure lives at skb->head and must be allocated by callers.
  120. */
  121. struct deferred_unmap_info {
  122. struct pci_dev *pdev;
  123. dma_addr_t addr[MAX_SKB_FRAGS + 1];
  124. };
  125. /*
  126. * Maps a number of flits to the number of Tx descriptors that can hold them.
  127. * The formula is
  128. *
  129. * desc = 1 + (flits - 2) / (WR_FLITS - 1).
  130. *
  131. * HW allows up to 4 descriptors to be combined into a WR.
  132. */
  133. static u8 flit_desc_map[] = {
  134. 0,
  135. #if SGE_NUM_GENBITS == 1
  136. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  137. 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  138. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  139. 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
  140. #elif SGE_NUM_GENBITS == 2
  141. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  142. 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  143. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
  144. 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
  145. #else
  146. # error "SGE_NUM_GENBITS must be 1 or 2"
  147. #endif
  148. };
  149. static inline struct sge_qset *fl_to_qset(const struct sge_fl *q, int qidx)
  150. {
  151. return container_of(q, struct sge_qset, fl[qidx]);
  152. }
  153. static inline struct sge_qset *rspq_to_qset(const struct sge_rspq *q)
  154. {
  155. return container_of(q, struct sge_qset, rspq);
  156. }
  157. static inline struct sge_qset *txq_to_qset(const struct sge_txq *q, int qidx)
  158. {
  159. return container_of(q, struct sge_qset, txq[qidx]);
  160. }
  161. /**
  162. * refill_rspq - replenish an SGE response queue
  163. * @adapter: the adapter
  164. * @q: the response queue to replenish
  165. * @credits: how many new responses to make available
  166. *
  167. * Replenishes a response queue by making the supplied number of responses
  168. * available to HW.
  169. */
  170. static inline void refill_rspq(struct adapter *adapter,
  171. const struct sge_rspq *q, unsigned int credits)
  172. {
  173. rmb();
  174. t3_write_reg(adapter, A_SG_RSPQ_CREDIT_RETURN,
  175. V_RSPQ(q->cntxt_id) | V_CREDITS(credits));
  176. }
  177. /**
  178. * need_skb_unmap - does the platform need unmapping of sk_buffs?
  179. *
  180. * Returns true if the platform needs sk_buff unmapping. The compiler
  181. * optimizes away unnecessary code if this returns true.
  182. */
  183. static inline int need_skb_unmap(void)
  184. {
  185. #ifdef CONFIG_NEED_DMA_MAP_STATE
  186. return 1;
  187. #else
  188. return 0;
  189. #endif
  190. }
  191. /**
  192. * unmap_skb - unmap a packet main body and its page fragments
  193. * @skb: the packet
  194. * @q: the Tx queue containing Tx descriptors for the packet
  195. * @cidx: index of Tx descriptor
  196. * @pdev: the PCI device
  197. *
  198. * Unmap the main body of an sk_buff and its page fragments, if any.
  199. * Because of the fairly complicated structure of our SGLs and the desire
  200. * to conserve space for metadata, the information necessary to unmap an
  201. * sk_buff is spread across the sk_buff itself (buffer lengths), the HW Tx
  202. * descriptors (the physical addresses of the various data buffers), and
  203. * the SW descriptor state (assorted indices). The send functions
  204. * initialize the indices for the first packet descriptor so we can unmap
  205. * the buffers held in the first Tx descriptor here, and we have enough
  206. * information at this point to set the state for the next Tx descriptor.
  207. *
  208. * Note that it is possible to clean up the first descriptor of a packet
  209. * before the send routines have written the next descriptors, but this
  210. * race does not cause any problem. We just end up writing the unmapping
  211. * info for the descriptor first.
  212. */
  213. static inline void unmap_skb(struct sk_buff *skb, struct sge_txq *q,
  214. unsigned int cidx, struct pci_dev *pdev)
  215. {
  216. const struct sg_ent *sgp;
  217. struct tx_sw_desc *d = &q->sdesc[cidx];
  218. int nfrags, frag_idx, curflit, j = d->addr_idx;
  219. sgp = (struct sg_ent *)&q->desc[cidx].flit[d->sflit];
  220. frag_idx = d->fragidx;
  221. if (frag_idx == 0 && skb_headlen(skb)) {
  222. pci_unmap_single(pdev, be64_to_cpu(sgp->addr[0]),
  223. skb_headlen(skb), PCI_DMA_TODEVICE);
  224. j = 1;
  225. }
  226. curflit = d->sflit + 1 + j;
  227. nfrags = skb_shinfo(skb)->nr_frags;
  228. while (frag_idx < nfrags && curflit < WR_FLITS) {
  229. pci_unmap_page(pdev, be64_to_cpu(sgp->addr[j]),
  230. skb_shinfo(skb)->frags[frag_idx].size,
  231. PCI_DMA_TODEVICE);
  232. j ^= 1;
  233. if (j == 0) {
  234. sgp++;
  235. curflit++;
  236. }
  237. curflit++;
  238. frag_idx++;
  239. }
  240. if (frag_idx < nfrags) { /* SGL continues into next Tx descriptor */
  241. d = cidx + 1 == q->size ? q->sdesc : d + 1;
  242. d->fragidx = frag_idx;
  243. d->addr_idx = j;
  244. d->sflit = curflit - WR_FLITS - j; /* sflit can be -1 */
  245. }
  246. }
  247. /**
  248. * free_tx_desc - reclaims Tx descriptors and their buffers
  249. * @adapter: the adapter
  250. * @q: the Tx queue to reclaim descriptors from
  251. * @n: the number of descriptors to reclaim
  252. *
  253. * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
  254. * Tx buffers. Called with the Tx queue lock held.
  255. */
  256. static void free_tx_desc(struct adapter *adapter, struct sge_txq *q,
  257. unsigned int n)
  258. {
  259. struct tx_sw_desc *d;
  260. struct pci_dev *pdev = adapter->pdev;
  261. unsigned int cidx = q->cidx;
  262. const int need_unmap = need_skb_unmap() &&
  263. q->cntxt_id >= FW_TUNNEL_SGEEC_START;
  264. d = &q->sdesc[cidx];
  265. while (n--) {
  266. if (d->skb) { /* an SGL is present */
  267. if (need_unmap)
  268. unmap_skb(d->skb, q, cidx, pdev);
  269. if (d->eop) {
  270. kfree_skb(d->skb);
  271. d->skb = NULL;
  272. }
  273. }
  274. ++d;
  275. if (++cidx == q->size) {
  276. cidx = 0;
  277. d = q->sdesc;
  278. }
  279. }
  280. q->cidx = cidx;
  281. }
  282. /**
  283. * reclaim_completed_tx - reclaims completed Tx descriptors
  284. * @adapter: the adapter
  285. * @q: the Tx queue to reclaim completed descriptors from
  286. * @chunk: maximum number of descriptors to reclaim
  287. *
  288. * Reclaims Tx descriptors that the SGE has indicated it has processed,
  289. * and frees the associated buffers if possible. Called with the Tx
  290. * queue's lock held.
  291. */
  292. static inline unsigned int reclaim_completed_tx(struct adapter *adapter,
  293. struct sge_txq *q,
  294. unsigned int chunk)
  295. {
  296. unsigned int reclaim = q->processed - q->cleaned;
  297. reclaim = min(chunk, reclaim);
  298. if (reclaim) {
  299. free_tx_desc(adapter, q, reclaim);
  300. q->cleaned += reclaim;
  301. q->in_use -= reclaim;
  302. }
  303. return q->processed - q->cleaned;
  304. }
  305. /**
  306. * should_restart_tx - are there enough resources to restart a Tx queue?
  307. * @q: the Tx queue
  308. *
  309. * Checks if there are enough descriptors to restart a suspended Tx queue.
  310. */
  311. static inline int should_restart_tx(const struct sge_txq *q)
  312. {
  313. unsigned int r = q->processed - q->cleaned;
  314. return q->in_use - r < (q->size >> 1);
  315. }
  316. static void clear_rx_desc(struct pci_dev *pdev, const struct sge_fl *q,
  317. struct rx_sw_desc *d)
  318. {
  319. if (q->use_pages && d->pg_chunk.page) {
  320. (*d->pg_chunk.p_cnt)--;
  321. if (!*d->pg_chunk.p_cnt)
  322. pci_unmap_page(pdev,
  323. d->pg_chunk.mapping,
  324. q->alloc_size, PCI_DMA_FROMDEVICE);
  325. put_page(d->pg_chunk.page);
  326. d->pg_chunk.page = NULL;
  327. } else {
  328. pci_unmap_single(pdev, dma_unmap_addr(d, dma_addr),
  329. q->buf_size, PCI_DMA_FROMDEVICE);
  330. kfree_skb(d->skb);
  331. d->skb = NULL;
  332. }
  333. }
  334. /**
  335. * free_rx_bufs - free the Rx buffers on an SGE free list
  336. * @pdev: the PCI device associated with the adapter
  337. * @rxq: the SGE free list to clean up
  338. *
  339. * Release the buffers on an SGE free-buffer Rx queue. HW fetching from
  340. * this queue should be stopped before calling this function.
  341. */
  342. static void free_rx_bufs(struct pci_dev *pdev, struct sge_fl *q)
  343. {
  344. unsigned int cidx = q->cidx;
  345. while (q->credits--) {
  346. struct rx_sw_desc *d = &q->sdesc[cidx];
  347. clear_rx_desc(pdev, q, d);
  348. if (++cidx == q->size)
  349. cidx = 0;
  350. }
  351. if (q->pg_chunk.page) {
  352. __free_pages(q->pg_chunk.page, q->order);
  353. q->pg_chunk.page = NULL;
  354. }
  355. }
  356. /**
  357. * add_one_rx_buf - add a packet buffer to a free-buffer list
  358. * @va: buffer start VA
  359. * @len: the buffer length
  360. * @d: the HW Rx descriptor to write
  361. * @sd: the SW Rx descriptor to write
  362. * @gen: the generation bit value
  363. * @pdev: the PCI device associated with the adapter
  364. *
  365. * Add a buffer of the given length to the supplied HW and SW Rx
  366. * descriptors.
  367. */
  368. static inline int add_one_rx_buf(void *va, unsigned int len,
  369. struct rx_desc *d, struct rx_sw_desc *sd,
  370. unsigned int gen, struct pci_dev *pdev)
  371. {
  372. dma_addr_t mapping;
  373. mapping = pci_map_single(pdev, va, len, PCI_DMA_FROMDEVICE);
  374. if (unlikely(pci_dma_mapping_error(pdev, mapping)))
  375. return -ENOMEM;
  376. dma_unmap_addr_set(sd, dma_addr, mapping);
  377. d->addr_lo = cpu_to_be32(mapping);
  378. d->addr_hi = cpu_to_be32((u64) mapping >> 32);
  379. wmb();
  380. d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
  381. d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
  382. return 0;
  383. }
  384. static inline int add_one_rx_chunk(dma_addr_t mapping, struct rx_desc *d,
  385. unsigned int gen)
  386. {
  387. d->addr_lo = cpu_to_be32(mapping);
  388. d->addr_hi = cpu_to_be32((u64) mapping >> 32);
  389. wmb();
  390. d->len_gen = cpu_to_be32(V_FLD_GEN1(gen));
  391. d->gen2 = cpu_to_be32(V_FLD_GEN2(gen));
  392. return 0;
  393. }
  394. static int alloc_pg_chunk(struct adapter *adapter, struct sge_fl *q,
  395. struct rx_sw_desc *sd, gfp_t gfp,
  396. unsigned int order)
  397. {
  398. if (!q->pg_chunk.page) {
  399. dma_addr_t mapping;
  400. q->pg_chunk.page = alloc_pages(gfp, order);
  401. if (unlikely(!q->pg_chunk.page))
  402. return -ENOMEM;
  403. q->pg_chunk.va = page_address(q->pg_chunk.page);
  404. q->pg_chunk.p_cnt = q->pg_chunk.va + (PAGE_SIZE << order) -
  405. SGE_PG_RSVD;
  406. q->pg_chunk.offset = 0;
  407. mapping = pci_map_page(adapter->pdev, q->pg_chunk.page,
  408. 0, q->alloc_size, PCI_DMA_FROMDEVICE);
  409. q->pg_chunk.mapping = mapping;
  410. }
  411. sd->pg_chunk = q->pg_chunk;
  412. prefetch(sd->pg_chunk.p_cnt);
  413. q->pg_chunk.offset += q->buf_size;
  414. if (q->pg_chunk.offset == (PAGE_SIZE << order))
  415. q->pg_chunk.page = NULL;
  416. else {
  417. q->pg_chunk.va += q->buf_size;
  418. get_page(q->pg_chunk.page);
  419. }
  420. if (sd->pg_chunk.offset == 0)
  421. *sd->pg_chunk.p_cnt = 1;
  422. else
  423. *sd->pg_chunk.p_cnt += 1;
  424. return 0;
  425. }
  426. static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
  427. {
  428. if (q->pend_cred >= q->credits / 4) {
  429. q->pend_cred = 0;
  430. wmb();
  431. t3_write_reg(adap, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
  432. }
  433. }
  434. /**
  435. * refill_fl - refill an SGE free-buffer list
  436. * @adapter: the adapter
  437. * @q: the free-list to refill
  438. * @n: the number of new buffers to allocate
  439. * @gfp: the gfp flags for allocating new buffers
  440. *
  441. * (Re)populate an SGE free-buffer list with up to @n new packet buffers,
  442. * allocated with the supplied gfp flags. The caller must assure that
  443. * @n does not exceed the queue's capacity.
  444. */
  445. static int refill_fl(struct adapter *adap, struct sge_fl *q, int n, gfp_t gfp)
  446. {
  447. struct rx_sw_desc *sd = &q->sdesc[q->pidx];
  448. struct rx_desc *d = &q->desc[q->pidx];
  449. unsigned int count = 0;
  450. while (n--) {
  451. dma_addr_t mapping;
  452. int err;
  453. if (q->use_pages) {
  454. if (unlikely(alloc_pg_chunk(adap, q, sd, gfp,
  455. q->order))) {
  456. nomem: q->alloc_failed++;
  457. break;
  458. }
  459. mapping = sd->pg_chunk.mapping + sd->pg_chunk.offset;
  460. dma_unmap_addr_set(sd, dma_addr, mapping);
  461. add_one_rx_chunk(mapping, d, q->gen);
  462. pci_dma_sync_single_for_device(adap->pdev, mapping,
  463. q->buf_size - SGE_PG_RSVD,
  464. PCI_DMA_FROMDEVICE);
  465. } else {
  466. void *buf_start;
  467. struct sk_buff *skb = alloc_skb(q->buf_size, gfp);
  468. if (!skb)
  469. goto nomem;
  470. sd->skb = skb;
  471. buf_start = skb->data;
  472. err = add_one_rx_buf(buf_start, q->buf_size, d, sd,
  473. q->gen, adap->pdev);
  474. if (unlikely(err)) {
  475. clear_rx_desc(adap->pdev, q, sd);
  476. break;
  477. }
  478. }
  479. d++;
  480. sd++;
  481. if (++q->pidx == q->size) {
  482. q->pidx = 0;
  483. q->gen ^= 1;
  484. sd = q->sdesc;
  485. d = q->desc;
  486. }
  487. count++;
  488. }
  489. q->credits += count;
  490. q->pend_cred += count;
  491. ring_fl_db(adap, q);
  492. return count;
  493. }
  494. static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
  495. {
  496. refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits),
  497. GFP_ATOMIC | __GFP_COMP);
  498. }
  499. /**
  500. * recycle_rx_buf - recycle a receive buffer
  501. * @adapter: the adapter
  502. * @q: the SGE free list
  503. * @idx: index of buffer to recycle
  504. *
  505. * Recycles the specified buffer on the given free list by adding it at
  506. * the next available slot on the list.
  507. */
  508. static void recycle_rx_buf(struct adapter *adap, struct sge_fl *q,
  509. unsigned int idx)
  510. {
  511. struct rx_desc *from = &q->desc[idx];
  512. struct rx_desc *to = &q->desc[q->pidx];
  513. q->sdesc[q->pidx] = q->sdesc[idx];
  514. to->addr_lo = from->addr_lo; /* already big endian */
  515. to->addr_hi = from->addr_hi; /* likewise */
  516. wmb();
  517. to->len_gen = cpu_to_be32(V_FLD_GEN1(q->gen));
  518. to->gen2 = cpu_to_be32(V_FLD_GEN2(q->gen));
  519. if (++q->pidx == q->size) {
  520. q->pidx = 0;
  521. q->gen ^= 1;
  522. }
  523. q->credits++;
  524. q->pend_cred++;
  525. ring_fl_db(adap, q);
  526. }
  527. /**
  528. * alloc_ring - allocate resources for an SGE descriptor ring
  529. * @pdev: the PCI device
  530. * @nelem: the number of descriptors
  531. * @elem_size: the size of each descriptor
  532. * @sw_size: the size of the SW state associated with each ring element
  533. * @phys: the physical address of the allocated ring
  534. * @metadata: address of the array holding the SW state for the ring
  535. *
  536. * Allocates resources for an SGE descriptor ring, such as Tx queues,
  537. * free buffer lists, or response queues. Each SGE ring requires
  538. * space for its HW descriptors plus, optionally, space for the SW state
  539. * associated with each HW entry (the metadata). The function returns
  540. * three values: the virtual address for the HW ring (the return value
  541. * of the function), the physical address of the HW ring, and the address
  542. * of the SW ring.
  543. */
  544. static void *alloc_ring(struct pci_dev *pdev, size_t nelem, size_t elem_size,
  545. size_t sw_size, dma_addr_t * phys, void *metadata)
  546. {
  547. size_t len = nelem * elem_size;
  548. void *s = NULL;
  549. void *p = dma_alloc_coherent(&pdev->dev, len, phys, GFP_KERNEL);
  550. if (!p)
  551. return NULL;
  552. if (sw_size && metadata) {
  553. s = kcalloc(nelem, sw_size, GFP_KERNEL);
  554. if (!s) {
  555. dma_free_coherent(&pdev->dev, len, p, *phys);
  556. return NULL;
  557. }
  558. *(void **)metadata = s;
  559. }
  560. memset(p, 0, len);
  561. return p;
  562. }
  563. /**
  564. * t3_reset_qset - reset a sge qset
  565. * @q: the queue set
  566. *
  567. * Reset the qset structure.
  568. * the NAPI structure is preserved in the event of
  569. * the qset's reincarnation, for example during EEH recovery.
  570. */
  571. static void t3_reset_qset(struct sge_qset *q)
  572. {
  573. if (q->adap &&
  574. !(q->adap->flags & NAPI_INIT)) {
  575. memset(q, 0, sizeof(*q));
  576. return;
  577. }
  578. q->adap = NULL;
  579. memset(&q->rspq, 0, sizeof(q->rspq));
  580. memset(q->fl, 0, sizeof(struct sge_fl) * SGE_RXQ_PER_SET);
  581. memset(q->txq, 0, sizeof(struct sge_txq) * SGE_TXQ_PER_SET);
  582. q->txq_stopped = 0;
  583. q->tx_reclaim_timer.function = NULL; /* for t3_stop_sge_timers() */
  584. q->rx_reclaim_timer.function = NULL;
  585. q->nomem = 0;
  586. napi_free_frags(&q->napi);
  587. }
  588. /**
  589. * free_qset - free the resources of an SGE queue set
  590. * @adapter: the adapter owning the queue set
  591. * @q: the queue set
  592. *
  593. * Release the HW and SW resources associated with an SGE queue set, such
  594. * as HW contexts, packet buffers, and descriptor rings. Traffic to the
  595. * queue set must be quiesced prior to calling this.
  596. */
  597. static void t3_free_qset(struct adapter *adapter, struct sge_qset *q)
  598. {
  599. int i;
  600. struct pci_dev *pdev = adapter->pdev;
  601. for (i = 0; i < SGE_RXQ_PER_SET; ++i)
  602. if (q->fl[i].desc) {
  603. spin_lock_irq(&adapter->sge.reg_lock);
  604. t3_sge_disable_fl(adapter, q->fl[i].cntxt_id);
  605. spin_unlock_irq(&adapter->sge.reg_lock);
  606. free_rx_bufs(pdev, &q->fl[i]);
  607. kfree(q->fl[i].sdesc);
  608. dma_free_coherent(&pdev->dev,
  609. q->fl[i].size *
  610. sizeof(struct rx_desc), q->fl[i].desc,
  611. q->fl[i].phys_addr);
  612. }
  613. for (i = 0; i < SGE_TXQ_PER_SET; ++i)
  614. if (q->txq[i].desc) {
  615. spin_lock_irq(&adapter->sge.reg_lock);
  616. t3_sge_enable_ecntxt(adapter, q->txq[i].cntxt_id, 0);
  617. spin_unlock_irq(&adapter->sge.reg_lock);
  618. if (q->txq[i].sdesc) {
  619. free_tx_desc(adapter, &q->txq[i],
  620. q->txq[i].in_use);
  621. kfree(q->txq[i].sdesc);
  622. }
  623. dma_free_coherent(&pdev->dev,
  624. q->txq[i].size *
  625. sizeof(struct tx_desc),
  626. q->txq[i].desc, q->txq[i].phys_addr);
  627. __skb_queue_purge(&q->txq[i].sendq);
  628. }
  629. if (q->rspq.desc) {
  630. spin_lock_irq(&adapter->sge.reg_lock);
  631. t3_sge_disable_rspcntxt(adapter, q->rspq.cntxt_id);
  632. spin_unlock_irq(&adapter->sge.reg_lock);
  633. dma_free_coherent(&pdev->dev,
  634. q->rspq.size * sizeof(struct rsp_desc),
  635. q->rspq.desc, q->rspq.phys_addr);
  636. }
  637. t3_reset_qset(q);
  638. }
  639. /**
  640. * init_qset_cntxt - initialize an SGE queue set context info
  641. * @qs: the queue set
  642. * @id: the queue set id
  643. *
  644. * Initializes the TIDs and context ids for the queues of a queue set.
  645. */
  646. static void init_qset_cntxt(struct sge_qset *qs, unsigned int id)
  647. {
  648. qs->rspq.cntxt_id = id;
  649. qs->fl[0].cntxt_id = 2 * id;
  650. qs->fl[1].cntxt_id = 2 * id + 1;
  651. qs->txq[TXQ_ETH].cntxt_id = FW_TUNNEL_SGEEC_START + id;
  652. qs->txq[TXQ_ETH].token = FW_TUNNEL_TID_START + id;
  653. qs->txq[TXQ_OFLD].cntxt_id = FW_OFLD_SGEEC_START + id;
  654. qs->txq[TXQ_CTRL].cntxt_id = FW_CTRL_SGEEC_START + id;
  655. qs->txq[TXQ_CTRL].token = FW_CTRL_TID_START + id;
  656. }
  657. /**
  658. * sgl_len - calculates the size of an SGL of the given capacity
  659. * @n: the number of SGL entries
  660. *
  661. * Calculates the number of flits needed for a scatter/gather list that
  662. * can hold the given number of entries.
  663. */
  664. static inline unsigned int sgl_len(unsigned int n)
  665. {
  666. /* alternatively: 3 * (n / 2) + 2 * (n & 1) */
  667. return (3 * n) / 2 + (n & 1);
  668. }
  669. /**
  670. * flits_to_desc - returns the num of Tx descriptors for the given flits
  671. * @n: the number of flits
  672. *
  673. * Calculates the number of Tx descriptors needed for the supplied number
  674. * of flits.
  675. */
  676. static inline unsigned int flits_to_desc(unsigned int n)
  677. {
  678. BUG_ON(n >= ARRAY_SIZE(flit_desc_map));
  679. return flit_desc_map[n];
  680. }
  681. /**
  682. * get_packet - return the next ingress packet buffer from a free list
  683. * @adap: the adapter that received the packet
  684. * @fl: the SGE free list holding the packet
  685. * @len: the packet length including any SGE padding
  686. * @drop_thres: # of remaining buffers before we start dropping packets
  687. *
  688. * Get the next packet from a free list and complete setup of the
  689. * sk_buff. If the packet is small we make a copy and recycle the
  690. * original buffer, otherwise we use the original buffer itself. If a
  691. * positive drop threshold is supplied packets are dropped and their
  692. * buffers recycled if (a) the number of remaining buffers is under the
  693. * threshold and the packet is too big to copy, or (b) the packet should
  694. * be copied but there is no memory for the copy.
  695. */
  696. static struct sk_buff *get_packet(struct adapter *adap, struct sge_fl *fl,
  697. unsigned int len, unsigned int drop_thres)
  698. {
  699. struct sk_buff *skb = NULL;
  700. struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
  701. prefetch(sd->skb->data);
  702. fl->credits--;
  703. if (len <= SGE_RX_COPY_THRES) {
  704. skb = alloc_skb(len, GFP_ATOMIC);
  705. if (likely(skb != NULL)) {
  706. __skb_put(skb, len);
  707. pci_dma_sync_single_for_cpu(adap->pdev,
  708. dma_unmap_addr(sd, dma_addr), len,
  709. PCI_DMA_FROMDEVICE);
  710. memcpy(skb->data, sd->skb->data, len);
  711. pci_dma_sync_single_for_device(adap->pdev,
  712. dma_unmap_addr(sd, dma_addr), len,
  713. PCI_DMA_FROMDEVICE);
  714. } else if (!drop_thres)
  715. goto use_orig_buf;
  716. recycle:
  717. recycle_rx_buf(adap, fl, fl->cidx);
  718. return skb;
  719. }
  720. if (unlikely(fl->credits < drop_thres) &&
  721. refill_fl(adap, fl, min(MAX_RX_REFILL, fl->size - fl->credits - 1),
  722. GFP_ATOMIC | __GFP_COMP) == 0)
  723. goto recycle;
  724. use_orig_buf:
  725. pci_unmap_single(adap->pdev, dma_unmap_addr(sd, dma_addr),
  726. fl->buf_size, PCI_DMA_FROMDEVICE);
  727. skb = sd->skb;
  728. skb_put(skb, len);
  729. __refill_fl(adap, fl);
  730. return skb;
  731. }
  732. /**
  733. * get_packet_pg - return the next ingress packet buffer from a free list
  734. * @adap: the adapter that received the packet
  735. * @fl: the SGE free list holding the packet
  736. * @len: the packet length including any SGE padding
  737. * @drop_thres: # of remaining buffers before we start dropping packets
  738. *
  739. * Get the next packet from a free list populated with page chunks.
  740. * If the packet is small we make a copy and recycle the original buffer,
  741. * otherwise we attach the original buffer as a page fragment to a fresh
  742. * sk_buff. If a positive drop threshold is supplied packets are dropped
  743. * and their buffers recycled if (a) the number of remaining buffers is
  744. * under the threshold and the packet is too big to copy, or (b) there's
  745. * no system memory.
  746. *
  747. * Note: this function is similar to @get_packet but deals with Rx buffers
  748. * that are page chunks rather than sk_buffs.
  749. */
  750. static struct sk_buff *get_packet_pg(struct adapter *adap, struct sge_fl *fl,
  751. struct sge_rspq *q, unsigned int len,
  752. unsigned int drop_thres)
  753. {
  754. struct sk_buff *newskb, *skb;
  755. struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
  756. dma_addr_t dma_addr = dma_unmap_addr(sd, dma_addr);
  757. newskb = skb = q->pg_skb;
  758. if (!skb && (len <= SGE_RX_COPY_THRES)) {
  759. newskb = alloc_skb(len, GFP_ATOMIC);
  760. if (likely(newskb != NULL)) {
  761. __skb_put(newskb, len);
  762. pci_dma_sync_single_for_cpu(adap->pdev, dma_addr, len,
  763. PCI_DMA_FROMDEVICE);
  764. memcpy(newskb->data, sd->pg_chunk.va, len);
  765. pci_dma_sync_single_for_device(adap->pdev, dma_addr,
  766. len,
  767. PCI_DMA_FROMDEVICE);
  768. } else if (!drop_thres)
  769. return NULL;
  770. recycle:
  771. fl->credits--;
  772. recycle_rx_buf(adap, fl, fl->cidx);
  773. q->rx_recycle_buf++;
  774. return newskb;
  775. }
  776. if (unlikely(q->rx_recycle_buf || (!skb && fl->credits <= drop_thres)))
  777. goto recycle;
  778. prefetch(sd->pg_chunk.p_cnt);
  779. if (!skb)
  780. newskb = alloc_skb(SGE_RX_PULL_LEN, GFP_ATOMIC);
  781. if (unlikely(!newskb)) {
  782. if (!drop_thres)
  783. return NULL;
  784. goto recycle;
  785. }
  786. pci_dma_sync_single_for_cpu(adap->pdev, dma_addr, len,
  787. PCI_DMA_FROMDEVICE);
  788. (*sd->pg_chunk.p_cnt)--;
  789. if (!*sd->pg_chunk.p_cnt && sd->pg_chunk.page != fl->pg_chunk.page)
  790. pci_unmap_page(adap->pdev,
  791. sd->pg_chunk.mapping,
  792. fl->alloc_size,
  793. PCI_DMA_FROMDEVICE);
  794. if (!skb) {
  795. __skb_put(newskb, SGE_RX_PULL_LEN);
  796. memcpy(newskb->data, sd->pg_chunk.va, SGE_RX_PULL_LEN);
  797. skb_fill_page_desc(newskb, 0, sd->pg_chunk.page,
  798. sd->pg_chunk.offset + SGE_RX_PULL_LEN,
  799. len - SGE_RX_PULL_LEN);
  800. newskb->len = len;
  801. newskb->data_len = len - SGE_RX_PULL_LEN;
  802. newskb->truesize += newskb->data_len;
  803. } else {
  804. skb_fill_page_desc(newskb, skb_shinfo(newskb)->nr_frags,
  805. sd->pg_chunk.page,
  806. sd->pg_chunk.offset, len);
  807. newskb->len += len;
  808. newskb->data_len += len;
  809. newskb->truesize += len;
  810. }
  811. fl->credits--;
  812. /*
  813. * We do not refill FLs here, we let the caller do it to overlap a
  814. * prefetch.
  815. */
  816. return newskb;
  817. }
  818. /**
  819. * get_imm_packet - return the next ingress packet buffer from a response
  820. * @resp: the response descriptor containing the packet data
  821. *
  822. * Return a packet containing the immediate data of the given response.
  823. */
  824. static inline struct sk_buff *get_imm_packet(const struct rsp_desc *resp)
  825. {
  826. struct sk_buff *skb = alloc_skb(IMMED_PKT_SIZE, GFP_ATOMIC);
  827. if (skb) {
  828. __skb_put(skb, IMMED_PKT_SIZE);
  829. skb_copy_to_linear_data(skb, resp->imm_data, IMMED_PKT_SIZE);
  830. }
  831. return skb;
  832. }
  833. /**
  834. * calc_tx_descs - calculate the number of Tx descriptors for a packet
  835. * @skb: the packet
  836. *
  837. * Returns the number of Tx descriptors needed for the given Ethernet
  838. * packet. Ethernet packets require addition of WR and CPL headers.
  839. */
  840. static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
  841. {
  842. unsigned int flits;
  843. if (skb->len <= WR_LEN - sizeof(struct cpl_tx_pkt))
  844. return 1;
  845. flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 2;
  846. if (skb_shinfo(skb)->gso_size)
  847. flits++;
  848. return flits_to_desc(flits);
  849. }
  850. /**
  851. * make_sgl - populate a scatter/gather list for a packet
  852. * @skb: the packet
  853. * @sgp: the SGL to populate
  854. * @start: start address of skb main body data to include in the SGL
  855. * @len: length of skb main body data to include in the SGL
  856. * @pdev: the PCI device
  857. *
  858. * Generates a scatter/gather list for the buffers that make up a packet
  859. * and returns the SGL size in 8-byte words. The caller must size the SGL
  860. * appropriately.
  861. */
  862. static inline unsigned int make_sgl(const struct sk_buff *skb,
  863. struct sg_ent *sgp, unsigned char *start,
  864. unsigned int len, struct pci_dev *pdev)
  865. {
  866. dma_addr_t mapping;
  867. unsigned int i, j = 0, nfrags;
  868. if (len) {
  869. mapping = pci_map_single(pdev, start, len, PCI_DMA_TODEVICE);
  870. sgp->len[0] = cpu_to_be32(len);
  871. sgp->addr[0] = cpu_to_be64(mapping);
  872. j = 1;
  873. }
  874. nfrags = skb_shinfo(skb)->nr_frags;
  875. for (i = 0; i < nfrags; i++) {
  876. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  877. mapping = pci_map_page(pdev, frag->page, frag->page_offset,
  878. frag->size, PCI_DMA_TODEVICE);
  879. sgp->len[j] = cpu_to_be32(frag->size);
  880. sgp->addr[j] = cpu_to_be64(mapping);
  881. j ^= 1;
  882. if (j == 0)
  883. ++sgp;
  884. }
  885. if (j)
  886. sgp->len[j] = 0;
  887. return ((nfrags + (len != 0)) * 3) / 2 + j;
  888. }
  889. /**
  890. * check_ring_tx_db - check and potentially ring a Tx queue's doorbell
  891. * @adap: the adapter
  892. * @q: the Tx queue
  893. *
  894. * Ring the doorbel if a Tx queue is asleep. There is a natural race,
  895. * where the HW is going to sleep just after we checked, however,
  896. * then the interrupt handler will detect the outstanding TX packet
  897. * and ring the doorbell for us.
  898. *
  899. * When GTS is disabled we unconditionally ring the doorbell.
  900. */
  901. static inline void check_ring_tx_db(struct adapter *adap, struct sge_txq *q)
  902. {
  903. #if USE_GTS
  904. clear_bit(TXQ_LAST_PKT_DB, &q->flags);
  905. if (test_and_set_bit(TXQ_RUNNING, &q->flags) == 0) {
  906. set_bit(TXQ_LAST_PKT_DB, &q->flags);
  907. t3_write_reg(adap, A_SG_KDOORBELL,
  908. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  909. }
  910. #else
  911. wmb(); /* write descriptors before telling HW */
  912. t3_write_reg(adap, A_SG_KDOORBELL,
  913. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  914. #endif
  915. }
  916. static inline void wr_gen2(struct tx_desc *d, unsigned int gen)
  917. {
  918. #if SGE_NUM_GENBITS == 2
  919. d->flit[TX_DESC_FLITS - 1] = cpu_to_be64(gen);
  920. #endif
  921. }
  922. /**
  923. * write_wr_hdr_sgl - write a WR header and, optionally, SGL
  924. * @ndesc: number of Tx descriptors spanned by the SGL
  925. * @skb: the packet corresponding to the WR
  926. * @d: first Tx descriptor to be written
  927. * @pidx: index of above descriptors
  928. * @q: the SGE Tx queue
  929. * @sgl: the SGL
  930. * @flits: number of flits to the start of the SGL in the first descriptor
  931. * @sgl_flits: the SGL size in flits
  932. * @gen: the Tx descriptor generation
  933. * @wr_hi: top 32 bits of WR header based on WR type (big endian)
  934. * @wr_lo: low 32 bits of WR header based on WR type (big endian)
  935. *
  936. * Write a work request header and an associated SGL. If the SGL is
  937. * small enough to fit into one Tx descriptor it has already been written
  938. * and we just need to write the WR header. Otherwise we distribute the
  939. * SGL across the number of descriptors it spans.
  940. */
  941. static void write_wr_hdr_sgl(unsigned int ndesc, struct sk_buff *skb,
  942. struct tx_desc *d, unsigned int pidx,
  943. const struct sge_txq *q,
  944. const struct sg_ent *sgl,
  945. unsigned int flits, unsigned int sgl_flits,
  946. unsigned int gen, __be32 wr_hi,
  947. __be32 wr_lo)
  948. {
  949. struct work_request_hdr *wrp = (struct work_request_hdr *)d;
  950. struct tx_sw_desc *sd = &q->sdesc[pidx];
  951. sd->skb = skb;
  952. if (need_skb_unmap()) {
  953. sd->fragidx = 0;
  954. sd->addr_idx = 0;
  955. sd->sflit = flits;
  956. }
  957. if (likely(ndesc == 1)) {
  958. sd->eop = 1;
  959. wrp->wr_hi = htonl(F_WR_SOP | F_WR_EOP | V_WR_DATATYPE(1) |
  960. V_WR_SGLSFLT(flits)) | wr_hi;
  961. wmb();
  962. wrp->wr_lo = htonl(V_WR_LEN(flits + sgl_flits) |
  963. V_WR_GEN(gen)) | wr_lo;
  964. wr_gen2(d, gen);
  965. } else {
  966. unsigned int ogen = gen;
  967. const u64 *fp = (const u64 *)sgl;
  968. struct work_request_hdr *wp = wrp;
  969. wrp->wr_hi = htonl(F_WR_SOP | V_WR_DATATYPE(1) |
  970. V_WR_SGLSFLT(flits)) | wr_hi;
  971. while (sgl_flits) {
  972. unsigned int avail = WR_FLITS - flits;
  973. if (avail > sgl_flits)
  974. avail = sgl_flits;
  975. memcpy(&d->flit[flits], fp, avail * sizeof(*fp));
  976. sgl_flits -= avail;
  977. ndesc--;
  978. if (!sgl_flits)
  979. break;
  980. fp += avail;
  981. d++;
  982. sd->eop = 0;
  983. sd++;
  984. if (++pidx == q->size) {
  985. pidx = 0;
  986. gen ^= 1;
  987. d = q->desc;
  988. sd = q->sdesc;
  989. }
  990. sd->skb = skb;
  991. wrp = (struct work_request_hdr *)d;
  992. wrp->wr_hi = htonl(V_WR_DATATYPE(1) |
  993. V_WR_SGLSFLT(1)) | wr_hi;
  994. wrp->wr_lo = htonl(V_WR_LEN(min(WR_FLITS,
  995. sgl_flits + 1)) |
  996. V_WR_GEN(gen)) | wr_lo;
  997. wr_gen2(d, gen);
  998. flits = 1;
  999. }
  1000. sd->eop = 1;
  1001. wrp->wr_hi |= htonl(F_WR_EOP);
  1002. wmb();
  1003. wp->wr_lo = htonl(V_WR_LEN(WR_FLITS) | V_WR_GEN(ogen)) | wr_lo;
  1004. wr_gen2((struct tx_desc *)wp, ogen);
  1005. WARN_ON(ndesc != 0);
  1006. }
  1007. }
  1008. /**
  1009. * write_tx_pkt_wr - write a TX_PKT work request
  1010. * @adap: the adapter
  1011. * @skb: the packet to send
  1012. * @pi: the egress interface
  1013. * @pidx: index of the first Tx descriptor to write
  1014. * @gen: the generation value to use
  1015. * @q: the Tx queue
  1016. * @ndesc: number of descriptors the packet will occupy
  1017. * @compl: the value of the COMPL bit to use
  1018. *
  1019. * Generate a TX_PKT work request to send the supplied packet.
  1020. */
  1021. static void write_tx_pkt_wr(struct adapter *adap, struct sk_buff *skb,
  1022. const struct port_info *pi,
  1023. unsigned int pidx, unsigned int gen,
  1024. struct sge_txq *q, unsigned int ndesc,
  1025. unsigned int compl)
  1026. {
  1027. unsigned int flits, sgl_flits, cntrl, tso_info;
  1028. struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
  1029. struct tx_desc *d = &q->desc[pidx];
  1030. struct cpl_tx_pkt *cpl = (struct cpl_tx_pkt *)d;
  1031. cpl->len = htonl(skb->len);
  1032. cntrl = V_TXPKT_INTF(pi->port_id);
  1033. if (vlan_tx_tag_present(skb))
  1034. cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(vlan_tx_tag_get(skb));
  1035. tso_info = V_LSO_MSS(skb_shinfo(skb)->gso_size);
  1036. if (tso_info) {
  1037. int eth_type;
  1038. struct cpl_tx_pkt_lso *hdr = (struct cpl_tx_pkt_lso *)cpl;
  1039. d->flit[2] = 0;
  1040. cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT_LSO);
  1041. hdr->cntrl = htonl(cntrl);
  1042. eth_type = skb_network_offset(skb) == ETH_HLEN ?
  1043. CPL_ETH_II : CPL_ETH_II_VLAN;
  1044. tso_info |= V_LSO_ETH_TYPE(eth_type) |
  1045. V_LSO_IPHDR_WORDS(ip_hdr(skb)->ihl) |
  1046. V_LSO_TCPHDR_WORDS(tcp_hdr(skb)->doff);
  1047. hdr->lso_info = htonl(tso_info);
  1048. flits = 3;
  1049. } else {
  1050. cntrl |= V_TXPKT_OPCODE(CPL_TX_PKT);
  1051. cntrl |= F_TXPKT_IPCSUM_DIS; /* SW calculates IP csum */
  1052. cntrl |= V_TXPKT_L4CSUM_DIS(skb->ip_summed != CHECKSUM_PARTIAL);
  1053. cpl->cntrl = htonl(cntrl);
  1054. if (skb->len <= WR_LEN - sizeof(*cpl)) {
  1055. q->sdesc[pidx].skb = NULL;
  1056. if (!skb->data_len)
  1057. skb_copy_from_linear_data(skb, &d->flit[2],
  1058. skb->len);
  1059. else
  1060. skb_copy_bits(skb, 0, &d->flit[2], skb->len);
  1061. flits = (skb->len + 7) / 8 + 2;
  1062. cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(skb->len & 7) |
  1063. V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT)
  1064. | F_WR_SOP | F_WR_EOP | compl);
  1065. wmb();
  1066. cpl->wr.wr_lo = htonl(V_WR_LEN(flits) | V_WR_GEN(gen) |
  1067. V_WR_TID(q->token));
  1068. wr_gen2(d, gen);
  1069. kfree_skb(skb);
  1070. return;
  1071. }
  1072. flits = 2;
  1073. }
  1074. sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
  1075. sgl_flits = make_sgl(skb, sgp, skb->data, skb_headlen(skb), adap->pdev);
  1076. write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits, gen,
  1077. htonl(V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) | compl),
  1078. htonl(V_WR_TID(q->token)));
  1079. }
  1080. static inline void t3_stop_tx_queue(struct netdev_queue *txq,
  1081. struct sge_qset *qs, struct sge_txq *q)
  1082. {
  1083. netif_tx_stop_queue(txq);
  1084. set_bit(TXQ_ETH, &qs->txq_stopped);
  1085. q->stops++;
  1086. }
  1087. /**
  1088. * eth_xmit - add a packet to the Ethernet Tx queue
  1089. * @skb: the packet
  1090. * @dev: the egress net device
  1091. *
  1092. * Add a packet to an SGE Tx queue. Runs with softirqs disabled.
  1093. */
  1094. netdev_tx_t t3_eth_xmit(struct sk_buff *skb, struct net_device *dev)
  1095. {
  1096. int qidx;
  1097. unsigned int ndesc, pidx, credits, gen, compl;
  1098. const struct port_info *pi = netdev_priv(dev);
  1099. struct adapter *adap = pi->adapter;
  1100. struct netdev_queue *txq;
  1101. struct sge_qset *qs;
  1102. struct sge_txq *q;
  1103. /*
  1104. * The chip min packet length is 9 octets but play safe and reject
  1105. * anything shorter than an Ethernet header.
  1106. */
  1107. if (unlikely(skb->len < ETH_HLEN)) {
  1108. dev_kfree_skb(skb);
  1109. return NETDEV_TX_OK;
  1110. }
  1111. qidx = skb_get_queue_mapping(skb);
  1112. qs = &pi->qs[qidx];
  1113. q = &qs->txq[TXQ_ETH];
  1114. txq = netdev_get_tx_queue(dev, qidx);
  1115. reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
  1116. credits = q->size - q->in_use;
  1117. ndesc = calc_tx_descs(skb);
  1118. if (unlikely(credits < ndesc)) {
  1119. t3_stop_tx_queue(txq, qs, q);
  1120. dev_err(&adap->pdev->dev,
  1121. "%s: Tx ring %u full while queue awake!\n",
  1122. dev->name, q->cntxt_id & 7);
  1123. return NETDEV_TX_BUSY;
  1124. }
  1125. q->in_use += ndesc;
  1126. if (unlikely(credits - ndesc < q->stop_thres)) {
  1127. t3_stop_tx_queue(txq, qs, q);
  1128. if (should_restart_tx(q) &&
  1129. test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
  1130. q->restarts++;
  1131. netif_tx_start_queue(txq);
  1132. }
  1133. }
  1134. gen = q->gen;
  1135. q->unacked += ndesc;
  1136. compl = (q->unacked & 8) << (S_WR_COMPL - 3);
  1137. q->unacked &= 7;
  1138. pidx = q->pidx;
  1139. q->pidx += ndesc;
  1140. if (q->pidx >= q->size) {
  1141. q->pidx -= q->size;
  1142. q->gen ^= 1;
  1143. }
  1144. /* update port statistics */
  1145. if (skb->ip_summed == CHECKSUM_COMPLETE)
  1146. qs->port_stats[SGE_PSTAT_TX_CSUM]++;
  1147. if (skb_shinfo(skb)->gso_size)
  1148. qs->port_stats[SGE_PSTAT_TSO]++;
  1149. if (vlan_tx_tag_present(skb))
  1150. qs->port_stats[SGE_PSTAT_VLANINS]++;
  1151. /*
  1152. * We do not use Tx completion interrupts to free DMAd Tx packets.
  1153. * This is good for performance but means that we rely on new Tx
  1154. * packets arriving to run the destructors of completed packets,
  1155. * which open up space in their sockets' send queues. Sometimes
  1156. * we do not get such new packets causing Tx to stall. A single
  1157. * UDP transmitter is a good example of this situation. We have
  1158. * a clean up timer that periodically reclaims completed packets
  1159. * but it doesn't run often enough (nor do we want it to) to prevent
  1160. * lengthy stalls. A solution to this problem is to run the
  1161. * destructor early, after the packet is queued but before it's DMAd.
  1162. * A cons is that we lie to socket memory accounting, but the amount
  1163. * of extra memory is reasonable (limited by the number of Tx
  1164. * descriptors), the packets do actually get freed quickly by new
  1165. * packets almost always, and for protocols like TCP that wait for
  1166. * acks to really free up the data the extra memory is even less.
  1167. * On the positive side we run the destructors on the sending CPU
  1168. * rather than on a potentially different completing CPU, usually a
  1169. * good thing. We also run them without holding our Tx queue lock,
  1170. * unlike what reclaim_completed_tx() would otherwise do.
  1171. *
  1172. * Run the destructor before telling the DMA engine about the packet
  1173. * to make sure it doesn't complete and get freed prematurely.
  1174. */
  1175. if (likely(!skb_shared(skb)))
  1176. skb_orphan(skb);
  1177. write_tx_pkt_wr(adap, skb, pi, pidx, gen, q, ndesc, compl);
  1178. check_ring_tx_db(adap, q);
  1179. return NETDEV_TX_OK;
  1180. }
  1181. /**
  1182. * write_imm - write a packet into a Tx descriptor as immediate data
  1183. * @d: the Tx descriptor to write
  1184. * @skb: the packet
  1185. * @len: the length of packet data to write as immediate data
  1186. * @gen: the generation bit value to write
  1187. *
  1188. * Writes a packet as immediate data into a Tx descriptor. The packet
  1189. * contains a work request at its beginning. We must write the packet
  1190. * carefully so the SGE doesn't read it accidentally before it's written
  1191. * in its entirety.
  1192. */
  1193. static inline void write_imm(struct tx_desc *d, struct sk_buff *skb,
  1194. unsigned int len, unsigned int gen)
  1195. {
  1196. struct work_request_hdr *from = (struct work_request_hdr *)skb->data;
  1197. struct work_request_hdr *to = (struct work_request_hdr *)d;
  1198. if (likely(!skb->data_len))
  1199. memcpy(&to[1], &from[1], len - sizeof(*from));
  1200. else
  1201. skb_copy_bits(skb, sizeof(*from), &to[1], len - sizeof(*from));
  1202. to->wr_hi = from->wr_hi | htonl(F_WR_SOP | F_WR_EOP |
  1203. V_WR_BCNTLFLT(len & 7));
  1204. wmb();
  1205. to->wr_lo = from->wr_lo | htonl(V_WR_GEN(gen) |
  1206. V_WR_LEN((len + 7) / 8));
  1207. wr_gen2(d, gen);
  1208. kfree_skb(skb);
  1209. }
  1210. /**
  1211. * check_desc_avail - check descriptor availability on a send queue
  1212. * @adap: the adapter
  1213. * @q: the send queue
  1214. * @skb: the packet needing the descriptors
  1215. * @ndesc: the number of Tx descriptors needed
  1216. * @qid: the Tx queue number in its queue set (TXQ_OFLD or TXQ_CTRL)
  1217. *
  1218. * Checks if the requested number of Tx descriptors is available on an
  1219. * SGE send queue. If the queue is already suspended or not enough
  1220. * descriptors are available the packet is queued for later transmission.
  1221. * Must be called with the Tx queue locked.
  1222. *
  1223. * Returns 0 if enough descriptors are available, 1 if there aren't
  1224. * enough descriptors and the packet has been queued, and 2 if the caller
  1225. * needs to retry because there weren't enough descriptors at the
  1226. * beginning of the call but some freed up in the mean time.
  1227. */
  1228. static inline int check_desc_avail(struct adapter *adap, struct sge_txq *q,
  1229. struct sk_buff *skb, unsigned int ndesc,
  1230. unsigned int qid)
  1231. {
  1232. if (unlikely(!skb_queue_empty(&q->sendq))) {
  1233. addq_exit:__skb_queue_tail(&q->sendq, skb);
  1234. return 1;
  1235. }
  1236. if (unlikely(q->size - q->in_use < ndesc)) {
  1237. struct sge_qset *qs = txq_to_qset(q, qid);
  1238. set_bit(qid, &qs->txq_stopped);
  1239. smp_mb__after_clear_bit();
  1240. if (should_restart_tx(q) &&
  1241. test_and_clear_bit(qid, &qs->txq_stopped))
  1242. return 2;
  1243. q->stops++;
  1244. goto addq_exit;
  1245. }
  1246. return 0;
  1247. }
  1248. /**
  1249. * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
  1250. * @q: the SGE control Tx queue
  1251. *
  1252. * This is a variant of reclaim_completed_tx() that is used for Tx queues
  1253. * that send only immediate data (presently just the control queues) and
  1254. * thus do not have any sk_buffs to release.
  1255. */
  1256. static inline void reclaim_completed_tx_imm(struct sge_txq *q)
  1257. {
  1258. unsigned int reclaim = q->processed - q->cleaned;
  1259. q->in_use -= reclaim;
  1260. q->cleaned += reclaim;
  1261. }
  1262. static inline int immediate(const struct sk_buff *skb)
  1263. {
  1264. return skb->len <= WR_LEN;
  1265. }
  1266. /**
  1267. * ctrl_xmit - send a packet through an SGE control Tx queue
  1268. * @adap: the adapter
  1269. * @q: the control queue
  1270. * @skb: the packet
  1271. *
  1272. * Send a packet through an SGE control Tx queue. Packets sent through
  1273. * a control queue must fit entirely as immediate data in a single Tx
  1274. * descriptor and have no page fragments.
  1275. */
  1276. static int ctrl_xmit(struct adapter *adap, struct sge_txq *q,
  1277. struct sk_buff *skb)
  1278. {
  1279. int ret;
  1280. struct work_request_hdr *wrp = (struct work_request_hdr *)skb->data;
  1281. if (unlikely(!immediate(skb))) {
  1282. WARN_ON(1);
  1283. dev_kfree_skb(skb);
  1284. return NET_XMIT_SUCCESS;
  1285. }
  1286. wrp->wr_hi |= htonl(F_WR_SOP | F_WR_EOP);
  1287. wrp->wr_lo = htonl(V_WR_TID(q->token));
  1288. spin_lock(&q->lock);
  1289. again:reclaim_completed_tx_imm(q);
  1290. ret = check_desc_avail(adap, q, skb, 1, TXQ_CTRL);
  1291. if (unlikely(ret)) {
  1292. if (ret == 1) {
  1293. spin_unlock(&q->lock);
  1294. return NET_XMIT_CN;
  1295. }
  1296. goto again;
  1297. }
  1298. write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
  1299. q->in_use++;
  1300. if (++q->pidx >= q->size) {
  1301. q->pidx = 0;
  1302. q->gen ^= 1;
  1303. }
  1304. spin_unlock(&q->lock);
  1305. wmb();
  1306. t3_write_reg(adap, A_SG_KDOORBELL,
  1307. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  1308. return NET_XMIT_SUCCESS;
  1309. }
  1310. /**
  1311. * restart_ctrlq - restart a suspended control queue
  1312. * @qs: the queue set cotaining the control queue
  1313. *
  1314. * Resumes transmission on a suspended Tx control queue.
  1315. */
  1316. static void restart_ctrlq(unsigned long data)
  1317. {
  1318. struct sk_buff *skb;
  1319. struct sge_qset *qs = (struct sge_qset *)data;
  1320. struct sge_txq *q = &qs->txq[TXQ_CTRL];
  1321. spin_lock(&q->lock);
  1322. again:reclaim_completed_tx_imm(q);
  1323. while (q->in_use < q->size &&
  1324. (skb = __skb_dequeue(&q->sendq)) != NULL) {
  1325. write_imm(&q->desc[q->pidx], skb, skb->len, q->gen);
  1326. if (++q->pidx >= q->size) {
  1327. q->pidx = 0;
  1328. q->gen ^= 1;
  1329. }
  1330. q->in_use++;
  1331. }
  1332. if (!skb_queue_empty(&q->sendq)) {
  1333. set_bit(TXQ_CTRL, &qs->txq_stopped);
  1334. smp_mb__after_clear_bit();
  1335. if (should_restart_tx(q) &&
  1336. test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped))
  1337. goto again;
  1338. q->stops++;
  1339. }
  1340. spin_unlock(&q->lock);
  1341. wmb();
  1342. t3_write_reg(qs->adap, A_SG_KDOORBELL,
  1343. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  1344. }
  1345. /*
  1346. * Send a management message through control queue 0
  1347. */
  1348. int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
  1349. {
  1350. int ret;
  1351. local_bh_disable();
  1352. ret = ctrl_xmit(adap, &adap->sge.qs[0].txq[TXQ_CTRL], skb);
  1353. local_bh_enable();
  1354. return ret;
  1355. }
  1356. /**
  1357. * deferred_unmap_destructor - unmap a packet when it is freed
  1358. * @skb: the packet
  1359. *
  1360. * This is the packet destructor used for Tx packets that need to remain
  1361. * mapped until they are freed rather than until their Tx descriptors are
  1362. * freed.
  1363. */
  1364. static void deferred_unmap_destructor(struct sk_buff *skb)
  1365. {
  1366. int i;
  1367. const dma_addr_t *p;
  1368. const struct skb_shared_info *si;
  1369. const struct deferred_unmap_info *dui;
  1370. dui = (struct deferred_unmap_info *)skb->head;
  1371. p = dui->addr;
  1372. if (skb->tail - skb->transport_header)
  1373. pci_unmap_single(dui->pdev, *p++,
  1374. skb->tail - skb->transport_header,
  1375. PCI_DMA_TODEVICE);
  1376. si = skb_shinfo(skb);
  1377. for (i = 0; i < si->nr_frags; i++)
  1378. pci_unmap_page(dui->pdev, *p++, si->frags[i].size,
  1379. PCI_DMA_TODEVICE);
  1380. }
  1381. static void setup_deferred_unmapping(struct sk_buff *skb, struct pci_dev *pdev,
  1382. const struct sg_ent *sgl, int sgl_flits)
  1383. {
  1384. dma_addr_t *p;
  1385. struct deferred_unmap_info *dui;
  1386. dui = (struct deferred_unmap_info *)skb->head;
  1387. dui->pdev = pdev;
  1388. for (p = dui->addr; sgl_flits >= 3; sgl++, sgl_flits -= 3) {
  1389. *p++ = be64_to_cpu(sgl->addr[0]);
  1390. *p++ = be64_to_cpu(sgl->addr[1]);
  1391. }
  1392. if (sgl_flits)
  1393. *p = be64_to_cpu(sgl->addr[0]);
  1394. }
  1395. /**
  1396. * write_ofld_wr - write an offload work request
  1397. * @adap: the adapter
  1398. * @skb: the packet to send
  1399. * @q: the Tx queue
  1400. * @pidx: index of the first Tx descriptor to write
  1401. * @gen: the generation value to use
  1402. * @ndesc: number of descriptors the packet will occupy
  1403. *
  1404. * Write an offload work request to send the supplied packet. The packet
  1405. * data already carry the work request with most fields populated.
  1406. */
  1407. static void write_ofld_wr(struct adapter *adap, struct sk_buff *skb,
  1408. struct sge_txq *q, unsigned int pidx,
  1409. unsigned int gen, unsigned int ndesc)
  1410. {
  1411. unsigned int sgl_flits, flits;
  1412. struct work_request_hdr *from;
  1413. struct sg_ent *sgp, sgl[MAX_SKB_FRAGS / 2 + 1];
  1414. struct tx_desc *d = &q->desc[pidx];
  1415. if (immediate(skb)) {
  1416. q->sdesc[pidx].skb = NULL;
  1417. write_imm(d, skb, skb->len, gen);
  1418. return;
  1419. }
  1420. /* Only TX_DATA builds SGLs */
  1421. from = (struct work_request_hdr *)skb->data;
  1422. memcpy(&d->flit[1], &from[1],
  1423. skb_transport_offset(skb) - sizeof(*from));
  1424. flits = skb_transport_offset(skb) / 8;
  1425. sgp = ndesc == 1 ? (struct sg_ent *)&d->flit[flits] : sgl;
  1426. sgl_flits = make_sgl(skb, sgp, skb_transport_header(skb),
  1427. skb->tail - skb->transport_header,
  1428. adap->pdev);
  1429. if (need_skb_unmap()) {
  1430. setup_deferred_unmapping(skb, adap->pdev, sgp, sgl_flits);
  1431. skb->destructor = deferred_unmap_destructor;
  1432. }
  1433. write_wr_hdr_sgl(ndesc, skb, d, pidx, q, sgl, flits, sgl_flits,
  1434. gen, from->wr_hi, from->wr_lo);
  1435. }
  1436. /**
  1437. * calc_tx_descs_ofld - calculate # of Tx descriptors for an offload packet
  1438. * @skb: the packet
  1439. *
  1440. * Returns the number of Tx descriptors needed for the given offload
  1441. * packet. These packets are already fully constructed.
  1442. */
  1443. static inline unsigned int calc_tx_descs_ofld(const struct sk_buff *skb)
  1444. {
  1445. unsigned int flits, cnt;
  1446. if (skb->len <= WR_LEN)
  1447. return 1; /* packet fits as immediate data */
  1448. flits = skb_transport_offset(skb) / 8; /* headers */
  1449. cnt = skb_shinfo(skb)->nr_frags;
  1450. if (skb->tail != skb->transport_header)
  1451. cnt++;
  1452. return flits_to_desc(flits + sgl_len(cnt));
  1453. }
  1454. /**
  1455. * ofld_xmit - send a packet through an offload queue
  1456. * @adap: the adapter
  1457. * @q: the Tx offload queue
  1458. * @skb: the packet
  1459. *
  1460. * Send an offload packet through an SGE offload queue.
  1461. */
  1462. static int ofld_xmit(struct adapter *adap, struct sge_txq *q,
  1463. struct sk_buff *skb)
  1464. {
  1465. int ret;
  1466. unsigned int ndesc = calc_tx_descs_ofld(skb), pidx, gen;
  1467. spin_lock(&q->lock);
  1468. again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
  1469. ret = check_desc_avail(adap, q, skb, ndesc, TXQ_OFLD);
  1470. if (unlikely(ret)) {
  1471. if (ret == 1) {
  1472. skb->priority = ndesc; /* save for restart */
  1473. spin_unlock(&q->lock);
  1474. return NET_XMIT_CN;
  1475. }
  1476. goto again;
  1477. }
  1478. gen = q->gen;
  1479. q->in_use += ndesc;
  1480. pidx = q->pidx;
  1481. q->pidx += ndesc;
  1482. if (q->pidx >= q->size) {
  1483. q->pidx -= q->size;
  1484. q->gen ^= 1;
  1485. }
  1486. spin_unlock(&q->lock);
  1487. write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
  1488. check_ring_tx_db(adap, q);
  1489. return NET_XMIT_SUCCESS;
  1490. }
  1491. /**
  1492. * restart_offloadq - restart a suspended offload queue
  1493. * @qs: the queue set cotaining the offload queue
  1494. *
  1495. * Resumes transmission on a suspended Tx offload queue.
  1496. */
  1497. static void restart_offloadq(unsigned long data)
  1498. {
  1499. struct sk_buff *skb;
  1500. struct sge_qset *qs = (struct sge_qset *)data;
  1501. struct sge_txq *q = &qs->txq[TXQ_OFLD];
  1502. const struct port_info *pi = netdev_priv(qs->netdev);
  1503. struct adapter *adap = pi->adapter;
  1504. spin_lock(&q->lock);
  1505. again: reclaim_completed_tx(adap, q, TX_RECLAIM_CHUNK);
  1506. while ((skb = skb_peek(&q->sendq)) != NULL) {
  1507. unsigned int gen, pidx;
  1508. unsigned int ndesc = skb->priority;
  1509. if (unlikely(q->size - q->in_use < ndesc)) {
  1510. set_bit(TXQ_OFLD, &qs->txq_stopped);
  1511. smp_mb__after_clear_bit();
  1512. if (should_restart_tx(q) &&
  1513. test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped))
  1514. goto again;
  1515. q->stops++;
  1516. break;
  1517. }
  1518. gen = q->gen;
  1519. q->in_use += ndesc;
  1520. pidx = q->pidx;
  1521. q->pidx += ndesc;
  1522. if (q->pidx >= q->size) {
  1523. q->pidx -= q->size;
  1524. q->gen ^= 1;
  1525. }
  1526. __skb_unlink(skb, &q->sendq);
  1527. spin_unlock(&q->lock);
  1528. write_ofld_wr(adap, skb, q, pidx, gen, ndesc);
  1529. spin_lock(&q->lock);
  1530. }
  1531. spin_unlock(&q->lock);
  1532. #if USE_GTS
  1533. set_bit(TXQ_RUNNING, &q->flags);
  1534. set_bit(TXQ_LAST_PKT_DB, &q->flags);
  1535. #endif
  1536. wmb();
  1537. t3_write_reg(adap, A_SG_KDOORBELL,
  1538. F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
  1539. }
  1540. /**
  1541. * queue_set - return the queue set a packet should use
  1542. * @skb: the packet
  1543. *
  1544. * Maps a packet to the SGE queue set it should use. The desired queue
  1545. * set is carried in bits 1-3 in the packet's priority.
  1546. */
  1547. static inline int queue_set(const struct sk_buff *skb)
  1548. {
  1549. return skb->priority >> 1;
  1550. }
  1551. /**
  1552. * is_ctrl_pkt - return whether an offload packet is a control packet
  1553. * @skb: the packet
  1554. *
  1555. * Determines whether an offload packet should use an OFLD or a CTRL
  1556. * Tx queue. This is indicated by bit 0 in the packet's priority.
  1557. */
  1558. static inline int is_ctrl_pkt(const struct sk_buff *skb)
  1559. {
  1560. return skb->priority & 1;
  1561. }
  1562. /**
  1563. * t3_offload_tx - send an offload packet
  1564. * @tdev: the offload device to send to
  1565. * @skb: the packet
  1566. *
  1567. * Sends an offload packet. We use the packet priority to select the
  1568. * appropriate Tx queue as follows: bit 0 indicates whether the packet
  1569. * should be sent as regular or control, bits 1-3 select the queue set.
  1570. */
  1571. int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
  1572. {
  1573. struct adapter *adap = tdev2adap(tdev);
  1574. struct sge_qset *qs = &adap->sge.qs[queue_set(skb)];
  1575. if (unlikely(is_ctrl_pkt(skb)))
  1576. return ctrl_xmit(adap, &qs->txq[TXQ_CTRL], skb);
  1577. return ofld_xmit(adap, &qs->txq[TXQ_OFLD], skb);
  1578. }
  1579. /**
  1580. * offload_enqueue - add an offload packet to an SGE offload receive queue
  1581. * @q: the SGE response queue
  1582. * @skb: the packet
  1583. *
  1584. * Add a new offload packet to an SGE response queue's offload packet
  1585. * queue. If the packet is the first on the queue it schedules the RX
  1586. * softirq to process the queue.
  1587. */
  1588. static inline void offload_enqueue(struct sge_rspq *q, struct sk_buff *skb)
  1589. {
  1590. int was_empty = skb_queue_empty(&q->rx_queue);
  1591. __skb_queue_tail(&q->rx_queue, skb);
  1592. if (was_empty) {
  1593. struct sge_qset *qs = rspq_to_qset(q);
  1594. napi_schedule(&qs->napi);
  1595. }
  1596. }
  1597. /**
  1598. * deliver_partial_bundle - deliver a (partial) bundle of Rx offload pkts
  1599. * @tdev: the offload device that will be receiving the packets
  1600. * @q: the SGE response queue that assembled the bundle
  1601. * @skbs: the partial bundle
  1602. * @n: the number of packets in the bundle
  1603. *
  1604. * Delivers a (partial) bundle of Rx offload packets to an offload device.
  1605. */
  1606. static inline void deliver_partial_bundle(struct t3cdev *tdev,
  1607. struct sge_rspq *q,
  1608. struct sk_buff *skbs[], int n)
  1609. {
  1610. if (n) {
  1611. q->offload_bundles++;
  1612. tdev->recv(tdev, skbs, n);
  1613. }
  1614. }
  1615. /**
  1616. * ofld_poll - NAPI handler for offload packets in interrupt mode
  1617. * @dev: the network device doing the polling
  1618. * @budget: polling budget
  1619. *
  1620. * The NAPI handler for offload packets when a response queue is serviced
  1621. * by the hard interrupt handler, i.e., when it's operating in non-polling
  1622. * mode. Creates small packet batches and sends them through the offload
  1623. * receive handler. Batches need to be of modest size as we do prefetches
  1624. * on the packets in each.
  1625. */
  1626. static int ofld_poll(struct napi_struct *napi, int budget)
  1627. {
  1628. struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
  1629. struct sge_rspq *q = &qs->rspq;
  1630. struct adapter *adapter = qs->adap;
  1631. int work_done = 0;
  1632. while (work_done < budget) {
  1633. struct sk_buff *skb, *tmp, *skbs[RX_BUNDLE_SIZE];
  1634. struct sk_buff_head queue;
  1635. int ngathered;
  1636. spin_lock_irq(&q->lock);
  1637. __skb_queue_head_init(&queue);
  1638. skb_queue_splice_init(&q->rx_queue, &queue);
  1639. if (skb_queue_empty(&queue)) {
  1640. napi_complete(napi);
  1641. spin_unlock_irq(&q->lock);
  1642. return work_done;
  1643. }
  1644. spin_unlock_irq(&q->lock);
  1645. ngathered = 0;
  1646. skb_queue_walk_safe(&queue, skb, tmp) {
  1647. if (work_done >= budget)
  1648. break;
  1649. work_done++;
  1650. __skb_unlink(skb, &queue);
  1651. prefetch(skb->data);
  1652. skbs[ngathered] = skb;
  1653. if (++ngathered == RX_BUNDLE_SIZE) {
  1654. q->offload_bundles++;
  1655. adapter->tdev.recv(&adapter->tdev, skbs,
  1656. ngathered);
  1657. ngathered = 0;
  1658. }
  1659. }
  1660. if (!skb_queue_empty(&queue)) {
  1661. /* splice remaining packets back onto Rx queue */
  1662. spin_lock_irq(&q->lock);
  1663. skb_queue_splice(&queue, &q->rx_queue);
  1664. spin_unlock_irq(&q->lock);
  1665. }
  1666. deliver_partial_bundle(&adapter->tdev, q, skbs, ngathered);
  1667. }
  1668. return work_done;
  1669. }
  1670. /**
  1671. * rx_offload - process a received offload packet
  1672. * @tdev: the offload device receiving the packet
  1673. * @rq: the response queue that received the packet
  1674. * @skb: the packet
  1675. * @rx_gather: a gather list of packets if we are building a bundle
  1676. * @gather_idx: index of the next available slot in the bundle
  1677. *
  1678. * Process an ingress offload pakcet and add it to the offload ingress
  1679. * queue. Returns the index of the next available slot in the bundle.
  1680. */
  1681. static inline int rx_offload(struct t3cdev *tdev, struct sge_rspq *rq,
  1682. struct sk_buff *skb, struct sk_buff *rx_gather[],
  1683. unsigned int gather_idx)
  1684. {
  1685. skb_reset_mac_header(skb);
  1686. skb_reset_network_header(skb);
  1687. skb_reset_transport_header(skb);
  1688. if (rq->polling) {
  1689. rx_gather[gather_idx++] = skb;
  1690. if (gather_idx == RX_BUNDLE_SIZE) {
  1691. tdev->recv(tdev, rx_gather, RX_BUNDLE_SIZE);
  1692. gather_idx = 0;
  1693. rq->offload_bundles++;
  1694. }
  1695. } else
  1696. offload_enqueue(rq, skb);
  1697. return gather_idx;
  1698. }
  1699. /**
  1700. * restart_tx - check whether to restart suspended Tx queues
  1701. * @qs: the queue set to resume
  1702. *
  1703. * Restarts suspended Tx queues of an SGE queue set if they have enough
  1704. * free resources to resume operation.
  1705. */
  1706. static void restart_tx(struct sge_qset *qs)
  1707. {
  1708. if (test_bit(TXQ_ETH, &qs->txq_stopped) &&
  1709. should_restart_tx(&qs->txq[TXQ_ETH]) &&
  1710. test_and_clear_bit(TXQ_ETH, &qs->txq_stopped)) {
  1711. qs->txq[TXQ_ETH].restarts++;
  1712. if (netif_running(qs->netdev))
  1713. netif_tx_wake_queue(qs->tx_q);
  1714. }
  1715. if (test_bit(TXQ_OFLD, &qs->txq_stopped) &&
  1716. should_restart_tx(&qs->txq[TXQ_OFLD]) &&
  1717. test_and_clear_bit(TXQ_OFLD, &qs->txq_stopped)) {
  1718. qs->txq[TXQ_OFLD].restarts++;
  1719. tasklet_schedule(&qs->txq[TXQ_OFLD].qresume_tsk);
  1720. }
  1721. if (test_bit(TXQ_CTRL, &qs->txq_stopped) &&
  1722. should_restart_tx(&qs->txq[TXQ_CTRL]) &&
  1723. test_and_clear_bit(TXQ_CTRL, &qs->txq_stopped)) {
  1724. qs->txq[TXQ_CTRL].restarts++;
  1725. tasklet_schedule(&qs->txq[TXQ_CTRL].qresume_tsk);
  1726. }
  1727. }
  1728. /**
  1729. * cxgb3_arp_process - process an ARP request probing a private IP address
  1730. * @adapter: the adapter
  1731. * @skb: the skbuff containing the ARP request
  1732. *
  1733. * Check if the ARP request is probing the private IP address
  1734. * dedicated to iSCSI, generate an ARP reply if so.
  1735. */
  1736. static void cxgb3_arp_process(struct port_info *pi, struct sk_buff *skb)
  1737. {
  1738. struct net_device *dev = skb->dev;
  1739. struct arphdr *arp;
  1740. unsigned char *arp_ptr;
  1741. unsigned char *sha;
  1742. __be32 sip, tip;
  1743. if (!dev)
  1744. return;
  1745. skb_reset_network_header(skb);
  1746. arp = arp_hdr(skb);
  1747. if (arp->ar_op != htons(ARPOP_REQUEST))
  1748. return;
  1749. arp_ptr = (unsigned char *)(arp + 1);
  1750. sha = arp_ptr;
  1751. arp_ptr += dev->addr_len;
  1752. memcpy(&sip, arp_ptr, sizeof(sip));
  1753. arp_ptr += sizeof(sip);
  1754. arp_ptr += dev->addr_len;
  1755. memcpy(&tip, arp_ptr, sizeof(tip));
  1756. if (tip != pi->iscsi_ipv4addr)
  1757. return;
  1758. arp_send(ARPOP_REPLY, ETH_P_ARP, sip, dev, tip, sha,
  1759. pi->iscsic.mac_addr, sha);
  1760. }
  1761. static inline int is_arp(struct sk_buff *skb)
  1762. {
  1763. return skb->protocol == htons(ETH_P_ARP);
  1764. }
  1765. static void cxgb3_process_iscsi_prov_pack(struct port_info *pi,
  1766. struct sk_buff *skb)
  1767. {
  1768. if (is_arp(skb)) {
  1769. cxgb3_arp_process(pi, skb);
  1770. return;
  1771. }
  1772. if (pi->iscsic.recv)
  1773. pi->iscsic.recv(pi, skb);
  1774. }
  1775. /**
  1776. * rx_eth - process an ingress ethernet packet
  1777. * @adap: the adapter
  1778. * @rq: the response queue that received the packet
  1779. * @skb: the packet
  1780. * @pad: amount of padding at the start of the buffer
  1781. *
  1782. * Process an ingress ethernet pakcet and deliver it to the stack.
  1783. * The padding is 2 if the packet was delivered in an Rx buffer and 0
  1784. * if it was immediate data in a response.
  1785. */
  1786. static void rx_eth(struct adapter *adap, struct sge_rspq *rq,
  1787. struct sk_buff *skb, int pad, int lro)
  1788. {
  1789. struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)(skb->data + pad);
  1790. struct sge_qset *qs = rspq_to_qset(rq);
  1791. struct port_info *pi;
  1792. skb_pull(skb, sizeof(*p) + pad);
  1793. skb->protocol = eth_type_trans(skb, adap->port[p->iff]);
  1794. pi = netdev_priv(skb->dev);
  1795. if ((skb->dev->features & NETIF_F_RXCSUM) && p->csum_valid &&
  1796. p->csum == htons(0xffff) && !p->fragment) {
  1797. qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
  1798. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1799. } else
  1800. skb_checksum_none_assert(skb);
  1801. skb_record_rx_queue(skb, qs - &adap->sge.qs[0]);
  1802. if (unlikely(p->vlan_valid)) {
  1803. struct vlan_group *grp = pi->vlan_grp;
  1804. qs->port_stats[SGE_PSTAT_VLANEX]++;
  1805. if (likely(grp))
  1806. if (lro)
  1807. vlan_gro_receive(&qs->napi, grp,
  1808. ntohs(p->vlan), skb);
  1809. else {
  1810. if (unlikely(pi->iscsic.flags)) {
  1811. unsigned short vtag = ntohs(p->vlan) &
  1812. VLAN_VID_MASK;
  1813. skb->dev = vlan_group_get_device(grp,
  1814. vtag);
  1815. cxgb3_process_iscsi_prov_pack(pi, skb);
  1816. }
  1817. __vlan_hwaccel_rx(skb, grp, ntohs(p->vlan),
  1818. rq->polling);
  1819. }
  1820. else
  1821. dev_kfree_skb_any(skb);
  1822. } else if (rq->polling) {
  1823. if (lro)
  1824. napi_gro_receive(&qs->napi, skb);
  1825. else {
  1826. if (unlikely(pi->iscsic.flags))
  1827. cxgb3_process_iscsi_prov_pack(pi, skb);
  1828. netif_receive_skb(skb);
  1829. }
  1830. } else
  1831. netif_rx(skb);
  1832. }
  1833. static inline int is_eth_tcp(u32 rss)
  1834. {
  1835. return G_HASHTYPE(ntohl(rss)) == RSS_HASH_4_TUPLE;
  1836. }
  1837. /**
  1838. * lro_add_page - add a page chunk to an LRO session
  1839. * @adap: the adapter
  1840. * @qs: the associated queue set
  1841. * @fl: the free list containing the page chunk to add
  1842. * @len: packet length
  1843. * @complete: Indicates the last fragment of a frame
  1844. *
  1845. * Add a received packet contained in a page chunk to an existing LRO
  1846. * session.
  1847. */
  1848. static void lro_add_page(struct adapter *adap, struct sge_qset *qs,
  1849. struct sge_fl *fl, int len, int complete)
  1850. {
  1851. struct rx_sw_desc *sd = &fl->sdesc[fl->cidx];
  1852. struct port_info *pi = netdev_priv(qs->netdev);
  1853. struct sk_buff *skb = NULL;
  1854. struct cpl_rx_pkt *cpl;
  1855. struct skb_frag_struct *rx_frag;
  1856. int nr_frags;
  1857. int offset = 0;
  1858. if (!qs->nomem) {
  1859. skb = napi_get_frags(&qs->napi);
  1860. qs->nomem = !skb;
  1861. }
  1862. fl->credits--;
  1863. pci_dma_sync_single_for_cpu(adap->pdev,
  1864. dma_unmap_addr(sd, dma_addr),
  1865. fl->buf_size - SGE_PG_RSVD,
  1866. PCI_DMA_FROMDEVICE);
  1867. (*sd->pg_chunk.p_cnt)--;
  1868. if (!*sd->pg_chunk.p_cnt && sd->pg_chunk.page != fl->pg_chunk.page)
  1869. pci_unmap_page(adap->pdev,
  1870. sd->pg_chunk.mapping,
  1871. fl->alloc_size,
  1872. PCI_DMA_FROMDEVICE);
  1873. if (!skb) {
  1874. put_page(sd->pg_chunk.page);
  1875. if (complete)
  1876. qs->nomem = 0;
  1877. return;
  1878. }
  1879. rx_frag = skb_shinfo(skb)->frags;
  1880. nr_frags = skb_shinfo(skb)->nr_frags;
  1881. if (!nr_frags) {
  1882. offset = 2 + sizeof(struct cpl_rx_pkt);
  1883. cpl = qs->lro_va = sd->pg_chunk.va + 2;
  1884. if ((qs->netdev->features & NETIF_F_RXCSUM) &&
  1885. cpl->csum_valid && cpl->csum == htons(0xffff)) {
  1886. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1887. qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++;
  1888. } else
  1889. skb->ip_summed = CHECKSUM_NONE;
  1890. } else
  1891. cpl = qs->lro_va;
  1892. len -= offset;
  1893. rx_frag += nr_frags;
  1894. rx_frag->page = sd->pg_chunk.page;
  1895. rx_frag->page_offset = sd->pg_chunk.offset + offset;
  1896. rx_frag->size = len;
  1897. skb->len += len;
  1898. skb->data_len += len;
  1899. skb->truesize += len;
  1900. skb_shinfo(skb)->nr_frags++;
  1901. if (!complete)
  1902. return;
  1903. skb_record_rx_queue(skb, qs - &adap->sge.qs[0]);
  1904. if (unlikely(cpl->vlan_valid)) {
  1905. struct vlan_group *grp = pi->vlan_grp;
  1906. if (likely(grp != NULL)) {
  1907. vlan_gro_frags(&qs->napi, grp, ntohs(cpl->vlan));
  1908. return;
  1909. }
  1910. }
  1911. napi_gro_frags(&qs->napi);
  1912. }
  1913. /**
  1914. * handle_rsp_cntrl_info - handles control information in a response
  1915. * @qs: the queue set corresponding to the response
  1916. * @flags: the response control flags
  1917. *
  1918. * Handles the control information of an SGE response, such as GTS
  1919. * indications and completion credits for the queue set's Tx queues.
  1920. * HW coalesces credits, we don't do any extra SW coalescing.
  1921. */
  1922. static inline void handle_rsp_cntrl_info(struct sge_qset *qs, u32 flags)
  1923. {
  1924. unsigned int credits;
  1925. #if USE_GTS
  1926. if (flags & F_RSPD_TXQ0_GTS)
  1927. clear_bit(TXQ_RUNNING, &qs->txq[TXQ_ETH].flags);
  1928. #endif
  1929. credits = G_RSPD_TXQ0_CR(flags);
  1930. if (credits)
  1931. qs->txq[TXQ_ETH].processed += credits;
  1932. credits = G_RSPD_TXQ2_CR(flags);
  1933. if (credits)
  1934. qs->txq[TXQ_CTRL].processed += credits;
  1935. # if USE_GTS
  1936. if (flags & F_RSPD_TXQ1_GTS)
  1937. clear_bit(TXQ_RUNNING, &qs->txq[TXQ_OFLD].flags);
  1938. # endif
  1939. credits = G_RSPD_TXQ1_CR(flags);
  1940. if (credits)
  1941. qs->txq[TXQ_OFLD].processed += credits;
  1942. }
  1943. /**
  1944. * check_ring_db - check if we need to ring any doorbells
  1945. * @adapter: the adapter
  1946. * @qs: the queue set whose Tx queues are to be examined
  1947. * @sleeping: indicates which Tx queue sent GTS
  1948. *
  1949. * Checks if some of a queue set's Tx queues need to ring their doorbells
  1950. * to resume transmission after idling while they still have unprocessed
  1951. * descriptors.
  1952. */
  1953. static void check_ring_db(struct adapter *adap, struct sge_qset *qs,
  1954. unsigned int sleeping)
  1955. {
  1956. if (sleeping & F_RSPD_TXQ0_GTS) {
  1957. struct sge_txq *txq = &qs->txq[TXQ_ETH];
  1958. if (txq->cleaned + txq->in_use != txq->processed &&
  1959. !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
  1960. set_bit(TXQ_RUNNING, &txq->flags);
  1961. t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
  1962. V_EGRCNTX(txq->cntxt_id));
  1963. }
  1964. }
  1965. if (sleeping & F_RSPD_TXQ1_GTS) {
  1966. struct sge_txq *txq = &qs->txq[TXQ_OFLD];
  1967. if (txq->cleaned + txq->in_use != txq->processed &&
  1968. !test_and_set_bit(TXQ_LAST_PKT_DB, &txq->flags)) {
  1969. set_bit(TXQ_RUNNING, &txq->flags);
  1970. t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX |
  1971. V_EGRCNTX(txq->cntxt_id));
  1972. }
  1973. }
  1974. }
  1975. /**
  1976. * is_new_response - check if a response is newly written
  1977. * @r: the response descriptor
  1978. * @q: the response queue
  1979. *
  1980. * Returns true if a response descriptor contains a yet unprocessed
  1981. * response.
  1982. */
  1983. static inline int is_new_response(const struct rsp_desc *r,
  1984. const struct sge_rspq *q)
  1985. {
  1986. return (r->intr_gen & F_RSPD_GEN2) == q->gen;
  1987. }
  1988. static inline void clear_rspq_bufstate(struct sge_rspq * const q)
  1989. {
  1990. q->pg_skb = NULL;
  1991. q->rx_recycle_buf = 0;
  1992. }
  1993. #define RSPD_GTS_MASK (F_RSPD_TXQ0_GTS | F_RSPD_TXQ1_GTS)
  1994. #define RSPD_CTRL_MASK (RSPD_GTS_MASK | \
  1995. V_RSPD_TXQ0_CR(M_RSPD_TXQ0_CR) | \
  1996. V_RSPD_TXQ1_CR(M_RSPD_TXQ1_CR) | \
  1997. V_RSPD_TXQ2_CR(M_RSPD_TXQ2_CR))
  1998. /* How long to delay the next interrupt in case of memory shortage, in 0.1us. */
  1999. #define NOMEM_INTR_DELAY 2500
  2000. /**
  2001. * process_responses - process responses from an SGE response queue
  2002. * @adap: the adapter
  2003. * @qs: the queue set to which the response queue belongs
  2004. * @budget: how many responses can be processed in this round
  2005. *
  2006. * Process responses from an SGE response queue up to the supplied budget.
  2007. * Responses include received packets as well as credits and other events
  2008. * for the queues that belong to the response queue's queue set.
  2009. * A negative budget is effectively unlimited.
  2010. *
  2011. * Additionally choose the interrupt holdoff time for the next interrupt
  2012. * on this queue. If the system is under memory shortage use a fairly
  2013. * long delay to help recovery.
  2014. */
  2015. static int process_responses(struct adapter *adap, struct sge_qset *qs,
  2016. int budget)
  2017. {
  2018. struct sge_rspq *q = &qs->rspq;
  2019. struct rsp_desc *r = &q->desc[q->cidx];
  2020. int budget_left = budget;
  2021. unsigned int sleeping = 0;
  2022. struct sk_buff *offload_skbs[RX_BUNDLE_SIZE];
  2023. int ngathered = 0;
  2024. q->next_holdoff = q->holdoff_tmr;
  2025. while (likely(budget_left && is_new_response(r, q))) {
  2026. int packet_complete, eth, ethpad = 2;
  2027. int lro = !!(qs->netdev->features & NETIF_F_GRO);
  2028. struct sk_buff *skb = NULL;
  2029. u32 len, flags;
  2030. __be32 rss_hi, rss_lo;
  2031. rmb();
  2032. eth = r->rss_hdr.opcode == CPL_RX_PKT;
  2033. rss_hi = *(const __be32 *)r;
  2034. rss_lo = r->rss_hdr.rss_hash_val;
  2035. flags = ntohl(r->flags);
  2036. if (unlikely(flags & F_RSPD_ASYNC_NOTIF)) {
  2037. skb = alloc_skb(AN_PKT_SIZE, GFP_ATOMIC);
  2038. if (!skb)
  2039. goto no_mem;
  2040. memcpy(__skb_put(skb, AN_PKT_SIZE), r, AN_PKT_SIZE);
  2041. skb->data[0] = CPL_ASYNC_NOTIF;
  2042. rss_hi = htonl(CPL_ASYNC_NOTIF << 24);
  2043. q->async_notif++;
  2044. } else if (flags & F_RSPD_IMM_DATA_VALID) {
  2045. skb = get_imm_packet(r);
  2046. if (unlikely(!skb)) {
  2047. no_mem:
  2048. q->next_holdoff = NOMEM_INTR_DELAY;
  2049. q->nomem++;
  2050. /* consume one credit since we tried */
  2051. budget_left--;
  2052. break;
  2053. }
  2054. q->imm_data++;
  2055. ethpad = 0;
  2056. } else if ((len = ntohl(r->len_cq)) != 0) {
  2057. struct sge_fl *fl;
  2058. lro &= eth && is_eth_tcp(rss_hi);
  2059. fl = (len & F_RSPD_FLQ) ? &qs->fl[1] : &qs->fl[0];
  2060. if (fl->use_pages) {
  2061. void *addr = fl->sdesc[fl->cidx].pg_chunk.va;
  2062. prefetch(addr);
  2063. #if L1_CACHE_BYTES < 128
  2064. prefetch(addr + L1_CACHE_BYTES);
  2065. #endif
  2066. __refill_fl(adap, fl);
  2067. if (lro > 0) {
  2068. lro_add_page(adap, qs, fl,
  2069. G_RSPD_LEN(len),
  2070. flags & F_RSPD_EOP);
  2071. goto next_fl;
  2072. }
  2073. skb = get_packet_pg(adap, fl, q,
  2074. G_RSPD_LEN(len),
  2075. eth ?
  2076. SGE_RX_DROP_THRES : 0);
  2077. q->pg_skb = skb;
  2078. } else
  2079. skb = get_packet(adap, fl, G_RSPD_LEN(len),
  2080. eth ? SGE_RX_DROP_THRES : 0);
  2081. if (unlikely(!skb)) {
  2082. if (!eth)
  2083. goto no_mem;
  2084. q->rx_drops++;
  2085. } else if (unlikely(r->rss_hdr.opcode == CPL_TRACE_PKT))
  2086. __skb_pull(skb, 2);
  2087. next_fl:
  2088. if (++fl->cidx == fl->size)
  2089. fl->cidx = 0;
  2090. } else
  2091. q->pure_rsps++;
  2092. if (flags & RSPD_CTRL_MASK) {
  2093. sleeping |= flags & RSPD_GTS_MASK;
  2094. handle_rsp_cntrl_info(qs, flags);
  2095. }
  2096. r++;
  2097. if (unlikely(++q->cidx == q->size)) {
  2098. q->cidx = 0;
  2099. q->gen ^= 1;
  2100. r = q->desc;
  2101. }
  2102. prefetch(r);
  2103. if (++q->credits >= (q->size / 4)) {
  2104. refill_rspq(adap, q, q->credits);
  2105. q->credits = 0;
  2106. }
  2107. packet_complete = flags &
  2108. (F_RSPD_EOP | F_RSPD_IMM_DATA_VALID |
  2109. F_RSPD_ASYNC_NOTIF);
  2110. if (skb != NULL && packet_complete) {
  2111. if (eth)
  2112. rx_eth(adap, q, skb, ethpad, lro);
  2113. else {
  2114. q->offload_pkts++;
  2115. /* Preserve the RSS info in csum & priority */
  2116. skb->csum = rss_hi;
  2117. skb->priority = rss_lo;
  2118. ngathered = rx_offload(&adap->tdev, q, skb,
  2119. offload_skbs,
  2120. ngathered);
  2121. }
  2122. if (flags & F_RSPD_EOP)
  2123. clear_rspq_bufstate(q);
  2124. }
  2125. --budget_left;
  2126. }
  2127. deliver_partial_bundle(&adap->tdev, q, offload_skbs, ngathered);
  2128. if (sleeping)
  2129. check_ring_db(adap, qs, sleeping);
  2130. smp_mb(); /* commit Tx queue .processed updates */
  2131. if (unlikely(qs->txq_stopped != 0))
  2132. restart_tx(qs);
  2133. budget -= budget_left;
  2134. return budget;
  2135. }
  2136. static inline int is_pure_response(const struct rsp_desc *r)
  2137. {
  2138. __be32 n = r->flags & htonl(F_RSPD_ASYNC_NOTIF | F_RSPD_IMM_DATA_VALID);
  2139. return (n | r->len_cq) == 0;
  2140. }
  2141. /**
  2142. * napi_rx_handler - the NAPI handler for Rx processing
  2143. * @napi: the napi instance
  2144. * @budget: how many packets we can process in this round
  2145. *
  2146. * Handler for new data events when using NAPI.
  2147. */
  2148. static int napi_rx_handler(struct napi_struct *napi, int budget)
  2149. {
  2150. struct sge_qset *qs = container_of(napi, struct sge_qset, napi);
  2151. struct adapter *adap = qs->adap;
  2152. int work_done = process_responses(adap, qs, budget);
  2153. if (likely(work_done < budget)) {
  2154. napi_complete(napi);
  2155. /*
  2156. * Because we don't atomically flush the following
  2157. * write it is possible that in very rare cases it can
  2158. * reach the device in a way that races with a new
  2159. * response being written plus an error interrupt
  2160. * causing the NAPI interrupt handler below to return
  2161. * unhandled status to the OS. To protect against
  2162. * this would require flushing the write and doing
  2163. * both the write and the flush with interrupts off.
  2164. * Way too expensive and unjustifiable given the
  2165. * rarity of the race.
  2166. *
  2167. * The race cannot happen at all with MSI-X.
  2168. */
  2169. t3_write_reg(adap, A_SG_GTS, V_RSPQ(qs->rspq.cntxt_id) |
  2170. V_NEWTIMER(qs->rspq.next_holdoff) |
  2171. V_NEWINDEX(qs->rspq.cidx));
  2172. }
  2173. return work_done;
  2174. }
  2175. /*
  2176. * Returns true if the device is already scheduled for polling.
  2177. */
  2178. static inline int napi_is_scheduled(struct napi_struct *napi)
  2179. {
  2180. return test_bit(NAPI_STATE_SCHED, &napi->state);
  2181. }
  2182. /**
  2183. * process_pure_responses - process pure responses from a response queue
  2184. * @adap: the adapter
  2185. * @qs: the queue set owning the response queue
  2186. * @r: the first pure response to process
  2187. *
  2188. * A simpler version of process_responses() that handles only pure (i.e.,
  2189. * non data-carrying) responses. Such respones are too light-weight to
  2190. * justify calling a softirq under NAPI, so we handle them specially in
  2191. * the interrupt handler. The function is called with a pointer to a
  2192. * response, which the caller must ensure is a valid pure response.
  2193. *
  2194. * Returns 1 if it encounters a valid data-carrying response, 0 otherwise.
  2195. */
  2196. static int process_pure_responses(struct adapter *adap, struct sge_qset *qs,
  2197. struct rsp_desc *r)
  2198. {
  2199. struct sge_rspq *q = &qs->rspq;
  2200. unsigned int sleeping = 0;
  2201. do {
  2202. u32 flags = ntohl(r->flags);
  2203. r++;
  2204. if (unlikely(++q->cidx == q->size)) {
  2205. q->cidx = 0;
  2206. q->gen ^= 1;
  2207. r = q->desc;
  2208. }
  2209. prefetch(r);
  2210. if (flags & RSPD_CTRL_MASK) {
  2211. sleeping |= flags & RSPD_GTS_MASK;
  2212. handle_rsp_cntrl_info(qs, flags);
  2213. }
  2214. q->pure_rsps++;
  2215. if (++q->credits >= (q->size / 4)) {
  2216. refill_rspq(adap, q, q->credits);
  2217. q->credits = 0;
  2218. }
  2219. if (!is_new_response(r, q))
  2220. break;
  2221. rmb();
  2222. } while (is_pure_response(r));
  2223. if (sleeping)
  2224. check_ring_db(adap, qs, sleeping);
  2225. smp_mb(); /* commit Tx queue .processed updates */
  2226. if (unlikely(qs->txq_stopped != 0))
  2227. restart_tx(qs);
  2228. return is_new_response(r, q);
  2229. }
  2230. /**
  2231. * handle_responses - decide what to do with new responses in NAPI mode
  2232. * @adap: the adapter
  2233. * @q: the response queue
  2234. *
  2235. * This is used by the NAPI interrupt handlers to decide what to do with
  2236. * new SGE responses. If there are no new responses it returns -1. If
  2237. * there are new responses and they are pure (i.e., non-data carrying)
  2238. * it handles them straight in hard interrupt context as they are very
  2239. * cheap and don't deliver any packets. Finally, if there are any data
  2240. * signaling responses it schedules the NAPI handler. Returns 1 if it
  2241. * schedules NAPI, 0 if all new responses were pure.
  2242. *
  2243. * The caller must ascertain NAPI is not already running.
  2244. */
  2245. static inline int handle_responses(struct adapter *adap, struct sge_rspq *q)
  2246. {
  2247. struct sge_qset *qs = rspq_to_qset(q);
  2248. struct rsp_desc *r = &q->desc[q->cidx];
  2249. if (!is_new_response(r, q))
  2250. return -1;
  2251. rmb();
  2252. if (is_pure_response(r) && process_pure_responses(adap, qs, r) == 0) {
  2253. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
  2254. V_NEWTIMER(q->holdoff_tmr) | V_NEWINDEX(q->cidx));
  2255. return 0;
  2256. }
  2257. napi_schedule(&qs->napi);
  2258. return 1;
  2259. }
  2260. /*
  2261. * The MSI-X interrupt handler for an SGE response queue for the non-NAPI case
  2262. * (i.e., response queue serviced in hard interrupt).
  2263. */
  2264. static irqreturn_t t3_sge_intr_msix(int irq, void *cookie)
  2265. {
  2266. struct sge_qset *qs = cookie;
  2267. struct adapter *adap = qs->adap;
  2268. struct sge_rspq *q = &qs->rspq;
  2269. spin_lock(&q->lock);
  2270. if (process_responses(adap, qs, -1) == 0)
  2271. q->unhandled_irqs++;
  2272. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
  2273. V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
  2274. spin_unlock(&q->lock);
  2275. return IRQ_HANDLED;
  2276. }
  2277. /*
  2278. * The MSI-X interrupt handler for an SGE response queue for the NAPI case
  2279. * (i.e., response queue serviced by NAPI polling).
  2280. */
  2281. static irqreturn_t t3_sge_intr_msix_napi(int irq, void *cookie)
  2282. {
  2283. struct sge_qset *qs = cookie;
  2284. struct sge_rspq *q = &qs->rspq;
  2285. spin_lock(&q->lock);
  2286. if (handle_responses(qs->adap, q) < 0)
  2287. q->unhandled_irqs++;
  2288. spin_unlock(&q->lock);
  2289. return IRQ_HANDLED;
  2290. }
  2291. /*
  2292. * The non-NAPI MSI interrupt handler. This needs to handle data events from
  2293. * SGE response queues as well as error and other async events as they all use
  2294. * the same MSI vector. We use one SGE response queue per port in this mode
  2295. * and protect all response queues with queue 0's lock.
  2296. */
  2297. static irqreturn_t t3_intr_msi(int irq, void *cookie)
  2298. {
  2299. int new_packets = 0;
  2300. struct adapter *adap = cookie;
  2301. struct sge_rspq *q = &adap->sge.qs[0].rspq;
  2302. spin_lock(&q->lock);
  2303. if (process_responses(adap, &adap->sge.qs[0], -1)) {
  2304. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q->cntxt_id) |
  2305. V_NEWTIMER(q->next_holdoff) | V_NEWINDEX(q->cidx));
  2306. new_packets = 1;
  2307. }
  2308. if (adap->params.nports == 2 &&
  2309. process_responses(adap, &adap->sge.qs[1], -1)) {
  2310. struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
  2311. t3_write_reg(adap, A_SG_GTS, V_RSPQ(q1->cntxt_id) |
  2312. V_NEWTIMER(q1->next_holdoff) |
  2313. V_NEWINDEX(q1->cidx));
  2314. new_packets = 1;
  2315. }
  2316. if (!new_packets && t3_slow_intr_handler(adap) == 0)
  2317. q->unhandled_irqs++;
  2318. spin_unlock(&q->lock);
  2319. return IRQ_HANDLED;
  2320. }
  2321. static int rspq_check_napi(struct sge_qset *qs)
  2322. {
  2323. struct sge_rspq *q = &qs->rspq;
  2324. if (!napi_is_scheduled(&qs->napi) &&
  2325. is_new_response(&q->desc[q->cidx], q)) {
  2326. napi_schedule(&qs->napi);
  2327. return 1;
  2328. }
  2329. return 0;
  2330. }
  2331. /*
  2332. * The MSI interrupt handler for the NAPI case (i.e., response queues serviced
  2333. * by NAPI polling). Handles data events from SGE response queues as well as
  2334. * error and other async events as they all use the same MSI vector. We use
  2335. * one SGE response queue per port in this mode and protect all response
  2336. * queues with queue 0's lock.
  2337. */
  2338. static irqreturn_t t3_intr_msi_napi(int irq, void *cookie)
  2339. {
  2340. int new_packets;
  2341. struct adapter *adap = cookie;
  2342. struct sge_rspq *q = &adap->sge.qs[0].rspq;
  2343. spin_lock(&q->lock);
  2344. new_packets = rspq_check_napi(&adap->sge.qs[0]);
  2345. if (adap->params.nports == 2)
  2346. new_packets += rspq_check_napi(&adap->sge.qs[1]);
  2347. if (!new_packets && t3_slow_intr_handler(adap) == 0)
  2348. q->unhandled_irqs++;
  2349. spin_unlock(&q->lock);
  2350. return IRQ_HANDLED;
  2351. }
  2352. /*
  2353. * A helper function that processes responses and issues GTS.
  2354. */
  2355. static inline int process_responses_gts(struct adapter *adap,
  2356. struct sge_rspq *rq)
  2357. {
  2358. int work;
  2359. work = process_responses(adap, rspq_to_qset(rq), -1);
  2360. t3_write_reg(adap, A_SG_GTS, V_RSPQ(rq->cntxt_id) |
  2361. V_NEWTIMER(rq->next_holdoff) | V_NEWINDEX(rq->cidx));
  2362. return work;
  2363. }
  2364. /*
  2365. * The legacy INTx interrupt handler. This needs to handle data events from
  2366. * SGE response queues as well as error and other async events as they all use
  2367. * the same interrupt pin. We use one SGE response queue per port in this mode
  2368. * and protect all response queues with queue 0's lock.
  2369. */
  2370. static irqreturn_t t3_intr(int irq, void *cookie)
  2371. {
  2372. int work_done, w0, w1;
  2373. struct adapter *adap = cookie;
  2374. struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
  2375. struct sge_rspq *q1 = &adap->sge.qs[1].rspq;
  2376. spin_lock(&q0->lock);
  2377. w0 = is_new_response(&q0->desc[q0->cidx], q0);
  2378. w1 = adap->params.nports == 2 &&
  2379. is_new_response(&q1->desc[q1->cidx], q1);
  2380. if (likely(w0 | w1)) {
  2381. t3_write_reg(adap, A_PL_CLI, 0);
  2382. t3_read_reg(adap, A_PL_CLI); /* flush */
  2383. if (likely(w0))
  2384. process_responses_gts(adap, q0);
  2385. if (w1)
  2386. process_responses_gts(adap, q1);
  2387. work_done = w0 | w1;
  2388. } else
  2389. work_done = t3_slow_intr_handler(adap);
  2390. spin_unlock(&q0->lock);
  2391. return IRQ_RETVAL(work_done != 0);
  2392. }
  2393. /*
  2394. * Interrupt handler for legacy INTx interrupts for T3B-based cards.
  2395. * Handles data events from SGE response queues as well as error and other
  2396. * async events as they all use the same interrupt pin. We use one SGE
  2397. * response queue per port in this mode and protect all response queues with
  2398. * queue 0's lock.
  2399. */
  2400. static irqreturn_t t3b_intr(int irq, void *cookie)
  2401. {
  2402. u32 map;
  2403. struct adapter *adap = cookie;
  2404. struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
  2405. t3_write_reg(adap, A_PL_CLI, 0);
  2406. map = t3_read_reg(adap, A_SG_DATA_INTR);
  2407. if (unlikely(!map)) /* shared interrupt, most likely */
  2408. return IRQ_NONE;
  2409. spin_lock(&q0->lock);
  2410. if (unlikely(map & F_ERRINTR))
  2411. t3_slow_intr_handler(adap);
  2412. if (likely(map & 1))
  2413. process_responses_gts(adap, q0);
  2414. if (map & 2)
  2415. process_responses_gts(adap, &adap->sge.qs[1].rspq);
  2416. spin_unlock(&q0->lock);
  2417. return IRQ_HANDLED;
  2418. }
  2419. /*
  2420. * NAPI interrupt handler for legacy INTx interrupts for T3B-based cards.
  2421. * Handles data events from SGE response queues as well as error and other
  2422. * async events as they all use the same interrupt pin. We use one SGE
  2423. * response queue per port in this mode and protect all response queues with
  2424. * queue 0's lock.
  2425. */
  2426. static irqreturn_t t3b_intr_napi(int irq, void *cookie)
  2427. {
  2428. u32 map;
  2429. struct adapter *adap = cookie;
  2430. struct sge_qset *qs0 = &adap->sge.qs[0];
  2431. struct sge_rspq *q0 = &qs0->rspq;
  2432. t3_write_reg(adap, A_PL_CLI, 0);
  2433. map = t3_read_reg(adap, A_SG_DATA_INTR);
  2434. if (unlikely(!map)) /* shared interrupt, most likely */
  2435. return IRQ_NONE;
  2436. spin_lock(&q0->lock);
  2437. if (unlikely(map & F_ERRINTR))
  2438. t3_slow_intr_handler(adap);
  2439. if (likely(map & 1))
  2440. napi_schedule(&qs0->napi);
  2441. if (map & 2)
  2442. napi_schedule(&adap->sge.qs[1].napi);
  2443. spin_unlock(&q0->lock);
  2444. return IRQ_HANDLED;
  2445. }
  2446. /**
  2447. * t3_intr_handler - select the top-level interrupt handler
  2448. * @adap: the adapter
  2449. * @polling: whether using NAPI to service response queues
  2450. *
  2451. * Selects the top-level interrupt handler based on the type of interrupts
  2452. * (MSI-X, MSI, or legacy) and whether NAPI will be used to service the
  2453. * response queues.
  2454. */
  2455. irq_handler_t t3_intr_handler(struct adapter *adap, int polling)
  2456. {
  2457. if (adap->flags & USING_MSIX)
  2458. return polling ? t3_sge_intr_msix_napi : t3_sge_intr_msix;
  2459. if (adap->flags & USING_MSI)
  2460. return polling ? t3_intr_msi_napi : t3_intr_msi;
  2461. if (adap->params.rev > 0)
  2462. return polling ? t3b_intr_napi : t3b_intr;
  2463. return t3_intr;
  2464. }
  2465. #define SGE_PARERR (F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
  2466. F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
  2467. V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
  2468. F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
  2469. F_HIRCQPARITYERROR)
  2470. #define SGE_FRAMINGERR (F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR)
  2471. #define SGE_FATALERR (SGE_PARERR | SGE_FRAMINGERR | F_RSPQCREDITOVERFOW | \
  2472. F_RSPQDISABLED)
  2473. /**
  2474. * t3_sge_err_intr_handler - SGE async event interrupt handler
  2475. * @adapter: the adapter
  2476. *
  2477. * Interrupt handler for SGE asynchronous (non-data) events.
  2478. */
  2479. void t3_sge_err_intr_handler(struct adapter *adapter)
  2480. {
  2481. unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE) &
  2482. ~F_FLEMPTY;
  2483. if (status & SGE_PARERR)
  2484. CH_ALERT(adapter, "SGE parity error (0x%x)\n",
  2485. status & SGE_PARERR);
  2486. if (status & SGE_FRAMINGERR)
  2487. CH_ALERT(adapter, "SGE framing error (0x%x)\n",
  2488. status & SGE_FRAMINGERR);
  2489. if (status & F_RSPQCREDITOVERFOW)
  2490. CH_ALERT(adapter, "SGE response queue credit overflow\n");
  2491. if (status & F_RSPQDISABLED) {
  2492. v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
  2493. CH_ALERT(adapter,
  2494. "packet delivered to disabled response queue "
  2495. "(0x%x)\n", (v >> S_RSPQ0DISABLED) & 0xff);
  2496. }
  2497. if (status & (F_HIPIODRBDROPERR | F_LOPIODRBDROPERR))
  2498. queue_work(cxgb3_wq, &adapter->db_drop_task);
  2499. if (status & (F_HIPRIORITYDBFULL | F_LOPRIORITYDBFULL))
  2500. queue_work(cxgb3_wq, &adapter->db_full_task);
  2501. if (status & (F_HIPRIORITYDBEMPTY | F_LOPRIORITYDBEMPTY))
  2502. queue_work(cxgb3_wq, &adapter->db_empty_task);
  2503. t3_write_reg(adapter, A_SG_INT_CAUSE, status);
  2504. if (status & SGE_FATALERR)
  2505. t3_fatal_err(adapter);
  2506. }
  2507. /**
  2508. * sge_timer_tx - perform periodic maintenance of an SGE qset
  2509. * @data: the SGE queue set to maintain
  2510. *
  2511. * Runs periodically from a timer to perform maintenance of an SGE queue
  2512. * set. It performs two tasks:
  2513. *
  2514. * Cleans up any completed Tx descriptors that may still be pending.
  2515. * Normal descriptor cleanup happens when new packets are added to a Tx
  2516. * queue so this timer is relatively infrequent and does any cleanup only
  2517. * if the Tx queue has not seen any new packets in a while. We make a
  2518. * best effort attempt to reclaim descriptors, in that we don't wait
  2519. * around if we cannot get a queue's lock (which most likely is because
  2520. * someone else is queueing new packets and so will also handle the clean
  2521. * up). Since control queues use immediate data exclusively we don't
  2522. * bother cleaning them up here.
  2523. *
  2524. */
  2525. static void sge_timer_tx(unsigned long data)
  2526. {
  2527. struct sge_qset *qs = (struct sge_qset *)data;
  2528. struct port_info *pi = netdev_priv(qs->netdev);
  2529. struct adapter *adap = pi->adapter;
  2530. unsigned int tbd[SGE_TXQ_PER_SET] = {0, 0};
  2531. unsigned long next_period;
  2532. if (__netif_tx_trylock(qs->tx_q)) {
  2533. tbd[TXQ_ETH] = reclaim_completed_tx(adap, &qs->txq[TXQ_ETH],
  2534. TX_RECLAIM_TIMER_CHUNK);
  2535. __netif_tx_unlock(qs->tx_q);
  2536. }
  2537. if (spin_trylock(&qs->txq[TXQ_OFLD].lock)) {
  2538. tbd[TXQ_OFLD] = reclaim_completed_tx(adap, &qs->txq[TXQ_OFLD],
  2539. TX_RECLAIM_TIMER_CHUNK);
  2540. spin_unlock(&qs->txq[TXQ_OFLD].lock);
  2541. }
  2542. next_period = TX_RECLAIM_PERIOD >>
  2543. (max(tbd[TXQ_ETH], tbd[TXQ_OFLD]) /
  2544. TX_RECLAIM_TIMER_CHUNK);
  2545. mod_timer(&qs->tx_reclaim_timer, jiffies + next_period);
  2546. }
  2547. /*
  2548. * sge_timer_rx - perform periodic maintenance of an SGE qset
  2549. * @data: the SGE queue set to maintain
  2550. *
  2551. * a) Replenishes Rx queues that have run out due to memory shortage.
  2552. * Normally new Rx buffers are added when existing ones are consumed but
  2553. * when out of memory a queue can become empty. We try to add only a few
  2554. * buffers here, the queue will be replenished fully as these new buffers
  2555. * are used up if memory shortage has subsided.
  2556. *
  2557. * b) Return coalesced response queue credits in case a response queue is
  2558. * starved.
  2559. *
  2560. */
  2561. static void sge_timer_rx(unsigned long data)
  2562. {
  2563. spinlock_t *lock;
  2564. struct sge_qset *qs = (struct sge_qset *)data;
  2565. struct port_info *pi = netdev_priv(qs->netdev);
  2566. struct adapter *adap = pi->adapter;
  2567. u32 status;
  2568. lock = adap->params.rev > 0 ?
  2569. &qs->rspq.lock : &adap->sge.qs[0].rspq.lock;
  2570. if (!spin_trylock_irq(lock))
  2571. goto out;
  2572. if (napi_is_scheduled(&qs->napi))
  2573. goto unlock;
  2574. if (adap->params.rev < 4) {
  2575. status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS);
  2576. if (status & (1 << qs->rspq.cntxt_id)) {
  2577. qs->rspq.starved++;
  2578. if (qs->rspq.credits) {
  2579. qs->rspq.credits--;
  2580. refill_rspq(adap, &qs->rspq, 1);
  2581. qs->rspq.restarted++;
  2582. t3_write_reg(adap, A_SG_RSPQ_FL_STATUS,
  2583. 1 << qs->rspq.cntxt_id);
  2584. }
  2585. }
  2586. }
  2587. if (qs->fl[0].credits < qs->fl[0].size)
  2588. __refill_fl(adap, &qs->fl[0]);
  2589. if (qs->fl[1].credits < qs->fl[1].size)
  2590. __refill_fl(adap, &qs->fl[1]);
  2591. unlock:
  2592. spin_unlock_irq(lock);
  2593. out:
  2594. mod_timer(&qs->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD);
  2595. }
  2596. /**
  2597. * t3_update_qset_coalesce - update coalescing settings for a queue set
  2598. * @qs: the SGE queue set
  2599. * @p: new queue set parameters
  2600. *
  2601. * Update the coalescing settings for an SGE queue set. Nothing is done
  2602. * if the queue set is not initialized yet.
  2603. */
  2604. void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p)
  2605. {
  2606. qs->rspq.holdoff_tmr = max(p->coalesce_usecs * 10, 1U);/* can't be 0 */
  2607. qs->rspq.polling = p->polling;
  2608. qs->napi.poll = p->polling ? napi_rx_handler : ofld_poll;
  2609. }
  2610. /**
  2611. * t3_sge_alloc_qset - initialize an SGE queue set
  2612. * @adapter: the adapter
  2613. * @id: the queue set id
  2614. * @nports: how many Ethernet ports will be using this queue set
  2615. * @irq_vec_idx: the IRQ vector index for response queue interrupts
  2616. * @p: configuration parameters for this queue set
  2617. * @ntxq: number of Tx queues for the queue set
  2618. * @netdev: net device associated with this queue set
  2619. * @netdevq: net device TX queue associated with this queue set
  2620. *
  2621. * Allocate resources and initialize an SGE queue set. A queue set
  2622. * comprises a response queue, two Rx free-buffer queues, and up to 3
  2623. * Tx queues. The Tx queues are assigned roles in the order Ethernet
  2624. * queue, offload queue, and control queue.
  2625. */
  2626. int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
  2627. int irq_vec_idx, const struct qset_params *p,
  2628. int ntxq, struct net_device *dev,
  2629. struct netdev_queue *netdevq)
  2630. {
  2631. int i, avail, ret = -ENOMEM;
  2632. struct sge_qset *q = &adapter->sge.qs[id];
  2633. init_qset_cntxt(q, id);
  2634. setup_timer(&q->tx_reclaim_timer, sge_timer_tx, (unsigned long)q);
  2635. setup_timer(&q->rx_reclaim_timer, sge_timer_rx, (unsigned long)q);
  2636. q->fl[0].desc = alloc_ring(adapter->pdev, p->fl_size,
  2637. sizeof(struct rx_desc),
  2638. sizeof(struct rx_sw_desc),
  2639. &q->fl[0].phys_addr, &q->fl[0].sdesc);
  2640. if (!q->fl[0].desc)
  2641. goto err;
  2642. q->fl[1].desc = alloc_ring(adapter->pdev, p->jumbo_size,
  2643. sizeof(struct rx_desc),
  2644. sizeof(struct rx_sw_desc),
  2645. &q->fl[1].phys_addr, &q->fl[1].sdesc);
  2646. if (!q->fl[1].desc)
  2647. goto err;
  2648. q->rspq.desc = alloc_ring(adapter->pdev, p->rspq_size,
  2649. sizeof(struct rsp_desc), 0,
  2650. &q->rspq.phys_addr, NULL);
  2651. if (!q->rspq.desc)
  2652. goto err;
  2653. for (i = 0; i < ntxq; ++i) {
  2654. /*
  2655. * The control queue always uses immediate data so does not
  2656. * need to keep track of any sk_buffs.
  2657. */
  2658. size_t sz = i == TXQ_CTRL ? 0 : sizeof(struct tx_sw_desc);
  2659. q->txq[i].desc = alloc_ring(adapter->pdev, p->txq_size[i],
  2660. sizeof(struct tx_desc), sz,
  2661. &q->txq[i].phys_addr,
  2662. &q->txq[i].sdesc);
  2663. if (!q->txq[i].desc)
  2664. goto err;
  2665. q->txq[i].gen = 1;
  2666. q->txq[i].size = p->txq_size[i];
  2667. spin_lock_init(&q->txq[i].lock);
  2668. skb_queue_head_init(&q->txq[i].sendq);
  2669. }
  2670. tasklet_init(&q->txq[TXQ_OFLD].qresume_tsk, restart_offloadq,
  2671. (unsigned long)q);
  2672. tasklet_init(&q->txq[TXQ_CTRL].qresume_tsk, restart_ctrlq,
  2673. (unsigned long)q);
  2674. q->fl[0].gen = q->fl[1].gen = 1;
  2675. q->fl[0].size = p->fl_size;
  2676. q->fl[1].size = p->jumbo_size;
  2677. q->rspq.gen = 1;
  2678. q->rspq.size = p->rspq_size;
  2679. spin_lock_init(&q->rspq.lock);
  2680. skb_queue_head_init(&q->rspq.rx_queue);
  2681. q->txq[TXQ_ETH].stop_thres = nports *
  2682. flits_to_desc(sgl_len(MAX_SKB_FRAGS + 1) + 3);
  2683. #if FL0_PG_CHUNK_SIZE > 0
  2684. q->fl[0].buf_size = FL0_PG_CHUNK_SIZE;
  2685. #else
  2686. q->fl[0].buf_size = SGE_RX_SM_BUF_SIZE + sizeof(struct cpl_rx_data);
  2687. #endif
  2688. #if FL1_PG_CHUNK_SIZE > 0
  2689. q->fl[1].buf_size = FL1_PG_CHUNK_SIZE;
  2690. #else
  2691. q->fl[1].buf_size = is_offload(adapter) ?
  2692. (16 * 1024) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
  2693. MAX_FRAME_SIZE + 2 + sizeof(struct cpl_rx_pkt);
  2694. #endif
  2695. q->fl[0].use_pages = FL0_PG_CHUNK_SIZE > 0;
  2696. q->fl[1].use_pages = FL1_PG_CHUNK_SIZE > 0;
  2697. q->fl[0].order = FL0_PG_ORDER;
  2698. q->fl[1].order = FL1_PG_ORDER;
  2699. q->fl[0].alloc_size = FL0_PG_ALLOC_SIZE;
  2700. q->fl[1].alloc_size = FL1_PG_ALLOC_SIZE;
  2701. spin_lock_irq(&adapter->sge.reg_lock);
  2702. /* FL threshold comparison uses < */
  2703. ret = t3_sge_init_rspcntxt(adapter, q->rspq.cntxt_id, irq_vec_idx,
  2704. q->rspq.phys_addr, q->rspq.size,
  2705. q->fl[0].buf_size - SGE_PG_RSVD, 1, 0);
  2706. if (ret)
  2707. goto err_unlock;
  2708. for (i = 0; i < SGE_RXQ_PER_SET; ++i) {
  2709. ret = t3_sge_init_flcntxt(adapter, q->fl[i].cntxt_id, 0,
  2710. q->fl[i].phys_addr, q->fl[i].size,
  2711. q->fl[i].buf_size - SGE_PG_RSVD,
  2712. p->cong_thres, 1, 0);
  2713. if (ret)
  2714. goto err_unlock;
  2715. }
  2716. ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_ETH].cntxt_id, USE_GTS,
  2717. SGE_CNTXT_ETH, id, q->txq[TXQ_ETH].phys_addr,
  2718. q->txq[TXQ_ETH].size, q->txq[TXQ_ETH].token,
  2719. 1, 0);
  2720. if (ret)
  2721. goto err_unlock;
  2722. if (ntxq > 1) {
  2723. ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_OFLD].cntxt_id,
  2724. USE_GTS, SGE_CNTXT_OFLD, id,
  2725. q->txq[TXQ_OFLD].phys_addr,
  2726. q->txq[TXQ_OFLD].size, 0, 1, 0);
  2727. if (ret)
  2728. goto err_unlock;
  2729. }
  2730. if (ntxq > 2) {
  2731. ret = t3_sge_init_ecntxt(adapter, q->txq[TXQ_CTRL].cntxt_id, 0,
  2732. SGE_CNTXT_CTRL, id,
  2733. q->txq[TXQ_CTRL].phys_addr,
  2734. q->txq[TXQ_CTRL].size,
  2735. q->txq[TXQ_CTRL].token, 1, 0);
  2736. if (ret)
  2737. goto err_unlock;
  2738. }
  2739. spin_unlock_irq(&adapter->sge.reg_lock);
  2740. q->adap = adapter;
  2741. q->netdev = dev;
  2742. q->tx_q = netdevq;
  2743. t3_update_qset_coalesce(q, p);
  2744. avail = refill_fl(adapter, &q->fl[0], q->fl[0].size,
  2745. GFP_KERNEL | __GFP_COMP);
  2746. if (!avail) {
  2747. CH_ALERT(adapter, "free list queue 0 initialization failed\n");
  2748. goto err;
  2749. }
  2750. if (avail < q->fl[0].size)
  2751. CH_WARN(adapter, "free list queue 0 enabled with %d credits\n",
  2752. avail);
  2753. avail = refill_fl(adapter, &q->fl[1], q->fl[1].size,
  2754. GFP_KERNEL | __GFP_COMP);
  2755. if (avail < q->fl[1].size)
  2756. CH_WARN(adapter, "free list queue 1 enabled with %d credits\n",
  2757. avail);
  2758. refill_rspq(adapter, &q->rspq, q->rspq.size - 1);
  2759. t3_write_reg(adapter, A_SG_GTS, V_RSPQ(q->rspq.cntxt_id) |
  2760. V_NEWTIMER(q->rspq.holdoff_tmr));
  2761. return 0;
  2762. err_unlock:
  2763. spin_unlock_irq(&adapter->sge.reg_lock);
  2764. err:
  2765. t3_free_qset(adapter, q);
  2766. return ret;
  2767. }
  2768. /**
  2769. * t3_start_sge_timers - start SGE timer call backs
  2770. * @adap: the adapter
  2771. *
  2772. * Starts each SGE queue set's timer call back
  2773. */
  2774. void t3_start_sge_timers(struct adapter *adap)
  2775. {
  2776. int i;
  2777. for (i = 0; i < SGE_QSETS; ++i) {
  2778. struct sge_qset *q = &adap->sge.qs[i];
  2779. if (q->tx_reclaim_timer.function)
  2780. mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
  2781. if (q->rx_reclaim_timer.function)
  2782. mod_timer(&q->rx_reclaim_timer, jiffies + RX_RECLAIM_PERIOD);
  2783. }
  2784. }
  2785. /**
  2786. * t3_stop_sge_timers - stop SGE timer call backs
  2787. * @adap: the adapter
  2788. *
  2789. * Stops each SGE queue set's timer call back
  2790. */
  2791. void t3_stop_sge_timers(struct adapter *adap)
  2792. {
  2793. int i;
  2794. for (i = 0; i < SGE_QSETS; ++i) {
  2795. struct sge_qset *q = &adap->sge.qs[i];
  2796. if (q->tx_reclaim_timer.function)
  2797. del_timer_sync(&q->tx_reclaim_timer);
  2798. if (q->rx_reclaim_timer.function)
  2799. del_timer_sync(&q->rx_reclaim_timer);
  2800. }
  2801. }
  2802. /**
  2803. * t3_free_sge_resources - free SGE resources
  2804. * @adap: the adapter
  2805. *
  2806. * Frees resources used by the SGE queue sets.
  2807. */
  2808. void t3_free_sge_resources(struct adapter *adap)
  2809. {
  2810. int i;
  2811. for (i = 0; i < SGE_QSETS; ++i)
  2812. t3_free_qset(adap, &adap->sge.qs[i]);
  2813. }
  2814. /**
  2815. * t3_sge_start - enable SGE
  2816. * @adap: the adapter
  2817. *
  2818. * Enables the SGE for DMAs. This is the last step in starting packet
  2819. * transfers.
  2820. */
  2821. void t3_sge_start(struct adapter *adap)
  2822. {
  2823. t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, F_GLOBALENABLE);
  2824. }
  2825. /**
  2826. * t3_sge_stop - disable SGE operation
  2827. * @adap: the adapter
  2828. *
  2829. * Disables the DMA engine. This can be called in emeregencies (e.g.,
  2830. * from error interrupts) or from normal process context. In the latter
  2831. * case it also disables any pending queue restart tasklets. Note that
  2832. * if it is called in interrupt context it cannot disable the restart
  2833. * tasklets as it cannot wait, however the tasklets will have no effect
  2834. * since the doorbells are disabled and the driver will call this again
  2835. * later from process context, at which time the tasklets will be stopped
  2836. * if they are still running.
  2837. */
  2838. void t3_sge_stop(struct adapter *adap)
  2839. {
  2840. t3_set_reg_field(adap, A_SG_CONTROL, F_GLOBALENABLE, 0);
  2841. if (!in_interrupt()) {
  2842. int i;
  2843. for (i = 0; i < SGE_QSETS; ++i) {
  2844. struct sge_qset *qs = &adap->sge.qs[i];
  2845. tasklet_kill(&qs->txq[TXQ_OFLD].qresume_tsk);
  2846. tasklet_kill(&qs->txq[TXQ_CTRL].qresume_tsk);
  2847. }
  2848. }
  2849. }
  2850. /**
  2851. * t3_sge_init - initialize SGE
  2852. * @adap: the adapter
  2853. * @p: the SGE parameters
  2854. *
  2855. * Performs SGE initialization needed every time after a chip reset.
  2856. * We do not initialize any of the queue sets here, instead the driver
  2857. * top-level must request those individually. We also do not enable DMA
  2858. * here, that should be done after the queues have been set up.
  2859. */
  2860. void t3_sge_init(struct adapter *adap, struct sge_params *p)
  2861. {
  2862. unsigned int ctrl, ups = ffs(pci_resource_len(adap->pdev, 2) >> 12);
  2863. ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |
  2864. F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN |
  2865. V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS |
  2866. V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING;
  2867. #if SGE_NUM_GENBITS == 1
  2868. ctrl |= F_EGRGENCTRL;
  2869. #endif
  2870. if (adap->params.rev > 0) {
  2871. if (!(adap->flags & (USING_MSIX | USING_MSI)))
  2872. ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;
  2873. }
  2874. t3_write_reg(adap, A_SG_CONTROL, ctrl);
  2875. t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
  2876. V_LORCQDRBTHRSH(512));
  2877. t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);
  2878. t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |
  2879. V_TIMEOUT(200 * core_ticks_per_usec(adap)));
  2880. t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH,
  2881. adap->params.rev < T3_REV_C ? 1000 : 500);
  2882. t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);
  2883. t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);
  2884. t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);
  2885. t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff));
  2886. t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024);
  2887. }
  2888. /**
  2889. * t3_sge_prep - one-time SGE initialization
  2890. * @adap: the associated adapter
  2891. * @p: SGE parameters
  2892. *
  2893. * Performs one-time initialization of SGE SW state. Includes determining
  2894. * defaults for the assorted SGE parameters, which admins can change until
  2895. * they are used to initialize the SGE.
  2896. */
  2897. void t3_sge_prep(struct adapter *adap, struct sge_params *p)
  2898. {
  2899. int i;
  2900. p->max_pkt_size = (16 * 1024) - sizeof(struct cpl_rx_data) -
  2901. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  2902. for (i = 0; i < SGE_QSETS; ++i) {
  2903. struct qset_params *q = p->qset + i;
  2904. q->polling = adap->params.rev > 0;
  2905. q->coalesce_usecs = 5;
  2906. q->rspq_size = 1024;
  2907. q->fl_size = 1024;
  2908. q->jumbo_size = 512;
  2909. q->txq_size[TXQ_ETH] = 1024;
  2910. q->txq_size[TXQ_OFLD] = 1024;
  2911. q->txq_size[TXQ_CTRL] = 256;
  2912. q->cong_thres = 0;
  2913. }
  2914. spin_lock_init(&adap->sge.reg_lock);
  2915. }