gdth.c 174 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include <linux/scatterlist.h>
  127. #include "scsi.h"
  128. #include <scsi/scsi_host.h>
  129. #include "gdth.h"
  130. static void gdth_delay(int milliseconds);
  131. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  132. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  133. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  134. int gdth_from_wait, int* pIndex);
  135. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  136. Scsi_Cmnd *scp);
  137. static int gdth_async_event(gdth_ha_str *ha);
  138. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  139. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  140. static void gdth_next(gdth_ha_str *ha);
  141. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  142. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  143. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  144. ushort idx, gdth_evt_data *evt);
  145. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  146. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  147. gdth_evt_str *estr);
  148. static void gdth_clear_events(void);
  149. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  150. char *buffer, ushort count);
  151. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  152. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  153. static void gdth_enable_int(gdth_ha_str *ha);
  154. static int gdth_test_busy(gdth_ha_str *ha);
  155. static int gdth_get_cmd_index(gdth_ha_str *ha);
  156. static void gdth_release_event(gdth_ha_str *ha);
  157. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  158. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  159. ulong32 p1, ulong64 p2,ulong64 p3);
  160. static int gdth_search_drives(gdth_ha_str *ha);
  161. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  162. static const char *gdth_ctr_name(gdth_ha_str *ha);
  163. static int gdth_open(struct inode *inode, struct file *filep);
  164. static int gdth_close(struct inode *inode, struct file *filep);
  165. static int gdth_ioctl(struct inode *inode, struct file *filep,
  166. unsigned int cmd, unsigned long arg);
  167. static void gdth_flush(gdth_ha_str *ha);
  168. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  169. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  170. struct gdth_cmndinfo *cmndinfo);
  171. static void gdth_scsi_done(struct scsi_cmnd *scp);
  172. #ifdef DEBUG_GDTH
  173. static unchar DebugState = DEBUG_GDTH;
  174. #ifdef __SERIAL__
  175. #define MAX_SERBUF 160
  176. static void ser_init(void);
  177. static void ser_puts(char *str);
  178. static void ser_putc(char c);
  179. static int ser_printk(const char *fmt, ...);
  180. static char strbuf[MAX_SERBUF+1];
  181. #ifdef __COM2__
  182. #define COM_BASE 0x2f8
  183. #else
  184. #define COM_BASE 0x3f8
  185. #endif
  186. static void ser_init()
  187. {
  188. unsigned port=COM_BASE;
  189. outb(0x80,port+3);
  190. outb(0,port+1);
  191. /* 19200 Baud, if 9600: outb(12,port) */
  192. outb(6, port);
  193. outb(3,port+3);
  194. outb(0,port+1);
  195. /*
  196. ser_putc('I');
  197. ser_putc(' ');
  198. */
  199. }
  200. static void ser_puts(char *str)
  201. {
  202. char *ptr;
  203. ser_init();
  204. for (ptr=str;*ptr;++ptr)
  205. ser_putc(*ptr);
  206. }
  207. static void ser_putc(char c)
  208. {
  209. unsigned port=COM_BASE;
  210. while ((inb(port+5) & 0x20)==0);
  211. outb(c,port);
  212. if (c==0x0a)
  213. {
  214. while ((inb(port+5) & 0x20)==0);
  215. outb(0x0d,port);
  216. }
  217. }
  218. static int ser_printk(const char *fmt, ...)
  219. {
  220. va_list args;
  221. int i;
  222. va_start(args,fmt);
  223. i = vsprintf(strbuf,fmt,args);
  224. ser_puts(strbuf);
  225. va_end(args);
  226. return i;
  227. }
  228. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  229. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  230. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  231. #else /* !__SERIAL__ */
  232. #define TRACE(a) {if (DebugState==1) {printk a;}}
  233. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  234. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  235. #endif
  236. #else /* !DEBUG */
  237. #define TRACE(a)
  238. #define TRACE2(a)
  239. #define TRACE3(a)
  240. #endif
  241. #ifdef GDTH_STATISTICS
  242. static ulong32 max_rq=0, max_index=0, max_sg=0;
  243. #ifdef INT_COAL
  244. static ulong32 max_int_coal=0;
  245. #endif
  246. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  247. static struct timer_list gdth_timer;
  248. #endif
  249. #define PTR2USHORT(a) (ushort)(ulong)(a)
  250. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  251. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  252. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  253. #ifdef CONFIG_ISA
  254. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  255. #endif
  256. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  257. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  258. #endif
  259. static unchar gdth_polling; /* polling if TRUE */
  260. static int gdth_ctr_count = 0; /* controller count */
  261. static LIST_HEAD(gdth_instances); /* controller list */
  262. static unchar gdth_write_through = FALSE; /* write through */
  263. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  264. static int elastidx;
  265. static int eoldidx;
  266. static int major;
  267. #define DIN 1 /* IN data direction */
  268. #define DOU 2 /* OUT data direction */
  269. #define DNO DIN /* no data transfer */
  270. #define DUN DIN /* unknown data direction */
  271. static unchar gdth_direction_tab[0x100] = {
  272. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  273. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  274. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  275. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  276. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  277. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  283. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  284. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  288. };
  289. /* LILO and modprobe/insmod parameters */
  290. /* IRQ list for GDT3000/3020 EISA controllers */
  291. static int irq[MAXHA] __initdata =
  292. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  293. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  294. /* disable driver flag */
  295. static int disable __initdata = 0;
  296. /* reserve flag */
  297. static int reserve_mode = 1;
  298. /* reserve list */
  299. static int reserve_list[MAX_RES_ARGS] =
  300. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  301. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  302. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  303. /* scan order for PCI controllers */
  304. static int reverse_scan = 0;
  305. /* virtual channel for the host drives */
  306. static int hdr_channel = 0;
  307. /* max. IDs per channel */
  308. static int max_ids = MAXID;
  309. /* rescan all IDs */
  310. static int rescan = 0;
  311. /* shared access */
  312. static int shared_access = 1;
  313. /* enable support for EISA and ISA controllers */
  314. static int probe_eisa_isa = 0;
  315. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  316. static int force_dma32 = 0;
  317. /* parameters for modprobe/insmod */
  318. module_param_array(irq, int, NULL, 0);
  319. module_param(disable, int, 0);
  320. module_param(reserve_mode, int, 0);
  321. module_param_array(reserve_list, int, NULL, 0);
  322. module_param(reverse_scan, int, 0);
  323. module_param(hdr_channel, int, 0);
  324. module_param(max_ids, int, 0);
  325. module_param(rescan, int, 0);
  326. module_param(shared_access, int, 0);
  327. module_param(probe_eisa_isa, int, 0);
  328. module_param(force_dma32, int, 0);
  329. MODULE_AUTHOR("Achim Leubner");
  330. MODULE_LICENSE("GPL");
  331. /* ioctl interface */
  332. static const struct file_operations gdth_fops = {
  333. .ioctl = gdth_ioctl,
  334. .open = gdth_open,
  335. .release = gdth_close,
  336. };
  337. #include "gdth_proc.h"
  338. #include "gdth_proc.c"
  339. static gdth_ha_str *gdth_find_ha(int hanum)
  340. {
  341. gdth_ha_str *ha;
  342. list_for_each_entry(ha, &gdth_instances, list)
  343. if (hanum == ha->hanum)
  344. return ha;
  345. return NULL;
  346. }
  347. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  348. {
  349. struct gdth_cmndinfo *priv = NULL;
  350. ulong flags;
  351. int i;
  352. spin_lock_irqsave(&ha->smp_lock, flags);
  353. for (i=0; i<GDTH_MAXCMDS; ++i) {
  354. if (ha->cmndinfo[i].index == 0) {
  355. priv = &ha->cmndinfo[i];
  356. memset(priv, 0, sizeof(*priv));
  357. priv->index = i+1;
  358. break;
  359. }
  360. }
  361. spin_unlock_irqrestore(&ha->smp_lock, flags);
  362. return priv;
  363. }
  364. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  365. {
  366. BUG_ON(!priv);
  367. priv->index = 0;
  368. }
  369. static void gdth_delay(int milliseconds)
  370. {
  371. if (milliseconds == 0) {
  372. udelay(1);
  373. } else {
  374. mdelay(milliseconds);
  375. }
  376. }
  377. static void gdth_scsi_done(struct scsi_cmnd *scp)
  378. {
  379. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  380. int internal_command = cmndinfo->internal_command;
  381. TRACE2(("gdth_scsi_done()\n"));
  382. gdth_put_cmndinfo(cmndinfo);
  383. scp->host_scribble = NULL;
  384. if (internal_command)
  385. complete((struct completion *)scp->request);
  386. else
  387. scp->scsi_done(scp);
  388. }
  389. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  390. int timeout, u32 *info)
  391. {
  392. gdth_ha_str *ha = shost_priv(sdev->host);
  393. Scsi_Cmnd *scp;
  394. struct gdth_cmndinfo cmndinfo;
  395. DECLARE_COMPLETION_ONSTACK(wait);
  396. int rval;
  397. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  398. if (!scp)
  399. return -ENOMEM;
  400. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  401. if (!scp->sense_buffer) {
  402. kfree(scp);
  403. return -ENOMEM;
  404. }
  405. scp->device = sdev;
  406. memset(&cmndinfo, 0, sizeof(cmndinfo));
  407. /* use request field to save the ptr. to completion struct. */
  408. scp->request = (struct request *)&wait;
  409. scp->timeout_per_command = timeout*HZ;
  410. scp->cmd_len = 12;
  411. scp->cmnd = cmnd;
  412. cmndinfo.priority = IOCTL_PRI;
  413. cmndinfo.internal_cmd_str = gdtcmd;
  414. cmndinfo.internal_command = 1;
  415. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  416. __gdth_queuecommand(ha, scp, &cmndinfo);
  417. wait_for_completion(&wait);
  418. rval = cmndinfo.status;
  419. if (info)
  420. *info = cmndinfo.info;
  421. kfree(scp->sense_buffer);
  422. kfree(scp);
  423. return rval;
  424. }
  425. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  426. int timeout, u32 *info)
  427. {
  428. struct scsi_device *sdev = scsi_get_host_dev(shost);
  429. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  430. scsi_free_host_dev(sdev);
  431. return rval;
  432. }
  433. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  434. {
  435. *cyls = size /HEADS/SECS;
  436. if (*cyls <= MAXCYLS) {
  437. *heads = HEADS;
  438. *secs = SECS;
  439. } else { /* too high for 64*32 */
  440. *cyls = size /MEDHEADS/MEDSECS;
  441. if (*cyls <= MAXCYLS) {
  442. *heads = MEDHEADS;
  443. *secs = MEDSECS;
  444. } else { /* too high for 127*63 */
  445. *cyls = size /BIGHEADS/BIGSECS;
  446. *heads = BIGHEADS;
  447. *secs = BIGSECS;
  448. }
  449. }
  450. }
  451. /* controller search and initialization functions */
  452. #ifdef CONFIG_EISA
  453. static int __init gdth_search_eisa(ushort eisa_adr)
  454. {
  455. ulong32 id;
  456. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  457. id = inl(eisa_adr+ID0REG);
  458. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  459. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  460. return 0; /* not EISA configured */
  461. return 1;
  462. }
  463. if (id == GDT3_ID) /* GDT3000 */
  464. return 1;
  465. return 0;
  466. }
  467. #endif /* CONFIG_EISA */
  468. #ifdef CONFIG_ISA
  469. static int __init gdth_search_isa(ulong32 bios_adr)
  470. {
  471. void __iomem *addr;
  472. ulong32 id;
  473. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  474. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  475. id = readl(addr);
  476. iounmap(addr);
  477. if (id == GDT2_ID) /* GDT2000 */
  478. return 1;
  479. }
  480. return 0;
  481. }
  482. #endif /* CONFIG_ISA */
  483. #ifdef CONFIG_PCI
  484. static bool gdth_search_vortex(ushort device)
  485. {
  486. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  487. return true;
  488. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  489. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  490. return true;
  491. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  492. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  493. return true;
  494. return false;
  495. }
  496. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  497. static int gdth_pci_init_one(struct pci_dev *pdev,
  498. const struct pci_device_id *ent);
  499. static void gdth_pci_remove_one(struct pci_dev *pdev);
  500. static void gdth_remove_one(gdth_ha_str *ha);
  501. /* Vortex only makes RAID controllers.
  502. * We do not really want to specify all 550 ids here, so wildcard match.
  503. */
  504. static const struct pci_device_id gdthtable[] = {
  505. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  506. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  507. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  508. { } /* terminate list */
  509. };
  510. MODULE_DEVICE_TABLE(pci, gdthtable);
  511. static struct pci_driver gdth_pci_driver = {
  512. .name = "gdth",
  513. .id_table = gdthtable,
  514. .probe = gdth_pci_init_one,
  515. .remove = gdth_pci_remove_one,
  516. };
  517. static void gdth_pci_remove_one(struct pci_dev *pdev)
  518. {
  519. gdth_ha_str *ha = pci_get_drvdata(pdev);
  520. pci_set_drvdata(pdev, NULL);
  521. list_del(&ha->list);
  522. gdth_remove_one(ha);
  523. pci_disable_device(pdev);
  524. }
  525. static int gdth_pci_init_one(struct pci_dev *pdev,
  526. const struct pci_device_id *ent)
  527. {
  528. ushort vendor = pdev->vendor;
  529. ushort device = pdev->device;
  530. ulong base0, base1, base2;
  531. int rc;
  532. gdth_pci_str gdth_pcistr;
  533. gdth_ha_str *ha = NULL;
  534. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  535. gdth_ctr_count, vendor, device));
  536. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  537. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  538. return -ENODEV;
  539. rc = pci_enable_device(pdev);
  540. if (rc)
  541. return rc;
  542. if (gdth_ctr_count >= MAXHA)
  543. return -EBUSY;
  544. /* GDT PCI controller found, resources are already in pdev */
  545. gdth_pcistr.pdev = pdev;
  546. base0 = pci_resource_flags(pdev, 0);
  547. base1 = pci_resource_flags(pdev, 1);
  548. base2 = pci_resource_flags(pdev, 2);
  549. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  550. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  551. if (!(base0 & IORESOURCE_MEM))
  552. return -ENODEV;
  553. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  554. } else { /* GDT6110, GDT6120, .. */
  555. if (!(base0 & IORESOURCE_MEM) ||
  556. !(base2 & IORESOURCE_MEM) ||
  557. !(base1 & IORESOURCE_IO))
  558. return -ENODEV;
  559. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  560. gdth_pcistr.io = pci_resource_start(pdev, 1);
  561. }
  562. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  563. gdth_pcistr.pdev->bus->number,
  564. PCI_SLOT(gdth_pcistr.pdev->devfn),
  565. gdth_pcistr.irq,
  566. gdth_pcistr.dpmem));
  567. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  568. if (rc)
  569. return rc;
  570. return 0;
  571. }
  572. #endif /* CONFIG_PCI */
  573. #ifdef CONFIG_EISA
  574. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  575. {
  576. ulong32 retries,id;
  577. unchar prot_ver,eisacf,i,irq_found;
  578. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  579. /* disable board interrupts, deinitialize services */
  580. outb(0xff,eisa_adr+EDOORREG);
  581. outb(0x00,eisa_adr+EDENABREG);
  582. outb(0x00,eisa_adr+EINTENABREG);
  583. outb(0xff,eisa_adr+LDOORREG);
  584. retries = INIT_RETRIES;
  585. gdth_delay(20);
  586. while (inb(eisa_adr+EDOORREG) != 0xff) {
  587. if (--retries == 0) {
  588. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  589. return 0;
  590. }
  591. gdth_delay(1);
  592. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  593. }
  594. prot_ver = inb(eisa_adr+MAILBOXREG);
  595. outb(0xff,eisa_adr+EDOORREG);
  596. if (prot_ver != PROTOCOL_VERSION) {
  597. printk("GDT-EISA: Illegal protocol version\n");
  598. return 0;
  599. }
  600. ha->bmic = eisa_adr;
  601. ha->brd_phys = (ulong32)eisa_adr >> 12;
  602. outl(0,eisa_adr+MAILBOXREG);
  603. outl(0,eisa_adr+MAILBOXREG+4);
  604. outl(0,eisa_adr+MAILBOXREG+8);
  605. outl(0,eisa_adr+MAILBOXREG+12);
  606. /* detect IRQ */
  607. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  608. ha->oem_id = OEM_ID_ICP;
  609. ha->type = GDT_EISA;
  610. ha->stype = id;
  611. outl(1,eisa_adr+MAILBOXREG+8);
  612. outb(0xfe,eisa_adr+LDOORREG);
  613. retries = INIT_RETRIES;
  614. gdth_delay(20);
  615. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  616. if (--retries == 0) {
  617. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  618. return 0;
  619. }
  620. gdth_delay(1);
  621. }
  622. ha->irq = inb(eisa_adr+MAILBOXREG);
  623. outb(0xff,eisa_adr+EDOORREG);
  624. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  625. /* check the result */
  626. if (ha->irq == 0) {
  627. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  628. for (i = 0, irq_found = FALSE;
  629. i < MAXHA && irq[i] != 0xff; ++i) {
  630. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  631. irq_found = TRUE;
  632. break;
  633. }
  634. }
  635. if (irq_found) {
  636. ha->irq = irq[i];
  637. irq[i] = 0;
  638. printk("GDT-EISA: Can not detect controller IRQ,\n");
  639. printk("Use IRQ setting from command line (IRQ = %d)\n",
  640. ha->irq);
  641. } else {
  642. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  643. printk("the controller BIOS or use command line parameters\n");
  644. return 0;
  645. }
  646. }
  647. } else {
  648. eisacf = inb(eisa_adr+EISAREG) & 7;
  649. if (eisacf > 4) /* level triggered */
  650. eisacf -= 4;
  651. ha->irq = gdth_irq_tab[eisacf];
  652. ha->oem_id = OEM_ID_ICP;
  653. ha->type = GDT_EISA;
  654. ha->stype = id;
  655. }
  656. ha->dma64_support = 0;
  657. return 1;
  658. }
  659. #endif /* CONFIG_EISA */
  660. #ifdef CONFIG_ISA
  661. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  662. {
  663. register gdt2_dpram_str __iomem *dp2_ptr;
  664. int i;
  665. unchar irq_drq,prot_ver;
  666. ulong32 retries;
  667. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  668. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  669. if (ha->brd == NULL) {
  670. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  671. return 0;
  672. }
  673. dp2_ptr = ha->brd;
  674. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  675. /* reset interface area */
  676. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  677. if (readl(&dp2_ptr->u) != 0) {
  678. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  679. iounmap(ha->brd);
  680. return 0;
  681. }
  682. /* disable board interrupts, read DRQ and IRQ */
  683. writeb(0xff, &dp2_ptr->io.irqdel);
  684. writeb(0x00, &dp2_ptr->io.irqen);
  685. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  686. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  687. irq_drq = readb(&dp2_ptr->io.rq);
  688. for (i=0; i<3; ++i) {
  689. if ((irq_drq & 1)==0)
  690. break;
  691. irq_drq >>= 1;
  692. }
  693. ha->drq = gdth_drq_tab[i];
  694. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  695. for (i=1; i<5; ++i) {
  696. if ((irq_drq & 1)==0)
  697. break;
  698. irq_drq >>= 1;
  699. }
  700. ha->irq = gdth_irq_tab[i];
  701. /* deinitialize services */
  702. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  703. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  704. writeb(0, &dp2_ptr->io.event);
  705. retries = INIT_RETRIES;
  706. gdth_delay(20);
  707. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  708. if (--retries == 0) {
  709. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  710. iounmap(ha->brd);
  711. return 0;
  712. }
  713. gdth_delay(1);
  714. }
  715. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  716. writeb(0, &dp2_ptr->u.ic.Status);
  717. writeb(0xff, &dp2_ptr->io.irqdel);
  718. if (prot_ver != PROTOCOL_VERSION) {
  719. printk("GDT-ISA: Illegal protocol version\n");
  720. iounmap(ha->brd);
  721. return 0;
  722. }
  723. ha->oem_id = OEM_ID_ICP;
  724. ha->type = GDT_ISA;
  725. ha->ic_all_size = sizeof(dp2_ptr->u);
  726. ha->stype= GDT2_ID;
  727. ha->brd_phys = bios_adr >> 4;
  728. /* special request to controller BIOS */
  729. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  730. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  731. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  732. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  733. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  734. writeb(0, &dp2_ptr->io.event);
  735. retries = INIT_RETRIES;
  736. gdth_delay(20);
  737. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  738. if (--retries == 0) {
  739. printk("GDT-ISA: Initialization error\n");
  740. iounmap(ha->brd);
  741. return 0;
  742. }
  743. gdth_delay(1);
  744. }
  745. writeb(0, &dp2_ptr->u.ic.Status);
  746. writeb(0xff, &dp2_ptr->io.irqdel);
  747. ha->dma64_support = 0;
  748. return 1;
  749. }
  750. #endif /* CONFIG_ISA */
  751. #ifdef CONFIG_PCI
  752. static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  753. gdth_ha_str *ha)
  754. {
  755. register gdt6_dpram_str __iomem *dp6_ptr;
  756. register gdt6c_dpram_str __iomem *dp6c_ptr;
  757. register gdt6m_dpram_str __iomem *dp6m_ptr;
  758. ulong32 retries;
  759. unchar prot_ver;
  760. ushort command;
  761. int i, found = FALSE;
  762. TRACE(("gdth_init_pci()\n"));
  763. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  764. ha->oem_id = OEM_ID_INTEL;
  765. else
  766. ha->oem_id = OEM_ID_ICP;
  767. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  768. ha->stype = (ulong32)pdev->device;
  769. ha->irq = pdev->irq;
  770. ha->pdev = pdev;
  771. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  772. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  773. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  774. if (ha->brd == NULL) {
  775. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  776. return 0;
  777. }
  778. /* check and reset interface area */
  779. dp6_ptr = ha->brd;
  780. writel(DPMEM_MAGIC, &dp6_ptr->u);
  781. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  782. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  783. pcistr->dpmem);
  784. found = FALSE;
  785. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  786. iounmap(ha->brd);
  787. ha->brd = ioremap(i, sizeof(ushort));
  788. if (ha->brd == NULL) {
  789. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  790. return 0;
  791. }
  792. if (readw(ha->brd) != 0xffff) {
  793. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  794. continue;
  795. }
  796. iounmap(ha->brd);
  797. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  798. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  799. if (ha->brd == NULL) {
  800. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  801. return 0;
  802. }
  803. dp6_ptr = ha->brd;
  804. writel(DPMEM_MAGIC, &dp6_ptr->u);
  805. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  806. printk("GDT-PCI: Use free address at 0x%x\n", i);
  807. found = TRUE;
  808. break;
  809. }
  810. }
  811. if (!found) {
  812. printk("GDT-PCI: No free address found!\n");
  813. iounmap(ha->brd);
  814. return 0;
  815. }
  816. }
  817. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  818. if (readl(&dp6_ptr->u) != 0) {
  819. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  820. iounmap(ha->brd);
  821. return 0;
  822. }
  823. /* disable board interrupts, deinit services */
  824. writeb(0xff, &dp6_ptr->io.irqdel);
  825. writeb(0x00, &dp6_ptr->io.irqen);
  826. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  827. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  828. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  829. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  830. writeb(0, &dp6_ptr->io.event);
  831. retries = INIT_RETRIES;
  832. gdth_delay(20);
  833. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  834. if (--retries == 0) {
  835. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  836. iounmap(ha->brd);
  837. return 0;
  838. }
  839. gdth_delay(1);
  840. }
  841. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  842. writeb(0, &dp6_ptr->u.ic.S_Status);
  843. writeb(0xff, &dp6_ptr->io.irqdel);
  844. if (prot_ver != PROTOCOL_VERSION) {
  845. printk("GDT-PCI: Illegal protocol version\n");
  846. iounmap(ha->brd);
  847. return 0;
  848. }
  849. ha->type = GDT_PCI;
  850. ha->ic_all_size = sizeof(dp6_ptr->u);
  851. /* special command to controller BIOS */
  852. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  853. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  854. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  856. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  857. writeb(0, &dp6_ptr->io.event);
  858. retries = INIT_RETRIES;
  859. gdth_delay(20);
  860. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  861. if (--retries == 0) {
  862. printk("GDT-PCI: Initialization error\n");
  863. iounmap(ha->brd);
  864. return 0;
  865. }
  866. gdth_delay(1);
  867. }
  868. writeb(0, &dp6_ptr->u.ic.S_Status);
  869. writeb(0xff, &dp6_ptr->io.irqdel);
  870. ha->dma64_support = 0;
  871. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  872. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  873. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  874. pcistr->dpmem,ha->irq));
  875. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  876. if (ha->brd == NULL) {
  877. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  878. iounmap(ha->brd);
  879. return 0;
  880. }
  881. /* check and reset interface area */
  882. dp6c_ptr = ha->brd;
  883. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  884. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  885. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  886. pcistr->dpmem);
  887. found = FALSE;
  888. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  889. iounmap(ha->brd);
  890. ha->brd = ioremap(i, sizeof(ushort));
  891. if (ha->brd == NULL) {
  892. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  893. return 0;
  894. }
  895. if (readw(ha->brd) != 0xffff) {
  896. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  897. continue;
  898. }
  899. iounmap(ha->brd);
  900. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  901. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  902. if (ha->brd == NULL) {
  903. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  904. return 0;
  905. }
  906. dp6c_ptr = ha->brd;
  907. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  908. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  909. printk("GDT-PCI: Use free address at 0x%x\n", i);
  910. found = TRUE;
  911. break;
  912. }
  913. }
  914. if (!found) {
  915. printk("GDT-PCI: No free address found!\n");
  916. iounmap(ha->brd);
  917. return 0;
  918. }
  919. }
  920. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  921. if (readl(&dp6c_ptr->u) != 0) {
  922. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  923. iounmap(ha->brd);
  924. return 0;
  925. }
  926. /* disable board interrupts, deinit services */
  927. outb(0x00,PTR2USHORT(&ha->plx->control1));
  928. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  929. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  930. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  931. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  932. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  933. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  934. retries = INIT_RETRIES;
  935. gdth_delay(20);
  936. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  937. if (--retries == 0) {
  938. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  939. iounmap(ha->brd);
  940. return 0;
  941. }
  942. gdth_delay(1);
  943. }
  944. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  945. writeb(0, &dp6c_ptr->u.ic.Status);
  946. if (prot_ver != PROTOCOL_VERSION) {
  947. printk("GDT-PCI: Illegal protocol version\n");
  948. iounmap(ha->brd);
  949. return 0;
  950. }
  951. ha->type = GDT_PCINEW;
  952. ha->ic_all_size = sizeof(dp6c_ptr->u);
  953. /* special command to controller BIOS */
  954. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  955. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  956. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  958. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  959. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  960. retries = INIT_RETRIES;
  961. gdth_delay(20);
  962. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  963. if (--retries == 0) {
  964. printk("GDT-PCI: Initialization error\n");
  965. iounmap(ha->brd);
  966. return 0;
  967. }
  968. gdth_delay(1);
  969. }
  970. writeb(0, &dp6c_ptr->u.ic.S_Status);
  971. ha->dma64_support = 0;
  972. } else { /* MPR */
  973. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  974. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  975. if (ha->brd == NULL) {
  976. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  977. return 0;
  978. }
  979. /* manipulate config. space to enable DPMEM, start RP controller */
  980. pci_read_config_word(pdev, PCI_COMMAND, &command);
  981. command |= 6;
  982. pci_write_config_word(pdev, PCI_COMMAND, command);
  983. if (pci_resource_start(pdev, 8) == 1UL)
  984. pci_resource_start(pdev, 8) = 0UL;
  985. i = 0xFEFF0001UL;
  986. pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
  987. gdth_delay(1);
  988. pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
  989. pci_resource_start(pdev, 8));
  990. dp6m_ptr = ha->brd;
  991. /* Ensure that it is safe to access the non HW portions of DPMEM.
  992. * Aditional check needed for Xscale based RAID controllers */
  993. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  994. gdth_delay(1);
  995. /* check and reset interface area */
  996. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  997. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  998. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  999. pcistr->dpmem);
  1000. found = FALSE;
  1001. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1002. iounmap(ha->brd);
  1003. ha->brd = ioremap(i, sizeof(ushort));
  1004. if (ha->brd == NULL) {
  1005. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1006. return 0;
  1007. }
  1008. if (readw(ha->brd) != 0xffff) {
  1009. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1010. continue;
  1011. }
  1012. iounmap(ha->brd);
  1013. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1014. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1015. if (ha->brd == NULL) {
  1016. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1017. return 0;
  1018. }
  1019. dp6m_ptr = ha->brd;
  1020. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1021. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1022. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1023. found = TRUE;
  1024. break;
  1025. }
  1026. }
  1027. if (!found) {
  1028. printk("GDT-PCI: No free address found!\n");
  1029. iounmap(ha->brd);
  1030. return 0;
  1031. }
  1032. }
  1033. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1034. /* disable board interrupts, deinit services */
  1035. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1036. &dp6m_ptr->i960r.edoor_en_reg);
  1037. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1038. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1039. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1040. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1041. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1042. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1043. retries = INIT_RETRIES;
  1044. gdth_delay(20);
  1045. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1046. if (--retries == 0) {
  1047. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1048. iounmap(ha->brd);
  1049. return 0;
  1050. }
  1051. gdth_delay(1);
  1052. }
  1053. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1054. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1055. if (prot_ver != PROTOCOL_VERSION) {
  1056. printk("GDT-PCI: Illegal protocol version\n");
  1057. iounmap(ha->brd);
  1058. return 0;
  1059. }
  1060. ha->type = GDT_PCIMPR;
  1061. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1062. /* special command to controller BIOS */
  1063. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1064. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1065. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1066. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1067. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1068. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1069. retries = INIT_RETRIES;
  1070. gdth_delay(20);
  1071. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1072. if (--retries == 0) {
  1073. printk("GDT-PCI: Initialization error\n");
  1074. iounmap(ha->brd);
  1075. return 0;
  1076. }
  1077. gdth_delay(1);
  1078. }
  1079. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1080. /* read FW version to detect 64-bit DMA support */
  1081. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1082. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1083. retries = INIT_RETRIES;
  1084. gdth_delay(20);
  1085. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1086. if (--retries == 0) {
  1087. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1088. iounmap(ha->brd);
  1089. return 0;
  1090. }
  1091. gdth_delay(1);
  1092. }
  1093. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1094. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1095. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1096. ha->dma64_support = 0;
  1097. else
  1098. ha->dma64_support = 1;
  1099. }
  1100. return 1;
  1101. }
  1102. #endif /* CONFIG_PCI */
  1103. /* controller protocol functions */
  1104. static void __init gdth_enable_int(gdth_ha_str *ha)
  1105. {
  1106. ulong flags;
  1107. gdt2_dpram_str __iomem *dp2_ptr;
  1108. gdt6_dpram_str __iomem *dp6_ptr;
  1109. gdt6m_dpram_str __iomem *dp6m_ptr;
  1110. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1111. spin_lock_irqsave(&ha->smp_lock, flags);
  1112. if (ha->type == GDT_EISA) {
  1113. outb(0xff, ha->bmic + EDOORREG);
  1114. outb(0xff, ha->bmic + EDENABREG);
  1115. outb(0x01, ha->bmic + EINTENABREG);
  1116. } else if (ha->type == GDT_ISA) {
  1117. dp2_ptr = ha->brd;
  1118. writeb(1, &dp2_ptr->io.irqdel);
  1119. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1120. writeb(1, &dp2_ptr->io.irqen);
  1121. } else if (ha->type == GDT_PCI) {
  1122. dp6_ptr = ha->brd;
  1123. writeb(1, &dp6_ptr->io.irqdel);
  1124. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1125. writeb(1, &dp6_ptr->io.irqen);
  1126. } else if (ha->type == GDT_PCINEW) {
  1127. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1128. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1129. } else if (ha->type == GDT_PCIMPR) {
  1130. dp6m_ptr = ha->brd;
  1131. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1132. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1133. &dp6m_ptr->i960r.edoor_en_reg);
  1134. }
  1135. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1136. }
  1137. /* return IStatus if interrupt was from this card else 0 */
  1138. static unchar gdth_get_status(gdth_ha_str *ha)
  1139. {
  1140. unchar IStatus = 0;
  1141. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1142. if (ha->type == GDT_EISA)
  1143. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1144. else if (ha->type == GDT_ISA)
  1145. IStatus =
  1146. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1147. else if (ha->type == GDT_PCI)
  1148. IStatus =
  1149. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1150. else if (ha->type == GDT_PCINEW)
  1151. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1152. else if (ha->type == GDT_PCIMPR)
  1153. IStatus =
  1154. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1155. return IStatus;
  1156. }
  1157. static int gdth_test_busy(gdth_ha_str *ha)
  1158. {
  1159. register int gdtsema0 = 0;
  1160. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1161. if (ha->type == GDT_EISA)
  1162. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1163. else if (ha->type == GDT_ISA)
  1164. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1165. else if (ha->type == GDT_PCI)
  1166. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1167. else if (ha->type == GDT_PCINEW)
  1168. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1169. else if (ha->type == GDT_PCIMPR)
  1170. gdtsema0 =
  1171. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1172. return (gdtsema0 & 1);
  1173. }
  1174. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1175. {
  1176. int i;
  1177. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1178. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1179. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1180. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1181. ha->cmd_tab[i].service = ha->pccb->Service;
  1182. ha->pccb->CommandIndex = (ulong32)i+2;
  1183. return (i+2);
  1184. }
  1185. }
  1186. return 0;
  1187. }
  1188. static void gdth_set_sema0(gdth_ha_str *ha)
  1189. {
  1190. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1191. if (ha->type == GDT_EISA) {
  1192. outb(1, ha->bmic + SEMA0REG);
  1193. } else if (ha->type == GDT_ISA) {
  1194. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1195. } else if (ha->type == GDT_PCI) {
  1196. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1197. } else if (ha->type == GDT_PCINEW) {
  1198. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1199. } else if (ha->type == GDT_PCIMPR) {
  1200. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1201. }
  1202. }
  1203. static void gdth_copy_command(gdth_ha_str *ha)
  1204. {
  1205. register gdth_cmd_str *cmd_ptr;
  1206. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1207. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1208. gdt6_dpram_str __iomem *dp6_ptr;
  1209. gdt2_dpram_str __iomem *dp2_ptr;
  1210. ushort cp_count,dp_offset,cmd_no;
  1211. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1212. cp_count = ha->cmd_len;
  1213. dp_offset= ha->cmd_offs_dpmem;
  1214. cmd_no = ha->cmd_cnt;
  1215. cmd_ptr = ha->pccb;
  1216. ++ha->cmd_cnt;
  1217. if (ha->type == GDT_EISA)
  1218. return; /* no DPMEM, no copy */
  1219. /* set cpcount dword aligned */
  1220. if (cp_count & 3)
  1221. cp_count += (4 - (cp_count & 3));
  1222. ha->cmd_offs_dpmem += cp_count;
  1223. /* set offset and service, copy command to DPMEM */
  1224. if (ha->type == GDT_ISA) {
  1225. dp2_ptr = ha->brd;
  1226. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1227. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1228. writew((ushort)cmd_ptr->Service,
  1229. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1230. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1231. } else if (ha->type == GDT_PCI) {
  1232. dp6_ptr = ha->brd;
  1233. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1234. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1235. writew((ushort)cmd_ptr->Service,
  1236. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1237. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1238. } else if (ha->type == GDT_PCINEW) {
  1239. dp6c_ptr = ha->brd;
  1240. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1241. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1242. writew((ushort)cmd_ptr->Service,
  1243. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1244. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1245. } else if (ha->type == GDT_PCIMPR) {
  1246. dp6m_ptr = ha->brd;
  1247. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1248. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1249. writew((ushort)cmd_ptr->Service,
  1250. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1251. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1252. }
  1253. }
  1254. static void gdth_release_event(gdth_ha_str *ha)
  1255. {
  1256. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1257. #ifdef GDTH_STATISTICS
  1258. {
  1259. ulong32 i,j;
  1260. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1261. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1262. ++i;
  1263. }
  1264. if (max_index < i) {
  1265. max_index = i;
  1266. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1267. }
  1268. }
  1269. #endif
  1270. if (ha->pccb->OpCode == GDT_INIT)
  1271. ha->pccb->Service |= 0x80;
  1272. if (ha->type == GDT_EISA) {
  1273. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1274. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1275. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1276. } else if (ha->type == GDT_ISA) {
  1277. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1278. } else if (ha->type == GDT_PCI) {
  1279. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1280. } else if (ha->type == GDT_PCINEW) {
  1281. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1282. } else if (ha->type == GDT_PCIMPR) {
  1283. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1284. }
  1285. }
  1286. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1287. {
  1288. int answer_found = FALSE;
  1289. int wait_index = 0;
  1290. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1291. if (index == 0)
  1292. return 1; /* no wait required */
  1293. do {
  1294. __gdth_interrupt(ha, true, &wait_index);
  1295. if (wait_index == index) {
  1296. answer_found = TRUE;
  1297. break;
  1298. }
  1299. gdth_delay(1);
  1300. } while (--time);
  1301. while (gdth_test_busy(ha))
  1302. gdth_delay(0);
  1303. return (answer_found);
  1304. }
  1305. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1306. ulong32 p1, ulong64 p2, ulong64 p3)
  1307. {
  1308. register gdth_cmd_str *cmd_ptr;
  1309. int retries,index;
  1310. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1311. cmd_ptr = ha->pccb;
  1312. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1313. /* make command */
  1314. for (retries = INIT_RETRIES;;) {
  1315. cmd_ptr->Service = service;
  1316. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1317. if (!(index=gdth_get_cmd_index(ha))) {
  1318. TRACE(("GDT: No free command index found\n"));
  1319. return 0;
  1320. }
  1321. gdth_set_sema0(ha);
  1322. cmd_ptr->OpCode = opcode;
  1323. cmd_ptr->BoardNode = LOCALBOARD;
  1324. if (service == CACHESERVICE) {
  1325. if (opcode == GDT_IOCTL) {
  1326. cmd_ptr->u.ioctl.subfunc = p1;
  1327. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1328. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1329. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1330. } else {
  1331. if (ha->cache_feat & GDT_64BIT) {
  1332. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1333. cmd_ptr->u.cache64.BlockNo = p2;
  1334. } else {
  1335. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1336. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1337. }
  1338. }
  1339. } else if (service == SCSIRAWSERVICE) {
  1340. if (ha->raw_feat & GDT_64BIT) {
  1341. cmd_ptr->u.raw64.direction = p1;
  1342. cmd_ptr->u.raw64.bus = (unchar)p2;
  1343. cmd_ptr->u.raw64.target = (unchar)p3;
  1344. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1345. } else {
  1346. cmd_ptr->u.raw.direction = p1;
  1347. cmd_ptr->u.raw.bus = (unchar)p2;
  1348. cmd_ptr->u.raw.target = (unchar)p3;
  1349. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1350. }
  1351. } else if (service == SCREENSERVICE) {
  1352. if (opcode == GDT_REALTIME) {
  1353. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1354. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1355. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1356. }
  1357. }
  1358. ha->cmd_len = sizeof(gdth_cmd_str);
  1359. ha->cmd_offs_dpmem = 0;
  1360. ha->cmd_cnt = 0;
  1361. gdth_copy_command(ha);
  1362. gdth_release_event(ha);
  1363. gdth_delay(20);
  1364. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1365. printk("GDT: Initialization error (timeout service %d)\n",service);
  1366. return 0;
  1367. }
  1368. if (ha->status != S_BSY || --retries == 0)
  1369. break;
  1370. gdth_delay(1);
  1371. }
  1372. return (ha->status != S_OK ? 0:1);
  1373. }
  1374. /* search for devices */
  1375. static int __init gdth_search_drives(gdth_ha_str *ha)
  1376. {
  1377. ushort cdev_cnt, i;
  1378. int ok;
  1379. ulong32 bus_no, drv_cnt, drv_no, j;
  1380. gdth_getch_str *chn;
  1381. gdth_drlist_str *drl;
  1382. gdth_iochan_str *ioc;
  1383. gdth_raw_iochan_str *iocr;
  1384. gdth_arcdl_str *alst;
  1385. gdth_alist_str *alst2;
  1386. gdth_oem_str_ioctl *oemstr;
  1387. #ifdef INT_COAL
  1388. gdth_perf_modes *pmod;
  1389. #endif
  1390. #ifdef GDTH_RTC
  1391. unchar rtc[12];
  1392. ulong flags;
  1393. #endif
  1394. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1395. ok = 0;
  1396. /* initialize controller services, at first: screen service */
  1397. ha->screen_feat = 0;
  1398. if (!force_dma32) {
  1399. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1400. if (ok)
  1401. ha->screen_feat = GDT_64BIT;
  1402. }
  1403. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1404. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1405. if (!ok) {
  1406. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1407. ha->hanum, ha->status);
  1408. return 0;
  1409. }
  1410. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1411. #ifdef GDTH_RTC
  1412. /* read realtime clock info, send to controller */
  1413. /* 1. wait for the falling edge of update flag */
  1414. spin_lock_irqsave(&rtc_lock, flags);
  1415. for (j = 0; j < 1000000; ++j)
  1416. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1417. break;
  1418. for (j = 0; j < 1000000; ++j)
  1419. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1420. break;
  1421. /* 2. read info */
  1422. do {
  1423. for (j = 0; j < 12; ++j)
  1424. rtc[j] = CMOS_READ(j);
  1425. } while (rtc[0] != CMOS_READ(0));
  1426. spin_unlock_irqrestore(&rtc_lock, flags);
  1427. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1428. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1429. /* 3. send to controller firmware */
  1430. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1431. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1432. #endif
  1433. /* unfreeze all IOs */
  1434. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1435. /* initialize cache service */
  1436. ha->cache_feat = 0;
  1437. if (!force_dma32) {
  1438. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1439. 0, 0);
  1440. if (ok)
  1441. ha->cache_feat = GDT_64BIT;
  1442. }
  1443. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1444. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1445. if (!ok) {
  1446. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1447. ha->hanum, ha->status);
  1448. return 0;
  1449. }
  1450. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1451. cdev_cnt = (ushort)ha->info;
  1452. ha->fw_vers = ha->service;
  1453. #ifdef INT_COAL
  1454. if (ha->type == GDT_PCIMPR) {
  1455. /* set perf. modes */
  1456. pmod = (gdth_perf_modes *)ha->pscratch;
  1457. pmod->version = 1;
  1458. pmod->st_mode = 1; /* enable one status buffer */
  1459. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1460. pmod->st_buff_indx1 = COALINDEX;
  1461. pmod->st_buff_addr2 = 0;
  1462. pmod->st_buff_u_addr2 = 0;
  1463. pmod->st_buff_indx2 = 0;
  1464. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1465. pmod->cmd_mode = 0; // disable all cmd buffers
  1466. pmod->cmd_buff_addr1 = 0;
  1467. pmod->cmd_buff_u_addr1 = 0;
  1468. pmod->cmd_buff_indx1 = 0;
  1469. pmod->cmd_buff_addr2 = 0;
  1470. pmod->cmd_buff_u_addr2 = 0;
  1471. pmod->cmd_buff_indx2 = 0;
  1472. pmod->cmd_buff_size = 0;
  1473. pmod->reserved1 = 0;
  1474. pmod->reserved2 = 0;
  1475. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1476. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1477. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1478. }
  1479. }
  1480. #endif
  1481. /* detect number of buses - try new IOCTL */
  1482. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1483. iocr->hdr.version = 0xffffffff;
  1484. iocr->hdr.list_entries = MAXBUS;
  1485. iocr->hdr.first_chan = 0;
  1486. iocr->hdr.last_chan = MAXBUS-1;
  1487. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1488. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1489. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1490. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1491. ha->bus_cnt = iocr->hdr.chan_count;
  1492. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1493. if (iocr->list[bus_no].proc_id < MAXID)
  1494. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1495. else
  1496. ha->bus_id[bus_no] = 0xff;
  1497. }
  1498. } else {
  1499. /* old method */
  1500. chn = (gdth_getch_str *)ha->pscratch;
  1501. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1502. chn->channel_no = bus_no;
  1503. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1504. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1505. IO_CHANNEL | INVALID_CHANNEL,
  1506. sizeof(gdth_getch_str))) {
  1507. if (bus_no == 0) {
  1508. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1509. ha->hanum, ha->status);
  1510. return 0;
  1511. }
  1512. break;
  1513. }
  1514. if (chn->siop_id < MAXID)
  1515. ha->bus_id[bus_no] = chn->siop_id;
  1516. else
  1517. ha->bus_id[bus_no] = 0xff;
  1518. }
  1519. ha->bus_cnt = (unchar)bus_no;
  1520. }
  1521. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1522. /* read cache configuration */
  1523. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1524. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1525. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1526. ha->hanum, ha->status);
  1527. return 0;
  1528. }
  1529. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1530. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1531. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1532. ha->cpar.write_back,ha->cpar.block_size));
  1533. /* read board info and features */
  1534. ha->more_proc = FALSE;
  1535. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1536. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1537. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1538. sizeof(gdth_binfo_str));
  1539. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1540. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1541. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1542. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1543. ha->more_proc = TRUE;
  1544. }
  1545. } else {
  1546. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1547. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1548. }
  1549. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1550. /* read more informations */
  1551. if (ha->more_proc) {
  1552. /* physical drives, channel addresses */
  1553. ioc = (gdth_iochan_str *)ha->pscratch;
  1554. ioc->hdr.version = 0xffffffff;
  1555. ioc->hdr.list_entries = MAXBUS;
  1556. ioc->hdr.first_chan = 0;
  1557. ioc->hdr.last_chan = MAXBUS-1;
  1558. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1559. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1560. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1561. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1562. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1563. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1564. }
  1565. } else {
  1566. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1567. ha->raw[bus_no].address = IO_CHANNEL;
  1568. ha->raw[bus_no].local_no = bus_no;
  1569. }
  1570. }
  1571. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1572. chn = (gdth_getch_str *)ha->pscratch;
  1573. chn->channel_no = ha->raw[bus_no].local_no;
  1574. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1575. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1576. ha->raw[bus_no].address | INVALID_CHANNEL,
  1577. sizeof(gdth_getch_str))) {
  1578. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1579. TRACE2(("Channel %d: %d phys. drives\n",
  1580. bus_no,chn->drive_cnt));
  1581. }
  1582. if (ha->raw[bus_no].pdev_cnt > 0) {
  1583. drl = (gdth_drlist_str *)ha->pscratch;
  1584. drl->sc_no = ha->raw[bus_no].local_no;
  1585. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1586. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1587. SCSI_DR_LIST | L_CTRL_PATTERN,
  1588. ha->raw[bus_no].address | INVALID_CHANNEL,
  1589. sizeof(gdth_drlist_str))) {
  1590. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1591. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1592. } else {
  1593. ha->raw[bus_no].pdev_cnt = 0;
  1594. }
  1595. }
  1596. }
  1597. /* logical drives */
  1598. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1599. INVALID_CHANNEL,sizeof(ulong32))) {
  1600. drv_cnt = *(ulong32 *)ha->pscratch;
  1601. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1602. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1603. for (j = 0; j < drv_cnt; ++j) {
  1604. drv_no = ((ulong32 *)ha->pscratch)[j];
  1605. if (drv_no < MAX_LDRIVES) {
  1606. ha->hdr[drv_no].is_logdrv = TRUE;
  1607. TRACE2(("Drive %d is log. drive\n",drv_no));
  1608. }
  1609. }
  1610. }
  1611. alst = (gdth_arcdl_str *)ha->pscratch;
  1612. alst->entries_avail = MAX_LDRIVES;
  1613. alst->first_entry = 0;
  1614. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1615. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1616. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1617. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1618. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1619. for (j = 0; j < alst->entries_init; ++j) {
  1620. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1621. ha->hdr[j].is_master = alst->list[j].is_master;
  1622. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1623. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1624. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1625. }
  1626. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1627. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1628. 0, 35 * sizeof(gdth_alist_str))) {
  1629. for (j = 0; j < 35; ++j) {
  1630. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1631. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1632. ha->hdr[j].is_master = alst2->is_master;
  1633. ha->hdr[j].is_parity = alst2->is_parity;
  1634. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1635. ha->hdr[j].master_no = alst2->cd_handle;
  1636. }
  1637. }
  1638. }
  1639. }
  1640. /* initialize raw service */
  1641. ha->raw_feat = 0;
  1642. if (!force_dma32) {
  1643. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1644. if (ok)
  1645. ha->raw_feat = GDT_64BIT;
  1646. }
  1647. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1648. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1649. if (!ok) {
  1650. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1651. ha->hanum, ha->status);
  1652. return 0;
  1653. }
  1654. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1655. /* set/get features raw service (scatter/gather) */
  1656. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1657. 0, 0)) {
  1658. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1659. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1660. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1661. ha->info));
  1662. ha->raw_feat |= (ushort)ha->info;
  1663. }
  1664. }
  1665. /* set/get features cache service (equal to raw service) */
  1666. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1667. SCATTER_GATHER,0)) {
  1668. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1669. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1670. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1671. ha->info));
  1672. ha->cache_feat |= (ushort)ha->info;
  1673. }
  1674. }
  1675. /* reserve drives for raw service */
  1676. if (reserve_mode != 0) {
  1677. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1678. reserve_mode == 1 ? 1 : 3, 0, 0);
  1679. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1680. ha->status));
  1681. }
  1682. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1683. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1684. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1685. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1686. reserve_list[i], reserve_list[i+1],
  1687. reserve_list[i+2], reserve_list[i+3]));
  1688. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1689. reserve_list[i+1], reserve_list[i+2] |
  1690. (reserve_list[i+3] << 8))) {
  1691. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1692. ha->hanum, ha->status);
  1693. }
  1694. }
  1695. }
  1696. /* Determine OEM string using IOCTL */
  1697. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1698. oemstr->params.ctl_version = 0x01;
  1699. oemstr->params.buffer_size = sizeof(oemstr->text);
  1700. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1701. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1702. sizeof(gdth_oem_str_ioctl))) {
  1703. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1704. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1705. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1706. /* Save the Host Drive inquiry data */
  1707. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1708. sizeof(ha->oem_name));
  1709. } else {
  1710. /* Old method, based on PCI ID */
  1711. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1712. printk("GDT-HA %d: Name: %s\n",
  1713. ha->hanum, ha->binfo.type_string);
  1714. if (ha->oem_id == OEM_ID_INTEL)
  1715. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1716. else
  1717. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1718. }
  1719. /* scanning for host drives */
  1720. for (i = 0; i < cdev_cnt; ++i)
  1721. gdth_analyse_hdrive(ha, i);
  1722. TRACE(("gdth_search_drives() OK\n"));
  1723. return 1;
  1724. }
  1725. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1726. {
  1727. ulong32 drv_cyls;
  1728. int drv_hds, drv_secs;
  1729. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1730. if (hdrive >= MAX_HDRIVES)
  1731. return 0;
  1732. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1733. return 0;
  1734. ha->hdr[hdrive].present = TRUE;
  1735. ha->hdr[hdrive].size = ha->info;
  1736. /* evaluate mapping (sectors per head, heads per cylinder) */
  1737. ha->hdr[hdrive].size &= ~SECS32;
  1738. if (ha->info2 == 0) {
  1739. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1740. } else {
  1741. drv_hds = ha->info2 & 0xff;
  1742. drv_secs = (ha->info2 >> 8) & 0xff;
  1743. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1744. }
  1745. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1746. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1747. /* round size */
  1748. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1749. if (ha->cache_feat & GDT_64BIT) {
  1750. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1751. && ha->info2 != 0) {
  1752. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1753. }
  1754. }
  1755. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1756. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1757. /* get informations about device */
  1758. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1759. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1760. hdrive,ha->info));
  1761. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1762. }
  1763. /* cluster info */
  1764. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1765. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1766. hdrive,ha->info));
  1767. if (!shared_access)
  1768. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1769. }
  1770. /* R/W attributes */
  1771. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1772. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1773. hdrive,ha->info));
  1774. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1775. }
  1776. return 1;
  1777. }
  1778. /* command queueing/sending functions */
  1779. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1780. {
  1781. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1782. register Scsi_Cmnd *pscp;
  1783. register Scsi_Cmnd *nscp;
  1784. ulong flags;
  1785. unchar b, t;
  1786. TRACE(("gdth_putq() priority %d\n",priority));
  1787. spin_lock_irqsave(&ha->smp_lock, flags);
  1788. if (!cmndinfo->internal_command) {
  1789. cmndinfo->priority = priority;
  1790. b = scp->device->channel;
  1791. t = scp->device->id;
  1792. if (priority >= DEFAULT_PRI) {
  1793. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1794. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1795. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1796. cmndinfo->timeout = gdth_update_timeout(scp, 0);
  1797. }
  1798. }
  1799. }
  1800. if (ha->req_first==NULL) {
  1801. ha->req_first = scp; /* queue was empty */
  1802. scp->SCp.ptr = NULL;
  1803. } else { /* queue not empty */
  1804. pscp = ha->req_first;
  1805. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1806. /* priority: 0-highest,..,0xff-lowest */
  1807. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1808. pscp = nscp;
  1809. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1810. }
  1811. pscp->SCp.ptr = (char *)scp;
  1812. scp->SCp.ptr = (char *)nscp;
  1813. }
  1814. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1815. #ifdef GDTH_STATISTICS
  1816. flags = 0;
  1817. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1818. ++flags;
  1819. if (max_rq < flags) {
  1820. max_rq = flags;
  1821. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1822. }
  1823. #endif
  1824. }
  1825. static void gdth_next(gdth_ha_str *ha)
  1826. {
  1827. register Scsi_Cmnd *pscp;
  1828. register Scsi_Cmnd *nscp;
  1829. unchar b, t, l, firsttime;
  1830. unchar this_cmd, next_cmd;
  1831. ulong flags = 0;
  1832. int cmd_index;
  1833. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1834. if (!gdth_polling)
  1835. spin_lock_irqsave(&ha->smp_lock, flags);
  1836. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1837. this_cmd = firsttime = TRUE;
  1838. next_cmd = gdth_polling ? FALSE:TRUE;
  1839. cmd_index = 0;
  1840. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1841. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1842. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1843. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1844. if (!nscp_cmndinfo->internal_command) {
  1845. b = nscp->device->channel;
  1846. t = nscp->device->id;
  1847. l = nscp->device->lun;
  1848. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1849. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1850. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1851. continue;
  1852. }
  1853. } else
  1854. b = t = l = 0;
  1855. if (firsttime) {
  1856. if (gdth_test_busy(ha)) { /* controller busy ? */
  1857. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1858. if (!gdth_polling) {
  1859. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1860. return;
  1861. }
  1862. while (gdth_test_busy(ha))
  1863. gdth_delay(1);
  1864. }
  1865. firsttime = FALSE;
  1866. }
  1867. if (!nscp_cmndinfo->internal_command) {
  1868. if (nscp_cmndinfo->phase == -1) {
  1869. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1870. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1871. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1872. b, t, l));
  1873. /* TEST_UNIT_READY -> set scan mode */
  1874. if ((ha->scan_mode & 0x0f) == 0) {
  1875. if (b == 0 && t == 0 && l == 0) {
  1876. ha->scan_mode |= 1;
  1877. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1878. }
  1879. } else if ((ha->scan_mode & 0x0f) == 1) {
  1880. if (b == 0 && ((t == 0 && l == 1) ||
  1881. (t == 1 && l == 0))) {
  1882. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1883. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1884. | SCSIRAWSERVICE;
  1885. ha->scan_mode = 0x12;
  1886. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1887. ha->scan_mode));
  1888. } else {
  1889. ha->scan_mode &= 0x10;
  1890. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1891. }
  1892. } else if (ha->scan_mode == 0x12) {
  1893. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1894. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1895. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1896. ha->scan_mode &= 0x10;
  1897. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1898. ha->scan_mode));
  1899. }
  1900. }
  1901. }
  1902. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1903. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1904. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1905. /* always GDT_CLUST_INFO! */
  1906. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1907. }
  1908. }
  1909. }
  1910. if (nscp_cmndinfo->OpCode != -1) {
  1911. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1912. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1913. this_cmd = FALSE;
  1914. next_cmd = FALSE;
  1915. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1916. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1917. this_cmd = FALSE;
  1918. next_cmd = FALSE;
  1919. } else {
  1920. memset((char*)nscp->sense_buffer,0,16);
  1921. nscp->sense_buffer[0] = 0x70;
  1922. nscp->sense_buffer[2] = NOT_READY;
  1923. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1924. if (!nscp_cmndinfo->wait_for_completion)
  1925. nscp_cmndinfo->wait_for_completion++;
  1926. else
  1927. gdth_scsi_done(nscp);
  1928. }
  1929. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1930. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1931. this_cmd = FALSE;
  1932. next_cmd = FALSE;
  1933. } else if (b != ha->virt_bus) {
  1934. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1935. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1936. this_cmd = FALSE;
  1937. else
  1938. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1939. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1940. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1941. nscp->cmnd[0], b, t, l));
  1942. nscp->result = DID_BAD_TARGET << 16;
  1943. if (!nscp_cmndinfo->wait_for_completion)
  1944. nscp_cmndinfo->wait_for_completion++;
  1945. else
  1946. gdth_scsi_done(nscp);
  1947. } else {
  1948. switch (nscp->cmnd[0]) {
  1949. case TEST_UNIT_READY:
  1950. case INQUIRY:
  1951. case REQUEST_SENSE:
  1952. case READ_CAPACITY:
  1953. case VERIFY:
  1954. case START_STOP:
  1955. case MODE_SENSE:
  1956. case SERVICE_ACTION_IN:
  1957. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1958. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1959. nscp->cmnd[4],nscp->cmnd[5]));
  1960. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1961. /* return UNIT_ATTENTION */
  1962. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1963. nscp->cmnd[0], t));
  1964. ha->hdr[t].media_changed = FALSE;
  1965. memset((char*)nscp->sense_buffer,0,16);
  1966. nscp->sense_buffer[0] = 0x70;
  1967. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1968. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1969. if (!nscp_cmndinfo->wait_for_completion)
  1970. nscp_cmndinfo->wait_for_completion++;
  1971. else
  1972. gdth_scsi_done(nscp);
  1973. } else if (gdth_internal_cache_cmd(ha, nscp))
  1974. gdth_scsi_done(nscp);
  1975. break;
  1976. case ALLOW_MEDIUM_REMOVAL:
  1977. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1978. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1979. nscp->cmnd[4],nscp->cmnd[5]));
  1980. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1981. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1982. nscp->result = DID_OK << 16;
  1983. nscp->sense_buffer[0] = 0;
  1984. if (!nscp_cmndinfo->wait_for_completion)
  1985. nscp_cmndinfo->wait_for_completion++;
  1986. else
  1987. gdth_scsi_done(nscp);
  1988. } else {
  1989. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1990. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1991. nscp->cmnd[4],nscp->cmnd[3]));
  1992. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1993. this_cmd = FALSE;
  1994. }
  1995. break;
  1996. case RESERVE:
  1997. case RELEASE:
  1998. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1999. "RESERVE" : "RELEASE"));
  2000. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2001. this_cmd = FALSE;
  2002. break;
  2003. case READ_6:
  2004. case WRITE_6:
  2005. case READ_10:
  2006. case WRITE_10:
  2007. case READ_16:
  2008. case WRITE_16:
  2009. if (ha->hdr[t].media_changed) {
  2010. /* return UNIT_ATTENTION */
  2011. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2012. nscp->cmnd[0], t));
  2013. ha->hdr[t].media_changed = FALSE;
  2014. memset((char*)nscp->sense_buffer,0,16);
  2015. nscp->sense_buffer[0] = 0x70;
  2016. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2017. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2018. if (!nscp_cmndinfo->wait_for_completion)
  2019. nscp_cmndinfo->wait_for_completion++;
  2020. else
  2021. gdth_scsi_done(nscp);
  2022. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2023. this_cmd = FALSE;
  2024. break;
  2025. default:
  2026. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2027. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2028. nscp->cmnd[4],nscp->cmnd[5]));
  2029. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2030. ha->hanum, nscp->cmnd[0]);
  2031. nscp->result = DID_ABORT << 16;
  2032. if (!nscp_cmndinfo->wait_for_completion)
  2033. nscp_cmndinfo->wait_for_completion++;
  2034. else
  2035. gdth_scsi_done(nscp);
  2036. break;
  2037. }
  2038. }
  2039. if (!this_cmd)
  2040. break;
  2041. if (nscp == ha->req_first)
  2042. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2043. else
  2044. pscp->SCp.ptr = nscp->SCp.ptr;
  2045. if (!next_cmd)
  2046. break;
  2047. }
  2048. if (ha->cmd_cnt > 0) {
  2049. gdth_release_event(ha);
  2050. }
  2051. if (!gdth_polling)
  2052. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2053. if (gdth_polling && ha->cmd_cnt > 0) {
  2054. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2055. printk("GDT-HA %d: Command %d timed out !\n",
  2056. ha->hanum, cmd_index);
  2057. }
  2058. }
  2059. /*
  2060. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2061. * buffers, kmap_atomic() as needed.
  2062. */
  2063. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2064. char *buffer, ushort count)
  2065. {
  2066. ushort cpcount,i, max_sg = scsi_sg_count(scp);
  2067. ushort cpsum,cpnow;
  2068. struct scatterlist *sl;
  2069. char *address;
  2070. cpcount = min_t(ushort, count, scsi_bufflen(scp));
  2071. if (cpcount) {
  2072. cpsum=0;
  2073. scsi_for_each_sg(scp, sl, max_sg, i) {
  2074. unsigned long flags;
  2075. cpnow = (ushort)sl->length;
  2076. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2077. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2078. if (cpsum+cpnow > cpcount)
  2079. cpnow = cpcount - cpsum;
  2080. cpsum += cpnow;
  2081. if (!sg_page(sl)) {
  2082. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2083. ha->hanum);
  2084. return;
  2085. }
  2086. local_irq_save(flags);
  2087. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2088. memcpy(address, buffer, cpnow);
  2089. flush_dcache_page(sg_page(sl));
  2090. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2091. local_irq_restore(flags);
  2092. if (cpsum == cpcount)
  2093. break;
  2094. buffer += cpnow;
  2095. }
  2096. } else if (count) {
  2097. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2098. ha->hanum);
  2099. WARN_ON(1);
  2100. }
  2101. }
  2102. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2103. {
  2104. unchar t;
  2105. gdth_inq_data inq;
  2106. gdth_rdcap_data rdc;
  2107. gdth_sense_data sd;
  2108. gdth_modep_data mpd;
  2109. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2110. t = scp->device->id;
  2111. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2112. scp->cmnd[0],t));
  2113. scp->result = DID_OK << 16;
  2114. scp->sense_buffer[0] = 0;
  2115. switch (scp->cmnd[0]) {
  2116. case TEST_UNIT_READY:
  2117. case VERIFY:
  2118. case START_STOP:
  2119. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2120. break;
  2121. case INQUIRY:
  2122. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2123. t,ha->hdr[t].devtype));
  2124. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2125. /* you can here set all disks to removable, if you want to do
  2126. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2127. inq.modif_rmb = 0x00;
  2128. if ((ha->hdr[t].devtype & 1) ||
  2129. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2130. inq.modif_rmb = 0x80;
  2131. inq.version = 2;
  2132. inq.resp_aenc = 2;
  2133. inq.add_length= 32;
  2134. strcpy(inq.vendor,ha->oem_name);
  2135. sprintf(inq.product,"Host Drive #%02d",t);
  2136. strcpy(inq.revision," ");
  2137. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2138. break;
  2139. case REQUEST_SENSE:
  2140. TRACE2(("Request sense hdrive %d\n",t));
  2141. sd.errorcode = 0x70;
  2142. sd.segno = 0x00;
  2143. sd.key = NO_SENSE;
  2144. sd.info = 0;
  2145. sd.add_length= 0;
  2146. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2147. break;
  2148. case MODE_SENSE:
  2149. TRACE2(("Mode sense hdrive %d\n",t));
  2150. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2151. mpd.hd.data_length = sizeof(gdth_modep_data);
  2152. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2153. mpd.hd.bd_length = sizeof(mpd.bd);
  2154. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2155. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2156. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2157. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2158. break;
  2159. case READ_CAPACITY:
  2160. TRACE2(("Read capacity hdrive %d\n",t));
  2161. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2162. rdc.last_block_no = 0xffffffff;
  2163. else
  2164. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2165. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2166. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2167. break;
  2168. case SERVICE_ACTION_IN:
  2169. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2170. (ha->cache_feat & GDT_64BIT)) {
  2171. gdth_rdcap16_data rdc16;
  2172. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2173. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2174. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2175. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2176. sizeof(gdth_rdcap16_data));
  2177. } else {
  2178. scp->result = DID_ABORT << 16;
  2179. }
  2180. break;
  2181. default:
  2182. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2183. break;
  2184. }
  2185. if (!cmndinfo->wait_for_completion)
  2186. cmndinfo->wait_for_completion++;
  2187. else
  2188. return 1;
  2189. return 0;
  2190. }
  2191. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2192. {
  2193. register gdth_cmd_str *cmdp;
  2194. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2195. ulong32 cnt, blockcnt;
  2196. ulong64 no, blockno;
  2197. int i, cmd_index, read_write, sgcnt, mode64;
  2198. cmdp = ha->pccb;
  2199. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2200. scp->cmnd[0],scp->cmd_len,hdrive));
  2201. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2202. return 0;
  2203. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2204. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2205. not required, should not occur due to error return on
  2206. READ_CAPACITY_16 */
  2207. cmdp->Service = CACHESERVICE;
  2208. cmdp->RequestBuffer = scp;
  2209. /* search free command index */
  2210. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2211. TRACE(("GDT: No free command index found\n"));
  2212. return 0;
  2213. }
  2214. /* if it's the first command, set command semaphore */
  2215. if (ha->cmd_cnt == 0)
  2216. gdth_set_sema0(ha);
  2217. /* fill command */
  2218. read_write = 0;
  2219. if (cmndinfo->OpCode != -1)
  2220. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2221. else if (scp->cmnd[0] == RESERVE)
  2222. cmdp->OpCode = GDT_RESERVE_DRV;
  2223. else if (scp->cmnd[0] == RELEASE)
  2224. cmdp->OpCode = GDT_RELEASE_DRV;
  2225. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2226. if (scp->cmnd[4] & 1) /* prevent ? */
  2227. cmdp->OpCode = GDT_MOUNT;
  2228. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2229. cmdp->OpCode = GDT_UNMOUNT;
  2230. else
  2231. cmdp->OpCode = GDT_FLUSH;
  2232. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2233. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2234. ) {
  2235. read_write = 1;
  2236. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2237. (ha->cache_feat & GDT_WR_THROUGH)))
  2238. cmdp->OpCode = GDT_WRITE_THR;
  2239. else
  2240. cmdp->OpCode = GDT_WRITE;
  2241. } else {
  2242. read_write = 2;
  2243. cmdp->OpCode = GDT_READ;
  2244. }
  2245. cmdp->BoardNode = LOCALBOARD;
  2246. if (mode64) {
  2247. cmdp->u.cache64.DeviceNo = hdrive;
  2248. cmdp->u.cache64.BlockNo = 1;
  2249. cmdp->u.cache64.sg_canz = 0;
  2250. } else {
  2251. cmdp->u.cache.DeviceNo = hdrive;
  2252. cmdp->u.cache.BlockNo = 1;
  2253. cmdp->u.cache.sg_canz = 0;
  2254. }
  2255. if (read_write) {
  2256. if (scp->cmd_len == 16) {
  2257. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2258. blockno = be64_to_cpu(no);
  2259. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2260. blockcnt = be32_to_cpu(cnt);
  2261. } else if (scp->cmd_len == 10) {
  2262. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2263. blockno = be32_to_cpu(no);
  2264. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2265. blockcnt = be16_to_cpu(cnt);
  2266. } else {
  2267. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2268. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2269. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2270. }
  2271. if (mode64) {
  2272. cmdp->u.cache64.BlockNo = blockno;
  2273. cmdp->u.cache64.BlockCnt = blockcnt;
  2274. } else {
  2275. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2276. cmdp->u.cache.BlockCnt = blockcnt;
  2277. }
  2278. if (scsi_bufflen(scp)) {
  2279. cmndinfo->dma_dir = (read_write == 1 ?
  2280. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2281. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2282. cmndinfo->dma_dir);
  2283. if (mode64) {
  2284. struct scatterlist *sl;
  2285. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2286. cmdp->u.cache64.sg_canz = sgcnt;
  2287. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2288. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2289. #ifdef GDTH_DMA_STATISTICS
  2290. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2291. ha->dma64_cnt++;
  2292. else
  2293. ha->dma32_cnt++;
  2294. #endif
  2295. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2296. }
  2297. } else {
  2298. struct scatterlist *sl;
  2299. cmdp->u.cache.DestAddr= 0xffffffff;
  2300. cmdp->u.cache.sg_canz = sgcnt;
  2301. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2302. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2303. #ifdef GDTH_DMA_STATISTICS
  2304. ha->dma32_cnt++;
  2305. #endif
  2306. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2307. }
  2308. }
  2309. #ifdef GDTH_STATISTICS
  2310. if (max_sg < (ulong32)sgcnt) {
  2311. max_sg = (ulong32)sgcnt;
  2312. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2313. }
  2314. #endif
  2315. }
  2316. }
  2317. /* evaluate command size, check space */
  2318. if (mode64) {
  2319. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2320. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2321. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2322. cmdp->u.cache64.sg_lst[0].sg_len));
  2323. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2324. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2325. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2326. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2327. } else {
  2328. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2329. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2330. cmdp->u.cache.sg_lst[0].sg_ptr,
  2331. cmdp->u.cache.sg_lst[0].sg_len));
  2332. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2333. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2334. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2335. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2336. }
  2337. if (ha->cmd_len & 3)
  2338. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2339. if (ha->cmd_cnt > 0) {
  2340. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2341. ha->ic_all_size) {
  2342. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2343. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2344. return 0;
  2345. }
  2346. }
  2347. /* copy command */
  2348. gdth_copy_command(ha);
  2349. return cmd_index;
  2350. }
  2351. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2352. {
  2353. register gdth_cmd_str *cmdp;
  2354. ushort i;
  2355. dma_addr_t sense_paddr;
  2356. int cmd_index, sgcnt, mode64;
  2357. unchar t,l;
  2358. struct page *page;
  2359. ulong offset;
  2360. struct gdth_cmndinfo *cmndinfo;
  2361. t = scp->device->id;
  2362. l = scp->device->lun;
  2363. cmdp = ha->pccb;
  2364. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2365. scp->cmnd[0],b,t,l));
  2366. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2367. return 0;
  2368. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2369. cmdp->Service = SCSIRAWSERVICE;
  2370. cmdp->RequestBuffer = scp;
  2371. /* search free command index */
  2372. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2373. TRACE(("GDT: No free command index found\n"));
  2374. return 0;
  2375. }
  2376. /* if it's the first command, set command semaphore */
  2377. if (ha->cmd_cnt == 0)
  2378. gdth_set_sema0(ha);
  2379. cmndinfo = gdth_cmnd_priv(scp);
  2380. /* fill command */
  2381. if (cmndinfo->OpCode != -1) {
  2382. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2383. cmdp->BoardNode = LOCALBOARD;
  2384. if (mode64) {
  2385. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2386. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2387. cmdp->OpCode, cmdp->u.raw64.direction));
  2388. /* evaluate command size */
  2389. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2390. } else {
  2391. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2392. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2393. cmdp->OpCode, cmdp->u.raw.direction));
  2394. /* evaluate command size */
  2395. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2396. }
  2397. } else {
  2398. page = virt_to_page(scp->sense_buffer);
  2399. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2400. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2401. 16,PCI_DMA_FROMDEVICE);
  2402. cmndinfo->sense_paddr = sense_paddr;
  2403. cmdp->OpCode = GDT_WRITE; /* always */
  2404. cmdp->BoardNode = LOCALBOARD;
  2405. if (mode64) {
  2406. cmdp->u.raw64.reserved = 0;
  2407. cmdp->u.raw64.mdisc_time = 0;
  2408. cmdp->u.raw64.mcon_time = 0;
  2409. cmdp->u.raw64.clen = scp->cmd_len;
  2410. cmdp->u.raw64.target = t;
  2411. cmdp->u.raw64.lun = l;
  2412. cmdp->u.raw64.bus = b;
  2413. cmdp->u.raw64.priority = 0;
  2414. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2415. cmdp->u.raw64.sense_len = 16;
  2416. cmdp->u.raw64.sense_data = sense_paddr;
  2417. cmdp->u.raw64.direction =
  2418. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2419. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2420. cmdp->u.raw64.sg_ranz = 0;
  2421. } else {
  2422. cmdp->u.raw.reserved = 0;
  2423. cmdp->u.raw.mdisc_time = 0;
  2424. cmdp->u.raw.mcon_time = 0;
  2425. cmdp->u.raw.clen = scp->cmd_len;
  2426. cmdp->u.raw.target = t;
  2427. cmdp->u.raw.lun = l;
  2428. cmdp->u.raw.bus = b;
  2429. cmdp->u.raw.priority = 0;
  2430. cmdp->u.raw.link_p = 0;
  2431. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2432. cmdp->u.raw.sense_len = 16;
  2433. cmdp->u.raw.sense_data = sense_paddr;
  2434. cmdp->u.raw.direction =
  2435. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2436. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2437. cmdp->u.raw.sg_ranz = 0;
  2438. }
  2439. if (scsi_bufflen(scp)) {
  2440. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2441. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2442. cmndinfo->dma_dir);
  2443. if (mode64) {
  2444. struct scatterlist *sl;
  2445. cmdp->u.raw64.sdata = (ulong64)-1;
  2446. cmdp->u.raw64.sg_ranz = sgcnt;
  2447. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2448. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2449. #ifdef GDTH_DMA_STATISTICS
  2450. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2451. ha->dma64_cnt++;
  2452. else
  2453. ha->dma32_cnt++;
  2454. #endif
  2455. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2456. }
  2457. } else {
  2458. struct scatterlist *sl;
  2459. cmdp->u.raw.sdata = 0xffffffff;
  2460. cmdp->u.raw.sg_ranz = sgcnt;
  2461. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2462. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2463. #ifdef GDTH_DMA_STATISTICS
  2464. ha->dma32_cnt++;
  2465. #endif
  2466. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2467. }
  2468. }
  2469. #ifdef GDTH_STATISTICS
  2470. if (max_sg < sgcnt) {
  2471. max_sg = sgcnt;
  2472. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2473. }
  2474. #endif
  2475. }
  2476. if (mode64) {
  2477. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2478. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2479. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2480. cmdp->u.raw64.sg_lst[0].sg_len));
  2481. /* evaluate command size */
  2482. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2483. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2484. } else {
  2485. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2486. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2487. cmdp->u.raw.sg_lst[0].sg_ptr,
  2488. cmdp->u.raw.sg_lst[0].sg_len));
  2489. /* evaluate command size */
  2490. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2491. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2492. }
  2493. }
  2494. /* check space */
  2495. if (ha->cmd_len & 3)
  2496. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2497. if (ha->cmd_cnt > 0) {
  2498. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2499. ha->ic_all_size) {
  2500. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2501. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2502. return 0;
  2503. }
  2504. }
  2505. /* copy command */
  2506. gdth_copy_command(ha);
  2507. return cmd_index;
  2508. }
  2509. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2510. {
  2511. register gdth_cmd_str *cmdp;
  2512. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2513. int cmd_index;
  2514. cmdp= ha->pccb;
  2515. TRACE2(("gdth_special_cmd(): "));
  2516. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2517. return 0;
  2518. *cmdp = *cmndinfo->internal_cmd_str;
  2519. cmdp->RequestBuffer = scp;
  2520. /* search free command index */
  2521. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2522. TRACE(("GDT: No free command index found\n"));
  2523. return 0;
  2524. }
  2525. /* if it's the first command, set command semaphore */
  2526. if (ha->cmd_cnt == 0)
  2527. gdth_set_sema0(ha);
  2528. /* evaluate command size, check space */
  2529. if (cmdp->OpCode == GDT_IOCTL) {
  2530. TRACE2(("IOCTL\n"));
  2531. ha->cmd_len =
  2532. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2533. } else if (cmdp->Service == CACHESERVICE) {
  2534. TRACE2(("cache command %d\n",cmdp->OpCode));
  2535. if (ha->cache_feat & GDT_64BIT)
  2536. ha->cmd_len =
  2537. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2538. else
  2539. ha->cmd_len =
  2540. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2541. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2542. TRACE2(("raw command %d\n",cmdp->OpCode));
  2543. if (ha->raw_feat & GDT_64BIT)
  2544. ha->cmd_len =
  2545. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2546. else
  2547. ha->cmd_len =
  2548. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2549. }
  2550. if (ha->cmd_len & 3)
  2551. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2552. if (ha->cmd_cnt > 0) {
  2553. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2554. ha->ic_all_size) {
  2555. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2556. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2557. return 0;
  2558. }
  2559. }
  2560. /* copy command */
  2561. gdth_copy_command(ha);
  2562. return cmd_index;
  2563. }
  2564. /* Controller event handling functions */
  2565. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2566. ushort idx, gdth_evt_data *evt)
  2567. {
  2568. gdth_evt_str *e;
  2569. struct timeval tv;
  2570. /* no GDTH_LOCK_HA() ! */
  2571. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2572. if (source == 0) /* no source -> no event */
  2573. return NULL;
  2574. if (ebuffer[elastidx].event_source == source &&
  2575. ebuffer[elastidx].event_idx == idx &&
  2576. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2577. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2578. (char *)&evt->eu, evt->size)) ||
  2579. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2580. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2581. (char *)&evt->event_string)))) {
  2582. e = &ebuffer[elastidx];
  2583. do_gettimeofday(&tv);
  2584. e->last_stamp = tv.tv_sec;
  2585. ++e->same_count;
  2586. } else {
  2587. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2588. ++elastidx;
  2589. if (elastidx == MAX_EVENTS)
  2590. elastidx = 0;
  2591. if (elastidx == eoldidx) { /* reached mark ? */
  2592. ++eoldidx;
  2593. if (eoldidx == MAX_EVENTS)
  2594. eoldidx = 0;
  2595. }
  2596. }
  2597. e = &ebuffer[elastidx];
  2598. e->event_source = source;
  2599. e->event_idx = idx;
  2600. do_gettimeofday(&tv);
  2601. e->first_stamp = e->last_stamp = tv.tv_sec;
  2602. e->same_count = 1;
  2603. e->event_data = *evt;
  2604. e->application = 0;
  2605. }
  2606. return e;
  2607. }
  2608. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2609. {
  2610. gdth_evt_str *e;
  2611. int eindex;
  2612. ulong flags;
  2613. TRACE2(("gdth_read_event() handle %d\n", handle));
  2614. spin_lock_irqsave(&ha->smp_lock, flags);
  2615. if (handle == -1)
  2616. eindex = eoldidx;
  2617. else
  2618. eindex = handle;
  2619. estr->event_source = 0;
  2620. if (eindex >= MAX_EVENTS) {
  2621. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2622. return eindex;
  2623. }
  2624. e = &ebuffer[eindex];
  2625. if (e->event_source != 0) {
  2626. if (eindex != elastidx) {
  2627. if (++eindex == MAX_EVENTS)
  2628. eindex = 0;
  2629. } else {
  2630. eindex = -1;
  2631. }
  2632. memcpy(estr, e, sizeof(gdth_evt_str));
  2633. }
  2634. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2635. return eindex;
  2636. }
  2637. static void gdth_readapp_event(gdth_ha_str *ha,
  2638. unchar application, gdth_evt_str *estr)
  2639. {
  2640. gdth_evt_str *e;
  2641. int eindex;
  2642. ulong flags;
  2643. unchar found = FALSE;
  2644. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2645. spin_lock_irqsave(&ha->smp_lock, flags);
  2646. eindex = eoldidx;
  2647. for (;;) {
  2648. e = &ebuffer[eindex];
  2649. if (e->event_source == 0)
  2650. break;
  2651. if ((e->application & application) == 0) {
  2652. e->application |= application;
  2653. found = TRUE;
  2654. break;
  2655. }
  2656. if (eindex == elastidx)
  2657. break;
  2658. if (++eindex == MAX_EVENTS)
  2659. eindex = 0;
  2660. }
  2661. if (found)
  2662. memcpy(estr, e, sizeof(gdth_evt_str));
  2663. else
  2664. estr->event_source = 0;
  2665. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2666. }
  2667. static void gdth_clear_events(void)
  2668. {
  2669. TRACE(("gdth_clear_events()"));
  2670. eoldidx = elastidx = 0;
  2671. ebuffer[0].event_source = 0;
  2672. }
  2673. /* SCSI interface functions */
  2674. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2675. int gdth_from_wait, int* pIndex)
  2676. {
  2677. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2678. gdt6_dpram_str __iomem *dp6_ptr;
  2679. gdt2_dpram_str __iomem *dp2_ptr;
  2680. Scsi_Cmnd *scp;
  2681. int rval, i;
  2682. unchar IStatus;
  2683. ushort Service;
  2684. ulong flags = 0;
  2685. #ifdef INT_COAL
  2686. int coalesced = FALSE;
  2687. int next = FALSE;
  2688. gdth_coal_status *pcs = NULL;
  2689. int act_int_coal = 0;
  2690. #endif
  2691. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2692. /* if polling and not from gdth_wait() -> return */
  2693. if (gdth_polling) {
  2694. if (!gdth_from_wait) {
  2695. return IRQ_HANDLED;
  2696. }
  2697. }
  2698. if (!gdth_polling)
  2699. spin_lock_irqsave(&ha->smp_lock, flags);
  2700. /* search controller */
  2701. IStatus = gdth_get_status(ha);
  2702. if (IStatus == 0) {
  2703. /* spurious interrupt */
  2704. if (!gdth_polling)
  2705. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2706. return IRQ_HANDLED;
  2707. }
  2708. #ifdef GDTH_STATISTICS
  2709. ++act_ints;
  2710. #endif
  2711. #ifdef INT_COAL
  2712. /* See if the fw is returning coalesced status */
  2713. if (IStatus == COALINDEX) {
  2714. /* Coalesced status. Setup the initial status
  2715. buffer pointer and flags */
  2716. pcs = ha->coal_stat;
  2717. coalesced = TRUE;
  2718. next = TRUE;
  2719. }
  2720. do {
  2721. if (coalesced) {
  2722. /* For coalesced requests all status
  2723. information is found in the status buffer */
  2724. IStatus = (unchar)(pcs->status & 0xff);
  2725. }
  2726. #endif
  2727. if (ha->type == GDT_EISA) {
  2728. if (IStatus & 0x80) { /* error flag */
  2729. IStatus &= ~0x80;
  2730. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2731. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2732. } else /* no error */
  2733. ha->status = S_OK;
  2734. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2735. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2736. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2737. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2738. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2739. } else if (ha->type == GDT_ISA) {
  2740. dp2_ptr = ha->brd;
  2741. if (IStatus & 0x80) { /* error flag */
  2742. IStatus &= ~0x80;
  2743. ha->status = readw(&dp2_ptr->u.ic.Status);
  2744. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2745. } else /* no error */
  2746. ha->status = S_OK;
  2747. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2748. ha->service = readw(&dp2_ptr->u.ic.Service);
  2749. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2750. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2751. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2752. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2753. } else if (ha->type == GDT_PCI) {
  2754. dp6_ptr = ha->brd;
  2755. if (IStatus & 0x80) { /* error flag */
  2756. IStatus &= ~0x80;
  2757. ha->status = readw(&dp6_ptr->u.ic.Status);
  2758. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2759. } else /* no error */
  2760. ha->status = S_OK;
  2761. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2762. ha->service = readw(&dp6_ptr->u.ic.Service);
  2763. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2764. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2765. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2766. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2767. } else if (ha->type == GDT_PCINEW) {
  2768. if (IStatus & 0x80) { /* error flag */
  2769. IStatus &= ~0x80;
  2770. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2771. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2772. } else
  2773. ha->status = S_OK;
  2774. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2775. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2776. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2777. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2778. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2779. } else if (ha->type == GDT_PCIMPR) {
  2780. dp6m_ptr = ha->brd;
  2781. if (IStatus & 0x80) { /* error flag */
  2782. IStatus &= ~0x80;
  2783. #ifdef INT_COAL
  2784. if (coalesced)
  2785. ha->status = pcs->ext_status & 0xffff;
  2786. else
  2787. #endif
  2788. ha->status = readw(&dp6m_ptr->i960r.status);
  2789. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2790. } else /* no error */
  2791. ha->status = S_OK;
  2792. #ifdef INT_COAL
  2793. /* get information */
  2794. if (coalesced) {
  2795. ha->info = pcs->info0;
  2796. ha->info2 = pcs->info1;
  2797. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2798. } else
  2799. #endif
  2800. {
  2801. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2802. ha->service = readw(&dp6m_ptr->i960r.service);
  2803. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2804. }
  2805. /* event string */
  2806. if (IStatus == ASYNCINDEX) {
  2807. if (ha->service != SCREENSERVICE &&
  2808. (ha->fw_vers & 0xff) >= 0x1a) {
  2809. ha->dvr.severity = readb
  2810. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2811. for (i = 0; i < 256; ++i) {
  2812. ha->dvr.event_string[i] = readb
  2813. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2814. if (ha->dvr.event_string[i] == 0)
  2815. break;
  2816. }
  2817. }
  2818. }
  2819. #ifdef INT_COAL
  2820. /* Make sure that non coalesced interrupts get cleared
  2821. before being handled by gdth_async_event/gdth_sync_event */
  2822. if (!coalesced)
  2823. #endif
  2824. {
  2825. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2826. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2827. }
  2828. } else {
  2829. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2830. if (!gdth_polling)
  2831. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2832. return IRQ_HANDLED;
  2833. }
  2834. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2835. IStatus,ha->status,ha->info));
  2836. if (gdth_from_wait) {
  2837. *pIndex = (int)IStatus;
  2838. }
  2839. if (IStatus == ASYNCINDEX) {
  2840. TRACE2(("gdth_interrupt() async. event\n"));
  2841. gdth_async_event(ha);
  2842. if (!gdth_polling)
  2843. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2844. gdth_next(ha);
  2845. return IRQ_HANDLED;
  2846. }
  2847. if (IStatus == SPEZINDEX) {
  2848. TRACE2(("Service unknown or not initialized !\n"));
  2849. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2850. ha->dvr.eu.driver.ionode = ha->hanum;
  2851. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2852. if (!gdth_polling)
  2853. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2854. return IRQ_HANDLED;
  2855. }
  2856. scp = ha->cmd_tab[IStatus-2].cmnd;
  2857. Service = ha->cmd_tab[IStatus-2].service;
  2858. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2859. if (scp == UNUSED_CMND) {
  2860. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2861. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2862. ha->dvr.eu.driver.ionode = ha->hanum;
  2863. ha->dvr.eu.driver.index = IStatus;
  2864. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2865. if (!gdth_polling)
  2866. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2867. return IRQ_HANDLED;
  2868. }
  2869. if (scp == INTERNAL_CMND) {
  2870. TRACE(("gdth_interrupt() answer to internal command\n"));
  2871. if (!gdth_polling)
  2872. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2873. return IRQ_HANDLED;
  2874. }
  2875. TRACE(("gdth_interrupt() sync. status\n"));
  2876. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2877. if (!gdth_polling)
  2878. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2879. if (rval == 2) {
  2880. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2881. } else if (rval == 1) {
  2882. gdth_scsi_done(scp);
  2883. }
  2884. #ifdef INT_COAL
  2885. if (coalesced) {
  2886. /* go to the next status in the status buffer */
  2887. ++pcs;
  2888. #ifdef GDTH_STATISTICS
  2889. ++act_int_coal;
  2890. if (act_int_coal > max_int_coal) {
  2891. max_int_coal = act_int_coal;
  2892. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2893. }
  2894. #endif
  2895. /* see if there is another status */
  2896. if (pcs->status == 0)
  2897. /* Stop the coalesce loop */
  2898. next = FALSE;
  2899. }
  2900. } while (next);
  2901. /* coalescing only for new GDT_PCIMPR controllers available */
  2902. if (ha->type == GDT_PCIMPR && coalesced) {
  2903. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2904. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2905. }
  2906. #endif
  2907. gdth_next(ha);
  2908. return IRQ_HANDLED;
  2909. }
  2910. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2911. {
  2912. gdth_ha_str *ha = dev_id;
  2913. return __gdth_interrupt(ha, false, NULL);
  2914. }
  2915. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2916. Scsi_Cmnd *scp)
  2917. {
  2918. gdth_msg_str *msg;
  2919. gdth_cmd_str *cmdp;
  2920. unchar b, t;
  2921. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2922. cmdp = ha->pccb;
  2923. TRACE(("gdth_sync_event() serv %d status %d\n",
  2924. service,ha->status));
  2925. if (service == SCREENSERVICE) {
  2926. msg = ha->pmsg;
  2927. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2928. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2929. if (msg->msg_len > MSGLEN+1)
  2930. msg->msg_len = MSGLEN+1;
  2931. if (msg->msg_len)
  2932. if (!(msg->msg_answer && msg->msg_ext)) {
  2933. msg->msg_text[msg->msg_len] = '\0';
  2934. printk("%s",msg->msg_text);
  2935. }
  2936. if (msg->msg_ext && !msg->msg_answer) {
  2937. while (gdth_test_busy(ha))
  2938. gdth_delay(0);
  2939. cmdp->Service = SCREENSERVICE;
  2940. cmdp->RequestBuffer = SCREEN_CMND;
  2941. gdth_get_cmd_index(ha);
  2942. gdth_set_sema0(ha);
  2943. cmdp->OpCode = GDT_READ;
  2944. cmdp->BoardNode = LOCALBOARD;
  2945. cmdp->u.screen.reserved = 0;
  2946. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2947. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2948. ha->cmd_offs_dpmem = 0;
  2949. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2950. + sizeof(ulong64);
  2951. ha->cmd_cnt = 0;
  2952. gdth_copy_command(ha);
  2953. gdth_release_event(ha);
  2954. return 0;
  2955. }
  2956. if (msg->msg_answer && msg->msg_alen) {
  2957. /* default answers (getchar() not possible) */
  2958. if (msg->msg_alen == 1) {
  2959. msg->msg_alen = 0;
  2960. msg->msg_len = 1;
  2961. msg->msg_text[0] = 0;
  2962. } else {
  2963. msg->msg_alen -= 2;
  2964. msg->msg_len = 2;
  2965. msg->msg_text[0] = 1;
  2966. msg->msg_text[1] = 0;
  2967. }
  2968. msg->msg_ext = 0;
  2969. msg->msg_answer = 0;
  2970. while (gdth_test_busy(ha))
  2971. gdth_delay(0);
  2972. cmdp->Service = SCREENSERVICE;
  2973. cmdp->RequestBuffer = SCREEN_CMND;
  2974. gdth_get_cmd_index(ha);
  2975. gdth_set_sema0(ha);
  2976. cmdp->OpCode = GDT_WRITE;
  2977. cmdp->BoardNode = LOCALBOARD;
  2978. cmdp->u.screen.reserved = 0;
  2979. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2980. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2981. ha->cmd_offs_dpmem = 0;
  2982. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2983. + sizeof(ulong64);
  2984. ha->cmd_cnt = 0;
  2985. gdth_copy_command(ha);
  2986. gdth_release_event(ha);
  2987. return 0;
  2988. }
  2989. printk("\n");
  2990. } else {
  2991. b = scp->device->channel;
  2992. t = scp->device->id;
  2993. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2994. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2995. }
  2996. /* cache or raw service */
  2997. if (ha->status == S_BSY) {
  2998. TRACE2(("Controller busy -> retry !\n"));
  2999. if (cmndinfo->OpCode == GDT_MOUNT)
  3000. cmndinfo->OpCode = GDT_CLUST_INFO;
  3001. /* retry */
  3002. return 2;
  3003. }
  3004. if (scsi_bufflen(scp))
  3005. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  3006. cmndinfo->dma_dir);
  3007. if (cmndinfo->sense_paddr)
  3008. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3009. PCI_DMA_FROMDEVICE);
  3010. if (ha->status == S_OK) {
  3011. cmndinfo->status = S_OK;
  3012. cmndinfo->info = ha->info;
  3013. if (cmndinfo->OpCode != -1) {
  3014. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3015. cmndinfo->OpCode));
  3016. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3017. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3018. ha->hdr[t].cluster_type = (unchar)ha->info;
  3019. if (!(ha->hdr[t].cluster_type &
  3020. CLUSTER_MOUNTED)) {
  3021. /* NOT MOUNTED -> MOUNT */
  3022. cmndinfo->OpCode = GDT_MOUNT;
  3023. if (ha->hdr[t].cluster_type &
  3024. CLUSTER_RESERVED) {
  3025. /* cluster drive RESERVED (on the other node) */
  3026. cmndinfo->phase = -2; /* reservation conflict */
  3027. }
  3028. } else {
  3029. cmndinfo->OpCode = -1;
  3030. }
  3031. } else {
  3032. if (cmndinfo->OpCode == GDT_MOUNT) {
  3033. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3034. ha->hdr[t].media_changed = TRUE;
  3035. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3036. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3037. ha->hdr[t].media_changed = TRUE;
  3038. }
  3039. cmndinfo->OpCode = -1;
  3040. }
  3041. /* retry */
  3042. cmndinfo->priority = HIGH_PRI;
  3043. return 2;
  3044. } else {
  3045. /* RESERVE/RELEASE ? */
  3046. if (scp->cmnd[0] == RESERVE) {
  3047. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3048. } else if (scp->cmnd[0] == RELEASE) {
  3049. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3050. }
  3051. scp->result = DID_OK << 16;
  3052. scp->sense_buffer[0] = 0;
  3053. }
  3054. } else {
  3055. cmndinfo->status = ha->status;
  3056. cmndinfo->info = ha->info;
  3057. if (cmndinfo->OpCode != -1) {
  3058. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3059. cmndinfo->OpCode, ha->status));
  3060. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3061. cmndinfo->OpCode == GDT_SCAN_END) {
  3062. cmndinfo->OpCode = -1;
  3063. /* retry */
  3064. cmndinfo->priority = HIGH_PRI;
  3065. return 2;
  3066. }
  3067. memset((char*)scp->sense_buffer,0,16);
  3068. scp->sense_buffer[0] = 0x70;
  3069. scp->sense_buffer[2] = NOT_READY;
  3070. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3071. } else if (service == CACHESERVICE) {
  3072. if (ha->status == S_CACHE_UNKNOWN &&
  3073. (ha->hdr[t].cluster_type &
  3074. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3075. /* bus reset -> force GDT_CLUST_INFO */
  3076. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3077. }
  3078. memset((char*)scp->sense_buffer,0,16);
  3079. if (ha->status == (ushort)S_CACHE_RESERV) {
  3080. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3081. } else {
  3082. scp->sense_buffer[0] = 0x70;
  3083. scp->sense_buffer[2] = NOT_READY;
  3084. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3085. }
  3086. if (!cmndinfo->internal_command) {
  3087. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3088. ha->dvr.eu.sync.ionode = ha->hanum;
  3089. ha->dvr.eu.sync.service = service;
  3090. ha->dvr.eu.sync.status = ha->status;
  3091. ha->dvr.eu.sync.info = ha->info;
  3092. ha->dvr.eu.sync.hostdrive = t;
  3093. if (ha->status >= 0x8000)
  3094. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3095. else
  3096. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3097. }
  3098. } else {
  3099. /* sense buffer filled from controller firmware (DMA) */
  3100. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3101. scp->result = DID_BAD_TARGET << 16;
  3102. } else {
  3103. scp->result = (DID_OK << 16) | ha->info;
  3104. }
  3105. }
  3106. }
  3107. if (!cmndinfo->wait_for_completion)
  3108. cmndinfo->wait_for_completion++;
  3109. else
  3110. return 1;
  3111. }
  3112. return 0;
  3113. }
  3114. static char *async_cache_tab[] = {
  3115. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3116. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3117. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3118. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3119. /* 2*/ "\005\000\002\006\004"
  3120. "GDT HA %u, Host Drive %lu not ready",
  3121. /* 3*/ "\005\000\002\006\004"
  3122. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3123. /* 4*/ "\005\000\002\006\004"
  3124. "GDT HA %u, mirror update on Host Drive %lu failed",
  3125. /* 5*/ "\005\000\002\006\004"
  3126. "GDT HA %u, Mirror Drive %lu failed",
  3127. /* 6*/ "\005\000\002\006\004"
  3128. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3129. /* 7*/ "\005\000\002\006\004"
  3130. "GDT HA %u, Host Drive %lu write protected",
  3131. /* 8*/ "\005\000\002\006\004"
  3132. "GDT HA %u, media changed in Host Drive %lu",
  3133. /* 9*/ "\005\000\002\006\004"
  3134. "GDT HA %u, Host Drive %lu is offline",
  3135. /*10*/ "\005\000\002\006\004"
  3136. "GDT HA %u, media change of Mirror Drive %lu",
  3137. /*11*/ "\005\000\002\006\004"
  3138. "GDT HA %u, Mirror Drive %lu is write protected",
  3139. /*12*/ "\005\000\002\006\004"
  3140. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3141. /*13*/ "\007\000\002\006\002\010\002"
  3142. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3143. /*14*/ "\005\000\002\006\002"
  3144. "GDT HA %u, Array Drive %u: FAIL state entered",
  3145. /*15*/ "\005\000\002\006\002"
  3146. "GDT HA %u, Array Drive %u: error",
  3147. /*16*/ "\007\000\002\006\002\010\002"
  3148. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3149. /*17*/ "\005\000\002\006\002"
  3150. "GDT HA %u, Array Drive %u: parity build failed",
  3151. /*18*/ "\005\000\002\006\002"
  3152. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3153. /*19*/ "\005\000\002\010\002"
  3154. "GDT HA %u, Test of Hot Fix %u failed",
  3155. /*20*/ "\005\000\002\006\002"
  3156. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3157. /*21*/ "\005\000\002\006\002"
  3158. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3159. /*22*/ "\007\000\002\006\002\010\002"
  3160. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3161. /*23*/ "\005\000\002\006\002"
  3162. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3163. /*24*/ "\005\000\002\010\002"
  3164. "GDT HA %u, mirror update on Cache Drive %u completed",
  3165. /*25*/ "\005\000\002\010\002"
  3166. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3167. /*26*/ "\005\000\002\006\002"
  3168. "GDT HA %u, Array Drive %u: drive rebuild started",
  3169. /*27*/ "\005\000\002\012\001"
  3170. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3171. /*28*/ "\005\000\002\012\001"
  3172. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3173. /*29*/ "\007\000\002\012\001\013\001"
  3174. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3175. /*30*/ "\007\000\002\012\001\013\001"
  3176. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3177. /*31*/ "\007\000\002\012\001\013\001"
  3178. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3179. /*32*/ "\007\000\002\012\001\013\001"
  3180. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3181. /*33*/ "\007\000\002\012\001\013\001"
  3182. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3183. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3184. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3185. /*35*/ "\007\000\002\012\001\013\001"
  3186. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3187. /*36*/ "\007\000\002\012\001\013\001"
  3188. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3189. /*37*/ "\007\000\002\012\001\006\004"
  3190. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3191. /*38*/ "\007\000\002\012\001\013\001"
  3192. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3193. /*39*/ "\007\000\002\012\001\013\001"
  3194. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3195. /*40*/ "\007\000\002\012\001\013\001"
  3196. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3197. /*41*/ "\007\000\002\012\001\013\001"
  3198. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3199. /*42*/ "\005\000\002\006\002"
  3200. "GDT HA %u, Array Drive %u: drive build started",
  3201. /*43*/ "\003\000\002"
  3202. "GDT HA %u, DRAM parity error detected",
  3203. /*44*/ "\005\000\002\006\002"
  3204. "GDT HA %u, Mirror Drive %u: update started",
  3205. /*45*/ "\007\000\002\006\002\010\002"
  3206. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3207. /*46*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3209. /*47*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3211. /*48*/ "\005\000\002\006\002"
  3212. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3213. /*49*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3215. /*50*/ "\007\000\002\012\001\013\001"
  3216. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3217. /*51*/ "\005\000\002\006\002"
  3218. "GDT HA %u, Array Drive %u: expand started",
  3219. /*52*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Array Drive %u: expand finished successfully",
  3221. /*53*/ "\005\000\002\006\002"
  3222. "GDT HA %u, Array Drive %u: expand failed",
  3223. /*54*/ "\003\000\002"
  3224. "GDT HA %u, CPU temperature critical",
  3225. /*55*/ "\003\000\002"
  3226. "GDT HA %u, CPU temperature OK",
  3227. /*56*/ "\005\000\002\006\004"
  3228. "GDT HA %u, Host drive %lu created",
  3229. /*57*/ "\005\000\002\006\002"
  3230. "GDT HA %u, Array Drive %u: expand restarted",
  3231. /*58*/ "\005\000\002\006\002"
  3232. "GDT HA %u, Array Drive %u: expand stopped",
  3233. /*59*/ "\005\000\002\010\002"
  3234. "GDT HA %u, Mirror Drive %u: drive build quited",
  3235. /*60*/ "\005\000\002\006\002"
  3236. "GDT HA %u, Array Drive %u: parity build quited",
  3237. /*61*/ "\005\000\002\006\002"
  3238. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3239. /*62*/ "\005\000\002\006\002"
  3240. "GDT HA %u, Array Drive %u: parity verify started",
  3241. /*63*/ "\005\000\002\006\002"
  3242. "GDT HA %u, Array Drive %u: parity verify done",
  3243. /*64*/ "\005\000\002\006\002"
  3244. "GDT HA %u, Array Drive %u: parity verify failed",
  3245. /*65*/ "\005\000\002\006\002"
  3246. "GDT HA %u, Array Drive %u: parity error detected",
  3247. /*66*/ "\005\000\002\006\002"
  3248. "GDT HA %u, Array Drive %u: parity verify quited",
  3249. /*67*/ "\005\000\002\006\002"
  3250. "GDT HA %u, Host Drive %u reserved",
  3251. /*68*/ "\005\000\002\006\002"
  3252. "GDT HA %u, Host Drive %u mounted and released",
  3253. /*69*/ "\005\000\002\006\002"
  3254. "GDT HA %u, Host Drive %u released",
  3255. /*70*/ "\003\000\002"
  3256. "GDT HA %u, DRAM error detected and corrected with ECC",
  3257. /*71*/ "\003\000\002"
  3258. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3259. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3260. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3261. /*73*/ "\005\000\002\006\002"
  3262. "GDT HA %u, Host drive %u resetted locally",
  3263. /*74*/ "\005\000\002\006\002"
  3264. "GDT HA %u, Host drive %u resetted remotely",
  3265. /*75*/ "\003\000\002"
  3266. "GDT HA %u, async. status 75 unknown",
  3267. };
  3268. static int gdth_async_event(gdth_ha_str *ha)
  3269. {
  3270. gdth_cmd_str *cmdp;
  3271. int cmd_index;
  3272. cmdp= ha->pccb;
  3273. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3274. ha->hanum, ha->service));
  3275. if (ha->service == SCREENSERVICE) {
  3276. if (ha->status == MSG_REQUEST) {
  3277. while (gdth_test_busy(ha))
  3278. gdth_delay(0);
  3279. cmdp->Service = SCREENSERVICE;
  3280. cmdp->RequestBuffer = SCREEN_CMND;
  3281. cmd_index = gdth_get_cmd_index(ha);
  3282. gdth_set_sema0(ha);
  3283. cmdp->OpCode = GDT_READ;
  3284. cmdp->BoardNode = LOCALBOARD;
  3285. cmdp->u.screen.reserved = 0;
  3286. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3287. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3288. ha->cmd_offs_dpmem = 0;
  3289. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3290. + sizeof(ulong64);
  3291. ha->cmd_cnt = 0;
  3292. gdth_copy_command(ha);
  3293. if (ha->type == GDT_EISA)
  3294. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3295. else if (ha->type == GDT_ISA)
  3296. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3297. else
  3298. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3299. (ushort)((ha->brd_phys>>3)&0x1f));
  3300. gdth_release_event(ha);
  3301. }
  3302. } else {
  3303. if (ha->type == GDT_PCIMPR &&
  3304. (ha->fw_vers & 0xff) >= 0x1a) {
  3305. ha->dvr.size = 0;
  3306. ha->dvr.eu.async.ionode = ha->hanum;
  3307. ha->dvr.eu.async.status = ha->status;
  3308. /* severity and event_string already set! */
  3309. } else {
  3310. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3311. ha->dvr.eu.async.ionode = ha->hanum;
  3312. ha->dvr.eu.async.service = ha->service;
  3313. ha->dvr.eu.async.status = ha->status;
  3314. ha->dvr.eu.async.info = ha->info;
  3315. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3316. }
  3317. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3318. gdth_log_event( &ha->dvr, NULL );
  3319. /* new host drive from expand? */
  3320. if (ha->service == CACHESERVICE && ha->status == 56) {
  3321. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3322. (ushort)ha->info));
  3323. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3324. }
  3325. }
  3326. return 1;
  3327. }
  3328. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3329. {
  3330. gdth_stackframe stack;
  3331. char *f = NULL;
  3332. int i,j;
  3333. TRACE2(("gdth_log_event()\n"));
  3334. if (dvr->size == 0) {
  3335. if (buffer == NULL) {
  3336. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3337. } else {
  3338. sprintf(buffer,"Adapter %d: %s\n",
  3339. dvr->eu.async.ionode,dvr->event_string);
  3340. }
  3341. } else if (dvr->eu.async.service == CACHESERVICE &&
  3342. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3343. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3344. dvr->eu.async.status));
  3345. f = async_cache_tab[dvr->eu.async.status];
  3346. /* i: parameter to push, j: stack element to fill */
  3347. for (j=0,i=1; i < f[0]; i+=2) {
  3348. switch (f[i+1]) {
  3349. case 4:
  3350. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3351. break;
  3352. case 2:
  3353. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3354. break;
  3355. case 1:
  3356. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3357. break;
  3358. default:
  3359. break;
  3360. }
  3361. }
  3362. if (buffer == NULL) {
  3363. printk(&f[(int)f[0]],stack);
  3364. printk("\n");
  3365. } else {
  3366. sprintf(buffer,&f[(int)f[0]],stack);
  3367. }
  3368. } else {
  3369. if (buffer == NULL) {
  3370. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3371. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3372. } else {
  3373. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3374. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3375. }
  3376. }
  3377. }
  3378. #ifdef GDTH_STATISTICS
  3379. static unchar gdth_timer_running;
  3380. static void gdth_timeout(ulong data)
  3381. {
  3382. ulong32 i;
  3383. Scsi_Cmnd *nscp;
  3384. gdth_ha_str *ha;
  3385. ulong flags;
  3386. if(unlikely(list_empty(&gdth_instances))) {
  3387. gdth_timer_running = 0;
  3388. return;
  3389. }
  3390. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3391. spin_lock_irqsave(&ha->smp_lock, flags);
  3392. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3393. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3394. ++act_stats;
  3395. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3396. ++act_rq;
  3397. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3398. act_ints, act_ios, act_stats, act_rq));
  3399. act_ints = act_ios = 0;
  3400. gdth_timer.expires = jiffies + 30 * HZ;
  3401. add_timer(&gdth_timer);
  3402. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3403. }
  3404. static void gdth_timer_init(void)
  3405. {
  3406. if (gdth_timer_running)
  3407. return;
  3408. gdth_timer_running = 1;
  3409. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3410. gdth_timer.expires = jiffies + HZ;
  3411. gdth_timer.data = 0L;
  3412. gdth_timer.function = gdth_timeout;
  3413. add_timer(&gdth_timer);
  3414. }
  3415. #else
  3416. static inline void gdth_timer_init(void)
  3417. {
  3418. }
  3419. #endif
  3420. static void __init internal_setup(char *str,int *ints)
  3421. {
  3422. int i, argc;
  3423. char *cur_str, *argv;
  3424. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3425. str ? str:"NULL", ints ? ints[0]:0));
  3426. /* read irq[] from ints[] */
  3427. if (ints) {
  3428. argc = ints[0];
  3429. if (argc > 0) {
  3430. if (argc > MAXHA)
  3431. argc = MAXHA;
  3432. for (i = 0; i < argc; ++i)
  3433. irq[i] = ints[i+1];
  3434. }
  3435. }
  3436. /* analyse string */
  3437. argv = str;
  3438. while (argv && (cur_str = strchr(argv, ':'))) {
  3439. int val = 0, c = *++cur_str;
  3440. if (c == 'n' || c == 'N')
  3441. val = 0;
  3442. else if (c == 'y' || c == 'Y')
  3443. val = 1;
  3444. else
  3445. val = (int)simple_strtoul(cur_str, NULL, 0);
  3446. if (!strncmp(argv, "disable:", 8))
  3447. disable = val;
  3448. else if (!strncmp(argv, "reserve_mode:", 13))
  3449. reserve_mode = val;
  3450. else if (!strncmp(argv, "reverse_scan:", 13))
  3451. reverse_scan = val;
  3452. else if (!strncmp(argv, "hdr_channel:", 12))
  3453. hdr_channel = val;
  3454. else if (!strncmp(argv, "max_ids:", 8))
  3455. max_ids = val;
  3456. else if (!strncmp(argv, "rescan:", 7))
  3457. rescan = val;
  3458. else if (!strncmp(argv, "shared_access:", 14))
  3459. shared_access = val;
  3460. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3461. probe_eisa_isa = val;
  3462. else if (!strncmp(argv, "reserve_list:", 13)) {
  3463. reserve_list[0] = val;
  3464. for (i = 1; i < MAX_RES_ARGS; i++) {
  3465. cur_str = strchr(cur_str, ',');
  3466. if (!cur_str)
  3467. break;
  3468. if (!isdigit((int)*++cur_str)) {
  3469. --cur_str;
  3470. break;
  3471. }
  3472. reserve_list[i] =
  3473. (int)simple_strtoul(cur_str, NULL, 0);
  3474. }
  3475. if (!cur_str)
  3476. break;
  3477. argv = ++cur_str;
  3478. continue;
  3479. }
  3480. if ((argv = strchr(argv, ',')))
  3481. ++argv;
  3482. }
  3483. }
  3484. int __init option_setup(char *str)
  3485. {
  3486. int ints[MAXHA];
  3487. char *cur = str;
  3488. int i = 1;
  3489. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3490. while (cur && isdigit(*cur) && i <= MAXHA) {
  3491. ints[i++] = simple_strtoul(cur, NULL, 0);
  3492. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3493. }
  3494. ints[0] = i - 1;
  3495. internal_setup(cur, ints);
  3496. return 1;
  3497. }
  3498. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3499. {
  3500. TRACE2(("gdth_ctr_name()\n"));
  3501. if (ha->type == GDT_EISA) {
  3502. switch (ha->stype) {
  3503. case GDT3_ID:
  3504. return("GDT3000/3020");
  3505. case GDT3A_ID:
  3506. return("GDT3000A/3020A/3050A");
  3507. case GDT3B_ID:
  3508. return("GDT3000B/3010A");
  3509. }
  3510. } else if (ha->type == GDT_ISA) {
  3511. return("GDT2000/2020");
  3512. } else if (ha->type == GDT_PCI) {
  3513. switch (ha->pdev->device) {
  3514. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3515. return("GDT6000/6020/6050");
  3516. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3517. return("GDT6000B/6010");
  3518. }
  3519. }
  3520. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3521. return("");
  3522. }
  3523. static const char *gdth_info(struct Scsi_Host *shp)
  3524. {
  3525. gdth_ha_str *ha = shost_priv(shp);
  3526. TRACE2(("gdth_info()\n"));
  3527. return ((const char *)ha->binfo.type_string);
  3528. }
  3529. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3530. {
  3531. gdth_ha_str *ha = shost_priv(scp->device->host);
  3532. int i;
  3533. ulong flags;
  3534. Scsi_Cmnd *cmnd;
  3535. unchar b;
  3536. TRACE2(("gdth_eh_bus_reset()\n"));
  3537. b = scp->device->channel;
  3538. /* clear command tab */
  3539. spin_lock_irqsave(&ha->smp_lock, flags);
  3540. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3541. cmnd = ha->cmd_tab[i].cmnd;
  3542. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3543. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3544. }
  3545. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3546. if (b == ha->virt_bus) {
  3547. /* host drives */
  3548. for (i = 0; i < MAX_HDRIVES; ++i) {
  3549. if (ha->hdr[i].present) {
  3550. spin_lock_irqsave(&ha->smp_lock, flags);
  3551. gdth_polling = TRUE;
  3552. while (gdth_test_busy(ha))
  3553. gdth_delay(0);
  3554. if (gdth_internal_cmd(ha, CACHESERVICE,
  3555. GDT_CLUST_RESET, i, 0, 0))
  3556. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3557. gdth_polling = FALSE;
  3558. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3559. }
  3560. }
  3561. } else {
  3562. /* raw devices */
  3563. spin_lock_irqsave(&ha->smp_lock, flags);
  3564. for (i = 0; i < MAXID; ++i)
  3565. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3566. gdth_polling = TRUE;
  3567. while (gdth_test_busy(ha))
  3568. gdth_delay(0);
  3569. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3570. BUS_L2P(ha,b), 0, 0);
  3571. gdth_polling = FALSE;
  3572. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3573. }
  3574. return SUCCESS;
  3575. }
  3576. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3577. {
  3578. unchar b, t;
  3579. gdth_ha_str *ha = shost_priv(sdev->host);
  3580. struct scsi_device *sd;
  3581. unsigned capacity;
  3582. sd = sdev;
  3583. capacity = cap;
  3584. b = sd->channel;
  3585. t = sd->id;
  3586. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3587. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3588. /* raw device or host drive without mapping information */
  3589. TRACE2(("Evaluate mapping\n"));
  3590. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3591. } else {
  3592. ip[0] = ha->hdr[t].heads;
  3593. ip[1] = ha->hdr[t].secs;
  3594. ip[2] = capacity / ip[0] / ip[1];
  3595. }
  3596. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3597. ip[0],ip[1],ip[2]));
  3598. return 0;
  3599. }
  3600. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3601. void (*done)(struct scsi_cmnd *))
  3602. {
  3603. gdth_ha_str *ha = shost_priv(scp->device->host);
  3604. struct gdth_cmndinfo *cmndinfo;
  3605. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3606. cmndinfo = gdth_get_cmndinfo(ha);
  3607. BUG_ON(!cmndinfo);
  3608. scp->scsi_done = done;
  3609. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3610. cmndinfo->priority = DEFAULT_PRI;
  3611. return __gdth_queuecommand(ha, scp, cmndinfo);
  3612. }
  3613. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3614. struct gdth_cmndinfo *cmndinfo)
  3615. {
  3616. scp->host_scribble = (unsigned char *)cmndinfo;
  3617. cmndinfo->wait_for_completion = 1;
  3618. cmndinfo->phase = -1;
  3619. cmndinfo->OpCode = -1;
  3620. #ifdef GDTH_STATISTICS
  3621. ++act_ios;
  3622. #endif
  3623. gdth_putq(ha, scp, cmndinfo->priority);
  3624. gdth_next(ha);
  3625. return 0;
  3626. }
  3627. static int gdth_open(struct inode *inode, struct file *filep)
  3628. {
  3629. gdth_ha_str *ha;
  3630. list_for_each_entry(ha, &gdth_instances, list) {
  3631. if (!ha->sdev)
  3632. ha->sdev = scsi_get_host_dev(ha->shost);
  3633. }
  3634. TRACE(("gdth_open()\n"));
  3635. return 0;
  3636. }
  3637. static int gdth_close(struct inode *inode, struct file *filep)
  3638. {
  3639. TRACE(("gdth_close()\n"));
  3640. return 0;
  3641. }
  3642. static int ioc_event(void __user *arg)
  3643. {
  3644. gdth_ioctl_event evt;
  3645. gdth_ha_str *ha;
  3646. ulong flags;
  3647. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3648. return -EFAULT;
  3649. ha = gdth_find_ha(evt.ionode);
  3650. if (!ha)
  3651. return -EFAULT;
  3652. if (evt.erase == 0xff) {
  3653. if (evt.event.event_source == ES_TEST)
  3654. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3655. else if (evt.event.event_source == ES_DRIVER)
  3656. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3657. else if (evt.event.event_source == ES_SYNC)
  3658. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3659. else
  3660. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3661. spin_lock_irqsave(&ha->smp_lock, flags);
  3662. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3663. &evt.event.event_data);
  3664. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3665. } else if (evt.erase == 0xfe) {
  3666. gdth_clear_events();
  3667. } else if (evt.erase == 0) {
  3668. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3669. } else {
  3670. gdth_readapp_event(ha, evt.erase, &evt.event);
  3671. }
  3672. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3673. return -EFAULT;
  3674. return 0;
  3675. }
  3676. static int ioc_lockdrv(void __user *arg)
  3677. {
  3678. gdth_ioctl_lockdrv ldrv;
  3679. unchar i, j;
  3680. ulong flags;
  3681. gdth_ha_str *ha;
  3682. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3683. return -EFAULT;
  3684. ha = gdth_find_ha(ldrv.ionode);
  3685. if (!ha)
  3686. return -EFAULT;
  3687. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3688. j = ldrv.drives[i];
  3689. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3690. continue;
  3691. if (ldrv.lock) {
  3692. spin_lock_irqsave(&ha->smp_lock, flags);
  3693. ha->hdr[j].lock = 1;
  3694. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3695. gdth_wait_completion(ha, ha->bus_cnt, j);
  3696. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3697. } else {
  3698. spin_lock_irqsave(&ha->smp_lock, flags);
  3699. ha->hdr[j].lock = 0;
  3700. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3701. gdth_start_timeout(ha, ha->bus_cnt, j);
  3702. gdth_next(ha);
  3703. }
  3704. }
  3705. return 0;
  3706. }
  3707. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3708. {
  3709. gdth_ioctl_reset res;
  3710. gdth_cmd_str cmd;
  3711. gdth_ha_str *ha;
  3712. int rval;
  3713. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3714. res.number >= MAX_HDRIVES)
  3715. return -EFAULT;
  3716. ha = gdth_find_ha(res.ionode);
  3717. if (!ha)
  3718. return -EFAULT;
  3719. if (!ha->hdr[res.number].present)
  3720. return 0;
  3721. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3722. cmd.Service = CACHESERVICE;
  3723. cmd.OpCode = GDT_CLUST_RESET;
  3724. if (ha->cache_feat & GDT_64BIT)
  3725. cmd.u.cache64.DeviceNo = res.number;
  3726. else
  3727. cmd.u.cache.DeviceNo = res.number;
  3728. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3729. if (rval < 0)
  3730. return rval;
  3731. res.status = rval;
  3732. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3733. return -EFAULT;
  3734. return 0;
  3735. }
  3736. static int ioc_general(void __user *arg, char *cmnd)
  3737. {
  3738. gdth_ioctl_general gen;
  3739. char *buf = NULL;
  3740. ulong64 paddr;
  3741. gdth_ha_str *ha;
  3742. int rval;
  3743. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3744. return -EFAULT;
  3745. ha = gdth_find_ha(gen.ionode);
  3746. if (!ha)
  3747. return -EFAULT;
  3748. if (gen.data_len + gen.sense_len != 0) {
  3749. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3750. FALSE, &paddr)))
  3751. return -EFAULT;
  3752. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3753. gen.data_len + gen.sense_len)) {
  3754. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3755. return -EFAULT;
  3756. }
  3757. if (gen.command.OpCode == GDT_IOCTL) {
  3758. gen.command.u.ioctl.p_param = paddr;
  3759. } else if (gen.command.Service == CACHESERVICE) {
  3760. if (ha->cache_feat & GDT_64BIT) {
  3761. /* copy elements from 32-bit IOCTL structure */
  3762. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3763. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3764. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3765. /* addresses */
  3766. if (ha->cache_feat & SCATTER_GATHER) {
  3767. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3768. gen.command.u.cache64.sg_canz = 1;
  3769. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3770. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3771. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3772. } else {
  3773. gen.command.u.cache64.DestAddr = paddr;
  3774. gen.command.u.cache64.sg_canz = 0;
  3775. }
  3776. } else {
  3777. if (ha->cache_feat & SCATTER_GATHER) {
  3778. gen.command.u.cache.DestAddr = 0xffffffff;
  3779. gen.command.u.cache.sg_canz = 1;
  3780. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3781. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3782. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3783. } else {
  3784. gen.command.u.cache.DestAddr = paddr;
  3785. gen.command.u.cache.sg_canz = 0;
  3786. }
  3787. }
  3788. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3789. if (ha->raw_feat & GDT_64BIT) {
  3790. /* copy elements from 32-bit IOCTL structure */
  3791. char cmd[16];
  3792. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3793. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3794. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3795. gen.command.u.raw64.target = gen.command.u.raw.target;
  3796. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3797. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3798. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3799. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3800. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3801. /* addresses */
  3802. if (ha->raw_feat & SCATTER_GATHER) {
  3803. gen.command.u.raw64.sdata = (ulong64)-1;
  3804. gen.command.u.raw64.sg_ranz = 1;
  3805. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3806. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3807. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3808. } else {
  3809. gen.command.u.raw64.sdata = paddr;
  3810. gen.command.u.raw64.sg_ranz = 0;
  3811. }
  3812. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3813. } else {
  3814. if (ha->raw_feat & SCATTER_GATHER) {
  3815. gen.command.u.raw.sdata = 0xffffffff;
  3816. gen.command.u.raw.sg_ranz = 1;
  3817. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3818. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3819. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3820. } else {
  3821. gen.command.u.raw.sdata = paddr;
  3822. gen.command.u.raw.sg_ranz = 0;
  3823. }
  3824. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3825. }
  3826. } else {
  3827. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3828. return -EFAULT;
  3829. }
  3830. }
  3831. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3832. if (rval < 0)
  3833. return rval;
  3834. gen.status = rval;
  3835. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3836. gen.data_len + gen.sense_len)) {
  3837. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3838. return -EFAULT;
  3839. }
  3840. if (copy_to_user(arg, &gen,
  3841. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3842. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3843. return -EFAULT;
  3844. }
  3845. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3846. return 0;
  3847. }
  3848. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3849. {
  3850. gdth_ioctl_rescan *rsc;
  3851. gdth_cmd_str *cmd;
  3852. gdth_ha_str *ha;
  3853. unchar i;
  3854. int rc = -ENOMEM;
  3855. u32 cluster_type = 0;
  3856. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3857. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3858. if (!rsc || !cmd)
  3859. goto free_fail;
  3860. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3861. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3862. rc = -EFAULT;
  3863. goto free_fail;
  3864. }
  3865. memset(cmd, 0, sizeof(gdth_cmd_str));
  3866. for (i = 0; i < MAX_HDRIVES; ++i) {
  3867. if (!ha->hdr[i].present) {
  3868. rsc->hdr_list[i].bus = 0xff;
  3869. continue;
  3870. }
  3871. rsc->hdr_list[i].bus = ha->virt_bus;
  3872. rsc->hdr_list[i].target = i;
  3873. rsc->hdr_list[i].lun = 0;
  3874. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3875. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3876. cmd->Service = CACHESERVICE;
  3877. cmd->OpCode = GDT_CLUST_INFO;
  3878. if (ha->cache_feat & GDT_64BIT)
  3879. cmd->u.cache64.DeviceNo = i;
  3880. else
  3881. cmd->u.cache.DeviceNo = i;
  3882. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3883. rsc->hdr_list[i].cluster_type = cluster_type;
  3884. }
  3885. }
  3886. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3887. rc = -EFAULT;
  3888. else
  3889. rc = 0;
  3890. free_fail:
  3891. kfree(rsc);
  3892. kfree(cmd);
  3893. return rc;
  3894. }
  3895. static int ioc_rescan(void __user *arg, char *cmnd)
  3896. {
  3897. gdth_ioctl_rescan *rsc;
  3898. gdth_cmd_str *cmd;
  3899. ushort i, status, hdr_cnt;
  3900. ulong32 info;
  3901. int cyls, hds, secs;
  3902. int rc = -ENOMEM;
  3903. ulong flags;
  3904. gdth_ha_str *ha;
  3905. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3906. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3907. if (!cmd || !rsc)
  3908. goto free_fail;
  3909. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3910. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3911. rc = -EFAULT;
  3912. goto free_fail;
  3913. }
  3914. memset(cmd, 0, sizeof(gdth_cmd_str));
  3915. if (rsc->flag == 0) {
  3916. /* old method: re-init. cache service */
  3917. cmd->Service = CACHESERVICE;
  3918. if (ha->cache_feat & GDT_64BIT) {
  3919. cmd->OpCode = GDT_X_INIT_HOST;
  3920. cmd->u.cache64.DeviceNo = LINUX_OS;
  3921. } else {
  3922. cmd->OpCode = GDT_INIT;
  3923. cmd->u.cache.DeviceNo = LINUX_OS;
  3924. }
  3925. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3926. i = 0;
  3927. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3928. } else {
  3929. i = rsc->hdr_no;
  3930. hdr_cnt = i + 1;
  3931. }
  3932. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3933. cmd->Service = CACHESERVICE;
  3934. cmd->OpCode = GDT_INFO;
  3935. if (ha->cache_feat & GDT_64BIT)
  3936. cmd->u.cache64.DeviceNo = i;
  3937. else
  3938. cmd->u.cache.DeviceNo = i;
  3939. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3940. spin_lock_irqsave(&ha->smp_lock, flags);
  3941. rsc->hdr_list[i].bus = ha->virt_bus;
  3942. rsc->hdr_list[i].target = i;
  3943. rsc->hdr_list[i].lun = 0;
  3944. if (status != S_OK) {
  3945. ha->hdr[i].present = FALSE;
  3946. } else {
  3947. ha->hdr[i].present = TRUE;
  3948. ha->hdr[i].size = info;
  3949. /* evaluate mapping */
  3950. ha->hdr[i].size &= ~SECS32;
  3951. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3952. ha->hdr[i].heads = hds;
  3953. ha->hdr[i].secs = secs;
  3954. /* round size */
  3955. ha->hdr[i].size = cyls * hds * secs;
  3956. }
  3957. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3958. if (status != S_OK)
  3959. continue;
  3960. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3961. /* but we need ha->info2, not yet stored in scp->SCp */
  3962. /* devtype, cluster info, R/W attribs */
  3963. cmd->Service = CACHESERVICE;
  3964. cmd->OpCode = GDT_DEVTYPE;
  3965. if (ha->cache_feat & GDT_64BIT)
  3966. cmd->u.cache64.DeviceNo = i;
  3967. else
  3968. cmd->u.cache.DeviceNo = i;
  3969. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3970. spin_lock_irqsave(&ha->smp_lock, flags);
  3971. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  3972. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3973. cmd->Service = CACHESERVICE;
  3974. cmd->OpCode = GDT_CLUST_INFO;
  3975. if (ha->cache_feat & GDT_64BIT)
  3976. cmd->u.cache64.DeviceNo = i;
  3977. else
  3978. cmd->u.cache.DeviceNo = i;
  3979. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3980. spin_lock_irqsave(&ha->smp_lock, flags);
  3981. ha->hdr[i].cluster_type =
  3982. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  3983. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3984. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3985. cmd->Service = CACHESERVICE;
  3986. cmd->OpCode = GDT_RW_ATTRIBS;
  3987. if (ha->cache_feat & GDT_64BIT)
  3988. cmd->u.cache64.DeviceNo = i;
  3989. else
  3990. cmd->u.cache.DeviceNo = i;
  3991. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3992. spin_lock_irqsave(&ha->smp_lock, flags);
  3993. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  3994. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3995. }
  3996. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3997. rc = -EFAULT;
  3998. else
  3999. rc = 0;
  4000. free_fail:
  4001. kfree(rsc);
  4002. kfree(cmd);
  4003. return rc;
  4004. }
  4005. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4006. unsigned int cmd, unsigned long arg)
  4007. {
  4008. gdth_ha_str *ha;
  4009. Scsi_Cmnd *scp;
  4010. ulong flags;
  4011. char cmnd[MAX_COMMAND_SIZE];
  4012. void __user *argp = (void __user *)arg;
  4013. memset(cmnd, 0xff, 12);
  4014. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4015. switch (cmd) {
  4016. case GDTIOCTL_CTRCNT:
  4017. {
  4018. int cnt = gdth_ctr_count;
  4019. if (put_user(cnt, (int __user *)argp))
  4020. return -EFAULT;
  4021. break;
  4022. }
  4023. case GDTIOCTL_DRVERS:
  4024. {
  4025. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4026. if (put_user(ver, (int __user *)argp))
  4027. return -EFAULT;
  4028. break;
  4029. }
  4030. case GDTIOCTL_OSVERS:
  4031. {
  4032. gdth_ioctl_osvers osv;
  4033. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4034. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4035. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4036. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4037. return -EFAULT;
  4038. break;
  4039. }
  4040. case GDTIOCTL_CTRTYPE:
  4041. {
  4042. gdth_ioctl_ctrtype ctrt;
  4043. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4044. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4045. return -EFAULT;
  4046. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4047. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4048. } else {
  4049. if (ha->type != GDT_PCIMPR) {
  4050. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4051. } else {
  4052. ctrt.type =
  4053. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4054. if (ha->stype >= 0x300)
  4055. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4056. else
  4057. ctrt.ext_type = 0x6000 | ha->stype;
  4058. }
  4059. ctrt.device_id = ha->pdev->device;
  4060. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4061. }
  4062. ctrt.info = ha->brd_phys;
  4063. ctrt.oem_id = ha->oem_id;
  4064. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4065. return -EFAULT;
  4066. break;
  4067. }
  4068. case GDTIOCTL_GENERAL:
  4069. return ioc_general(argp, cmnd);
  4070. case GDTIOCTL_EVENT:
  4071. return ioc_event(argp);
  4072. case GDTIOCTL_LOCKDRV:
  4073. return ioc_lockdrv(argp);
  4074. case GDTIOCTL_LOCKCHN:
  4075. {
  4076. gdth_ioctl_lockchn lchn;
  4077. unchar i, j;
  4078. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4079. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4080. return -EFAULT;
  4081. i = lchn.channel;
  4082. if (i < ha->bus_cnt) {
  4083. if (lchn.lock) {
  4084. spin_lock_irqsave(&ha->smp_lock, flags);
  4085. ha->raw[i].lock = 1;
  4086. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4087. for (j = 0; j < ha->tid_cnt; ++j) {
  4088. gdth_wait_completion(ha, i, j);
  4089. gdth_stop_timeout(ha, i, j);
  4090. }
  4091. } else {
  4092. spin_lock_irqsave(&ha->smp_lock, flags);
  4093. ha->raw[i].lock = 0;
  4094. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4095. for (j = 0; j < ha->tid_cnt; ++j) {
  4096. gdth_start_timeout(ha, i, j);
  4097. gdth_next(ha);
  4098. }
  4099. }
  4100. }
  4101. break;
  4102. }
  4103. case GDTIOCTL_RESCAN:
  4104. return ioc_rescan(argp, cmnd);
  4105. case GDTIOCTL_HDRLIST:
  4106. return ioc_hdrlist(argp, cmnd);
  4107. case GDTIOCTL_RESET_BUS:
  4108. {
  4109. gdth_ioctl_reset res;
  4110. int rval;
  4111. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4112. (NULL == (ha = gdth_find_ha(res.ionode))))
  4113. return -EFAULT;
  4114. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4115. if (!scp)
  4116. return -ENOMEM;
  4117. scp->device = ha->sdev;
  4118. scp->cmd_len = 12;
  4119. scp->device->channel = res.number;
  4120. rval = gdth_eh_bus_reset(scp);
  4121. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4122. kfree(scp);
  4123. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4124. return -EFAULT;
  4125. break;
  4126. }
  4127. case GDTIOCTL_RESET_DRV:
  4128. return ioc_resetdrv(argp, cmnd);
  4129. default:
  4130. break;
  4131. }
  4132. return 0;
  4133. }
  4134. /* flush routine */
  4135. static void gdth_flush(gdth_ha_str *ha)
  4136. {
  4137. int i;
  4138. gdth_cmd_str gdtcmd;
  4139. char cmnd[MAX_COMMAND_SIZE];
  4140. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4141. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4142. for (i = 0; i < MAX_HDRIVES; ++i) {
  4143. if (ha->hdr[i].present) {
  4144. gdtcmd.BoardNode = LOCALBOARD;
  4145. gdtcmd.Service = CACHESERVICE;
  4146. gdtcmd.OpCode = GDT_FLUSH;
  4147. if (ha->cache_feat & GDT_64BIT) {
  4148. gdtcmd.u.cache64.DeviceNo = i;
  4149. gdtcmd.u.cache64.BlockNo = 1;
  4150. gdtcmd.u.cache64.sg_canz = 0;
  4151. } else {
  4152. gdtcmd.u.cache.DeviceNo = i;
  4153. gdtcmd.u.cache.BlockNo = 1;
  4154. gdtcmd.u.cache.sg_canz = 0;
  4155. }
  4156. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4157. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4158. }
  4159. }
  4160. }
  4161. /* configure lun */
  4162. static int gdth_slave_configure(struct scsi_device *sdev)
  4163. {
  4164. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4165. sdev->skip_ms_page_3f = 1;
  4166. sdev->skip_ms_page_8 = 1;
  4167. return 0;
  4168. }
  4169. static struct scsi_host_template gdth_template = {
  4170. .name = "GDT SCSI Disk Array Controller",
  4171. .info = gdth_info,
  4172. .queuecommand = gdth_queuecommand,
  4173. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4174. .slave_configure = gdth_slave_configure,
  4175. .bios_param = gdth_bios_param,
  4176. .proc_info = gdth_proc_info,
  4177. .proc_name = "gdth",
  4178. .can_queue = GDTH_MAXCMDS,
  4179. .this_id = -1,
  4180. .sg_tablesize = GDTH_MAXSG,
  4181. .cmd_per_lun = GDTH_MAXC_P_L,
  4182. .unchecked_isa_dma = 1,
  4183. .use_clustering = ENABLE_CLUSTERING,
  4184. };
  4185. #ifdef CONFIG_ISA
  4186. static int __init gdth_isa_probe_one(ulong32 isa_bios)
  4187. {
  4188. struct Scsi_Host *shp;
  4189. gdth_ha_str *ha;
  4190. dma_addr_t scratch_dma_handle = 0;
  4191. int error, i;
  4192. if (!gdth_search_isa(isa_bios))
  4193. return -ENXIO;
  4194. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4195. if (!shp)
  4196. return -ENOMEM;
  4197. ha = shost_priv(shp);
  4198. error = -ENODEV;
  4199. if (!gdth_init_isa(isa_bios,ha))
  4200. goto out_host_put;
  4201. /* controller found and initialized */
  4202. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4203. isa_bios, ha->irq, ha->drq);
  4204. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4205. if (error) {
  4206. printk("GDT-ISA: Unable to allocate IRQ\n");
  4207. goto out_host_put;
  4208. }
  4209. error = request_dma(ha->drq, "gdth");
  4210. if (error) {
  4211. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4212. goto out_free_irq;
  4213. }
  4214. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4215. enable_dma(ha->drq);
  4216. shp->unchecked_isa_dma = 1;
  4217. shp->irq = ha->irq;
  4218. shp->dma_channel = ha->drq;
  4219. ha->hanum = gdth_ctr_count++;
  4220. ha->shost = shp;
  4221. ha->pccb = &ha->cmdext;
  4222. ha->ccb_phys = 0L;
  4223. ha->pdev = NULL;
  4224. error = -ENOMEM;
  4225. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4226. &scratch_dma_handle);
  4227. if (!ha->pscratch)
  4228. goto out_dec_counters;
  4229. ha->scratch_phys = scratch_dma_handle;
  4230. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4231. &scratch_dma_handle);
  4232. if (!ha->pmsg)
  4233. goto out_free_pscratch;
  4234. ha->msg_phys = scratch_dma_handle;
  4235. #ifdef INT_COAL
  4236. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4237. sizeof(gdth_coal_status) * MAXOFFSETS,
  4238. &scratch_dma_handle);
  4239. if (!ha->coal_stat)
  4240. goto out_free_pmsg;
  4241. ha->coal_stat_phys = scratch_dma_handle;
  4242. #endif
  4243. ha->scratch_busy = FALSE;
  4244. ha->req_first = NULL;
  4245. ha->tid_cnt = MAX_HDRIVES;
  4246. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4247. ha->tid_cnt = max_ids;
  4248. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4249. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4250. ha->scan_mode = rescan ? 0x10 : 0;
  4251. error = -ENODEV;
  4252. if (!gdth_search_drives(ha)) {
  4253. printk("GDT-ISA: Error during device scan\n");
  4254. goto out_free_coal_stat;
  4255. }
  4256. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4257. hdr_channel = ha->bus_cnt;
  4258. ha->virt_bus = hdr_channel;
  4259. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4260. shp->max_cmd_len = 16;
  4261. shp->max_id = ha->tid_cnt;
  4262. shp->max_lun = MAXLUN;
  4263. shp->max_channel = ha->bus_cnt;
  4264. spin_lock_init(&ha->smp_lock);
  4265. gdth_enable_int(ha);
  4266. error = scsi_add_host(shp, NULL);
  4267. if (error)
  4268. goto out_free_coal_stat;
  4269. list_add_tail(&ha->list, &gdth_instances);
  4270. gdth_timer_init();
  4271. scsi_scan_host(shp);
  4272. return 0;
  4273. out_free_coal_stat:
  4274. #ifdef INT_COAL
  4275. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4276. ha->coal_stat, ha->coal_stat_phys);
  4277. out_free_pmsg:
  4278. #endif
  4279. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4280. ha->pmsg, ha->msg_phys);
  4281. out_free_pscratch:
  4282. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4283. ha->pscratch, ha->scratch_phys);
  4284. out_dec_counters:
  4285. gdth_ctr_count--;
  4286. out_free_irq:
  4287. free_irq(ha->irq, ha);
  4288. out_host_put:
  4289. scsi_host_put(shp);
  4290. return error;
  4291. }
  4292. #endif /* CONFIG_ISA */
  4293. #ifdef CONFIG_EISA
  4294. static int __init gdth_eisa_probe_one(ushort eisa_slot)
  4295. {
  4296. struct Scsi_Host *shp;
  4297. gdth_ha_str *ha;
  4298. dma_addr_t scratch_dma_handle = 0;
  4299. int error, i;
  4300. if (!gdth_search_eisa(eisa_slot))
  4301. return -ENXIO;
  4302. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4303. if (!shp)
  4304. return -ENOMEM;
  4305. ha = shost_priv(shp);
  4306. error = -ENODEV;
  4307. if (!gdth_init_eisa(eisa_slot,ha))
  4308. goto out_host_put;
  4309. /* controller found and initialized */
  4310. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4311. eisa_slot >> 12, ha->irq);
  4312. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4313. if (error) {
  4314. printk("GDT-EISA: Unable to allocate IRQ\n");
  4315. goto out_host_put;
  4316. }
  4317. shp->unchecked_isa_dma = 0;
  4318. shp->irq = ha->irq;
  4319. shp->dma_channel = 0xff;
  4320. ha->hanum = gdth_ctr_count++;
  4321. ha->shost = shp;
  4322. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4323. ha->pccb = &ha->cmdext;
  4324. ha->ccb_phys = 0L;
  4325. error = -ENOMEM;
  4326. ha->pdev = NULL;
  4327. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4328. &scratch_dma_handle);
  4329. if (!ha->pscratch)
  4330. goto out_free_irq;
  4331. ha->scratch_phys = scratch_dma_handle;
  4332. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4333. &scratch_dma_handle);
  4334. if (!ha->pmsg)
  4335. goto out_free_pscratch;
  4336. ha->msg_phys = scratch_dma_handle;
  4337. #ifdef INT_COAL
  4338. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4339. sizeof(gdth_coal_status) * MAXOFFSETS,
  4340. &scratch_dma_handle);
  4341. if (!ha->coal_stat)
  4342. goto out_free_pmsg;
  4343. ha->coal_stat_phys = scratch_dma_handle;
  4344. #endif
  4345. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4346. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4347. if (!ha->ccb_phys)
  4348. goto out_free_coal_stat;
  4349. ha->scratch_busy = FALSE;
  4350. ha->req_first = NULL;
  4351. ha->tid_cnt = MAX_HDRIVES;
  4352. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4353. ha->tid_cnt = max_ids;
  4354. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4355. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4356. ha->scan_mode = rescan ? 0x10 : 0;
  4357. if (!gdth_search_drives(ha)) {
  4358. printk("GDT-EISA: Error during device scan\n");
  4359. error = -ENODEV;
  4360. goto out_free_ccb_phys;
  4361. }
  4362. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4363. hdr_channel = ha->bus_cnt;
  4364. ha->virt_bus = hdr_channel;
  4365. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4366. shp->max_cmd_len = 16;
  4367. shp->max_id = ha->tid_cnt;
  4368. shp->max_lun = MAXLUN;
  4369. shp->max_channel = ha->bus_cnt;
  4370. spin_lock_init(&ha->smp_lock);
  4371. gdth_enable_int(ha);
  4372. error = scsi_add_host(shp, NULL);
  4373. if (error)
  4374. goto out_free_coal_stat;
  4375. list_add_tail(&ha->list, &gdth_instances);
  4376. gdth_timer_init();
  4377. scsi_scan_host(shp);
  4378. return 0;
  4379. out_free_ccb_phys:
  4380. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4381. PCI_DMA_BIDIRECTIONAL);
  4382. out_free_coal_stat:
  4383. #ifdef INT_COAL
  4384. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4385. ha->coal_stat, ha->coal_stat_phys);
  4386. out_free_pmsg:
  4387. #endif
  4388. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4389. ha->pmsg, ha->msg_phys);
  4390. out_free_pscratch:
  4391. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4392. ha->pscratch, ha->scratch_phys);
  4393. out_free_irq:
  4394. free_irq(ha->irq, ha);
  4395. gdth_ctr_count--;
  4396. out_host_put:
  4397. scsi_host_put(shp);
  4398. return error;
  4399. }
  4400. #endif /* CONFIG_EISA */
  4401. #ifdef CONFIG_PCI
  4402. static int gdth_pci_probe_one(gdth_pci_str *pcistr,
  4403. gdth_ha_str **ha_out)
  4404. {
  4405. struct Scsi_Host *shp;
  4406. gdth_ha_str *ha;
  4407. dma_addr_t scratch_dma_handle = 0;
  4408. int error, i;
  4409. struct pci_dev *pdev = pcistr->pdev;
  4410. *ha_out = NULL;
  4411. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4412. if (!shp)
  4413. return -ENOMEM;
  4414. ha = shost_priv(shp);
  4415. error = -ENODEV;
  4416. if (!gdth_init_pci(pdev, pcistr, ha))
  4417. goto out_host_put;
  4418. /* controller found and initialized */
  4419. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4420. pdev->bus->number,
  4421. PCI_SLOT(pdev->devfn),
  4422. ha->irq);
  4423. error = request_irq(ha->irq, gdth_interrupt,
  4424. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4425. if (error) {
  4426. printk("GDT-PCI: Unable to allocate IRQ\n");
  4427. goto out_host_put;
  4428. }
  4429. shp->unchecked_isa_dma = 0;
  4430. shp->irq = ha->irq;
  4431. shp->dma_channel = 0xff;
  4432. ha->hanum = gdth_ctr_count++;
  4433. ha->shost = shp;
  4434. ha->pccb = &ha->cmdext;
  4435. ha->ccb_phys = 0L;
  4436. error = -ENOMEM;
  4437. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4438. &scratch_dma_handle);
  4439. if (!ha->pscratch)
  4440. goto out_free_irq;
  4441. ha->scratch_phys = scratch_dma_handle;
  4442. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4443. &scratch_dma_handle);
  4444. if (!ha->pmsg)
  4445. goto out_free_pscratch;
  4446. ha->msg_phys = scratch_dma_handle;
  4447. #ifdef INT_COAL
  4448. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4449. sizeof(gdth_coal_status) * MAXOFFSETS,
  4450. &scratch_dma_handle);
  4451. if (!ha->coal_stat)
  4452. goto out_free_pmsg;
  4453. ha->coal_stat_phys = scratch_dma_handle;
  4454. #endif
  4455. ha->scratch_busy = FALSE;
  4456. ha->req_first = NULL;
  4457. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4458. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4459. ha->tid_cnt = max_ids;
  4460. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4461. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4462. ha->scan_mode = rescan ? 0x10 : 0;
  4463. error = -ENODEV;
  4464. if (!gdth_search_drives(ha)) {
  4465. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4466. goto out_free_coal_stat;
  4467. }
  4468. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4469. hdr_channel = ha->bus_cnt;
  4470. ha->virt_bus = hdr_channel;
  4471. /* 64-bit DMA only supported from FW >= x.43 */
  4472. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4473. !ha->dma64_support) {
  4474. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  4475. printk(KERN_WARNING "GDT-PCI %d: "
  4476. "Unable to set 32-bit DMA\n", ha->hanum);
  4477. goto out_free_coal_stat;
  4478. }
  4479. } else {
  4480. shp->max_cmd_len = 16;
  4481. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  4482. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4483. } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  4484. printk(KERN_WARNING "GDT-PCI %d: "
  4485. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4486. goto out_free_coal_stat;
  4487. }
  4488. }
  4489. shp->max_id = ha->tid_cnt;
  4490. shp->max_lun = MAXLUN;
  4491. shp->max_channel = ha->bus_cnt;
  4492. spin_lock_init(&ha->smp_lock);
  4493. gdth_enable_int(ha);
  4494. error = scsi_add_host(shp, &pdev->dev);
  4495. if (error)
  4496. goto out_free_coal_stat;
  4497. list_add_tail(&ha->list, &gdth_instances);
  4498. pci_set_drvdata(ha->pdev, ha);
  4499. gdth_timer_init();
  4500. scsi_scan_host(shp);
  4501. *ha_out = ha;
  4502. return 0;
  4503. out_free_coal_stat:
  4504. #ifdef INT_COAL
  4505. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4506. ha->coal_stat, ha->coal_stat_phys);
  4507. out_free_pmsg:
  4508. #endif
  4509. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4510. ha->pmsg, ha->msg_phys);
  4511. out_free_pscratch:
  4512. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4513. ha->pscratch, ha->scratch_phys);
  4514. out_free_irq:
  4515. free_irq(ha->irq, ha);
  4516. gdth_ctr_count--;
  4517. out_host_put:
  4518. scsi_host_put(shp);
  4519. return error;
  4520. }
  4521. #endif /* CONFIG_PCI */
  4522. static void gdth_remove_one(gdth_ha_str *ha)
  4523. {
  4524. struct Scsi_Host *shp = ha->shost;
  4525. TRACE2(("gdth_remove_one()\n"));
  4526. scsi_remove_host(shp);
  4527. gdth_flush(ha);
  4528. if (ha->sdev) {
  4529. scsi_free_host_dev(ha->sdev);
  4530. ha->sdev = NULL;
  4531. }
  4532. if (shp->irq)
  4533. free_irq(shp->irq,ha);
  4534. #ifdef CONFIG_ISA
  4535. if (shp->dma_channel != 0xff)
  4536. free_dma(shp->dma_channel);
  4537. #endif
  4538. #ifdef INT_COAL
  4539. if (ha->coal_stat)
  4540. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4541. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4542. #endif
  4543. if (ha->pscratch)
  4544. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4545. ha->pscratch, ha->scratch_phys);
  4546. if (ha->pmsg)
  4547. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4548. ha->pmsg, ha->msg_phys);
  4549. if (ha->ccb_phys)
  4550. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4551. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4552. scsi_host_put(shp);
  4553. }
  4554. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4555. {
  4556. gdth_ha_str *ha;
  4557. TRACE2(("gdth_halt() event %d\n", (int)event));
  4558. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4559. return NOTIFY_DONE;
  4560. list_for_each_entry(ha, &gdth_instances, list)
  4561. gdth_flush(ha);
  4562. return NOTIFY_OK;
  4563. }
  4564. static struct notifier_block gdth_notifier = {
  4565. gdth_halt, NULL, 0
  4566. };
  4567. static int __init gdth_init(void)
  4568. {
  4569. if (disable) {
  4570. printk("GDT-HA: Controller driver disabled from"
  4571. " command line !\n");
  4572. return 0;
  4573. }
  4574. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4575. GDTH_VERSION_STR);
  4576. /* initializations */
  4577. gdth_polling = TRUE;
  4578. gdth_clear_events();
  4579. init_timer(&gdth_timer);
  4580. /* As default we do not probe for EISA or ISA controllers */
  4581. if (probe_eisa_isa) {
  4582. /* scanning for controllers, at first: ISA controller */
  4583. #ifdef CONFIG_ISA
  4584. ulong32 isa_bios;
  4585. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4586. isa_bios += 0x8000UL)
  4587. gdth_isa_probe_one(isa_bios);
  4588. #endif
  4589. #ifdef CONFIG_EISA
  4590. {
  4591. ushort eisa_slot;
  4592. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4593. eisa_slot += 0x1000)
  4594. gdth_eisa_probe_one(eisa_slot);
  4595. }
  4596. #endif
  4597. }
  4598. #ifdef CONFIG_PCI
  4599. /* scanning for PCI controllers */
  4600. if (pci_register_driver(&gdth_pci_driver)) {
  4601. gdth_ha_str *ha;
  4602. list_for_each_entry(ha, &gdth_instances, list)
  4603. gdth_remove_one(ha);
  4604. return -ENODEV;
  4605. }
  4606. #endif /* CONFIG_PCI */
  4607. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4608. major = register_chrdev(0,"gdth", &gdth_fops);
  4609. register_reboot_notifier(&gdth_notifier);
  4610. gdth_polling = FALSE;
  4611. return 0;
  4612. }
  4613. static void __exit gdth_exit(void)
  4614. {
  4615. gdth_ha_str *ha;
  4616. unregister_chrdev(major, "gdth");
  4617. unregister_reboot_notifier(&gdth_notifier);
  4618. #ifdef GDTH_STATISTICS
  4619. del_timer_sync(&gdth_timer);
  4620. #endif
  4621. #ifdef CONFIG_PCI
  4622. pci_unregister_driver(&gdth_pci_driver);
  4623. #endif
  4624. list_for_each_entry(ha, &gdth_instances, list)
  4625. gdth_remove_one(ha);
  4626. }
  4627. module_init(gdth_init);
  4628. module_exit(gdth_exit);
  4629. #ifndef MODULE
  4630. __setup("gdth=", option_setup);
  4631. #endif