iwl3945-base.c 234 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  95. {
  96. /* Single white space is for Linksys APs */
  97. if (essid_len == 1 && essid[0] == ' ')
  98. return 1;
  99. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  100. while (essid_len) {
  101. essid_len--;
  102. if (essid[essid_len] != '\0')
  103. return 0;
  104. }
  105. return 1;
  106. }
  107. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  108. {
  109. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  110. const char *s = essid;
  111. char *d = escaped;
  112. if (iwl3945_is_empty_essid(essid, essid_len)) {
  113. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  114. return escaped;
  115. }
  116. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  117. while (essid_len--) {
  118. if (*s == '\0') {
  119. *d++ = '\\';
  120. *d++ = '0';
  121. s++;
  122. } else
  123. *d++ = *s++;
  124. }
  125. *d = '\0';
  126. return escaped;
  127. }
  128. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  129. * DMA services
  130. *
  131. * Theory of operation
  132. *
  133. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  134. * of buffer descriptors, each of which points to one or more data buffers for
  135. * the device to read from or fill. Driver and device exchange status of each
  136. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  137. * entries in each circular buffer, to protect against confusing empty and full
  138. * queue states.
  139. *
  140. * The device reads or writes the data in the queues via the device's several
  141. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  142. *
  143. * For Tx queue, there are low mark and high mark limits. If, after queuing
  144. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  145. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  146. * Tx queue resumed.
  147. *
  148. * The 3945 operates with six queues: One receive queue, one transmit queue
  149. * (#4) for sending commands to the device firmware, and four transmit queues
  150. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  151. ***************************************************/
  152. int iwl3945_queue_space(const struct iwl3945_queue *q)
  153. {
  154. int s = q->read_ptr - q->write_ptr;
  155. if (q->read_ptr > q->write_ptr)
  156. s -= q->n_bd;
  157. if (s <= 0)
  158. s += q->n_window;
  159. /* keep some reserve to not confuse empty and full situations */
  160. s -= 2;
  161. if (s < 0)
  162. s = 0;
  163. return s;
  164. }
  165. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  166. {
  167. return q->write_ptr > q->read_ptr ?
  168. (i >= q->read_ptr && i < q->write_ptr) :
  169. !(i < q->read_ptr && i >= q->write_ptr);
  170. }
  171. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  172. {
  173. /* This is for scan command, the big buffer at end of command array */
  174. if (is_huge)
  175. return q->n_window; /* must be power of 2 */
  176. /* Otherwise, use normal size buffers */
  177. return index & (q->n_window - 1);
  178. }
  179. /**
  180. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  181. */
  182. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  183. int count, int slots_num, u32 id)
  184. {
  185. q->n_bd = count;
  186. q->n_window = slots_num;
  187. q->id = id;
  188. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  189. * and iwl_queue_dec_wrap are broken. */
  190. BUG_ON(!is_power_of_2(count));
  191. /* slots_num must be power-of-two size, otherwise
  192. * get_cmd_index is broken. */
  193. BUG_ON(!is_power_of_2(slots_num));
  194. q->low_mark = q->n_window / 4;
  195. if (q->low_mark < 4)
  196. q->low_mark = 4;
  197. q->high_mark = q->n_window / 8;
  198. if (q->high_mark < 2)
  199. q->high_mark = 2;
  200. q->write_ptr = q->read_ptr = 0;
  201. return 0;
  202. }
  203. /**
  204. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  205. */
  206. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  207. struct iwl3945_tx_queue *txq, u32 id)
  208. {
  209. struct pci_dev *dev = priv->pci_dev;
  210. /* Driver private data, only for Tx (not command) queues,
  211. * not shared with device. */
  212. if (id != IWL_CMD_QUEUE_NUM) {
  213. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  214. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  215. if (!txq->txb) {
  216. IWL_ERROR("kmalloc for auxiliary BD "
  217. "structures failed\n");
  218. goto error;
  219. }
  220. } else
  221. txq->txb = NULL;
  222. /* Circular buffer of transmit frame descriptors (TFDs),
  223. * shared with device */
  224. txq->bd = pci_alloc_consistent(dev,
  225. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  226. &txq->q.dma_addr);
  227. if (!txq->bd) {
  228. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  229. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  230. goto error;
  231. }
  232. txq->q.id = id;
  233. return 0;
  234. error:
  235. if (txq->txb) {
  236. kfree(txq->txb);
  237. txq->txb = NULL;
  238. }
  239. return -ENOMEM;
  240. }
  241. /**
  242. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  243. */
  244. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  245. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  246. {
  247. struct pci_dev *dev = priv->pci_dev;
  248. int len;
  249. int rc = 0;
  250. /*
  251. * Alloc buffer array for commands (Tx or other types of commands).
  252. * For the command queue (#4), allocate command space + one big
  253. * command for scan, since scan command is very huge; the system will
  254. * not have two scans at the same time, so only one is needed.
  255. * For data Tx queues (all other queues), no super-size command
  256. * space is needed.
  257. */
  258. len = sizeof(struct iwl3945_cmd) * slots_num;
  259. if (txq_id == IWL_CMD_QUEUE_NUM)
  260. len += IWL_MAX_SCAN_SIZE;
  261. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  262. if (!txq->cmd)
  263. return -ENOMEM;
  264. /* Alloc driver data array and TFD circular buffer */
  265. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  266. if (rc) {
  267. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  268. return -ENOMEM;
  269. }
  270. txq->need_update = 0;
  271. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  272. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  273. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  274. /* Initialize queue high/low-water, head/tail indexes */
  275. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  276. /* Tell device where to find queue, enable DMA channel. */
  277. iwl3945_hw_tx_queue_init(priv, txq);
  278. return 0;
  279. }
  280. /**
  281. * iwl3945_tx_queue_free - Deallocate DMA queue.
  282. * @txq: Transmit queue to deallocate.
  283. *
  284. * Empty queue by removing and destroying all BD's.
  285. * Free all buffers.
  286. * 0-fill, but do not free "txq" descriptor structure.
  287. */
  288. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  289. {
  290. struct iwl3945_queue *q = &txq->q;
  291. struct pci_dev *dev = priv->pci_dev;
  292. int len;
  293. if (q->n_bd == 0)
  294. return;
  295. /* first, empty all BD's */
  296. for (; q->write_ptr != q->read_ptr;
  297. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  298. iwl3945_hw_txq_free_tfd(priv, txq);
  299. len = sizeof(struct iwl3945_cmd) * q->n_window;
  300. if (q->id == IWL_CMD_QUEUE_NUM)
  301. len += IWL_MAX_SCAN_SIZE;
  302. /* De-alloc array of command/tx buffers */
  303. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  304. /* De-alloc circular buffer of TFDs */
  305. if (txq->q.n_bd)
  306. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  307. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  308. /* De-alloc array of per-TFD driver data */
  309. if (txq->txb) {
  310. kfree(txq->txb);
  311. txq->txb = NULL;
  312. }
  313. /* 0-fill queue descriptor structure */
  314. memset(txq, 0, sizeof(*txq));
  315. }
  316. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  317. /*************** STATION TABLE MANAGEMENT ****
  318. * mac80211 should be examined to determine if sta_info is duplicating
  319. * the functionality provided here
  320. */
  321. /**************************************************************/
  322. #if 0 /* temporary disable till we add real remove station */
  323. /**
  324. * iwl3945_remove_station - Remove driver's knowledge of station.
  325. *
  326. * NOTE: This does not remove station from device's station table.
  327. */
  328. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  329. {
  330. int index = IWL_INVALID_STATION;
  331. int i;
  332. unsigned long flags;
  333. spin_lock_irqsave(&priv->sta_lock, flags);
  334. if (is_ap)
  335. index = IWL_AP_ID;
  336. else if (is_broadcast_ether_addr(addr))
  337. index = priv->hw_setting.bcast_sta_id;
  338. else
  339. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  340. if (priv->stations[i].used &&
  341. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  342. addr)) {
  343. index = i;
  344. break;
  345. }
  346. if (unlikely(index == IWL_INVALID_STATION))
  347. goto out;
  348. if (priv->stations[index].used) {
  349. priv->stations[index].used = 0;
  350. priv->num_stations--;
  351. }
  352. BUG_ON(priv->num_stations < 0);
  353. out:
  354. spin_unlock_irqrestore(&priv->sta_lock, flags);
  355. return 0;
  356. }
  357. #endif
  358. /**
  359. * iwl3945_clear_stations_table - Clear the driver's station table
  360. *
  361. * NOTE: This does not clear or otherwise alter the device's station table.
  362. */
  363. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  364. {
  365. unsigned long flags;
  366. spin_lock_irqsave(&priv->sta_lock, flags);
  367. priv->num_stations = 0;
  368. memset(priv->stations, 0, sizeof(priv->stations));
  369. spin_unlock_irqrestore(&priv->sta_lock, flags);
  370. }
  371. /**
  372. * iwl3945_add_station - Add station to station tables in driver and device
  373. */
  374. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  375. {
  376. int i;
  377. int index = IWL_INVALID_STATION;
  378. struct iwl3945_station_entry *station;
  379. unsigned long flags_spin;
  380. DECLARE_MAC_BUF(mac);
  381. u8 rate;
  382. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  383. if (is_ap)
  384. index = IWL_AP_ID;
  385. else if (is_broadcast_ether_addr(addr))
  386. index = priv->hw_setting.bcast_sta_id;
  387. else
  388. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  389. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  390. addr)) {
  391. index = i;
  392. break;
  393. }
  394. if (!priv->stations[i].used &&
  395. index == IWL_INVALID_STATION)
  396. index = i;
  397. }
  398. /* These two conditions has the same outcome but keep them separate
  399. since they have different meaning */
  400. if (unlikely(index == IWL_INVALID_STATION)) {
  401. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  402. return index;
  403. }
  404. if (priv->stations[index].used &&
  405. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  406. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  407. return index;
  408. }
  409. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  410. station = &priv->stations[index];
  411. station->used = 1;
  412. priv->num_stations++;
  413. /* Set up the REPLY_ADD_STA command to send to device */
  414. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  415. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  416. station->sta.mode = 0;
  417. station->sta.sta.sta_id = index;
  418. station->sta.station_flags = 0;
  419. if (priv->band == IEEE80211_BAND_5GHZ)
  420. rate = IWL_RATE_6M_PLCP;
  421. else
  422. rate = IWL_RATE_1M_PLCP;
  423. /* Turn on both antennas for the station... */
  424. station->sta.rate_n_flags =
  425. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  426. station->current_rate.rate_n_flags =
  427. le16_to_cpu(station->sta.rate_n_flags);
  428. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  429. /* Add station to device's station table */
  430. iwl3945_send_add_station(priv, &station->sta, flags);
  431. return index;
  432. }
  433. /*************** DRIVER STATUS FUNCTIONS *****/
  434. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  435. {
  436. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  437. * set but EXIT_PENDING is not */
  438. return test_bit(STATUS_READY, &priv->status) &&
  439. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  440. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  441. }
  442. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  443. {
  444. return test_bit(STATUS_ALIVE, &priv->status);
  445. }
  446. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  447. {
  448. return test_bit(STATUS_INIT, &priv->status);
  449. }
  450. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  451. {
  452. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  453. test_bit(STATUS_RF_KILL_SW, &priv->status);
  454. }
  455. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  456. {
  457. if (iwl3945_is_rfkill(priv))
  458. return 0;
  459. return iwl3945_is_ready(priv);
  460. }
  461. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  462. #define IWL_CMD(x) case x : return #x
  463. static const char *get_cmd_string(u8 cmd)
  464. {
  465. switch (cmd) {
  466. IWL_CMD(REPLY_ALIVE);
  467. IWL_CMD(REPLY_ERROR);
  468. IWL_CMD(REPLY_RXON);
  469. IWL_CMD(REPLY_RXON_ASSOC);
  470. IWL_CMD(REPLY_QOS_PARAM);
  471. IWL_CMD(REPLY_RXON_TIMING);
  472. IWL_CMD(REPLY_ADD_STA);
  473. IWL_CMD(REPLY_REMOVE_STA);
  474. IWL_CMD(REPLY_REMOVE_ALL_STA);
  475. IWL_CMD(REPLY_3945_RX);
  476. IWL_CMD(REPLY_TX);
  477. IWL_CMD(REPLY_RATE_SCALE);
  478. IWL_CMD(REPLY_LEDS_CMD);
  479. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  480. IWL_CMD(RADAR_NOTIFICATION);
  481. IWL_CMD(REPLY_QUIET_CMD);
  482. IWL_CMD(REPLY_CHANNEL_SWITCH);
  483. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  484. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  485. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  486. IWL_CMD(POWER_TABLE_CMD);
  487. IWL_CMD(PM_SLEEP_NOTIFICATION);
  488. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  489. IWL_CMD(REPLY_SCAN_CMD);
  490. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  491. IWL_CMD(SCAN_START_NOTIFICATION);
  492. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  493. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  494. IWL_CMD(BEACON_NOTIFICATION);
  495. IWL_CMD(REPLY_TX_BEACON);
  496. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  497. IWL_CMD(QUIET_NOTIFICATION);
  498. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  499. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  500. IWL_CMD(REPLY_BT_CONFIG);
  501. IWL_CMD(REPLY_STATISTICS_CMD);
  502. IWL_CMD(STATISTICS_NOTIFICATION);
  503. IWL_CMD(REPLY_CARD_STATE_CMD);
  504. IWL_CMD(CARD_STATE_NOTIFICATION);
  505. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  506. default:
  507. return "UNKNOWN";
  508. }
  509. }
  510. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  511. /**
  512. * iwl3945_enqueue_hcmd - enqueue a uCode command
  513. * @priv: device private data point
  514. * @cmd: a point to the ucode command structure
  515. *
  516. * The function returns < 0 values to indicate the operation is
  517. * failed. On success, it turns the index (> 0) of command in the
  518. * command queue.
  519. */
  520. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  521. {
  522. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  523. struct iwl3945_queue *q = &txq->q;
  524. struct iwl3945_tfd_frame *tfd;
  525. u32 *control_flags;
  526. struct iwl3945_cmd *out_cmd;
  527. u32 idx;
  528. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  529. dma_addr_t phys_addr;
  530. int pad;
  531. u16 count;
  532. int ret;
  533. unsigned long flags;
  534. /* If any of the command structures end up being larger than
  535. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  536. * we will need to increase the size of the TFD entries */
  537. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  538. !(cmd->meta.flags & CMD_SIZE_HUGE));
  539. if (iwl3945_is_rfkill(priv)) {
  540. IWL_DEBUG_INFO("Not sending command - RF KILL");
  541. return -EIO;
  542. }
  543. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  544. IWL_ERROR("No space for Tx\n");
  545. return -ENOSPC;
  546. }
  547. spin_lock_irqsave(&priv->hcmd_lock, flags);
  548. tfd = &txq->bd[q->write_ptr];
  549. memset(tfd, 0, sizeof(*tfd));
  550. control_flags = (u32 *) tfd;
  551. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  552. out_cmd = &txq->cmd[idx];
  553. out_cmd->hdr.cmd = cmd->id;
  554. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  555. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  556. /* At this point, the out_cmd now has all of the incoming cmd
  557. * information */
  558. out_cmd->hdr.flags = 0;
  559. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  560. INDEX_TO_SEQ(q->write_ptr));
  561. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  562. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  563. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  564. offsetof(struct iwl3945_cmd, hdr);
  565. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  566. pad = U32_PAD(cmd->len);
  567. count = TFD_CTL_COUNT_GET(*control_flags);
  568. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  569. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  570. "%d bytes at %d[%d]:%d\n",
  571. get_cmd_string(out_cmd->hdr.cmd),
  572. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  573. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  574. txq->need_update = 1;
  575. /* Increment and update queue's write index */
  576. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  577. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  578. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  579. return ret ? ret : idx;
  580. }
  581. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  582. {
  583. int ret;
  584. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  585. /* An asynchronous command can not expect an SKB to be set. */
  586. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  587. /* An asynchronous command MUST have a callback. */
  588. BUG_ON(!cmd->meta.u.callback);
  589. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  590. return -EBUSY;
  591. ret = iwl3945_enqueue_hcmd(priv, cmd);
  592. if (ret < 0) {
  593. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  594. get_cmd_string(cmd->id), ret);
  595. return ret;
  596. }
  597. return 0;
  598. }
  599. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  600. {
  601. int cmd_idx;
  602. int ret;
  603. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  604. /* A synchronous command can not have a callback set. */
  605. BUG_ON(cmd->meta.u.callback != NULL);
  606. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  607. IWL_ERROR("Error sending %s: Already sending a host command\n",
  608. get_cmd_string(cmd->id));
  609. ret = -EBUSY;
  610. goto out;
  611. }
  612. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  613. if (cmd->meta.flags & CMD_WANT_SKB)
  614. cmd->meta.source = &cmd->meta;
  615. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  616. if (cmd_idx < 0) {
  617. ret = cmd_idx;
  618. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  619. get_cmd_string(cmd->id), ret);
  620. goto out;
  621. }
  622. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  623. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  624. HOST_COMPLETE_TIMEOUT);
  625. if (!ret) {
  626. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  627. IWL_ERROR("Error sending %s: time out after %dms.\n",
  628. get_cmd_string(cmd->id),
  629. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  630. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  631. ret = -ETIMEDOUT;
  632. goto cancel;
  633. }
  634. }
  635. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  636. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  637. get_cmd_string(cmd->id));
  638. ret = -ECANCELED;
  639. goto fail;
  640. }
  641. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  642. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  643. get_cmd_string(cmd->id));
  644. ret = -EIO;
  645. goto fail;
  646. }
  647. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  648. IWL_ERROR("Error: Response NULL in '%s'\n",
  649. get_cmd_string(cmd->id));
  650. ret = -EIO;
  651. goto out;
  652. }
  653. ret = 0;
  654. goto out;
  655. cancel:
  656. if (cmd->meta.flags & CMD_WANT_SKB) {
  657. struct iwl3945_cmd *qcmd;
  658. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  659. * TX cmd queue. Otherwise in case the cmd comes
  660. * in later, it will possibly set an invalid
  661. * address (cmd->meta.source). */
  662. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  663. qcmd->meta.flags &= ~CMD_WANT_SKB;
  664. }
  665. fail:
  666. if (cmd->meta.u.skb) {
  667. dev_kfree_skb_any(cmd->meta.u.skb);
  668. cmd->meta.u.skb = NULL;
  669. }
  670. out:
  671. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  672. return ret;
  673. }
  674. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  675. {
  676. if (cmd->meta.flags & CMD_ASYNC)
  677. return iwl3945_send_cmd_async(priv, cmd);
  678. return iwl3945_send_cmd_sync(priv, cmd);
  679. }
  680. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  681. {
  682. struct iwl3945_host_cmd cmd = {
  683. .id = id,
  684. .len = len,
  685. .data = data,
  686. };
  687. return iwl3945_send_cmd_sync(priv, &cmd);
  688. }
  689. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  690. {
  691. struct iwl3945_host_cmd cmd = {
  692. .id = id,
  693. .len = sizeof(val),
  694. .data = &val,
  695. };
  696. return iwl3945_send_cmd_sync(priv, &cmd);
  697. }
  698. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  699. {
  700. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  701. }
  702. /**
  703. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  704. * @band: 2.4 or 5 GHz band
  705. * @channel: Any channel valid for the requested band
  706. * In addition to setting the staging RXON, priv->band is also set.
  707. *
  708. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  709. * in the staging RXON flag structure based on the band
  710. */
  711. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  712. enum ieee80211_band band,
  713. u16 channel)
  714. {
  715. if (!iwl3945_get_channel_info(priv, band, channel)) {
  716. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  717. channel, band);
  718. return -EINVAL;
  719. }
  720. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  721. (priv->band == band))
  722. return 0;
  723. priv->staging_rxon.channel = cpu_to_le16(channel);
  724. if (band == IEEE80211_BAND_5GHZ)
  725. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  726. else
  727. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  728. priv->band = band;
  729. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  730. return 0;
  731. }
  732. /**
  733. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  734. *
  735. * NOTE: This is really only useful during development and can eventually
  736. * be #ifdef'd out once the driver is stable and folks aren't actively
  737. * making changes
  738. */
  739. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  740. {
  741. int error = 0;
  742. int counter = 1;
  743. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  744. error |= le32_to_cpu(rxon->flags &
  745. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  746. RXON_FLG_RADAR_DETECT_MSK));
  747. if (error)
  748. IWL_WARNING("check 24G fields %d | %d\n",
  749. counter++, error);
  750. } else {
  751. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  752. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  753. if (error)
  754. IWL_WARNING("check 52 fields %d | %d\n",
  755. counter++, error);
  756. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  757. if (error)
  758. IWL_WARNING("check 52 CCK %d | %d\n",
  759. counter++, error);
  760. }
  761. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  762. if (error)
  763. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  764. /* make sure basic rates 6Mbps and 1Mbps are supported */
  765. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  766. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  767. if (error)
  768. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  769. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  770. if (error)
  771. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  772. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  773. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  774. if (error)
  775. IWL_WARNING("check CCK and short slot %d | %d\n",
  776. counter++, error);
  777. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  778. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  779. if (error)
  780. IWL_WARNING("check CCK & auto detect %d | %d\n",
  781. counter++, error);
  782. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  783. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  784. if (error)
  785. IWL_WARNING("check TGG and auto detect %d | %d\n",
  786. counter++, error);
  787. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  788. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  789. RXON_FLG_ANT_A_MSK)) == 0);
  790. if (error)
  791. IWL_WARNING("check antenna %d %d\n", counter++, error);
  792. if (error)
  793. IWL_WARNING("Tuning to channel %d\n",
  794. le16_to_cpu(rxon->channel));
  795. if (error) {
  796. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  797. return -1;
  798. }
  799. return 0;
  800. }
  801. /**
  802. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  803. * @priv: staging_rxon is compared to active_rxon
  804. *
  805. * If the RXON structure is changing enough to require a new tune,
  806. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  807. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  808. */
  809. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  810. {
  811. /* These items are only settable from the full RXON command */
  812. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  813. compare_ether_addr(priv->staging_rxon.bssid_addr,
  814. priv->active_rxon.bssid_addr) ||
  815. compare_ether_addr(priv->staging_rxon.node_addr,
  816. priv->active_rxon.node_addr) ||
  817. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  818. priv->active_rxon.wlap_bssid_addr) ||
  819. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  820. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  821. (priv->staging_rxon.air_propagation !=
  822. priv->active_rxon.air_propagation) ||
  823. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  824. return 1;
  825. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  826. * be updated with the RXON_ASSOC command -- however only some
  827. * flag transitions are allowed using RXON_ASSOC */
  828. /* Check if we are not switching bands */
  829. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  830. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  831. return 1;
  832. /* Check if we are switching association toggle */
  833. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  834. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  835. return 1;
  836. return 0;
  837. }
  838. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  839. {
  840. int rc = 0;
  841. struct iwl3945_rx_packet *res = NULL;
  842. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  843. struct iwl3945_host_cmd cmd = {
  844. .id = REPLY_RXON_ASSOC,
  845. .len = sizeof(rxon_assoc),
  846. .meta.flags = CMD_WANT_SKB,
  847. .data = &rxon_assoc,
  848. };
  849. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  850. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  851. if ((rxon1->flags == rxon2->flags) &&
  852. (rxon1->filter_flags == rxon2->filter_flags) &&
  853. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  854. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  855. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  856. return 0;
  857. }
  858. rxon_assoc.flags = priv->staging_rxon.flags;
  859. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  860. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  861. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  862. rxon_assoc.reserved = 0;
  863. rc = iwl3945_send_cmd_sync(priv, &cmd);
  864. if (rc)
  865. return rc;
  866. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  867. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  868. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  869. rc = -EIO;
  870. }
  871. priv->alloc_rxb_skb--;
  872. dev_kfree_skb_any(cmd.meta.u.skb);
  873. return rc;
  874. }
  875. /**
  876. * iwl3945_commit_rxon - commit staging_rxon to hardware
  877. *
  878. * The RXON command in staging_rxon is committed to the hardware and
  879. * the active_rxon structure is updated with the new data. This
  880. * function correctly transitions out of the RXON_ASSOC_MSK state if
  881. * a HW tune is required based on the RXON structure changes.
  882. */
  883. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  884. {
  885. /* cast away the const for active_rxon in this function */
  886. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  887. int rc = 0;
  888. DECLARE_MAC_BUF(mac);
  889. if (!iwl3945_is_alive(priv))
  890. return -1;
  891. /* always get timestamp with Rx frame */
  892. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  893. /* select antenna */
  894. priv->staging_rxon.flags &=
  895. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  896. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  897. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  898. if (rc) {
  899. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  900. return -EINVAL;
  901. }
  902. /* If we don't need to send a full RXON, we can use
  903. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  904. * and other flags for the current radio configuration. */
  905. if (!iwl3945_full_rxon_required(priv)) {
  906. rc = iwl3945_send_rxon_assoc(priv);
  907. if (rc) {
  908. IWL_ERROR("Error setting RXON_ASSOC "
  909. "configuration (%d).\n", rc);
  910. return rc;
  911. }
  912. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  913. return 0;
  914. }
  915. /* If we are currently associated and the new config requires
  916. * an RXON_ASSOC and the new config wants the associated mask enabled,
  917. * we must clear the associated from the active configuration
  918. * before we apply the new config */
  919. if (iwl3945_is_associated(priv) &&
  920. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  921. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  922. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  923. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  924. sizeof(struct iwl3945_rxon_cmd),
  925. &priv->active_rxon);
  926. /* If the mask clearing failed then we set
  927. * active_rxon back to what it was previously */
  928. if (rc) {
  929. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  930. IWL_ERROR("Error clearing ASSOC_MSK on current "
  931. "configuration (%d).\n", rc);
  932. return rc;
  933. }
  934. }
  935. IWL_DEBUG_INFO("Sending RXON\n"
  936. "* with%s RXON_FILTER_ASSOC_MSK\n"
  937. "* channel = %d\n"
  938. "* bssid = %s\n",
  939. ((priv->staging_rxon.filter_flags &
  940. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  941. le16_to_cpu(priv->staging_rxon.channel),
  942. print_mac(mac, priv->staging_rxon.bssid_addr));
  943. /* Apply the new configuration */
  944. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  945. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  946. if (rc) {
  947. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  948. return rc;
  949. }
  950. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  951. iwl3945_clear_stations_table(priv);
  952. /* If we issue a new RXON command which required a tune then we must
  953. * send a new TXPOWER command or we won't be able to Tx any frames */
  954. rc = iwl3945_hw_reg_send_txpower(priv);
  955. if (rc) {
  956. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  957. return rc;
  958. }
  959. /* Add the broadcast address so we can send broadcast frames */
  960. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  961. IWL_INVALID_STATION) {
  962. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  963. return -EIO;
  964. }
  965. /* If we have set the ASSOC_MSK and we are in BSS mode then
  966. * add the IWL_AP_ID to the station rate table */
  967. if (iwl3945_is_associated(priv) &&
  968. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  969. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  970. == IWL_INVALID_STATION) {
  971. IWL_ERROR("Error adding AP address for transmit.\n");
  972. return -EIO;
  973. }
  974. /* Init the hardware's rate fallback order based on the band */
  975. rc = iwl3945_init_hw_rate_table(priv);
  976. if (rc) {
  977. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  978. return -EIO;
  979. }
  980. return 0;
  981. }
  982. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  983. {
  984. struct iwl3945_bt_cmd bt_cmd = {
  985. .flags = 3,
  986. .lead_time = 0xAA,
  987. .max_kill = 1,
  988. .kill_ack_mask = 0,
  989. .kill_cts_mask = 0,
  990. };
  991. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  992. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  993. }
  994. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  995. {
  996. int rc = 0;
  997. struct iwl3945_rx_packet *res;
  998. struct iwl3945_host_cmd cmd = {
  999. .id = REPLY_SCAN_ABORT_CMD,
  1000. .meta.flags = CMD_WANT_SKB,
  1001. };
  1002. /* If there isn't a scan actively going on in the hardware
  1003. * then we are in between scan bands and not actually
  1004. * actively scanning, so don't send the abort command */
  1005. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1006. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1007. return 0;
  1008. }
  1009. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1010. if (rc) {
  1011. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1012. return rc;
  1013. }
  1014. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1015. if (res->u.status != CAN_ABORT_STATUS) {
  1016. /* The scan abort will return 1 for success or
  1017. * 2 for "failure". A failure condition can be
  1018. * due to simply not being in an active scan which
  1019. * can occur if we send the scan abort before we
  1020. * the microcode has notified us that a scan is
  1021. * completed. */
  1022. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1023. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1024. clear_bit(STATUS_SCAN_HW, &priv->status);
  1025. }
  1026. dev_kfree_skb_any(cmd.meta.u.skb);
  1027. return rc;
  1028. }
  1029. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1030. struct iwl3945_cmd *cmd,
  1031. struct sk_buff *skb)
  1032. {
  1033. return 1;
  1034. }
  1035. /*
  1036. * CARD_STATE_CMD
  1037. *
  1038. * Use: Sets the device's internal card state to enable, disable, or halt
  1039. *
  1040. * When in the 'enable' state the card operates as normal.
  1041. * When in the 'disable' state, the card enters into a low power mode.
  1042. * When in the 'halt' state, the card is shut down and must be fully
  1043. * restarted to come back on.
  1044. */
  1045. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1046. {
  1047. struct iwl3945_host_cmd cmd = {
  1048. .id = REPLY_CARD_STATE_CMD,
  1049. .len = sizeof(u32),
  1050. .data = &flags,
  1051. .meta.flags = meta_flag,
  1052. };
  1053. if (meta_flag & CMD_ASYNC)
  1054. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1055. return iwl3945_send_cmd(priv, &cmd);
  1056. }
  1057. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1058. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1059. {
  1060. struct iwl3945_rx_packet *res = NULL;
  1061. if (!skb) {
  1062. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1063. return 1;
  1064. }
  1065. res = (struct iwl3945_rx_packet *)skb->data;
  1066. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1067. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1068. res->hdr.flags);
  1069. return 1;
  1070. }
  1071. switch (res->u.add_sta.status) {
  1072. case ADD_STA_SUCCESS_MSK:
  1073. break;
  1074. default:
  1075. break;
  1076. }
  1077. /* We didn't cache the SKB; let the caller free it */
  1078. return 1;
  1079. }
  1080. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1081. struct iwl3945_addsta_cmd *sta, u8 flags)
  1082. {
  1083. struct iwl3945_rx_packet *res = NULL;
  1084. int rc = 0;
  1085. struct iwl3945_host_cmd cmd = {
  1086. .id = REPLY_ADD_STA,
  1087. .len = sizeof(struct iwl3945_addsta_cmd),
  1088. .meta.flags = flags,
  1089. .data = sta,
  1090. };
  1091. if (flags & CMD_ASYNC)
  1092. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1093. else
  1094. cmd.meta.flags |= CMD_WANT_SKB;
  1095. rc = iwl3945_send_cmd(priv, &cmd);
  1096. if (rc || (flags & CMD_ASYNC))
  1097. return rc;
  1098. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1099. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1100. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1101. res->hdr.flags);
  1102. rc = -EIO;
  1103. }
  1104. if (rc == 0) {
  1105. switch (res->u.add_sta.status) {
  1106. case ADD_STA_SUCCESS_MSK:
  1107. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1108. break;
  1109. default:
  1110. rc = -EIO;
  1111. IWL_WARNING("REPLY_ADD_STA failed\n");
  1112. break;
  1113. }
  1114. }
  1115. priv->alloc_rxb_skb--;
  1116. dev_kfree_skb_any(cmd.meta.u.skb);
  1117. return rc;
  1118. }
  1119. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1120. struct ieee80211_key_conf *keyconf,
  1121. u8 sta_id)
  1122. {
  1123. unsigned long flags;
  1124. __le16 key_flags = 0;
  1125. switch (keyconf->alg) {
  1126. case ALG_CCMP:
  1127. key_flags |= STA_KEY_FLG_CCMP;
  1128. key_flags |= cpu_to_le16(
  1129. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1130. key_flags &= ~STA_KEY_FLG_INVALID;
  1131. break;
  1132. case ALG_TKIP:
  1133. case ALG_WEP:
  1134. default:
  1135. return -EINVAL;
  1136. }
  1137. spin_lock_irqsave(&priv->sta_lock, flags);
  1138. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1139. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1140. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1141. keyconf->keylen);
  1142. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1143. keyconf->keylen);
  1144. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1145. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1146. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1147. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1148. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1149. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1150. return 0;
  1151. }
  1152. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1153. {
  1154. unsigned long flags;
  1155. spin_lock_irqsave(&priv->sta_lock, flags);
  1156. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1157. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1158. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1159. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1160. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1161. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1162. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1163. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1164. return 0;
  1165. }
  1166. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1167. {
  1168. struct list_head *element;
  1169. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1170. priv->frames_count);
  1171. while (!list_empty(&priv->free_frames)) {
  1172. element = priv->free_frames.next;
  1173. list_del(element);
  1174. kfree(list_entry(element, struct iwl3945_frame, list));
  1175. priv->frames_count--;
  1176. }
  1177. if (priv->frames_count) {
  1178. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1179. priv->frames_count);
  1180. priv->frames_count = 0;
  1181. }
  1182. }
  1183. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1184. {
  1185. struct iwl3945_frame *frame;
  1186. struct list_head *element;
  1187. if (list_empty(&priv->free_frames)) {
  1188. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1189. if (!frame) {
  1190. IWL_ERROR("Could not allocate frame!\n");
  1191. return NULL;
  1192. }
  1193. priv->frames_count++;
  1194. return frame;
  1195. }
  1196. element = priv->free_frames.next;
  1197. list_del(element);
  1198. return list_entry(element, struct iwl3945_frame, list);
  1199. }
  1200. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1201. {
  1202. memset(frame, 0, sizeof(*frame));
  1203. list_add(&frame->list, &priv->free_frames);
  1204. }
  1205. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1206. struct ieee80211_hdr *hdr,
  1207. const u8 *dest, int left)
  1208. {
  1209. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1210. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1211. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1212. return 0;
  1213. if (priv->ibss_beacon->len > left)
  1214. return 0;
  1215. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1216. return priv->ibss_beacon->len;
  1217. }
  1218. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1219. {
  1220. u8 i;
  1221. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1222. i = iwl3945_rates[i].next_ieee) {
  1223. if (rate_mask & (1 << i))
  1224. return iwl3945_rates[i].plcp;
  1225. }
  1226. return IWL_RATE_INVALID;
  1227. }
  1228. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1229. {
  1230. struct iwl3945_frame *frame;
  1231. unsigned int frame_size;
  1232. int rc;
  1233. u8 rate;
  1234. frame = iwl3945_get_free_frame(priv);
  1235. if (!frame) {
  1236. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1237. "command.\n");
  1238. return -ENOMEM;
  1239. }
  1240. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1241. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1242. 0xFF0);
  1243. if (rate == IWL_INVALID_RATE)
  1244. rate = IWL_RATE_6M_PLCP;
  1245. } else {
  1246. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1247. if (rate == IWL_INVALID_RATE)
  1248. rate = IWL_RATE_1M_PLCP;
  1249. }
  1250. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1251. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1252. &frame->u.cmd[0]);
  1253. iwl3945_free_frame(priv, frame);
  1254. return rc;
  1255. }
  1256. /******************************************************************************
  1257. *
  1258. * EEPROM related functions
  1259. *
  1260. ******************************************************************************/
  1261. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1262. {
  1263. memcpy(mac, priv->eeprom.mac_address, 6);
  1264. }
  1265. /*
  1266. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1267. * embedded controller) as EEPROM reader; each read is a series of pulses
  1268. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1269. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1270. * simply claims ownership, which should be safe when this function is called
  1271. * (i.e. before loading uCode!).
  1272. */
  1273. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1274. {
  1275. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1276. return 0;
  1277. }
  1278. /**
  1279. * iwl3945_eeprom_init - read EEPROM contents
  1280. *
  1281. * Load the EEPROM contents from adapter into priv->eeprom
  1282. *
  1283. * NOTE: This routine uses the non-debug IO access functions.
  1284. */
  1285. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1286. {
  1287. u16 *e = (u16 *)&priv->eeprom;
  1288. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1289. u32 r;
  1290. int sz = sizeof(priv->eeprom);
  1291. int rc;
  1292. int i;
  1293. u16 addr;
  1294. /* The EEPROM structure has several padding buffers within it
  1295. * and when adding new EEPROM maps is subject to programmer errors
  1296. * which may be very difficult to identify without explicitly
  1297. * checking the resulting size of the eeprom map. */
  1298. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1299. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1300. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1301. return -ENOENT;
  1302. }
  1303. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1304. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1305. if (rc < 0) {
  1306. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1307. return -ENOENT;
  1308. }
  1309. /* eeprom is an array of 16bit values */
  1310. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1311. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1312. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1313. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1314. i += IWL_EEPROM_ACCESS_DELAY) {
  1315. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1316. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1317. break;
  1318. udelay(IWL_EEPROM_ACCESS_DELAY);
  1319. }
  1320. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1321. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1322. return -ETIMEDOUT;
  1323. }
  1324. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1325. }
  1326. return 0;
  1327. }
  1328. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1329. {
  1330. if (priv->hw_setting.shared_virt)
  1331. pci_free_consistent(priv->pci_dev,
  1332. sizeof(struct iwl3945_shared),
  1333. priv->hw_setting.shared_virt,
  1334. priv->hw_setting.shared_phys);
  1335. }
  1336. /**
  1337. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1338. *
  1339. * return : set the bit for each supported rate insert in ie
  1340. */
  1341. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1342. u16 basic_rate, int *left)
  1343. {
  1344. u16 ret_rates = 0, bit;
  1345. int i;
  1346. u8 *cnt = ie;
  1347. u8 *rates = ie + 1;
  1348. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1349. if (bit & supported_rate) {
  1350. ret_rates |= bit;
  1351. rates[*cnt] = iwl3945_rates[i].ieee |
  1352. ((bit & basic_rate) ? 0x80 : 0x00);
  1353. (*cnt)++;
  1354. (*left)--;
  1355. if ((*left <= 0) ||
  1356. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1357. break;
  1358. }
  1359. }
  1360. return ret_rates;
  1361. }
  1362. /**
  1363. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1364. */
  1365. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1366. struct ieee80211_mgmt *frame,
  1367. int left, int is_direct)
  1368. {
  1369. int len = 0;
  1370. u8 *pos = NULL;
  1371. u16 active_rates, ret_rates, cck_rates;
  1372. /* Make sure there is enough space for the probe request,
  1373. * two mandatory IEs and the data */
  1374. left -= 24;
  1375. if (left < 0)
  1376. return 0;
  1377. len += 24;
  1378. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1379. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1380. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1381. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1382. frame->seq_ctrl = 0;
  1383. /* fill in our indirect SSID IE */
  1384. /* ...next IE... */
  1385. left -= 2;
  1386. if (left < 0)
  1387. return 0;
  1388. len += 2;
  1389. pos = &(frame->u.probe_req.variable[0]);
  1390. *pos++ = WLAN_EID_SSID;
  1391. *pos++ = 0;
  1392. /* fill in our direct SSID IE... */
  1393. if (is_direct) {
  1394. /* ...next IE... */
  1395. left -= 2 + priv->essid_len;
  1396. if (left < 0)
  1397. return 0;
  1398. /* ... fill it in... */
  1399. *pos++ = WLAN_EID_SSID;
  1400. *pos++ = priv->essid_len;
  1401. memcpy(pos, priv->essid, priv->essid_len);
  1402. pos += priv->essid_len;
  1403. len += 2 + priv->essid_len;
  1404. }
  1405. /* fill in supported rate */
  1406. /* ...next IE... */
  1407. left -= 2;
  1408. if (left < 0)
  1409. return 0;
  1410. /* ... fill it in... */
  1411. *pos++ = WLAN_EID_SUPP_RATES;
  1412. *pos = 0;
  1413. priv->active_rate = priv->rates_mask;
  1414. active_rates = priv->active_rate;
  1415. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1416. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1417. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1418. priv->active_rate_basic, &left);
  1419. active_rates &= ~ret_rates;
  1420. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1421. priv->active_rate_basic, &left);
  1422. active_rates &= ~ret_rates;
  1423. len += 2 + *pos;
  1424. pos += (*pos) + 1;
  1425. if (active_rates == 0)
  1426. goto fill_end;
  1427. /* fill in supported extended rate */
  1428. /* ...next IE... */
  1429. left -= 2;
  1430. if (left < 0)
  1431. return 0;
  1432. /* ... fill it in... */
  1433. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1434. *pos = 0;
  1435. iwl3945_supported_rate_to_ie(pos, active_rates,
  1436. priv->active_rate_basic, &left);
  1437. if (*pos > 0)
  1438. len += 2 + *pos;
  1439. fill_end:
  1440. return (u16)len;
  1441. }
  1442. /*
  1443. * QoS support
  1444. */
  1445. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1446. struct iwl3945_qosparam_cmd *qos)
  1447. {
  1448. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1449. sizeof(struct iwl3945_qosparam_cmd), qos);
  1450. }
  1451. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1452. {
  1453. u16 cw_min = 15;
  1454. u16 cw_max = 1023;
  1455. u8 aifs = 2;
  1456. u8 is_legacy = 0;
  1457. unsigned long flags;
  1458. int i;
  1459. spin_lock_irqsave(&priv->lock, flags);
  1460. priv->qos_data.qos_active = 0;
  1461. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1462. if (priv->qos_data.qos_enable)
  1463. priv->qos_data.qos_active = 1;
  1464. if (!(priv->active_rate & 0xfff0)) {
  1465. cw_min = 31;
  1466. is_legacy = 1;
  1467. }
  1468. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1469. if (priv->qos_data.qos_enable)
  1470. priv->qos_data.qos_active = 1;
  1471. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1472. cw_min = 31;
  1473. is_legacy = 1;
  1474. }
  1475. if (priv->qos_data.qos_active)
  1476. aifs = 3;
  1477. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1478. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1479. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1480. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1481. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1482. if (priv->qos_data.qos_active) {
  1483. i = 1;
  1484. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1485. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1486. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1487. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1488. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1489. i = 2;
  1490. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1491. cpu_to_le16((cw_min + 1) / 2 - 1);
  1492. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1493. cpu_to_le16(cw_max);
  1494. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1495. if (is_legacy)
  1496. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1497. cpu_to_le16(6016);
  1498. else
  1499. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1500. cpu_to_le16(3008);
  1501. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1502. i = 3;
  1503. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1504. cpu_to_le16((cw_min + 1) / 4 - 1);
  1505. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1506. cpu_to_le16((cw_max + 1) / 2 - 1);
  1507. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1508. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1509. if (is_legacy)
  1510. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1511. cpu_to_le16(3264);
  1512. else
  1513. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1514. cpu_to_le16(1504);
  1515. } else {
  1516. for (i = 1; i < 4; i++) {
  1517. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1518. cpu_to_le16(cw_min);
  1519. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1520. cpu_to_le16(cw_max);
  1521. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1522. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1523. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1524. }
  1525. }
  1526. IWL_DEBUG_QOS("set QoS to default \n");
  1527. spin_unlock_irqrestore(&priv->lock, flags);
  1528. }
  1529. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1530. {
  1531. unsigned long flags;
  1532. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1533. return;
  1534. if (!priv->qos_data.qos_enable)
  1535. return;
  1536. spin_lock_irqsave(&priv->lock, flags);
  1537. priv->qos_data.def_qos_parm.qos_flags = 0;
  1538. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1539. !priv->qos_data.qos_cap.q_AP.txop_request)
  1540. priv->qos_data.def_qos_parm.qos_flags |=
  1541. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1542. if (priv->qos_data.qos_active)
  1543. priv->qos_data.def_qos_parm.qos_flags |=
  1544. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1545. spin_unlock_irqrestore(&priv->lock, flags);
  1546. if (force || iwl3945_is_associated(priv)) {
  1547. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1548. priv->qos_data.qos_active);
  1549. iwl3945_send_qos_params_command(priv,
  1550. &(priv->qos_data.def_qos_parm));
  1551. }
  1552. }
  1553. /*
  1554. * Power management (not Tx power!) functions
  1555. */
  1556. #define MSEC_TO_USEC 1024
  1557. #define NOSLP __constant_cpu_to_le32(0)
  1558. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1559. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1560. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1561. __constant_cpu_to_le32(X1), \
  1562. __constant_cpu_to_le32(X2), \
  1563. __constant_cpu_to_le32(X3), \
  1564. __constant_cpu_to_le32(X4)}
  1565. /* default power management (not Tx power) table values */
  1566. /* for tim 0-10 */
  1567. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1568. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1569. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1570. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1571. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1572. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1573. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1574. };
  1575. /* for tim > 10 */
  1576. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1577. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1578. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1579. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1580. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1581. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1582. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1583. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1584. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1585. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1586. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1587. };
  1588. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1589. {
  1590. int rc = 0, i;
  1591. struct iwl3945_power_mgr *pow_data;
  1592. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1593. u16 pci_pm;
  1594. IWL_DEBUG_POWER("Initialize power \n");
  1595. pow_data = &(priv->power_data);
  1596. memset(pow_data, 0, sizeof(*pow_data));
  1597. pow_data->active_index = IWL_POWER_RANGE_0;
  1598. pow_data->dtim_val = 0xffff;
  1599. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1600. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1601. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1602. if (rc != 0)
  1603. return 0;
  1604. else {
  1605. struct iwl3945_powertable_cmd *cmd;
  1606. IWL_DEBUG_POWER("adjust power command flags\n");
  1607. for (i = 0; i < IWL_POWER_AC; i++) {
  1608. cmd = &pow_data->pwr_range_0[i].cmd;
  1609. if (pci_pm & 0x1)
  1610. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1611. else
  1612. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1613. }
  1614. }
  1615. return rc;
  1616. }
  1617. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1618. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1619. {
  1620. int rc = 0, i;
  1621. u8 skip;
  1622. u32 max_sleep = 0;
  1623. struct iwl3945_power_vec_entry *range;
  1624. u8 period = 0;
  1625. struct iwl3945_power_mgr *pow_data;
  1626. if (mode > IWL_POWER_INDEX_5) {
  1627. IWL_DEBUG_POWER("Error invalid power mode \n");
  1628. return -1;
  1629. }
  1630. pow_data = &(priv->power_data);
  1631. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1632. range = &pow_data->pwr_range_0[0];
  1633. else
  1634. range = &pow_data->pwr_range_1[1];
  1635. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1636. #ifdef IWL_MAC80211_DISABLE
  1637. if (priv->assoc_network != NULL) {
  1638. unsigned long flags;
  1639. period = priv->assoc_network->tim.tim_period;
  1640. }
  1641. #endif /*IWL_MAC80211_DISABLE */
  1642. skip = range[mode].no_dtim;
  1643. if (period == 0) {
  1644. period = 1;
  1645. skip = 0;
  1646. }
  1647. if (skip == 0) {
  1648. max_sleep = period;
  1649. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1650. } else {
  1651. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1652. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1653. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1654. }
  1655. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1656. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1657. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1658. }
  1659. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1660. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1661. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1662. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1663. le32_to_cpu(cmd->sleep_interval[0]),
  1664. le32_to_cpu(cmd->sleep_interval[1]),
  1665. le32_to_cpu(cmd->sleep_interval[2]),
  1666. le32_to_cpu(cmd->sleep_interval[3]),
  1667. le32_to_cpu(cmd->sleep_interval[4]));
  1668. return rc;
  1669. }
  1670. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1671. {
  1672. u32 uninitialized_var(final_mode);
  1673. int rc;
  1674. struct iwl3945_powertable_cmd cmd;
  1675. /* If on battery, set to 3,
  1676. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1677. * else user level */
  1678. switch (mode) {
  1679. case IWL_POWER_BATTERY:
  1680. final_mode = IWL_POWER_INDEX_3;
  1681. break;
  1682. case IWL_POWER_AC:
  1683. final_mode = IWL_POWER_MODE_CAM;
  1684. break;
  1685. default:
  1686. final_mode = mode;
  1687. break;
  1688. }
  1689. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1690. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1691. if (final_mode == IWL_POWER_MODE_CAM)
  1692. clear_bit(STATUS_POWER_PMI, &priv->status);
  1693. else
  1694. set_bit(STATUS_POWER_PMI, &priv->status);
  1695. return rc;
  1696. }
  1697. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1698. {
  1699. /* Filter incoming packets to determine if they are targeted toward
  1700. * this network, discarding packets coming from ourselves */
  1701. switch (priv->iw_mode) {
  1702. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1703. /* packets from our adapter are dropped (echo) */
  1704. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1705. return 0;
  1706. /* {broad,multi}cast packets to our IBSS go through */
  1707. if (is_multicast_ether_addr(header->addr1))
  1708. return !compare_ether_addr(header->addr3, priv->bssid);
  1709. /* packets to our adapter go through */
  1710. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1711. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1712. /* packets from our adapter are dropped (echo) */
  1713. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1714. return 0;
  1715. /* {broad,multi}cast packets to our BSS go through */
  1716. if (is_multicast_ether_addr(header->addr1))
  1717. return !compare_ether_addr(header->addr2, priv->bssid);
  1718. /* packets to our adapter go through */
  1719. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1720. default:
  1721. return 1;
  1722. }
  1723. return 1;
  1724. }
  1725. /**
  1726. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1727. *
  1728. * NOTE: priv->mutex is not required before calling this function
  1729. */
  1730. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1731. {
  1732. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1733. clear_bit(STATUS_SCANNING, &priv->status);
  1734. return 0;
  1735. }
  1736. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1737. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1738. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1739. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1740. queue_work(priv->workqueue, &priv->abort_scan);
  1741. } else
  1742. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1743. return test_bit(STATUS_SCANNING, &priv->status);
  1744. }
  1745. return 0;
  1746. }
  1747. /**
  1748. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1749. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1750. *
  1751. * NOTE: priv->mutex must be held before calling this function
  1752. */
  1753. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1754. {
  1755. unsigned long now = jiffies;
  1756. int ret;
  1757. ret = iwl3945_scan_cancel(priv);
  1758. if (ret && ms) {
  1759. mutex_unlock(&priv->mutex);
  1760. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1761. test_bit(STATUS_SCANNING, &priv->status))
  1762. msleep(1);
  1763. mutex_lock(&priv->mutex);
  1764. return test_bit(STATUS_SCANNING, &priv->status);
  1765. }
  1766. return ret;
  1767. }
  1768. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1769. {
  1770. /* Reset ieee stats */
  1771. /* We don't reset the net_device_stats (ieee->stats) on
  1772. * re-association */
  1773. priv->last_seq_num = -1;
  1774. priv->last_frag_num = -1;
  1775. priv->last_packet_time = 0;
  1776. iwl3945_scan_cancel(priv);
  1777. }
  1778. #define MAX_UCODE_BEACON_INTERVAL 1024
  1779. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1780. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1781. {
  1782. u16 new_val = 0;
  1783. u16 beacon_factor = 0;
  1784. beacon_factor =
  1785. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1786. / MAX_UCODE_BEACON_INTERVAL;
  1787. new_val = beacon_val / beacon_factor;
  1788. return cpu_to_le16(new_val);
  1789. }
  1790. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1791. {
  1792. u64 interval_tm_unit;
  1793. u64 tsf, result;
  1794. unsigned long flags;
  1795. struct ieee80211_conf *conf = NULL;
  1796. u16 beacon_int = 0;
  1797. conf = ieee80211_get_hw_conf(priv->hw);
  1798. spin_lock_irqsave(&priv->lock, flags);
  1799. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1800. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1801. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1802. tsf = priv->timestamp1;
  1803. tsf = ((tsf << 32) | priv->timestamp0);
  1804. beacon_int = priv->beacon_int;
  1805. spin_unlock_irqrestore(&priv->lock, flags);
  1806. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1807. if (beacon_int == 0) {
  1808. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1809. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1810. } else {
  1811. priv->rxon_timing.beacon_interval =
  1812. cpu_to_le16(beacon_int);
  1813. priv->rxon_timing.beacon_interval =
  1814. iwl3945_adjust_beacon_interval(
  1815. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1816. }
  1817. priv->rxon_timing.atim_window = 0;
  1818. } else {
  1819. priv->rxon_timing.beacon_interval =
  1820. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1821. /* TODO: we need to get atim_window from upper stack
  1822. * for now we set to 0 */
  1823. priv->rxon_timing.atim_window = 0;
  1824. }
  1825. interval_tm_unit =
  1826. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1827. result = do_div(tsf, interval_tm_unit);
  1828. priv->rxon_timing.beacon_init_val =
  1829. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1830. IWL_DEBUG_ASSOC
  1831. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1832. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1833. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1834. le16_to_cpu(priv->rxon_timing.atim_window));
  1835. }
  1836. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1837. {
  1838. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1839. IWL_ERROR("APs don't scan.\n");
  1840. return 0;
  1841. }
  1842. if (!iwl3945_is_ready_rf(priv)) {
  1843. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1844. return -EIO;
  1845. }
  1846. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1847. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1848. return -EAGAIN;
  1849. }
  1850. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1851. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1852. "Queuing.\n");
  1853. return -EAGAIN;
  1854. }
  1855. IWL_DEBUG_INFO("Starting scan...\n");
  1856. priv->scan_bands = 2;
  1857. set_bit(STATUS_SCANNING, &priv->status);
  1858. priv->scan_start = jiffies;
  1859. priv->scan_pass_start = priv->scan_start;
  1860. queue_work(priv->workqueue, &priv->request_scan);
  1861. return 0;
  1862. }
  1863. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1864. {
  1865. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1866. if (hw_decrypt)
  1867. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1868. else
  1869. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1870. return 0;
  1871. }
  1872. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1873. enum ieee80211_band band)
  1874. {
  1875. if (band == IEEE80211_BAND_5GHZ) {
  1876. priv->staging_rxon.flags &=
  1877. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1878. | RXON_FLG_CCK_MSK);
  1879. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1880. } else {
  1881. /* Copied from iwl3945_bg_post_associate() */
  1882. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1883. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1884. else
  1885. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1886. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1887. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1888. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1889. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1890. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1891. }
  1892. }
  1893. /*
  1894. * initialize rxon structure with default values from eeprom
  1895. */
  1896. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1897. {
  1898. const struct iwl3945_channel_info *ch_info;
  1899. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1900. switch (priv->iw_mode) {
  1901. case IEEE80211_IF_TYPE_AP:
  1902. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1903. break;
  1904. case IEEE80211_IF_TYPE_STA:
  1905. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1906. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1907. break;
  1908. case IEEE80211_IF_TYPE_IBSS:
  1909. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1910. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1911. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1912. RXON_FILTER_ACCEPT_GRP_MSK;
  1913. break;
  1914. case IEEE80211_IF_TYPE_MNTR:
  1915. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1916. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1917. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1918. break;
  1919. default:
  1920. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1921. break;
  1922. }
  1923. #if 0
  1924. /* TODO: Figure out when short_preamble would be set and cache from
  1925. * that */
  1926. if (!hw_to_local(priv->hw)->short_preamble)
  1927. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1928. else
  1929. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1930. #endif
  1931. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1932. le16_to_cpu(priv->staging_rxon.channel));
  1933. if (!ch_info)
  1934. ch_info = &priv->channel_info[0];
  1935. /*
  1936. * in some case A channels are all non IBSS
  1937. * in this case force B/G channel
  1938. */
  1939. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1940. !(is_channel_ibss(ch_info)))
  1941. ch_info = &priv->channel_info[0];
  1942. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1943. if (is_channel_a_band(ch_info))
  1944. priv->band = IEEE80211_BAND_5GHZ;
  1945. else
  1946. priv->band = IEEE80211_BAND_2GHZ;
  1947. iwl3945_set_flags_for_phymode(priv, priv->band);
  1948. priv->staging_rxon.ofdm_basic_rates =
  1949. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1950. priv->staging_rxon.cck_basic_rates =
  1951. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1952. }
  1953. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1954. {
  1955. if (mode == IEEE80211_IF_TYPE_IBSS) {
  1956. const struct iwl3945_channel_info *ch_info;
  1957. ch_info = iwl3945_get_channel_info(priv,
  1958. priv->band,
  1959. le16_to_cpu(priv->staging_rxon.channel));
  1960. if (!ch_info || !is_channel_ibss(ch_info)) {
  1961. IWL_ERROR("channel %d not IBSS channel\n",
  1962. le16_to_cpu(priv->staging_rxon.channel));
  1963. return -EINVAL;
  1964. }
  1965. }
  1966. priv->iw_mode = mode;
  1967. iwl3945_connection_init_rx_config(priv);
  1968. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1969. iwl3945_clear_stations_table(priv);
  1970. /* dont commit rxon if rf-kill is on*/
  1971. if (!iwl3945_is_ready_rf(priv))
  1972. return -EAGAIN;
  1973. cancel_delayed_work(&priv->scan_check);
  1974. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1975. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1976. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1977. return -EAGAIN;
  1978. }
  1979. iwl3945_commit_rxon(priv);
  1980. return 0;
  1981. }
  1982. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1983. struct ieee80211_tx_info *info,
  1984. struct iwl3945_cmd *cmd,
  1985. struct sk_buff *skb_frag,
  1986. int last_frag)
  1987. {
  1988. struct iwl3945_hw_key *keyinfo =
  1989. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1990. switch (keyinfo->alg) {
  1991. case ALG_CCMP:
  1992. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1993. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1994. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  1995. break;
  1996. case ALG_TKIP:
  1997. #if 0
  1998. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1999. if (last_frag)
  2000. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2001. 8);
  2002. else
  2003. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2004. #endif
  2005. break;
  2006. case ALG_WEP:
  2007. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2008. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2009. if (keyinfo->keylen == 13)
  2010. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2011. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2012. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2013. "with key %d\n", info->control.hw_key->hw_key_idx);
  2014. break;
  2015. default:
  2016. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2017. break;
  2018. }
  2019. }
  2020. /*
  2021. * handle build REPLY_TX command notification.
  2022. */
  2023. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2024. struct iwl3945_cmd *cmd,
  2025. struct ieee80211_tx_info *info,
  2026. struct ieee80211_hdr *hdr,
  2027. int is_unicast, u8 std_id)
  2028. {
  2029. u16 fc = le16_to_cpu(hdr->frame_control);
  2030. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2031. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2032. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  2033. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2034. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2035. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2036. if (ieee80211_is_probe_response(fc) &&
  2037. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2038. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2039. } else {
  2040. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2041. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2042. }
  2043. cmd->cmd.tx.sta_id = std_id;
  2044. if (ieee80211_get_morefrag(hdr))
  2045. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2046. if (ieee80211_is_qos_data(fc)) {
  2047. u8 *qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
  2048. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  2049. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2050. } else {
  2051. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2052. }
  2053. if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
  2054. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2055. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2056. } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
  2057. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2058. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2059. }
  2060. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2061. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2062. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2063. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2064. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2065. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2066. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2067. else
  2068. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2069. } else {
  2070. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2071. #ifdef CONFIG_IWL3945_LEDS
  2072. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  2073. #endif
  2074. }
  2075. cmd->cmd.tx.driver_txop = 0;
  2076. cmd->cmd.tx.tx_flags = tx_flags;
  2077. cmd->cmd.tx.next_frame_len = 0;
  2078. }
  2079. /**
  2080. * iwl3945_get_sta_id - Find station's index within station table
  2081. */
  2082. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2083. {
  2084. int sta_id;
  2085. u16 fc = le16_to_cpu(hdr->frame_control);
  2086. /* If this frame is broadcast or management, use broadcast station id */
  2087. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2088. is_multicast_ether_addr(hdr->addr1))
  2089. return priv->hw_setting.bcast_sta_id;
  2090. switch (priv->iw_mode) {
  2091. /* If we are a client station in a BSS network, use the special
  2092. * AP station entry (that's the only station we communicate with) */
  2093. case IEEE80211_IF_TYPE_STA:
  2094. return IWL_AP_ID;
  2095. /* If we are an AP, then find the station, or use BCAST */
  2096. case IEEE80211_IF_TYPE_AP:
  2097. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2098. if (sta_id != IWL_INVALID_STATION)
  2099. return sta_id;
  2100. return priv->hw_setting.bcast_sta_id;
  2101. /* If this frame is going out to an IBSS network, find the station,
  2102. * or create a new station table entry */
  2103. case IEEE80211_IF_TYPE_IBSS: {
  2104. DECLARE_MAC_BUF(mac);
  2105. /* Create new station table entry */
  2106. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2107. if (sta_id != IWL_INVALID_STATION)
  2108. return sta_id;
  2109. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2110. if (sta_id != IWL_INVALID_STATION)
  2111. return sta_id;
  2112. IWL_DEBUG_DROP("Station %s not in station map. "
  2113. "Defaulting to broadcast...\n",
  2114. print_mac(mac, hdr->addr1));
  2115. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2116. return priv->hw_setting.bcast_sta_id;
  2117. }
  2118. default:
  2119. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2120. return priv->hw_setting.bcast_sta_id;
  2121. }
  2122. }
  2123. /*
  2124. * start REPLY_TX command process
  2125. */
  2126. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2127. {
  2128. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2129. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2130. struct iwl3945_tfd_frame *tfd;
  2131. u32 *control_flags;
  2132. int txq_id = skb_get_queue_mapping(skb);
  2133. struct iwl3945_tx_queue *txq = NULL;
  2134. struct iwl3945_queue *q = NULL;
  2135. dma_addr_t phys_addr;
  2136. dma_addr_t txcmd_phys;
  2137. struct iwl3945_cmd *out_cmd = NULL;
  2138. u16 len, idx, len_org, hdr_len;
  2139. u8 id;
  2140. u8 unicast;
  2141. u8 sta_id;
  2142. u8 tid = 0;
  2143. u16 seq_number = 0;
  2144. u16 fc;
  2145. u8 wait_write_ptr = 0;
  2146. u8 *qc = NULL;
  2147. unsigned long flags;
  2148. int rc;
  2149. spin_lock_irqsave(&priv->lock, flags);
  2150. if (iwl3945_is_rfkill(priv)) {
  2151. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2152. goto drop_unlock;
  2153. }
  2154. if (!priv->vif) {
  2155. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2156. goto drop_unlock;
  2157. }
  2158. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2159. IWL_ERROR("ERROR: No TX rate available.\n");
  2160. goto drop_unlock;
  2161. }
  2162. unicast = !is_multicast_ether_addr(hdr->addr1);
  2163. id = 0;
  2164. fc = le16_to_cpu(hdr->frame_control);
  2165. #ifdef CONFIG_IWL3945_DEBUG
  2166. if (ieee80211_is_auth(fc))
  2167. IWL_DEBUG_TX("Sending AUTH frame\n");
  2168. else if (ieee80211_is_assoc_request(fc))
  2169. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2170. else if (ieee80211_is_reassoc_request(fc))
  2171. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2172. #endif
  2173. /* drop all data frame if we are not associated */
  2174. if ((!iwl3945_is_associated(priv) ||
  2175. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2176. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2177. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2178. goto drop_unlock;
  2179. }
  2180. spin_unlock_irqrestore(&priv->lock, flags);
  2181. hdr_len = ieee80211_get_hdrlen(fc);
  2182. /* Find (or create) index into station table for destination station */
  2183. sta_id = iwl3945_get_sta_id(priv, hdr);
  2184. if (sta_id == IWL_INVALID_STATION) {
  2185. DECLARE_MAC_BUF(mac);
  2186. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2187. print_mac(mac, hdr->addr1));
  2188. goto drop;
  2189. }
  2190. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2191. if (ieee80211_is_qos_data(fc)) {
  2192. qc = ieee80211_get_qos_ctrl(hdr, hdr_len);
  2193. tid = qc[0] & 0xf;
  2194. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2195. IEEE80211_SCTL_SEQ;
  2196. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2197. (hdr->seq_ctrl &
  2198. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2199. seq_number += 0x10;
  2200. }
  2201. /* Descriptor for chosen Tx queue */
  2202. txq = &priv->txq[txq_id];
  2203. q = &txq->q;
  2204. spin_lock_irqsave(&priv->lock, flags);
  2205. /* Set up first empty TFD within this queue's circular TFD buffer */
  2206. tfd = &txq->bd[q->write_ptr];
  2207. memset(tfd, 0, sizeof(*tfd));
  2208. control_flags = (u32 *) tfd;
  2209. idx = get_cmd_index(q, q->write_ptr, 0);
  2210. /* Set up driver data for this TFD */
  2211. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2212. txq->txb[q->write_ptr].skb[0] = skb;
  2213. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2214. out_cmd = &txq->cmd[idx];
  2215. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2216. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2217. /*
  2218. * Set up the Tx-command (not MAC!) header.
  2219. * Store the chosen Tx queue and TFD index within the sequence field;
  2220. * after Tx, uCode's Tx response will return this value so driver can
  2221. * locate the frame within the tx queue and do post-tx processing.
  2222. */
  2223. out_cmd->hdr.cmd = REPLY_TX;
  2224. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2225. INDEX_TO_SEQ(q->write_ptr)));
  2226. /* Copy MAC header from skb into command buffer */
  2227. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2228. /*
  2229. * Use the first empty entry in this queue's command buffer array
  2230. * to contain the Tx command and MAC header concatenated together
  2231. * (payload data will be in another buffer).
  2232. * Size of this varies, due to varying MAC header length.
  2233. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2234. * of the MAC header (device reads on dword boundaries).
  2235. * We'll tell device about this padding later.
  2236. */
  2237. len = priv->hw_setting.tx_cmd_len +
  2238. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2239. len_org = len;
  2240. len = (len + 3) & ~3;
  2241. if (len_org != len)
  2242. len_org = 1;
  2243. else
  2244. len_org = 0;
  2245. /* Physical address of this Tx command's header (not MAC header!),
  2246. * within command buffer array. */
  2247. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2248. offsetof(struct iwl3945_cmd, hdr);
  2249. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2250. * first entry */
  2251. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2252. if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
  2253. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2254. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2255. * if any (802.11 null frames have no payload). */
  2256. len = skb->len - hdr_len;
  2257. if (len) {
  2258. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2259. len, PCI_DMA_TODEVICE);
  2260. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2261. }
  2262. if (!len)
  2263. /* If there is no payload, then we use only one Tx buffer */
  2264. *control_flags = TFD_CTL_COUNT_SET(1);
  2265. else
  2266. /* Else use 2 buffers.
  2267. * Tell 3945 about any padding after MAC header */
  2268. *control_flags = TFD_CTL_COUNT_SET(2) |
  2269. TFD_CTL_PAD_SET(U32_PAD(len));
  2270. /* Total # bytes to be transmitted */
  2271. len = (u16)skb->len;
  2272. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2273. /* TODO need this for burst mode later on */
  2274. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2275. /* set is_hcca to 0; it probably will never be implemented */
  2276. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2277. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2278. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2279. if (!ieee80211_get_morefrag(hdr)) {
  2280. txq->need_update = 1;
  2281. if (qc) {
  2282. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2283. }
  2284. } else {
  2285. wait_write_ptr = 1;
  2286. txq->need_update = 0;
  2287. }
  2288. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2289. sizeof(out_cmd->cmd.tx));
  2290. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2291. ieee80211_get_hdrlen(fc));
  2292. /* Tell device the write index *just past* this latest filled TFD */
  2293. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2294. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2295. spin_unlock_irqrestore(&priv->lock, flags);
  2296. if (rc)
  2297. return rc;
  2298. if ((iwl3945_queue_space(q) < q->high_mark)
  2299. && priv->mac80211_registered) {
  2300. if (wait_write_ptr) {
  2301. spin_lock_irqsave(&priv->lock, flags);
  2302. txq->need_update = 1;
  2303. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2304. spin_unlock_irqrestore(&priv->lock, flags);
  2305. }
  2306. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2307. }
  2308. return 0;
  2309. drop_unlock:
  2310. spin_unlock_irqrestore(&priv->lock, flags);
  2311. drop:
  2312. return -1;
  2313. }
  2314. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2315. {
  2316. const struct ieee80211_supported_band *sband = NULL;
  2317. struct ieee80211_rate *rate;
  2318. int i;
  2319. sband = iwl3945_get_band(priv, priv->band);
  2320. if (!sband) {
  2321. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2322. return;
  2323. }
  2324. priv->active_rate = 0;
  2325. priv->active_rate_basic = 0;
  2326. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2327. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2328. for (i = 0; i < sband->n_bitrates; i++) {
  2329. rate = &sband->bitrates[i];
  2330. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2331. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2332. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2333. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2334. priv->active_rate |= (1 << rate->hw_value);
  2335. }
  2336. }
  2337. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2338. priv->active_rate, priv->active_rate_basic);
  2339. /*
  2340. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2341. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2342. * OFDM
  2343. */
  2344. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2345. priv->staging_rxon.cck_basic_rates =
  2346. ((priv->active_rate_basic &
  2347. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2348. else
  2349. priv->staging_rxon.cck_basic_rates =
  2350. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2351. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2352. priv->staging_rxon.ofdm_basic_rates =
  2353. ((priv->active_rate_basic &
  2354. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2355. IWL_FIRST_OFDM_RATE) & 0xFF;
  2356. else
  2357. priv->staging_rxon.ofdm_basic_rates =
  2358. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2359. }
  2360. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2361. {
  2362. unsigned long flags;
  2363. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2364. return;
  2365. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2366. disable_radio ? "OFF" : "ON");
  2367. if (disable_radio) {
  2368. iwl3945_scan_cancel(priv);
  2369. /* FIXME: This is a workaround for AP */
  2370. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2371. spin_lock_irqsave(&priv->lock, flags);
  2372. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2373. CSR_UCODE_SW_BIT_RFKILL);
  2374. spin_unlock_irqrestore(&priv->lock, flags);
  2375. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2376. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2377. }
  2378. return;
  2379. }
  2380. spin_lock_irqsave(&priv->lock, flags);
  2381. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2382. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2383. spin_unlock_irqrestore(&priv->lock, flags);
  2384. /* wake up ucode */
  2385. msleep(10);
  2386. spin_lock_irqsave(&priv->lock, flags);
  2387. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2388. if (!iwl3945_grab_nic_access(priv))
  2389. iwl3945_release_nic_access(priv);
  2390. spin_unlock_irqrestore(&priv->lock, flags);
  2391. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2392. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2393. "disabled by HW switch\n");
  2394. return;
  2395. }
  2396. queue_work(priv->workqueue, &priv->restart);
  2397. return;
  2398. }
  2399. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2400. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2401. {
  2402. u16 fc =
  2403. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2404. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2405. return;
  2406. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2407. return;
  2408. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2409. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2410. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2411. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2412. RX_RES_STATUS_BAD_ICV_MIC)
  2413. stats->flag |= RX_FLAG_MMIC_ERROR;
  2414. case RX_RES_STATUS_SEC_TYPE_WEP:
  2415. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2416. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2417. RX_RES_STATUS_DECRYPT_OK) {
  2418. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2419. stats->flag |= RX_FLAG_DECRYPTED;
  2420. }
  2421. break;
  2422. default:
  2423. break;
  2424. }
  2425. }
  2426. #define IWL_PACKET_RETRY_TIME HZ
  2427. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2428. {
  2429. u16 sc = le16_to_cpu(header->seq_ctrl);
  2430. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2431. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2432. u16 *last_seq, *last_frag;
  2433. unsigned long *last_time;
  2434. switch (priv->iw_mode) {
  2435. case IEEE80211_IF_TYPE_IBSS:{
  2436. struct list_head *p;
  2437. struct iwl3945_ibss_seq *entry = NULL;
  2438. u8 *mac = header->addr2;
  2439. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2440. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2441. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2442. if (!compare_ether_addr(entry->mac, mac))
  2443. break;
  2444. }
  2445. if (p == &priv->ibss_mac_hash[index]) {
  2446. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2447. if (!entry) {
  2448. IWL_ERROR("Cannot malloc new mac entry\n");
  2449. return 0;
  2450. }
  2451. memcpy(entry->mac, mac, ETH_ALEN);
  2452. entry->seq_num = seq;
  2453. entry->frag_num = frag;
  2454. entry->packet_time = jiffies;
  2455. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2456. return 0;
  2457. }
  2458. last_seq = &entry->seq_num;
  2459. last_frag = &entry->frag_num;
  2460. last_time = &entry->packet_time;
  2461. break;
  2462. }
  2463. case IEEE80211_IF_TYPE_STA:
  2464. last_seq = &priv->last_seq_num;
  2465. last_frag = &priv->last_frag_num;
  2466. last_time = &priv->last_packet_time;
  2467. break;
  2468. default:
  2469. return 0;
  2470. }
  2471. if ((*last_seq == seq) &&
  2472. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2473. if (*last_frag == frag)
  2474. goto drop;
  2475. if (*last_frag + 1 != frag)
  2476. /* out-of-order fragment */
  2477. goto drop;
  2478. } else
  2479. *last_seq = seq;
  2480. *last_frag = frag;
  2481. *last_time = jiffies;
  2482. return 0;
  2483. drop:
  2484. return 1;
  2485. }
  2486. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2487. #include "iwl-spectrum.h"
  2488. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2489. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2490. #define TIME_UNIT 1024
  2491. /*
  2492. * extended beacon time format
  2493. * time in usec will be changed into a 32-bit value in 8:24 format
  2494. * the high 1 byte is the beacon counts
  2495. * the lower 3 bytes is the time in usec within one beacon interval
  2496. */
  2497. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2498. {
  2499. u32 quot;
  2500. u32 rem;
  2501. u32 interval = beacon_interval * 1024;
  2502. if (!interval || !usec)
  2503. return 0;
  2504. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2505. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2506. return (quot << 24) + rem;
  2507. }
  2508. /* base is usually what we get from ucode with each received frame,
  2509. * the same as HW timer counter counting down
  2510. */
  2511. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2512. {
  2513. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2514. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2515. u32 interval = beacon_interval * TIME_UNIT;
  2516. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2517. (addon & BEACON_TIME_MASK_HIGH);
  2518. if (base_low > addon_low)
  2519. res += base_low - addon_low;
  2520. else if (base_low < addon_low) {
  2521. res += interval + base_low - addon_low;
  2522. res += (1 << 24);
  2523. } else
  2524. res += (1 << 24);
  2525. return cpu_to_le32(res);
  2526. }
  2527. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2528. struct ieee80211_measurement_params *params,
  2529. u8 type)
  2530. {
  2531. struct iwl3945_spectrum_cmd spectrum;
  2532. struct iwl3945_rx_packet *res;
  2533. struct iwl3945_host_cmd cmd = {
  2534. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2535. .data = (void *)&spectrum,
  2536. .meta.flags = CMD_WANT_SKB,
  2537. };
  2538. u32 add_time = le64_to_cpu(params->start_time);
  2539. int rc;
  2540. int spectrum_resp_status;
  2541. int duration = le16_to_cpu(params->duration);
  2542. if (iwl3945_is_associated(priv))
  2543. add_time =
  2544. iwl3945_usecs_to_beacons(
  2545. le64_to_cpu(params->start_time) - priv->last_tsf,
  2546. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2547. memset(&spectrum, 0, sizeof(spectrum));
  2548. spectrum.channel_count = cpu_to_le16(1);
  2549. spectrum.flags =
  2550. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2551. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2552. cmd.len = sizeof(spectrum);
  2553. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2554. if (iwl3945_is_associated(priv))
  2555. spectrum.start_time =
  2556. iwl3945_add_beacon_time(priv->last_beacon_time,
  2557. add_time,
  2558. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2559. else
  2560. spectrum.start_time = 0;
  2561. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2562. spectrum.channels[0].channel = params->channel;
  2563. spectrum.channels[0].type = type;
  2564. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2565. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2566. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2567. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2568. if (rc)
  2569. return rc;
  2570. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2571. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2572. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2573. rc = -EIO;
  2574. }
  2575. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2576. switch (spectrum_resp_status) {
  2577. case 0: /* Command will be handled */
  2578. if (res->u.spectrum.id != 0xff) {
  2579. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2580. res->u.spectrum.id);
  2581. priv->measurement_status &= ~MEASUREMENT_READY;
  2582. }
  2583. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2584. rc = 0;
  2585. break;
  2586. case 1: /* Command will not be handled */
  2587. rc = -EAGAIN;
  2588. break;
  2589. }
  2590. dev_kfree_skb_any(cmd.meta.u.skb);
  2591. return rc;
  2592. }
  2593. #endif
  2594. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2595. struct iwl3945_rx_mem_buffer *rxb)
  2596. {
  2597. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2598. struct iwl3945_alive_resp *palive;
  2599. struct delayed_work *pwork;
  2600. palive = &pkt->u.alive_frame;
  2601. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2602. "0x%01X 0x%01X\n",
  2603. palive->is_valid, palive->ver_type,
  2604. palive->ver_subtype);
  2605. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2606. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2607. memcpy(&priv->card_alive_init,
  2608. &pkt->u.alive_frame,
  2609. sizeof(struct iwl3945_init_alive_resp));
  2610. pwork = &priv->init_alive_start;
  2611. } else {
  2612. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2613. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2614. sizeof(struct iwl3945_alive_resp));
  2615. pwork = &priv->alive_start;
  2616. iwl3945_disable_events(priv);
  2617. }
  2618. /* We delay the ALIVE response by 5ms to
  2619. * give the HW RF Kill time to activate... */
  2620. if (palive->is_valid == UCODE_VALID_OK)
  2621. queue_delayed_work(priv->workqueue, pwork,
  2622. msecs_to_jiffies(5));
  2623. else
  2624. IWL_WARNING("uCode did not respond OK.\n");
  2625. }
  2626. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2627. struct iwl3945_rx_mem_buffer *rxb)
  2628. {
  2629. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2630. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2631. return;
  2632. }
  2633. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2634. struct iwl3945_rx_mem_buffer *rxb)
  2635. {
  2636. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2637. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2638. "seq 0x%04X ser 0x%08X\n",
  2639. le32_to_cpu(pkt->u.err_resp.error_type),
  2640. get_cmd_string(pkt->u.err_resp.cmd_id),
  2641. pkt->u.err_resp.cmd_id,
  2642. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2643. le32_to_cpu(pkt->u.err_resp.error_info));
  2644. }
  2645. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2646. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2647. {
  2648. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2649. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2650. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2651. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2652. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2653. rxon->channel = csa->channel;
  2654. priv->staging_rxon.channel = csa->channel;
  2655. }
  2656. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2657. struct iwl3945_rx_mem_buffer *rxb)
  2658. {
  2659. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2660. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2661. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2662. if (!report->state) {
  2663. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2664. "Spectrum Measure Notification: Start\n");
  2665. return;
  2666. }
  2667. memcpy(&priv->measure_report, report, sizeof(*report));
  2668. priv->measurement_status |= MEASUREMENT_READY;
  2669. #endif
  2670. }
  2671. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2672. struct iwl3945_rx_mem_buffer *rxb)
  2673. {
  2674. #ifdef CONFIG_IWL3945_DEBUG
  2675. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2676. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2677. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2678. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2679. #endif
  2680. }
  2681. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2682. struct iwl3945_rx_mem_buffer *rxb)
  2683. {
  2684. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2685. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2686. "notification for %s:\n",
  2687. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2688. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2689. }
  2690. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2691. {
  2692. struct iwl3945_priv *priv =
  2693. container_of(work, struct iwl3945_priv, beacon_update);
  2694. struct sk_buff *beacon;
  2695. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2696. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2697. if (!beacon) {
  2698. IWL_ERROR("update beacon failed\n");
  2699. return;
  2700. }
  2701. mutex_lock(&priv->mutex);
  2702. /* new beacon skb is allocated every time; dispose previous.*/
  2703. if (priv->ibss_beacon)
  2704. dev_kfree_skb(priv->ibss_beacon);
  2705. priv->ibss_beacon = beacon;
  2706. mutex_unlock(&priv->mutex);
  2707. iwl3945_send_beacon_cmd(priv);
  2708. }
  2709. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2710. struct iwl3945_rx_mem_buffer *rxb)
  2711. {
  2712. #ifdef CONFIG_IWL3945_DEBUG
  2713. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2714. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2715. u8 rate = beacon->beacon_notify_hdr.rate;
  2716. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2717. "tsf %d %d rate %d\n",
  2718. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2719. beacon->beacon_notify_hdr.failure_frame,
  2720. le32_to_cpu(beacon->ibss_mgr_status),
  2721. le32_to_cpu(beacon->high_tsf),
  2722. le32_to_cpu(beacon->low_tsf), rate);
  2723. #endif
  2724. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2725. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2726. queue_work(priv->workqueue, &priv->beacon_update);
  2727. }
  2728. /* Service response to REPLY_SCAN_CMD (0x80) */
  2729. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2730. struct iwl3945_rx_mem_buffer *rxb)
  2731. {
  2732. #ifdef CONFIG_IWL3945_DEBUG
  2733. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2734. struct iwl3945_scanreq_notification *notif =
  2735. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2736. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2737. #endif
  2738. }
  2739. /* Service SCAN_START_NOTIFICATION (0x82) */
  2740. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2741. struct iwl3945_rx_mem_buffer *rxb)
  2742. {
  2743. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2744. struct iwl3945_scanstart_notification *notif =
  2745. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2746. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2747. IWL_DEBUG_SCAN("Scan start: "
  2748. "%d [802.11%s] "
  2749. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2750. notif->channel,
  2751. notif->band ? "bg" : "a",
  2752. notif->tsf_high,
  2753. notif->tsf_low, notif->status, notif->beacon_timer);
  2754. }
  2755. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2756. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2757. struct iwl3945_rx_mem_buffer *rxb)
  2758. {
  2759. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2760. struct iwl3945_scanresults_notification *notif =
  2761. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2762. IWL_DEBUG_SCAN("Scan ch.res: "
  2763. "%d [802.11%s] "
  2764. "(TSF: 0x%08X:%08X) - %d "
  2765. "elapsed=%lu usec (%dms since last)\n",
  2766. notif->channel,
  2767. notif->band ? "bg" : "a",
  2768. le32_to_cpu(notif->tsf_high),
  2769. le32_to_cpu(notif->tsf_low),
  2770. le32_to_cpu(notif->statistics[0]),
  2771. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2772. jiffies_to_msecs(elapsed_jiffies
  2773. (priv->last_scan_jiffies, jiffies)));
  2774. priv->last_scan_jiffies = jiffies;
  2775. priv->next_scan_jiffies = 0;
  2776. }
  2777. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2778. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2779. struct iwl3945_rx_mem_buffer *rxb)
  2780. {
  2781. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2782. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2783. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2784. scan_notif->scanned_channels,
  2785. scan_notif->tsf_low,
  2786. scan_notif->tsf_high, scan_notif->status);
  2787. /* The HW is no longer scanning */
  2788. clear_bit(STATUS_SCAN_HW, &priv->status);
  2789. /* The scan completion notification came in, so kill that timer... */
  2790. cancel_delayed_work(&priv->scan_check);
  2791. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2792. (priv->scan_bands == 2) ? "2.4" : "5.2",
  2793. jiffies_to_msecs(elapsed_jiffies
  2794. (priv->scan_pass_start, jiffies)));
  2795. /* Remove this scanned band from the list
  2796. * of pending bands to scan */
  2797. priv->scan_bands--;
  2798. /* If a request to abort was given, or the scan did not succeed
  2799. * then we reset the scan state machine and terminate,
  2800. * re-queuing another scan if one has been requested */
  2801. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2802. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2803. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2804. } else {
  2805. /* If there are more bands on this scan pass reschedule */
  2806. if (priv->scan_bands > 0)
  2807. goto reschedule;
  2808. }
  2809. priv->last_scan_jiffies = jiffies;
  2810. priv->next_scan_jiffies = 0;
  2811. IWL_DEBUG_INFO("Setting scan to off\n");
  2812. clear_bit(STATUS_SCANNING, &priv->status);
  2813. IWL_DEBUG_INFO("Scan took %dms\n",
  2814. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2815. queue_work(priv->workqueue, &priv->scan_completed);
  2816. return;
  2817. reschedule:
  2818. priv->scan_pass_start = jiffies;
  2819. queue_work(priv->workqueue, &priv->request_scan);
  2820. }
  2821. /* Handle notification from uCode that card's power state is changing
  2822. * due to software, hardware, or critical temperature RFKILL */
  2823. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2824. struct iwl3945_rx_mem_buffer *rxb)
  2825. {
  2826. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2827. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2828. unsigned long status = priv->status;
  2829. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2830. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2831. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2832. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2833. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2834. if (flags & HW_CARD_DISABLED)
  2835. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2836. else
  2837. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2838. if (flags & SW_CARD_DISABLED)
  2839. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2840. else
  2841. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2842. iwl3945_scan_cancel(priv);
  2843. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2844. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2845. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2846. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2847. queue_work(priv->workqueue, &priv->rf_kill);
  2848. else
  2849. wake_up_interruptible(&priv->wait_command_queue);
  2850. }
  2851. /**
  2852. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2853. *
  2854. * Setup the RX handlers for each of the reply types sent from the uCode
  2855. * to the host.
  2856. *
  2857. * This function chains into the hardware specific files for them to setup
  2858. * any hardware specific handlers as well.
  2859. */
  2860. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2861. {
  2862. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2863. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2864. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2865. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2866. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2867. iwl3945_rx_spectrum_measure_notif;
  2868. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2869. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2870. iwl3945_rx_pm_debug_statistics_notif;
  2871. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2872. /*
  2873. * The same handler is used for both the REPLY to a discrete
  2874. * statistics request from the host as well as for the periodic
  2875. * statistics notifications (after received beacons) from the uCode.
  2876. */
  2877. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2878. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2879. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2880. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2881. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2882. iwl3945_rx_scan_results_notif;
  2883. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2884. iwl3945_rx_scan_complete_notif;
  2885. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2886. /* Set up hardware specific Rx handlers */
  2887. iwl3945_hw_rx_handler_setup(priv);
  2888. }
  2889. /**
  2890. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2891. * When FW advances 'R' index, all entries between old and new 'R' index
  2892. * need to be reclaimed.
  2893. */
  2894. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2895. int txq_id, int index)
  2896. {
  2897. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2898. struct iwl3945_queue *q = &txq->q;
  2899. int nfreed = 0;
  2900. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2901. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2902. "is out of range [0-%d] %d %d.\n", txq_id,
  2903. index, q->n_bd, q->write_ptr, q->read_ptr);
  2904. return;
  2905. }
  2906. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2907. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2908. if (nfreed > 1) {
  2909. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2910. q->write_ptr, q->read_ptr);
  2911. queue_work(priv->workqueue, &priv->restart);
  2912. break;
  2913. }
  2914. nfreed++;
  2915. }
  2916. }
  2917. /**
  2918. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2919. * @rxb: Rx buffer to reclaim
  2920. *
  2921. * If an Rx buffer has an async callback associated with it the callback
  2922. * will be executed. The attached skb (if present) will only be freed
  2923. * if the callback returns 1
  2924. */
  2925. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2926. struct iwl3945_rx_mem_buffer *rxb)
  2927. {
  2928. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2929. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2930. int txq_id = SEQ_TO_QUEUE(sequence);
  2931. int index = SEQ_TO_INDEX(sequence);
  2932. int huge = sequence & SEQ_HUGE_FRAME;
  2933. int cmd_index;
  2934. struct iwl3945_cmd *cmd;
  2935. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2936. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2937. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2938. /* Input error checking is done when commands are added to queue. */
  2939. if (cmd->meta.flags & CMD_WANT_SKB) {
  2940. cmd->meta.source->u.skb = rxb->skb;
  2941. rxb->skb = NULL;
  2942. } else if (cmd->meta.u.callback &&
  2943. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2944. rxb->skb = NULL;
  2945. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2946. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2947. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2948. wake_up_interruptible(&priv->wait_command_queue);
  2949. }
  2950. }
  2951. /************************** RX-FUNCTIONS ****************************/
  2952. /*
  2953. * Rx theory of operation
  2954. *
  2955. * The host allocates 32 DMA target addresses and passes the host address
  2956. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2957. * 0 to 31
  2958. *
  2959. * Rx Queue Indexes
  2960. * The host/firmware share two index registers for managing the Rx buffers.
  2961. *
  2962. * The READ index maps to the first position that the firmware may be writing
  2963. * to -- the driver can read up to (but not including) this position and get
  2964. * good data.
  2965. * The READ index is managed by the firmware once the card is enabled.
  2966. *
  2967. * The WRITE index maps to the last position the driver has read from -- the
  2968. * position preceding WRITE is the last slot the firmware can place a packet.
  2969. *
  2970. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2971. * WRITE = READ.
  2972. *
  2973. * During initialization, the host sets up the READ queue position to the first
  2974. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2975. *
  2976. * When the firmware places a packet in a buffer, it will advance the READ index
  2977. * and fire the RX interrupt. The driver can then query the READ index and
  2978. * process as many packets as possible, moving the WRITE index forward as it
  2979. * resets the Rx queue buffers with new memory.
  2980. *
  2981. * The management in the driver is as follows:
  2982. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2983. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2984. * to replenish the iwl->rxq->rx_free.
  2985. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2986. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2987. * 'processed' and 'read' driver indexes as well)
  2988. * + A received packet is processed and handed to the kernel network stack,
  2989. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2990. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2991. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2992. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2993. * were enough free buffers and RX_STALLED is set it is cleared.
  2994. *
  2995. *
  2996. * Driver sequence:
  2997. *
  2998. * iwl3945_rx_queue_alloc() Allocates rx_free
  2999. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3000. * iwl3945_rx_queue_restock
  3001. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3002. * queue, updates firmware pointers, and updates
  3003. * the WRITE index. If insufficient rx_free buffers
  3004. * are available, schedules iwl3945_rx_replenish
  3005. *
  3006. * -- enable interrupts --
  3007. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3008. * READ INDEX, detaching the SKB from the pool.
  3009. * Moves the packet buffer from queue to rx_used.
  3010. * Calls iwl3945_rx_queue_restock to refill any empty
  3011. * slots.
  3012. * ...
  3013. *
  3014. */
  3015. /**
  3016. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3017. */
  3018. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3019. {
  3020. int s = q->read - q->write;
  3021. if (s <= 0)
  3022. s += RX_QUEUE_SIZE;
  3023. /* keep some buffer to not confuse full and empty queue */
  3024. s -= 2;
  3025. if (s < 0)
  3026. s = 0;
  3027. return s;
  3028. }
  3029. /**
  3030. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3031. */
  3032. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3033. {
  3034. u32 reg = 0;
  3035. int rc = 0;
  3036. unsigned long flags;
  3037. spin_lock_irqsave(&q->lock, flags);
  3038. if (q->need_update == 0)
  3039. goto exit_unlock;
  3040. /* If power-saving is in use, make sure device is awake */
  3041. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3042. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3043. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3044. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3045. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3046. goto exit_unlock;
  3047. }
  3048. rc = iwl3945_grab_nic_access(priv);
  3049. if (rc)
  3050. goto exit_unlock;
  3051. /* Device expects a multiple of 8 */
  3052. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3053. q->write & ~0x7);
  3054. iwl3945_release_nic_access(priv);
  3055. /* Else device is assumed to be awake */
  3056. } else
  3057. /* Device expects a multiple of 8 */
  3058. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3059. q->need_update = 0;
  3060. exit_unlock:
  3061. spin_unlock_irqrestore(&q->lock, flags);
  3062. return rc;
  3063. }
  3064. /**
  3065. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3066. */
  3067. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3068. dma_addr_t dma_addr)
  3069. {
  3070. return cpu_to_le32((u32)dma_addr);
  3071. }
  3072. /**
  3073. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3074. *
  3075. * If there are slots in the RX queue that need to be restocked,
  3076. * and we have free pre-allocated buffers, fill the ranks as much
  3077. * as we can, pulling from rx_free.
  3078. *
  3079. * This moves the 'write' index forward to catch up with 'processed', and
  3080. * also updates the memory address in the firmware to reference the new
  3081. * target buffer.
  3082. */
  3083. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3084. {
  3085. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3086. struct list_head *element;
  3087. struct iwl3945_rx_mem_buffer *rxb;
  3088. unsigned long flags;
  3089. int write, rc;
  3090. spin_lock_irqsave(&rxq->lock, flags);
  3091. write = rxq->write & ~0x7;
  3092. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3093. /* Get next free Rx buffer, remove from free list */
  3094. element = rxq->rx_free.next;
  3095. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3096. list_del(element);
  3097. /* Point to Rx buffer via next RBD in circular buffer */
  3098. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3099. rxq->queue[rxq->write] = rxb;
  3100. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3101. rxq->free_count--;
  3102. }
  3103. spin_unlock_irqrestore(&rxq->lock, flags);
  3104. /* If the pre-allocated buffer pool is dropping low, schedule to
  3105. * refill it */
  3106. if (rxq->free_count <= RX_LOW_WATERMARK)
  3107. queue_work(priv->workqueue, &priv->rx_replenish);
  3108. /* If we've added more space for the firmware to place data, tell it.
  3109. * Increment device's write pointer in multiples of 8. */
  3110. if ((write != (rxq->write & ~0x7))
  3111. || (abs(rxq->write - rxq->read) > 7)) {
  3112. spin_lock_irqsave(&rxq->lock, flags);
  3113. rxq->need_update = 1;
  3114. spin_unlock_irqrestore(&rxq->lock, flags);
  3115. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3116. if (rc)
  3117. return rc;
  3118. }
  3119. return 0;
  3120. }
  3121. /**
  3122. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3123. *
  3124. * When moving to rx_free an SKB is allocated for the slot.
  3125. *
  3126. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3127. * This is called as a scheduled work item (except for during initialization)
  3128. */
  3129. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3130. {
  3131. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3132. struct list_head *element;
  3133. struct iwl3945_rx_mem_buffer *rxb;
  3134. unsigned long flags;
  3135. spin_lock_irqsave(&rxq->lock, flags);
  3136. while (!list_empty(&rxq->rx_used)) {
  3137. element = rxq->rx_used.next;
  3138. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3139. /* Alloc a new receive buffer */
  3140. rxb->skb =
  3141. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3142. if (!rxb->skb) {
  3143. if (net_ratelimit())
  3144. printk(KERN_CRIT DRV_NAME
  3145. ": Can not allocate SKB buffers\n");
  3146. /* We don't reschedule replenish work here -- we will
  3147. * call the restock method and if it still needs
  3148. * more buffers it will schedule replenish */
  3149. break;
  3150. }
  3151. /* If radiotap head is required, reserve some headroom here.
  3152. * The physical head count is a variable rx_stats->phy_count.
  3153. * We reserve 4 bytes here. Plus these extra bytes, the
  3154. * headroom of the physical head should be enough for the
  3155. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3156. */
  3157. skb_reserve(rxb->skb, 4);
  3158. priv->alloc_rxb_skb++;
  3159. list_del(element);
  3160. /* Get physical address of RB/SKB */
  3161. rxb->dma_addr =
  3162. pci_map_single(priv->pci_dev, rxb->skb->data,
  3163. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3164. list_add_tail(&rxb->list, &rxq->rx_free);
  3165. rxq->free_count++;
  3166. }
  3167. spin_unlock_irqrestore(&rxq->lock, flags);
  3168. }
  3169. /*
  3170. * this should be called while priv->lock is locked
  3171. */
  3172. static void __iwl3945_rx_replenish(void *data)
  3173. {
  3174. struct iwl3945_priv *priv = data;
  3175. iwl3945_rx_allocate(priv);
  3176. iwl3945_rx_queue_restock(priv);
  3177. }
  3178. void iwl3945_rx_replenish(void *data)
  3179. {
  3180. struct iwl3945_priv *priv = data;
  3181. unsigned long flags;
  3182. iwl3945_rx_allocate(priv);
  3183. spin_lock_irqsave(&priv->lock, flags);
  3184. iwl3945_rx_queue_restock(priv);
  3185. spin_unlock_irqrestore(&priv->lock, flags);
  3186. }
  3187. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3188. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3189. * This free routine walks the list of POOL entries and if SKB is set to
  3190. * non NULL it is unmapped and freed
  3191. */
  3192. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3193. {
  3194. int i;
  3195. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3196. if (rxq->pool[i].skb != NULL) {
  3197. pci_unmap_single(priv->pci_dev,
  3198. rxq->pool[i].dma_addr,
  3199. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3200. dev_kfree_skb(rxq->pool[i].skb);
  3201. }
  3202. }
  3203. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3204. rxq->dma_addr);
  3205. rxq->bd = NULL;
  3206. }
  3207. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3208. {
  3209. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3210. struct pci_dev *dev = priv->pci_dev;
  3211. int i;
  3212. spin_lock_init(&rxq->lock);
  3213. INIT_LIST_HEAD(&rxq->rx_free);
  3214. INIT_LIST_HEAD(&rxq->rx_used);
  3215. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3216. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3217. if (!rxq->bd)
  3218. return -ENOMEM;
  3219. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3220. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3221. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3222. /* Set us so that we have processed and used all buffers, but have
  3223. * not restocked the Rx queue with fresh buffers */
  3224. rxq->read = rxq->write = 0;
  3225. rxq->free_count = 0;
  3226. rxq->need_update = 0;
  3227. return 0;
  3228. }
  3229. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3230. {
  3231. unsigned long flags;
  3232. int i;
  3233. spin_lock_irqsave(&rxq->lock, flags);
  3234. INIT_LIST_HEAD(&rxq->rx_free);
  3235. INIT_LIST_HEAD(&rxq->rx_used);
  3236. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3237. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3238. /* In the reset function, these buffers may have been allocated
  3239. * to an SKB, so we need to unmap and free potential storage */
  3240. if (rxq->pool[i].skb != NULL) {
  3241. pci_unmap_single(priv->pci_dev,
  3242. rxq->pool[i].dma_addr,
  3243. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3244. priv->alloc_rxb_skb--;
  3245. dev_kfree_skb(rxq->pool[i].skb);
  3246. rxq->pool[i].skb = NULL;
  3247. }
  3248. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3249. }
  3250. /* Set us so that we have processed and used all buffers, but have
  3251. * not restocked the Rx queue with fresh buffers */
  3252. rxq->read = rxq->write = 0;
  3253. rxq->free_count = 0;
  3254. spin_unlock_irqrestore(&rxq->lock, flags);
  3255. }
  3256. /* Convert linear signal-to-noise ratio into dB */
  3257. static u8 ratio2dB[100] = {
  3258. /* 0 1 2 3 4 5 6 7 8 9 */
  3259. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3260. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3261. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3262. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3263. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3264. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3265. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3266. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3267. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3268. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3269. };
  3270. /* Calculates a relative dB value from a ratio of linear
  3271. * (i.e. not dB) signal levels.
  3272. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3273. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3274. {
  3275. /* 1000:1 or higher just report as 60 dB */
  3276. if (sig_ratio >= 1000)
  3277. return 60;
  3278. /* 100:1 or higher, divide by 10 and use table,
  3279. * add 20 dB to make up for divide by 10 */
  3280. if (sig_ratio >= 100)
  3281. return (20 + (int)ratio2dB[sig_ratio/10]);
  3282. /* We shouldn't see this */
  3283. if (sig_ratio < 1)
  3284. return 0;
  3285. /* Use table for ratios 1:1 - 99:1 */
  3286. return (int)ratio2dB[sig_ratio];
  3287. }
  3288. #define PERFECT_RSSI (-20) /* dBm */
  3289. #define WORST_RSSI (-95) /* dBm */
  3290. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3291. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3292. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3293. * about formulas used below. */
  3294. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3295. {
  3296. int sig_qual;
  3297. int degradation = PERFECT_RSSI - rssi_dbm;
  3298. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3299. * as indicator; formula is (signal dbm - noise dbm).
  3300. * SNR at or above 40 is a great signal (100%).
  3301. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3302. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3303. if (noise_dbm) {
  3304. if (rssi_dbm - noise_dbm >= 40)
  3305. return 100;
  3306. else if (rssi_dbm < noise_dbm)
  3307. return 0;
  3308. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3309. /* Else use just the signal level.
  3310. * This formula is a least squares fit of data points collected and
  3311. * compared with a reference system that had a percentage (%) display
  3312. * for signal quality. */
  3313. } else
  3314. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3315. (15 * RSSI_RANGE + 62 * degradation)) /
  3316. (RSSI_RANGE * RSSI_RANGE);
  3317. if (sig_qual > 100)
  3318. sig_qual = 100;
  3319. else if (sig_qual < 1)
  3320. sig_qual = 0;
  3321. return sig_qual;
  3322. }
  3323. /**
  3324. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3325. *
  3326. * Uses the priv->rx_handlers callback function array to invoke
  3327. * the appropriate handlers, including command responses,
  3328. * frame-received notifications, and other notifications.
  3329. */
  3330. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3331. {
  3332. struct iwl3945_rx_mem_buffer *rxb;
  3333. struct iwl3945_rx_packet *pkt;
  3334. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3335. u32 r, i;
  3336. int reclaim;
  3337. unsigned long flags;
  3338. u8 fill_rx = 0;
  3339. u32 count = 8;
  3340. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3341. * buffer that the driver may process (last buffer filled by ucode). */
  3342. r = iwl3945_hw_get_rx_read(priv);
  3343. i = rxq->read;
  3344. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3345. fill_rx = 1;
  3346. /* Rx interrupt, but nothing sent from uCode */
  3347. if (i == r)
  3348. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3349. while (i != r) {
  3350. rxb = rxq->queue[i];
  3351. /* If an RXB doesn't have a Rx queue slot associated with it,
  3352. * then a bug has been introduced in the queue refilling
  3353. * routines -- catch it here */
  3354. BUG_ON(rxb == NULL);
  3355. rxq->queue[i] = NULL;
  3356. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3357. IWL_RX_BUF_SIZE,
  3358. PCI_DMA_FROMDEVICE);
  3359. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3360. /* Reclaim a command buffer only if this packet is a response
  3361. * to a (driver-originated) command.
  3362. * If the packet (e.g. Rx frame) originated from uCode,
  3363. * there is no command buffer to reclaim.
  3364. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3365. * but apparently a few don't get set; catch them here. */
  3366. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3367. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3368. (pkt->hdr.cmd != REPLY_TX);
  3369. /* Based on type of command response or notification,
  3370. * handle those that need handling via function in
  3371. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3372. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3373. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3374. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3375. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3376. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3377. } else {
  3378. /* No handling needed */
  3379. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3380. "r %d i %d No handler needed for %s, 0x%02x\n",
  3381. r, i, get_cmd_string(pkt->hdr.cmd),
  3382. pkt->hdr.cmd);
  3383. }
  3384. if (reclaim) {
  3385. /* Invoke any callbacks, transfer the skb to caller, and
  3386. * fire off the (possibly) blocking iwl3945_send_cmd()
  3387. * as we reclaim the driver command queue */
  3388. if (rxb && rxb->skb)
  3389. iwl3945_tx_cmd_complete(priv, rxb);
  3390. else
  3391. IWL_WARNING("Claim null rxb?\n");
  3392. }
  3393. /* For now we just don't re-use anything. We can tweak this
  3394. * later to try and re-use notification packets and SKBs that
  3395. * fail to Rx correctly */
  3396. if (rxb->skb != NULL) {
  3397. priv->alloc_rxb_skb--;
  3398. dev_kfree_skb_any(rxb->skb);
  3399. rxb->skb = NULL;
  3400. }
  3401. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3402. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3403. spin_lock_irqsave(&rxq->lock, flags);
  3404. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3405. spin_unlock_irqrestore(&rxq->lock, flags);
  3406. i = (i + 1) & RX_QUEUE_MASK;
  3407. /* If there are a lot of unused frames,
  3408. * restock the Rx queue so ucode won't assert. */
  3409. if (fill_rx) {
  3410. count++;
  3411. if (count >= 8) {
  3412. priv->rxq.read = i;
  3413. __iwl3945_rx_replenish(priv);
  3414. count = 0;
  3415. }
  3416. }
  3417. }
  3418. /* Backtrack one entry */
  3419. priv->rxq.read = i;
  3420. iwl3945_rx_queue_restock(priv);
  3421. }
  3422. /**
  3423. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3424. */
  3425. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3426. struct iwl3945_tx_queue *txq)
  3427. {
  3428. u32 reg = 0;
  3429. int rc = 0;
  3430. int txq_id = txq->q.id;
  3431. if (txq->need_update == 0)
  3432. return rc;
  3433. /* if we're trying to save power */
  3434. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3435. /* wake up nic if it's powered down ...
  3436. * uCode will wake up, and interrupt us again, so next
  3437. * time we'll skip this part. */
  3438. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3439. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3440. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3441. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3442. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3443. return rc;
  3444. }
  3445. /* restore this queue's parameters in nic hardware. */
  3446. rc = iwl3945_grab_nic_access(priv);
  3447. if (rc)
  3448. return rc;
  3449. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3450. txq->q.write_ptr | (txq_id << 8));
  3451. iwl3945_release_nic_access(priv);
  3452. /* else not in power-save mode, uCode will never sleep when we're
  3453. * trying to tx (during RFKILL, we're not trying to tx). */
  3454. } else
  3455. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3456. txq->q.write_ptr | (txq_id << 8));
  3457. txq->need_update = 0;
  3458. return rc;
  3459. }
  3460. #ifdef CONFIG_IWL3945_DEBUG
  3461. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3462. {
  3463. DECLARE_MAC_BUF(mac);
  3464. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3465. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3466. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3467. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3468. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3469. le32_to_cpu(rxon->filter_flags));
  3470. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3471. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3472. rxon->ofdm_basic_rates);
  3473. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3474. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3475. print_mac(mac, rxon->node_addr));
  3476. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3477. print_mac(mac, rxon->bssid_addr));
  3478. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3479. }
  3480. #endif
  3481. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3482. {
  3483. IWL_DEBUG_ISR("Enabling interrupts\n");
  3484. set_bit(STATUS_INT_ENABLED, &priv->status);
  3485. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3486. }
  3487. /* call this function to flush any scheduled tasklet */
  3488. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3489. {
  3490. /* wait to make sure we flush pedding tasklet*/
  3491. synchronize_irq(priv->pci_dev->irq);
  3492. tasklet_kill(&priv->irq_tasklet);
  3493. }
  3494. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3495. {
  3496. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3497. /* disable interrupts from uCode/NIC to host */
  3498. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3499. /* acknowledge/clear/reset any interrupts still pending
  3500. * from uCode or flow handler (Rx/Tx DMA) */
  3501. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3502. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3503. IWL_DEBUG_ISR("Disabled interrupts\n");
  3504. }
  3505. static const char *desc_lookup(int i)
  3506. {
  3507. switch (i) {
  3508. case 1:
  3509. return "FAIL";
  3510. case 2:
  3511. return "BAD_PARAM";
  3512. case 3:
  3513. return "BAD_CHECKSUM";
  3514. case 4:
  3515. return "NMI_INTERRUPT";
  3516. case 5:
  3517. return "SYSASSERT";
  3518. case 6:
  3519. return "FATAL_ERROR";
  3520. }
  3521. return "UNKNOWN";
  3522. }
  3523. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3524. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3525. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3526. {
  3527. u32 i;
  3528. u32 desc, time, count, base, data1;
  3529. u32 blink1, blink2, ilink1, ilink2;
  3530. int rc;
  3531. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3532. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3533. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3534. return;
  3535. }
  3536. rc = iwl3945_grab_nic_access(priv);
  3537. if (rc) {
  3538. IWL_WARNING("Can not read from adapter at this time.\n");
  3539. return;
  3540. }
  3541. count = iwl3945_read_targ_mem(priv, base);
  3542. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3543. IWL_ERROR("Start IWL Error Log Dump:\n");
  3544. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3545. }
  3546. IWL_ERROR("Desc Time asrtPC blink2 "
  3547. "ilink1 nmiPC Line\n");
  3548. for (i = ERROR_START_OFFSET;
  3549. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3550. i += ERROR_ELEM_SIZE) {
  3551. desc = iwl3945_read_targ_mem(priv, base + i);
  3552. time =
  3553. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3554. blink1 =
  3555. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3556. blink2 =
  3557. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3558. ilink1 =
  3559. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3560. ilink2 =
  3561. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3562. data1 =
  3563. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3564. IWL_ERROR
  3565. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3566. desc_lookup(desc), desc, time, blink1, blink2,
  3567. ilink1, ilink2, data1);
  3568. }
  3569. iwl3945_release_nic_access(priv);
  3570. }
  3571. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3572. /**
  3573. * iwl3945_print_event_log - Dump error event log to syslog
  3574. *
  3575. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3576. */
  3577. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3578. u32 num_events, u32 mode)
  3579. {
  3580. u32 i;
  3581. u32 base; /* SRAM byte address of event log header */
  3582. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3583. u32 ptr; /* SRAM byte address of log data */
  3584. u32 ev, time, data; /* event log data */
  3585. if (num_events == 0)
  3586. return;
  3587. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3588. if (mode == 0)
  3589. event_size = 2 * sizeof(u32);
  3590. else
  3591. event_size = 3 * sizeof(u32);
  3592. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3593. /* "time" is actually "data" for mode 0 (no timestamp).
  3594. * place event id # at far right for easier visual parsing. */
  3595. for (i = 0; i < num_events; i++) {
  3596. ev = iwl3945_read_targ_mem(priv, ptr);
  3597. ptr += sizeof(u32);
  3598. time = iwl3945_read_targ_mem(priv, ptr);
  3599. ptr += sizeof(u32);
  3600. if (mode == 0)
  3601. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3602. else {
  3603. data = iwl3945_read_targ_mem(priv, ptr);
  3604. ptr += sizeof(u32);
  3605. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3606. }
  3607. }
  3608. }
  3609. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3610. {
  3611. int rc;
  3612. u32 base; /* SRAM byte address of event log header */
  3613. u32 capacity; /* event log capacity in # entries */
  3614. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3615. u32 num_wraps; /* # times uCode wrapped to top of log */
  3616. u32 next_entry; /* index of next entry to be written by uCode */
  3617. u32 size; /* # entries that we'll print */
  3618. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3619. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3620. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3621. return;
  3622. }
  3623. rc = iwl3945_grab_nic_access(priv);
  3624. if (rc) {
  3625. IWL_WARNING("Can not read from adapter at this time.\n");
  3626. return;
  3627. }
  3628. /* event log header */
  3629. capacity = iwl3945_read_targ_mem(priv, base);
  3630. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3631. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3632. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3633. size = num_wraps ? capacity : next_entry;
  3634. /* bail out if nothing in log */
  3635. if (size == 0) {
  3636. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3637. iwl3945_release_nic_access(priv);
  3638. return;
  3639. }
  3640. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3641. size, num_wraps);
  3642. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3643. * i.e the next one that uCode would fill. */
  3644. if (num_wraps)
  3645. iwl3945_print_event_log(priv, next_entry,
  3646. capacity - next_entry, mode);
  3647. /* (then/else) start at top of log */
  3648. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3649. iwl3945_release_nic_access(priv);
  3650. }
  3651. /**
  3652. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3653. */
  3654. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3655. {
  3656. /* Set the FW error flag -- cleared on iwl3945_down */
  3657. set_bit(STATUS_FW_ERROR, &priv->status);
  3658. /* Cancel currently queued command. */
  3659. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3660. #ifdef CONFIG_IWL3945_DEBUG
  3661. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3662. iwl3945_dump_nic_error_log(priv);
  3663. iwl3945_dump_nic_event_log(priv);
  3664. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3665. }
  3666. #endif
  3667. wake_up_interruptible(&priv->wait_command_queue);
  3668. /* Keep the restart process from trying to send host
  3669. * commands by clearing the INIT status bit */
  3670. clear_bit(STATUS_READY, &priv->status);
  3671. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3672. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3673. "Restarting adapter due to uCode error.\n");
  3674. if (iwl3945_is_associated(priv)) {
  3675. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3676. sizeof(priv->recovery_rxon));
  3677. priv->error_recovering = 1;
  3678. }
  3679. queue_work(priv->workqueue, &priv->restart);
  3680. }
  3681. }
  3682. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3683. {
  3684. unsigned long flags;
  3685. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3686. sizeof(priv->staging_rxon));
  3687. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3688. iwl3945_commit_rxon(priv);
  3689. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3690. spin_lock_irqsave(&priv->lock, flags);
  3691. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3692. priv->error_recovering = 0;
  3693. spin_unlock_irqrestore(&priv->lock, flags);
  3694. }
  3695. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3696. {
  3697. u32 inta, handled = 0;
  3698. u32 inta_fh;
  3699. unsigned long flags;
  3700. #ifdef CONFIG_IWL3945_DEBUG
  3701. u32 inta_mask;
  3702. #endif
  3703. spin_lock_irqsave(&priv->lock, flags);
  3704. /* Ack/clear/reset pending uCode interrupts.
  3705. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3706. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3707. inta = iwl3945_read32(priv, CSR_INT);
  3708. iwl3945_write32(priv, CSR_INT, inta);
  3709. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3710. * Any new interrupts that happen after this, either while we're
  3711. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3712. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3713. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3714. #ifdef CONFIG_IWL3945_DEBUG
  3715. if (iwl3945_debug_level & IWL_DL_ISR) {
  3716. /* just for debug */
  3717. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3718. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3719. inta, inta_mask, inta_fh);
  3720. }
  3721. #endif
  3722. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3723. * atomic, make sure that inta covers all the interrupts that
  3724. * we've discovered, even if FH interrupt came in just after
  3725. * reading CSR_INT. */
  3726. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3727. inta |= CSR_INT_BIT_FH_RX;
  3728. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3729. inta |= CSR_INT_BIT_FH_TX;
  3730. /* Now service all interrupt bits discovered above. */
  3731. if (inta & CSR_INT_BIT_HW_ERR) {
  3732. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3733. /* Tell the device to stop sending interrupts */
  3734. iwl3945_disable_interrupts(priv);
  3735. iwl3945_irq_handle_error(priv);
  3736. handled |= CSR_INT_BIT_HW_ERR;
  3737. spin_unlock_irqrestore(&priv->lock, flags);
  3738. return;
  3739. }
  3740. #ifdef CONFIG_IWL3945_DEBUG
  3741. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3742. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3743. if (inta & CSR_INT_BIT_SCD)
  3744. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3745. "the frame/frames.\n");
  3746. /* Alive notification via Rx interrupt will do the real work */
  3747. if (inta & CSR_INT_BIT_ALIVE)
  3748. IWL_DEBUG_ISR("Alive interrupt\n");
  3749. }
  3750. #endif
  3751. /* Safely ignore these bits for debug checks below */
  3752. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3753. /* HW RF KILL switch toggled (4965 only) */
  3754. if (inta & CSR_INT_BIT_RF_KILL) {
  3755. int hw_rf_kill = 0;
  3756. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3757. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3758. hw_rf_kill = 1;
  3759. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3760. "RF_KILL bit toggled to %s.\n",
  3761. hw_rf_kill ? "disable radio":"enable radio");
  3762. /* Queue restart only if RF_KILL switch was set to "kill"
  3763. * when we loaded driver, and is now set to "enable".
  3764. * After we're Alive, RF_KILL gets handled by
  3765. * iwl3945_rx_card_state_notif() */
  3766. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3767. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3768. queue_work(priv->workqueue, &priv->restart);
  3769. }
  3770. handled |= CSR_INT_BIT_RF_KILL;
  3771. }
  3772. /* Chip got too hot and stopped itself (4965 only) */
  3773. if (inta & CSR_INT_BIT_CT_KILL) {
  3774. IWL_ERROR("Microcode CT kill error detected.\n");
  3775. handled |= CSR_INT_BIT_CT_KILL;
  3776. }
  3777. /* Error detected by uCode */
  3778. if (inta & CSR_INT_BIT_SW_ERR) {
  3779. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3780. inta);
  3781. iwl3945_irq_handle_error(priv);
  3782. handled |= CSR_INT_BIT_SW_ERR;
  3783. }
  3784. /* uCode wakes up after power-down sleep */
  3785. if (inta & CSR_INT_BIT_WAKEUP) {
  3786. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3787. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3788. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3789. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3790. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3791. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3792. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3793. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3794. handled |= CSR_INT_BIT_WAKEUP;
  3795. }
  3796. /* All uCode command responses, including Tx command responses,
  3797. * Rx "responses" (frame-received notification), and other
  3798. * notifications from uCode come through here*/
  3799. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3800. iwl3945_rx_handle(priv);
  3801. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3802. }
  3803. if (inta & CSR_INT_BIT_FH_TX) {
  3804. IWL_DEBUG_ISR("Tx interrupt\n");
  3805. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3806. if (!iwl3945_grab_nic_access(priv)) {
  3807. iwl3945_write_direct32(priv,
  3808. FH_TCSR_CREDIT
  3809. (ALM_FH_SRVC_CHNL), 0x0);
  3810. iwl3945_release_nic_access(priv);
  3811. }
  3812. handled |= CSR_INT_BIT_FH_TX;
  3813. }
  3814. if (inta & ~handled)
  3815. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3816. if (inta & ~CSR_INI_SET_MASK) {
  3817. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3818. inta & ~CSR_INI_SET_MASK);
  3819. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3820. }
  3821. /* Re-enable all interrupts */
  3822. /* only Re-enable if disabled by irq */
  3823. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3824. iwl3945_enable_interrupts(priv);
  3825. #ifdef CONFIG_IWL3945_DEBUG
  3826. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3827. inta = iwl3945_read32(priv, CSR_INT);
  3828. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3829. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3830. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3831. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3832. }
  3833. #endif
  3834. spin_unlock_irqrestore(&priv->lock, flags);
  3835. }
  3836. static irqreturn_t iwl3945_isr(int irq, void *data)
  3837. {
  3838. struct iwl3945_priv *priv = data;
  3839. u32 inta, inta_mask;
  3840. u32 inta_fh;
  3841. if (!priv)
  3842. return IRQ_NONE;
  3843. spin_lock(&priv->lock);
  3844. /* Disable (but don't clear!) interrupts here to avoid
  3845. * back-to-back ISRs and sporadic interrupts from our NIC.
  3846. * If we have something to service, the tasklet will re-enable ints.
  3847. * If we *don't* have something, we'll re-enable before leaving here. */
  3848. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3849. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3850. /* Discover which interrupts are active/pending */
  3851. inta = iwl3945_read32(priv, CSR_INT);
  3852. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3853. /* Ignore interrupt if there's nothing in NIC to service.
  3854. * This may be due to IRQ shared with another device,
  3855. * or due to sporadic interrupts thrown from our NIC. */
  3856. if (!inta && !inta_fh) {
  3857. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3858. goto none;
  3859. }
  3860. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3861. /* Hardware disappeared */
  3862. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3863. goto unplugged;
  3864. }
  3865. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3866. inta, inta_mask, inta_fh);
  3867. inta &= ~CSR_INT_BIT_SCD;
  3868. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3869. if (likely(inta || inta_fh))
  3870. tasklet_schedule(&priv->irq_tasklet);
  3871. unplugged:
  3872. spin_unlock(&priv->lock);
  3873. return IRQ_HANDLED;
  3874. none:
  3875. /* re-enable interrupts here since we don't have anything to service. */
  3876. /* only Re-enable if disabled by irq */
  3877. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3878. iwl3945_enable_interrupts(priv);
  3879. spin_unlock(&priv->lock);
  3880. return IRQ_NONE;
  3881. }
  3882. /************************** EEPROM BANDS ****************************
  3883. *
  3884. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3885. * EEPROM contents to the specific channel number supported for each
  3886. * band.
  3887. *
  3888. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3889. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3890. * The specific geography and calibration information for that channel
  3891. * is contained in the eeprom map itself.
  3892. *
  3893. * During init, we copy the eeprom information and channel map
  3894. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3895. *
  3896. * channel_map_24/52 provides the index in the channel_info array for a
  3897. * given channel. We have to have two separate maps as there is channel
  3898. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3899. * band_2
  3900. *
  3901. * A value of 0xff stored in the channel_map indicates that the channel
  3902. * is not supported by the hardware at all.
  3903. *
  3904. * A value of 0xfe in the channel_map indicates that the channel is not
  3905. * valid for Tx with the current hardware. This means that
  3906. * while the system can tune and receive on a given channel, it may not
  3907. * be able to associate or transmit any frames on that
  3908. * channel. There is no corresponding channel information for that
  3909. * entry.
  3910. *
  3911. *********************************************************************/
  3912. /* 2.4 GHz */
  3913. static const u8 iwl3945_eeprom_band_1[14] = {
  3914. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3915. };
  3916. /* 5.2 GHz bands */
  3917. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3918. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3919. };
  3920. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3921. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3922. };
  3923. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3924. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3925. };
  3926. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3927. 145, 149, 153, 157, 161, 165
  3928. };
  3929. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3930. int *eeprom_ch_count,
  3931. const struct iwl3945_eeprom_channel
  3932. **eeprom_ch_info,
  3933. const u8 **eeprom_ch_index)
  3934. {
  3935. switch (band) {
  3936. case 1: /* 2.4GHz band */
  3937. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3938. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3939. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3940. break;
  3941. case 2: /* 4.9GHz band */
  3942. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3943. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3944. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3945. break;
  3946. case 3: /* 5.2GHz band */
  3947. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3948. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3949. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3950. break;
  3951. case 4: /* 5.5GHz band */
  3952. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3953. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3954. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3955. break;
  3956. case 5: /* 5.7GHz band */
  3957. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3958. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3959. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3960. break;
  3961. default:
  3962. BUG();
  3963. return;
  3964. }
  3965. }
  3966. /**
  3967. * iwl3945_get_channel_info - Find driver's private channel info
  3968. *
  3969. * Based on band and channel number.
  3970. */
  3971. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3972. enum ieee80211_band band, u16 channel)
  3973. {
  3974. int i;
  3975. switch (band) {
  3976. case IEEE80211_BAND_5GHZ:
  3977. for (i = 14; i < priv->channel_count; i++) {
  3978. if (priv->channel_info[i].channel == channel)
  3979. return &priv->channel_info[i];
  3980. }
  3981. break;
  3982. case IEEE80211_BAND_2GHZ:
  3983. if (channel >= 1 && channel <= 14)
  3984. return &priv->channel_info[channel - 1];
  3985. break;
  3986. case IEEE80211_NUM_BANDS:
  3987. WARN_ON(1);
  3988. }
  3989. return NULL;
  3990. }
  3991. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3992. ? # x " " : "")
  3993. /**
  3994. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3995. */
  3996. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3997. {
  3998. int eeprom_ch_count = 0;
  3999. const u8 *eeprom_ch_index = NULL;
  4000. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4001. int band, ch;
  4002. struct iwl3945_channel_info *ch_info;
  4003. if (priv->channel_count) {
  4004. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4005. return 0;
  4006. }
  4007. if (priv->eeprom.version < 0x2f) {
  4008. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4009. priv->eeprom.version);
  4010. return -EINVAL;
  4011. }
  4012. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4013. priv->channel_count =
  4014. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4015. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4016. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4017. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4018. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4019. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4020. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4021. priv->channel_count, GFP_KERNEL);
  4022. if (!priv->channel_info) {
  4023. IWL_ERROR("Could not allocate channel_info\n");
  4024. priv->channel_count = 0;
  4025. return -ENOMEM;
  4026. }
  4027. ch_info = priv->channel_info;
  4028. /* Loop through the 5 EEPROM bands adding them in order to the
  4029. * channel map we maintain (that contains additional information than
  4030. * what just in the EEPROM) */
  4031. for (band = 1; band <= 5; band++) {
  4032. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4033. &eeprom_ch_info, &eeprom_ch_index);
  4034. /* Loop through each band adding each of the channels */
  4035. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4036. ch_info->channel = eeprom_ch_index[ch];
  4037. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4038. IEEE80211_BAND_5GHZ;
  4039. /* permanently store EEPROM's channel regulatory flags
  4040. * and max power in channel info database. */
  4041. ch_info->eeprom = eeprom_ch_info[ch];
  4042. /* Copy the run-time flags so they are there even on
  4043. * invalid channels */
  4044. ch_info->flags = eeprom_ch_info[ch].flags;
  4045. if (!(is_channel_valid(ch_info))) {
  4046. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4047. "No traffic\n",
  4048. ch_info->channel,
  4049. ch_info->flags,
  4050. is_channel_a_band(ch_info) ?
  4051. "5.2" : "2.4");
  4052. ch_info++;
  4053. continue;
  4054. }
  4055. /* Initialize regulatory-based run-time data */
  4056. ch_info->max_power_avg = ch_info->curr_txpow =
  4057. eeprom_ch_info[ch].max_power_avg;
  4058. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4059. ch_info->min_power = 0;
  4060. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4061. " %ddBm): Ad-Hoc %ssupported\n",
  4062. ch_info->channel,
  4063. is_channel_a_band(ch_info) ?
  4064. "5.2" : "2.4",
  4065. CHECK_AND_PRINT(VALID),
  4066. CHECK_AND_PRINT(IBSS),
  4067. CHECK_AND_PRINT(ACTIVE),
  4068. CHECK_AND_PRINT(RADAR),
  4069. CHECK_AND_PRINT(WIDE),
  4070. CHECK_AND_PRINT(DFS),
  4071. eeprom_ch_info[ch].flags,
  4072. eeprom_ch_info[ch].max_power_avg,
  4073. ((eeprom_ch_info[ch].
  4074. flags & EEPROM_CHANNEL_IBSS)
  4075. && !(eeprom_ch_info[ch].
  4076. flags & EEPROM_CHANNEL_RADAR))
  4077. ? "" : "not ");
  4078. /* Set the user_txpower_limit to the highest power
  4079. * supported by any channel */
  4080. if (eeprom_ch_info[ch].max_power_avg >
  4081. priv->user_txpower_limit)
  4082. priv->user_txpower_limit =
  4083. eeprom_ch_info[ch].max_power_avg;
  4084. ch_info++;
  4085. }
  4086. }
  4087. /* Set up txpower settings in driver for all channels */
  4088. if (iwl3945_txpower_set_from_eeprom(priv))
  4089. return -EIO;
  4090. return 0;
  4091. }
  4092. /*
  4093. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4094. */
  4095. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4096. {
  4097. kfree(priv->channel_info);
  4098. priv->channel_count = 0;
  4099. }
  4100. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4101. * sending probe req. This should be set long enough to hear probe responses
  4102. * from more than one AP. */
  4103. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4104. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4105. /* For faster active scanning, scan will move to the next channel if fewer than
  4106. * PLCP_QUIET_THRESH packets are heard on this channel within
  4107. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4108. * time if it's a quiet channel (nothing responded to our probe, and there's
  4109. * no other traffic).
  4110. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4111. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4112. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4113. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4114. * Must be set longer than active dwell time.
  4115. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4116. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4117. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4118. #define IWL_PASSIVE_DWELL_BASE (100)
  4119. #define IWL_CHANNEL_TUNE_TIME 5
  4120. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4121. enum ieee80211_band band)
  4122. {
  4123. if (band == IEEE80211_BAND_5GHZ)
  4124. return IWL_ACTIVE_DWELL_TIME_52;
  4125. else
  4126. return IWL_ACTIVE_DWELL_TIME_24;
  4127. }
  4128. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4129. enum ieee80211_band band)
  4130. {
  4131. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4132. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4133. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4134. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4135. if (iwl3945_is_associated(priv)) {
  4136. /* If we're associated, we clamp the maximum passive
  4137. * dwell time to be 98% of the beacon interval (minus
  4138. * 2 * channel tune time) */
  4139. passive = priv->beacon_int;
  4140. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4141. passive = IWL_PASSIVE_DWELL_BASE;
  4142. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4143. }
  4144. if (passive <= active)
  4145. passive = active + 1;
  4146. return passive;
  4147. }
  4148. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4149. enum ieee80211_band band,
  4150. u8 is_active, u8 direct_mask,
  4151. struct iwl3945_scan_channel *scan_ch)
  4152. {
  4153. const struct ieee80211_channel *channels = NULL;
  4154. const struct ieee80211_supported_band *sband;
  4155. const struct iwl3945_channel_info *ch_info;
  4156. u16 passive_dwell = 0;
  4157. u16 active_dwell = 0;
  4158. int added, i;
  4159. sband = iwl3945_get_band(priv, band);
  4160. if (!sband)
  4161. return 0;
  4162. channels = sband->channels;
  4163. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4164. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4165. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4166. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4167. continue;
  4168. scan_ch->channel = channels[i].hw_value;
  4169. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4170. if (!is_channel_valid(ch_info)) {
  4171. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4172. scan_ch->channel);
  4173. continue;
  4174. }
  4175. if (!is_active || is_channel_passive(ch_info) ||
  4176. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4177. scan_ch->type = 0; /* passive */
  4178. else
  4179. scan_ch->type = 1; /* active */
  4180. if (scan_ch->type & 1)
  4181. scan_ch->type |= (direct_mask << 1);
  4182. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4183. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4184. /* Set txpower levels to defaults */
  4185. scan_ch->tpc.dsp_atten = 110;
  4186. /* scan_pwr_info->tpc.dsp_atten; */
  4187. /*scan_pwr_info->tpc.tx_gain; */
  4188. if (band == IEEE80211_BAND_5GHZ)
  4189. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4190. else {
  4191. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4192. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4193. * power level:
  4194. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4195. */
  4196. }
  4197. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4198. scan_ch->channel,
  4199. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4200. (scan_ch->type & 1) ?
  4201. active_dwell : passive_dwell);
  4202. scan_ch++;
  4203. added++;
  4204. }
  4205. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4206. return added;
  4207. }
  4208. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4209. struct ieee80211_rate *rates)
  4210. {
  4211. int i;
  4212. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4213. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4214. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4215. rates[i].hw_value_short = i;
  4216. rates[i].flags = 0;
  4217. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4218. /*
  4219. * If CCK != 1M then set short preamble rate flag.
  4220. */
  4221. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4222. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4223. }
  4224. }
  4225. }
  4226. /**
  4227. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4228. */
  4229. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4230. {
  4231. struct iwl3945_channel_info *ch;
  4232. struct ieee80211_supported_band *sband;
  4233. struct ieee80211_channel *channels;
  4234. struct ieee80211_channel *geo_ch;
  4235. struct ieee80211_rate *rates;
  4236. int i = 0;
  4237. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4238. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4239. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4240. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4241. return 0;
  4242. }
  4243. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4244. priv->channel_count, GFP_KERNEL);
  4245. if (!channels)
  4246. return -ENOMEM;
  4247. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4248. GFP_KERNEL);
  4249. if (!rates) {
  4250. kfree(channels);
  4251. return -ENOMEM;
  4252. }
  4253. /* 5.2GHz channels start after the 2.4GHz channels */
  4254. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4255. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4256. /* just OFDM */
  4257. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4258. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4259. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4260. sband->channels = channels;
  4261. /* OFDM & CCK */
  4262. sband->bitrates = rates;
  4263. sband->n_bitrates = IWL_RATE_COUNT;
  4264. priv->ieee_channels = channels;
  4265. priv->ieee_rates = rates;
  4266. iwl3945_init_hw_rates(priv, rates);
  4267. for (i = 0; i < priv->channel_count; i++) {
  4268. ch = &priv->channel_info[i];
  4269. /* FIXME: might be removed if scan is OK*/
  4270. if (!is_channel_valid(ch))
  4271. continue;
  4272. if (is_channel_a_band(ch))
  4273. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4274. else
  4275. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4276. geo_ch = &sband->channels[sband->n_channels++];
  4277. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4278. geo_ch->max_power = ch->max_power_avg;
  4279. geo_ch->max_antenna_gain = 0xff;
  4280. geo_ch->hw_value = ch->channel;
  4281. if (is_channel_valid(ch)) {
  4282. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4283. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4284. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4285. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4286. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4287. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4288. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4289. priv->max_channel_txpower_limit =
  4290. ch->max_power_avg;
  4291. } else {
  4292. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4293. }
  4294. /* Save flags for reg domain usage */
  4295. geo_ch->orig_flags = geo_ch->flags;
  4296. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4297. ch->channel, geo_ch->center_freq,
  4298. is_channel_a_band(ch) ? "5.2" : "2.4",
  4299. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4300. "restricted" : "valid",
  4301. geo_ch->flags);
  4302. }
  4303. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4304. priv->cfg->sku & IWL_SKU_A) {
  4305. printk(KERN_INFO DRV_NAME
  4306. ": Incorrectly detected BG card as ABG. Please send "
  4307. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4308. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4309. priv->cfg->sku &= ~IWL_SKU_A;
  4310. }
  4311. printk(KERN_INFO DRV_NAME
  4312. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4313. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4314. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4315. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4316. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4317. &priv->bands[IEEE80211_BAND_2GHZ];
  4318. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4319. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4320. &priv->bands[IEEE80211_BAND_5GHZ];
  4321. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4322. return 0;
  4323. }
  4324. /*
  4325. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4326. */
  4327. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4328. {
  4329. kfree(priv->ieee_channels);
  4330. kfree(priv->ieee_rates);
  4331. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4332. }
  4333. /******************************************************************************
  4334. *
  4335. * uCode download functions
  4336. *
  4337. ******************************************************************************/
  4338. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4339. {
  4340. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4341. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4342. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4343. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4344. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4345. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4346. }
  4347. /**
  4348. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4349. * looking at all data.
  4350. */
  4351. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4352. {
  4353. u32 val;
  4354. u32 save_len = len;
  4355. int rc = 0;
  4356. u32 errcnt;
  4357. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4358. rc = iwl3945_grab_nic_access(priv);
  4359. if (rc)
  4360. return rc;
  4361. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4362. errcnt = 0;
  4363. for (; len > 0; len -= sizeof(u32), image++) {
  4364. /* read data comes through single port, auto-incr addr */
  4365. /* NOTE: Use the debugless read so we don't flood kernel log
  4366. * if IWL_DL_IO is set */
  4367. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4368. if (val != le32_to_cpu(*image)) {
  4369. IWL_ERROR("uCode INST section is invalid at "
  4370. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4371. save_len - len, val, le32_to_cpu(*image));
  4372. rc = -EIO;
  4373. errcnt++;
  4374. if (errcnt >= 20)
  4375. break;
  4376. }
  4377. }
  4378. iwl3945_release_nic_access(priv);
  4379. if (!errcnt)
  4380. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4381. return rc;
  4382. }
  4383. /**
  4384. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4385. * using sample data 100 bytes apart. If these sample points are good,
  4386. * it's a pretty good bet that everything between them is good, too.
  4387. */
  4388. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4389. {
  4390. u32 val;
  4391. int rc = 0;
  4392. u32 errcnt = 0;
  4393. u32 i;
  4394. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4395. rc = iwl3945_grab_nic_access(priv);
  4396. if (rc)
  4397. return rc;
  4398. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4399. /* read data comes through single port, auto-incr addr */
  4400. /* NOTE: Use the debugless read so we don't flood kernel log
  4401. * if IWL_DL_IO is set */
  4402. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4403. i + RTC_INST_LOWER_BOUND);
  4404. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4405. if (val != le32_to_cpu(*image)) {
  4406. #if 0 /* Enable this if you want to see details */
  4407. IWL_ERROR("uCode INST section is invalid at "
  4408. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4409. i, val, *image);
  4410. #endif
  4411. rc = -EIO;
  4412. errcnt++;
  4413. if (errcnt >= 3)
  4414. break;
  4415. }
  4416. }
  4417. iwl3945_release_nic_access(priv);
  4418. return rc;
  4419. }
  4420. /**
  4421. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4422. * and verify its contents
  4423. */
  4424. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4425. {
  4426. __le32 *image;
  4427. u32 len;
  4428. int rc = 0;
  4429. /* Try bootstrap */
  4430. image = (__le32 *)priv->ucode_boot.v_addr;
  4431. len = priv->ucode_boot.len;
  4432. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4433. if (rc == 0) {
  4434. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4435. return 0;
  4436. }
  4437. /* Try initialize */
  4438. image = (__le32 *)priv->ucode_init.v_addr;
  4439. len = priv->ucode_init.len;
  4440. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4441. if (rc == 0) {
  4442. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4443. return 0;
  4444. }
  4445. /* Try runtime/protocol */
  4446. image = (__le32 *)priv->ucode_code.v_addr;
  4447. len = priv->ucode_code.len;
  4448. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4449. if (rc == 0) {
  4450. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4451. return 0;
  4452. }
  4453. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4454. /* Since nothing seems to match, show first several data entries in
  4455. * instruction SRAM, so maybe visual inspection will give a clue.
  4456. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4457. image = (__le32 *)priv->ucode_boot.v_addr;
  4458. len = priv->ucode_boot.len;
  4459. rc = iwl3945_verify_inst_full(priv, image, len);
  4460. return rc;
  4461. }
  4462. /* check contents of special bootstrap uCode SRAM */
  4463. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4464. {
  4465. __le32 *image = priv->ucode_boot.v_addr;
  4466. u32 len = priv->ucode_boot.len;
  4467. u32 reg;
  4468. u32 val;
  4469. IWL_DEBUG_INFO("Begin verify bsm\n");
  4470. /* verify BSM SRAM contents */
  4471. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4472. for (reg = BSM_SRAM_LOWER_BOUND;
  4473. reg < BSM_SRAM_LOWER_BOUND + len;
  4474. reg += sizeof(u32), image ++) {
  4475. val = iwl3945_read_prph(priv, reg);
  4476. if (val != le32_to_cpu(*image)) {
  4477. IWL_ERROR("BSM uCode verification failed at "
  4478. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4479. BSM_SRAM_LOWER_BOUND,
  4480. reg - BSM_SRAM_LOWER_BOUND, len,
  4481. val, le32_to_cpu(*image));
  4482. return -EIO;
  4483. }
  4484. }
  4485. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4486. return 0;
  4487. }
  4488. /**
  4489. * iwl3945_load_bsm - Load bootstrap instructions
  4490. *
  4491. * BSM operation:
  4492. *
  4493. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4494. * in special SRAM that does not power down during RFKILL. When powering back
  4495. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4496. * the bootstrap program into the on-board processor, and starts it.
  4497. *
  4498. * The bootstrap program loads (via DMA) instructions and data for a new
  4499. * program from host DRAM locations indicated by the host driver in the
  4500. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4501. * automatically.
  4502. *
  4503. * When initializing the NIC, the host driver points the BSM to the
  4504. * "initialize" uCode image. This uCode sets up some internal data, then
  4505. * notifies host via "initialize alive" that it is complete.
  4506. *
  4507. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4508. * normal runtime uCode instructions and a backup uCode data cache buffer
  4509. * (filled initially with starting data values for the on-board processor),
  4510. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4511. * which begins normal operation.
  4512. *
  4513. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4514. * the backup data cache in DRAM before SRAM is powered down.
  4515. *
  4516. * When powering back up, the BSM loads the bootstrap program. This reloads
  4517. * the runtime uCode instructions and the backup data cache into SRAM,
  4518. * and re-launches the runtime uCode from where it left off.
  4519. */
  4520. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4521. {
  4522. __le32 *image = priv->ucode_boot.v_addr;
  4523. u32 len = priv->ucode_boot.len;
  4524. dma_addr_t pinst;
  4525. dma_addr_t pdata;
  4526. u32 inst_len;
  4527. u32 data_len;
  4528. int rc;
  4529. int i;
  4530. u32 done;
  4531. u32 reg_offset;
  4532. IWL_DEBUG_INFO("Begin load bsm\n");
  4533. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4534. if (len > IWL_MAX_BSM_SIZE)
  4535. return -EINVAL;
  4536. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4537. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4538. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4539. * after the "initialize" uCode has run, to point to
  4540. * runtime/protocol instructions and backup data cache. */
  4541. pinst = priv->ucode_init.p_addr;
  4542. pdata = priv->ucode_init_data.p_addr;
  4543. inst_len = priv->ucode_init.len;
  4544. data_len = priv->ucode_init_data.len;
  4545. rc = iwl3945_grab_nic_access(priv);
  4546. if (rc)
  4547. return rc;
  4548. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4549. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4550. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4551. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4552. /* Fill BSM memory with bootstrap instructions */
  4553. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4554. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4555. reg_offset += sizeof(u32), image++)
  4556. _iwl3945_write_prph(priv, reg_offset,
  4557. le32_to_cpu(*image));
  4558. rc = iwl3945_verify_bsm(priv);
  4559. if (rc) {
  4560. iwl3945_release_nic_access(priv);
  4561. return rc;
  4562. }
  4563. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4564. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4565. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4566. RTC_INST_LOWER_BOUND);
  4567. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4568. /* Load bootstrap code into instruction SRAM now,
  4569. * to prepare to load "initialize" uCode */
  4570. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4571. BSM_WR_CTRL_REG_BIT_START);
  4572. /* Wait for load of bootstrap uCode to finish */
  4573. for (i = 0; i < 100; i++) {
  4574. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4575. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4576. break;
  4577. udelay(10);
  4578. }
  4579. if (i < 100)
  4580. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4581. else {
  4582. IWL_ERROR("BSM write did not complete!\n");
  4583. return -EIO;
  4584. }
  4585. /* Enable future boot loads whenever power management unit triggers it
  4586. * (e.g. when powering back up after power-save shutdown) */
  4587. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4588. BSM_WR_CTRL_REG_BIT_START_EN);
  4589. iwl3945_release_nic_access(priv);
  4590. return 0;
  4591. }
  4592. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4593. {
  4594. /* Remove all resets to allow NIC to operate */
  4595. iwl3945_write32(priv, CSR_RESET, 0);
  4596. }
  4597. /**
  4598. * iwl3945_read_ucode - Read uCode images from disk file.
  4599. *
  4600. * Copy into buffers for card to fetch via bus-mastering
  4601. */
  4602. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4603. {
  4604. struct iwl3945_ucode *ucode;
  4605. int ret = 0;
  4606. const struct firmware *ucode_raw;
  4607. /* firmware file name contains uCode/driver compatibility version */
  4608. const char *name = priv->cfg->fw_name;
  4609. u8 *src;
  4610. size_t len;
  4611. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4612. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4613. * request_firmware() is synchronous, file is in memory on return. */
  4614. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4615. if (ret < 0) {
  4616. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4617. name, ret);
  4618. goto error;
  4619. }
  4620. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4621. name, ucode_raw->size);
  4622. /* Make sure that we got at least our header! */
  4623. if (ucode_raw->size < sizeof(*ucode)) {
  4624. IWL_ERROR("File size way too small!\n");
  4625. ret = -EINVAL;
  4626. goto err_release;
  4627. }
  4628. /* Data from ucode file: header followed by uCode images */
  4629. ucode = (void *)ucode_raw->data;
  4630. ver = le32_to_cpu(ucode->ver);
  4631. inst_size = le32_to_cpu(ucode->inst_size);
  4632. data_size = le32_to_cpu(ucode->data_size);
  4633. init_size = le32_to_cpu(ucode->init_size);
  4634. init_data_size = le32_to_cpu(ucode->init_data_size);
  4635. boot_size = le32_to_cpu(ucode->boot_size);
  4636. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4637. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4638. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4639. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4640. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4641. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4642. /* Verify size of file vs. image size info in file's header */
  4643. if (ucode_raw->size < sizeof(*ucode) +
  4644. inst_size + data_size + init_size +
  4645. init_data_size + boot_size) {
  4646. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4647. (int)ucode_raw->size);
  4648. ret = -EINVAL;
  4649. goto err_release;
  4650. }
  4651. /* Verify that uCode images will fit in card's SRAM */
  4652. if (inst_size > IWL_MAX_INST_SIZE) {
  4653. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4654. inst_size);
  4655. ret = -EINVAL;
  4656. goto err_release;
  4657. }
  4658. if (data_size > IWL_MAX_DATA_SIZE) {
  4659. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4660. data_size);
  4661. ret = -EINVAL;
  4662. goto err_release;
  4663. }
  4664. if (init_size > IWL_MAX_INST_SIZE) {
  4665. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4666. init_size);
  4667. ret = -EINVAL;
  4668. goto err_release;
  4669. }
  4670. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4671. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4672. init_data_size);
  4673. ret = -EINVAL;
  4674. goto err_release;
  4675. }
  4676. if (boot_size > IWL_MAX_BSM_SIZE) {
  4677. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4678. boot_size);
  4679. ret = -EINVAL;
  4680. goto err_release;
  4681. }
  4682. /* Allocate ucode buffers for card's bus-master loading ... */
  4683. /* Runtime instructions and 2 copies of data:
  4684. * 1) unmodified from disk
  4685. * 2) backup cache for save/restore during power-downs */
  4686. priv->ucode_code.len = inst_size;
  4687. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4688. priv->ucode_data.len = data_size;
  4689. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4690. priv->ucode_data_backup.len = data_size;
  4691. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4692. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4693. !priv->ucode_data_backup.v_addr)
  4694. goto err_pci_alloc;
  4695. /* Initialization instructions and data */
  4696. if (init_size && init_data_size) {
  4697. priv->ucode_init.len = init_size;
  4698. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4699. priv->ucode_init_data.len = init_data_size;
  4700. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4701. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4702. goto err_pci_alloc;
  4703. }
  4704. /* Bootstrap (instructions only, no data) */
  4705. if (boot_size) {
  4706. priv->ucode_boot.len = boot_size;
  4707. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4708. if (!priv->ucode_boot.v_addr)
  4709. goto err_pci_alloc;
  4710. }
  4711. /* Copy images into buffers for card's bus-master reads ... */
  4712. /* Runtime instructions (first block of data in file) */
  4713. src = &ucode->data[0];
  4714. len = priv->ucode_code.len;
  4715. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4716. memcpy(priv->ucode_code.v_addr, src, len);
  4717. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4718. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4719. /* Runtime data (2nd block)
  4720. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4721. src = &ucode->data[inst_size];
  4722. len = priv->ucode_data.len;
  4723. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4724. memcpy(priv->ucode_data.v_addr, src, len);
  4725. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4726. /* Initialization instructions (3rd block) */
  4727. if (init_size) {
  4728. src = &ucode->data[inst_size + data_size];
  4729. len = priv->ucode_init.len;
  4730. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4731. len);
  4732. memcpy(priv->ucode_init.v_addr, src, len);
  4733. }
  4734. /* Initialization data (4th block) */
  4735. if (init_data_size) {
  4736. src = &ucode->data[inst_size + data_size + init_size];
  4737. len = priv->ucode_init_data.len;
  4738. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4739. (int)len);
  4740. memcpy(priv->ucode_init_data.v_addr, src, len);
  4741. }
  4742. /* Bootstrap instructions (5th block) */
  4743. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4744. len = priv->ucode_boot.len;
  4745. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4746. (int)len);
  4747. memcpy(priv->ucode_boot.v_addr, src, len);
  4748. /* We have our copies now, allow OS release its copies */
  4749. release_firmware(ucode_raw);
  4750. return 0;
  4751. err_pci_alloc:
  4752. IWL_ERROR("failed to allocate pci memory\n");
  4753. ret = -ENOMEM;
  4754. iwl3945_dealloc_ucode_pci(priv);
  4755. err_release:
  4756. release_firmware(ucode_raw);
  4757. error:
  4758. return ret;
  4759. }
  4760. /**
  4761. * iwl3945_set_ucode_ptrs - Set uCode address location
  4762. *
  4763. * Tell initialization uCode where to find runtime uCode.
  4764. *
  4765. * BSM registers initially contain pointers to initialization uCode.
  4766. * We need to replace them to load runtime uCode inst and data,
  4767. * and to save runtime data when powering down.
  4768. */
  4769. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4770. {
  4771. dma_addr_t pinst;
  4772. dma_addr_t pdata;
  4773. int rc = 0;
  4774. unsigned long flags;
  4775. /* bits 31:0 for 3945 */
  4776. pinst = priv->ucode_code.p_addr;
  4777. pdata = priv->ucode_data_backup.p_addr;
  4778. spin_lock_irqsave(&priv->lock, flags);
  4779. rc = iwl3945_grab_nic_access(priv);
  4780. if (rc) {
  4781. spin_unlock_irqrestore(&priv->lock, flags);
  4782. return rc;
  4783. }
  4784. /* Tell bootstrap uCode where to find image to load */
  4785. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4786. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4787. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4788. priv->ucode_data.len);
  4789. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4790. * that all new ptr/size info is in place */
  4791. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4792. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4793. iwl3945_release_nic_access(priv);
  4794. spin_unlock_irqrestore(&priv->lock, flags);
  4795. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4796. return rc;
  4797. }
  4798. /**
  4799. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4800. *
  4801. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4802. *
  4803. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4804. */
  4805. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4806. {
  4807. /* Check alive response for "valid" sign from uCode */
  4808. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4809. /* We had an error bringing up the hardware, so take it
  4810. * all the way back down so we can try again */
  4811. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4812. goto restart;
  4813. }
  4814. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4815. * This is a paranoid check, because we would not have gotten the
  4816. * "initialize" alive if code weren't properly loaded. */
  4817. if (iwl3945_verify_ucode(priv)) {
  4818. /* Runtime instruction load was bad;
  4819. * take it all the way back down so we can try again */
  4820. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4821. goto restart;
  4822. }
  4823. /* Send pointers to protocol/runtime uCode image ... init code will
  4824. * load and launch runtime uCode, which will send us another "Alive"
  4825. * notification. */
  4826. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4827. if (iwl3945_set_ucode_ptrs(priv)) {
  4828. /* Runtime instruction load won't happen;
  4829. * take it all the way back down so we can try again */
  4830. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4831. goto restart;
  4832. }
  4833. return;
  4834. restart:
  4835. queue_work(priv->workqueue, &priv->restart);
  4836. }
  4837. /**
  4838. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4839. * from protocol/runtime uCode (initialization uCode's
  4840. * Alive gets handled by iwl3945_init_alive_start()).
  4841. */
  4842. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4843. {
  4844. int rc = 0;
  4845. int thermal_spin = 0;
  4846. u32 rfkill;
  4847. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4848. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4849. /* We had an error bringing up the hardware, so take it
  4850. * all the way back down so we can try again */
  4851. IWL_DEBUG_INFO("Alive failed.\n");
  4852. goto restart;
  4853. }
  4854. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4855. * This is a paranoid check, because we would not have gotten the
  4856. * "runtime" alive if code weren't properly loaded. */
  4857. if (iwl3945_verify_ucode(priv)) {
  4858. /* Runtime instruction load was bad;
  4859. * take it all the way back down so we can try again */
  4860. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4861. goto restart;
  4862. }
  4863. iwl3945_clear_stations_table(priv);
  4864. rc = iwl3945_grab_nic_access(priv);
  4865. if (rc) {
  4866. IWL_WARNING("Can not read rfkill status from adapter\n");
  4867. return;
  4868. }
  4869. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4870. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4871. iwl3945_release_nic_access(priv);
  4872. if (rfkill & 0x1) {
  4873. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4874. /* if rfkill is not on, then wait for thermal
  4875. * sensor in adapter to kick in */
  4876. while (iwl3945_hw_get_temperature(priv) == 0) {
  4877. thermal_spin++;
  4878. udelay(10);
  4879. }
  4880. if (thermal_spin)
  4881. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4882. thermal_spin * 10);
  4883. } else
  4884. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4885. /* After the ALIVE response, we can send commands to 3945 uCode */
  4886. set_bit(STATUS_ALIVE, &priv->status);
  4887. /* Clear out the uCode error bit if it is set */
  4888. clear_bit(STATUS_FW_ERROR, &priv->status);
  4889. if (iwl3945_is_rfkill(priv))
  4890. return;
  4891. ieee80211_wake_queues(priv->hw);
  4892. priv->active_rate = priv->rates_mask;
  4893. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4894. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4895. if (iwl3945_is_associated(priv)) {
  4896. struct iwl3945_rxon_cmd *active_rxon =
  4897. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4898. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4899. sizeof(priv->staging_rxon));
  4900. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4901. } else {
  4902. /* Initialize our rx_config data */
  4903. iwl3945_connection_init_rx_config(priv);
  4904. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4905. }
  4906. /* Configure Bluetooth device coexistence support */
  4907. iwl3945_send_bt_config(priv);
  4908. /* Configure the adapter for unassociated operation */
  4909. iwl3945_commit_rxon(priv);
  4910. iwl3945_reg_txpower_periodic(priv);
  4911. iwl3945_led_register(priv);
  4912. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4913. set_bit(STATUS_READY, &priv->status);
  4914. wake_up_interruptible(&priv->wait_command_queue);
  4915. if (priv->error_recovering)
  4916. iwl3945_error_recovery(priv);
  4917. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  4918. return;
  4919. restart:
  4920. queue_work(priv->workqueue, &priv->restart);
  4921. }
  4922. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4923. static void __iwl3945_down(struct iwl3945_priv *priv)
  4924. {
  4925. unsigned long flags;
  4926. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4927. struct ieee80211_conf *conf = NULL;
  4928. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4929. conf = ieee80211_get_hw_conf(priv->hw);
  4930. if (!exit_pending)
  4931. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4932. iwl3945_led_unregister(priv);
  4933. iwl3945_clear_stations_table(priv);
  4934. /* Unblock any waiting calls */
  4935. wake_up_interruptible_all(&priv->wait_command_queue);
  4936. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4937. * exiting the module */
  4938. if (!exit_pending)
  4939. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4940. /* stop and reset the on-board processor */
  4941. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4942. /* tell the device to stop sending interrupts */
  4943. spin_lock_irqsave(&priv->lock, flags);
  4944. iwl3945_disable_interrupts(priv);
  4945. spin_unlock_irqrestore(&priv->lock, flags);
  4946. iwl_synchronize_irq(priv);
  4947. if (priv->mac80211_registered)
  4948. ieee80211_stop_queues(priv->hw);
  4949. /* If we have not previously called iwl3945_init() then
  4950. * clear all bits but the RF Kill and SUSPEND bits and return */
  4951. if (!iwl3945_is_init(priv)) {
  4952. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4953. STATUS_RF_KILL_HW |
  4954. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4955. STATUS_RF_KILL_SW |
  4956. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4957. STATUS_GEO_CONFIGURED |
  4958. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4959. STATUS_IN_SUSPEND;
  4960. goto exit;
  4961. }
  4962. /* ...otherwise clear out all the status bits but the RF Kill and
  4963. * SUSPEND bits and continue taking the NIC down. */
  4964. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4965. STATUS_RF_KILL_HW |
  4966. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4967. STATUS_RF_KILL_SW |
  4968. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4969. STATUS_GEO_CONFIGURED |
  4970. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4971. STATUS_IN_SUSPEND |
  4972. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4973. STATUS_FW_ERROR;
  4974. spin_lock_irqsave(&priv->lock, flags);
  4975. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4976. spin_unlock_irqrestore(&priv->lock, flags);
  4977. iwl3945_hw_txq_ctx_stop(priv);
  4978. iwl3945_hw_rxq_stop(priv);
  4979. spin_lock_irqsave(&priv->lock, flags);
  4980. if (!iwl3945_grab_nic_access(priv)) {
  4981. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4982. APMG_CLK_VAL_DMA_CLK_RQT);
  4983. iwl3945_release_nic_access(priv);
  4984. }
  4985. spin_unlock_irqrestore(&priv->lock, flags);
  4986. udelay(5);
  4987. iwl3945_hw_nic_stop_master(priv);
  4988. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4989. iwl3945_hw_nic_reset(priv);
  4990. exit:
  4991. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  4992. if (priv->ibss_beacon)
  4993. dev_kfree_skb(priv->ibss_beacon);
  4994. priv->ibss_beacon = NULL;
  4995. /* clear out any free frames */
  4996. iwl3945_clear_free_frames(priv);
  4997. }
  4998. static void iwl3945_down(struct iwl3945_priv *priv)
  4999. {
  5000. mutex_lock(&priv->mutex);
  5001. __iwl3945_down(priv);
  5002. mutex_unlock(&priv->mutex);
  5003. iwl3945_cancel_deferred_work(priv);
  5004. }
  5005. #define MAX_HW_RESTARTS 5
  5006. static int __iwl3945_up(struct iwl3945_priv *priv)
  5007. {
  5008. int rc, i;
  5009. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5010. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5011. return -EIO;
  5012. }
  5013. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5014. IWL_WARNING("Radio disabled by SW RF kill (module "
  5015. "parameter)\n");
  5016. return -ENODEV;
  5017. }
  5018. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5019. IWL_ERROR("ucode not available for device bringup\n");
  5020. return -EIO;
  5021. }
  5022. /* If platform's RF_KILL switch is NOT set to KILL */
  5023. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5024. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5025. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5026. else {
  5027. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5028. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5029. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5030. return -ENODEV;
  5031. }
  5032. }
  5033. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5034. rc = iwl3945_hw_nic_init(priv);
  5035. if (rc) {
  5036. IWL_ERROR("Unable to int nic\n");
  5037. return rc;
  5038. }
  5039. /* make sure rfkill handshake bits are cleared */
  5040. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5041. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5042. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5043. /* clear (again), then enable host interrupts */
  5044. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5045. iwl3945_enable_interrupts(priv);
  5046. /* really make sure rfkill handshake bits are cleared */
  5047. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5048. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5049. /* Copy original ucode data image from disk into backup cache.
  5050. * This will be used to initialize the on-board processor's
  5051. * data SRAM for a clean start when the runtime program first loads. */
  5052. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5053. priv->ucode_data.len);
  5054. /* We return success when we resume from suspend and rf_kill is on. */
  5055. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5056. return 0;
  5057. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5058. iwl3945_clear_stations_table(priv);
  5059. /* load bootstrap state machine,
  5060. * load bootstrap program into processor's memory,
  5061. * prepare to load the "initialize" uCode */
  5062. rc = iwl3945_load_bsm(priv);
  5063. if (rc) {
  5064. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5065. continue;
  5066. }
  5067. /* start card; "initialize" will load runtime ucode */
  5068. iwl3945_nic_start(priv);
  5069. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5070. return 0;
  5071. }
  5072. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5073. __iwl3945_down(priv);
  5074. /* tried to restart and config the device for as long as our
  5075. * patience could withstand */
  5076. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5077. return -EIO;
  5078. }
  5079. /*****************************************************************************
  5080. *
  5081. * Workqueue callbacks
  5082. *
  5083. *****************************************************************************/
  5084. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5085. {
  5086. struct iwl3945_priv *priv =
  5087. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5088. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5089. return;
  5090. mutex_lock(&priv->mutex);
  5091. iwl3945_init_alive_start(priv);
  5092. mutex_unlock(&priv->mutex);
  5093. }
  5094. static void iwl3945_bg_alive_start(struct work_struct *data)
  5095. {
  5096. struct iwl3945_priv *priv =
  5097. container_of(data, struct iwl3945_priv, alive_start.work);
  5098. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5099. return;
  5100. mutex_lock(&priv->mutex);
  5101. iwl3945_alive_start(priv);
  5102. mutex_unlock(&priv->mutex);
  5103. }
  5104. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5105. {
  5106. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5107. wake_up_interruptible(&priv->wait_command_queue);
  5108. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5109. return;
  5110. mutex_lock(&priv->mutex);
  5111. if (!iwl3945_is_rfkill(priv)) {
  5112. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5113. "HW and/or SW RF Kill no longer active, restarting "
  5114. "device\n");
  5115. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5116. queue_work(priv->workqueue, &priv->restart);
  5117. } else {
  5118. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5119. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5120. "disabled by SW switch\n");
  5121. else
  5122. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5123. "Kill switch must be turned off for "
  5124. "wireless networking to work.\n");
  5125. }
  5126. mutex_unlock(&priv->mutex);
  5127. }
  5128. static void iwl3945_bg_set_monitor(struct work_struct *work)
  5129. {
  5130. struct iwl3945_priv *priv = container_of(work,
  5131. struct iwl3945_priv, set_monitor);
  5132. IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
  5133. mutex_lock(&priv->mutex);
  5134. if (!iwl3945_is_ready(priv))
  5135. IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
  5136. else
  5137. if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
  5138. IWL_ERROR("iwl3945_set_mode() failed\n");
  5139. mutex_unlock(&priv->mutex);
  5140. }
  5141. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5142. static void iwl3945_bg_scan_check(struct work_struct *data)
  5143. {
  5144. struct iwl3945_priv *priv =
  5145. container_of(data, struct iwl3945_priv, scan_check.work);
  5146. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5147. return;
  5148. mutex_lock(&priv->mutex);
  5149. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5150. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5151. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5152. "Scan completion watchdog resetting adapter (%dms)\n",
  5153. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5154. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5155. iwl3945_send_scan_abort(priv);
  5156. }
  5157. mutex_unlock(&priv->mutex);
  5158. }
  5159. static void iwl3945_bg_request_scan(struct work_struct *data)
  5160. {
  5161. struct iwl3945_priv *priv =
  5162. container_of(data, struct iwl3945_priv, request_scan);
  5163. struct iwl3945_host_cmd cmd = {
  5164. .id = REPLY_SCAN_CMD,
  5165. .len = sizeof(struct iwl3945_scan_cmd),
  5166. .meta.flags = CMD_SIZE_HUGE,
  5167. };
  5168. int rc = 0;
  5169. struct iwl3945_scan_cmd *scan;
  5170. struct ieee80211_conf *conf = NULL;
  5171. u8 direct_mask;
  5172. enum ieee80211_band band;
  5173. conf = ieee80211_get_hw_conf(priv->hw);
  5174. mutex_lock(&priv->mutex);
  5175. if (!iwl3945_is_ready(priv)) {
  5176. IWL_WARNING("request scan called when driver not ready.\n");
  5177. goto done;
  5178. }
  5179. /* Make sure the scan wasn't cancelled before this queued work
  5180. * was given the chance to run... */
  5181. if (!test_bit(STATUS_SCANNING, &priv->status))
  5182. goto done;
  5183. /* This should never be called or scheduled if there is currently
  5184. * a scan active in the hardware. */
  5185. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5186. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5187. "Ignoring second request.\n");
  5188. rc = -EIO;
  5189. goto done;
  5190. }
  5191. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5192. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5193. goto done;
  5194. }
  5195. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5196. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5197. goto done;
  5198. }
  5199. if (iwl3945_is_rfkill(priv)) {
  5200. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5201. goto done;
  5202. }
  5203. if (!test_bit(STATUS_READY, &priv->status)) {
  5204. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5205. goto done;
  5206. }
  5207. if (!priv->scan_bands) {
  5208. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5209. goto done;
  5210. }
  5211. if (!priv->scan) {
  5212. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5213. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5214. if (!priv->scan) {
  5215. rc = -ENOMEM;
  5216. goto done;
  5217. }
  5218. }
  5219. scan = priv->scan;
  5220. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5221. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5222. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5223. if (iwl3945_is_associated(priv)) {
  5224. u16 interval = 0;
  5225. u32 extra;
  5226. u32 suspend_time = 100;
  5227. u32 scan_suspend_time = 100;
  5228. unsigned long flags;
  5229. IWL_DEBUG_INFO("Scanning while associated...\n");
  5230. spin_lock_irqsave(&priv->lock, flags);
  5231. interval = priv->beacon_int;
  5232. spin_unlock_irqrestore(&priv->lock, flags);
  5233. scan->suspend_time = 0;
  5234. scan->max_out_time = cpu_to_le32(200 * 1024);
  5235. if (!interval)
  5236. interval = suspend_time;
  5237. /*
  5238. * suspend time format:
  5239. * 0-19: beacon interval in usec (time before exec.)
  5240. * 20-23: 0
  5241. * 24-31: number of beacons (suspend between channels)
  5242. */
  5243. extra = (suspend_time / interval) << 24;
  5244. scan_suspend_time = 0xFF0FFFFF &
  5245. (extra | ((suspend_time % interval) * 1024));
  5246. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5247. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5248. scan_suspend_time, interval);
  5249. }
  5250. /* We should add the ability for user to lock to PASSIVE ONLY */
  5251. if (priv->one_direct_scan) {
  5252. IWL_DEBUG_SCAN
  5253. ("Kicking off one direct scan for '%s'\n",
  5254. iwl3945_escape_essid(priv->direct_ssid,
  5255. priv->direct_ssid_len));
  5256. scan->direct_scan[0].id = WLAN_EID_SSID;
  5257. scan->direct_scan[0].len = priv->direct_ssid_len;
  5258. memcpy(scan->direct_scan[0].ssid,
  5259. priv->direct_ssid, priv->direct_ssid_len);
  5260. direct_mask = 1;
  5261. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5262. IWL_DEBUG_SCAN
  5263. ("Kicking off one direct scan for '%s' when not associated\n",
  5264. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5265. scan->direct_scan[0].id = WLAN_EID_SSID;
  5266. scan->direct_scan[0].len = priv->essid_len;
  5267. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5268. direct_mask = 1;
  5269. } else {
  5270. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5271. direct_mask = 0;
  5272. }
  5273. /* We don't build a direct scan probe request; the uCode will do
  5274. * that based on the direct_mask added to each channel entry */
  5275. scan->tx_cmd.len = cpu_to_le16(
  5276. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5277. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5278. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5279. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5280. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5281. /* flags + rate selection */
  5282. switch (priv->scan_bands) {
  5283. case 2:
  5284. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5285. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5286. scan->good_CRC_th = 0;
  5287. band = IEEE80211_BAND_2GHZ;
  5288. break;
  5289. case 1:
  5290. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5291. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5292. band = IEEE80211_BAND_5GHZ;
  5293. break;
  5294. default:
  5295. IWL_WARNING("Invalid scan band count\n");
  5296. goto done;
  5297. }
  5298. /* select Rx antennas */
  5299. scan->flags |= iwl3945_get_antenna_flags(priv);
  5300. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5301. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5302. if (direct_mask)
  5303. scan->channel_count =
  5304. iwl3945_get_channels_for_scan(
  5305. priv, band, 1, /* active */
  5306. direct_mask,
  5307. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5308. else
  5309. scan->channel_count =
  5310. iwl3945_get_channels_for_scan(
  5311. priv, band, 0, /* passive */
  5312. direct_mask,
  5313. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5314. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5315. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5316. cmd.data = scan;
  5317. scan->len = cpu_to_le16(cmd.len);
  5318. set_bit(STATUS_SCAN_HW, &priv->status);
  5319. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5320. if (rc)
  5321. goto done;
  5322. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5323. IWL_SCAN_CHECK_WATCHDOG);
  5324. mutex_unlock(&priv->mutex);
  5325. return;
  5326. done:
  5327. /* inform mac80211 scan aborted */
  5328. queue_work(priv->workqueue, &priv->scan_completed);
  5329. mutex_unlock(&priv->mutex);
  5330. }
  5331. static void iwl3945_bg_up(struct work_struct *data)
  5332. {
  5333. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5334. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5335. return;
  5336. mutex_lock(&priv->mutex);
  5337. __iwl3945_up(priv);
  5338. mutex_unlock(&priv->mutex);
  5339. }
  5340. static void iwl3945_bg_restart(struct work_struct *data)
  5341. {
  5342. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5343. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5344. return;
  5345. iwl3945_down(priv);
  5346. queue_work(priv->workqueue, &priv->up);
  5347. }
  5348. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5349. {
  5350. struct iwl3945_priv *priv =
  5351. container_of(data, struct iwl3945_priv, rx_replenish);
  5352. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5353. return;
  5354. mutex_lock(&priv->mutex);
  5355. iwl3945_rx_replenish(priv);
  5356. mutex_unlock(&priv->mutex);
  5357. }
  5358. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5359. static void iwl3945_bg_post_associate(struct work_struct *data)
  5360. {
  5361. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5362. post_associate.work);
  5363. int rc = 0;
  5364. struct ieee80211_conf *conf = NULL;
  5365. DECLARE_MAC_BUF(mac);
  5366. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5367. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5368. return;
  5369. }
  5370. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5371. priv->assoc_id,
  5372. print_mac(mac, priv->active_rxon.bssid_addr));
  5373. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5374. return;
  5375. mutex_lock(&priv->mutex);
  5376. if (!priv->vif || !priv->is_open) {
  5377. mutex_unlock(&priv->mutex);
  5378. return;
  5379. }
  5380. iwl3945_scan_cancel_timeout(priv, 200);
  5381. conf = ieee80211_get_hw_conf(priv->hw);
  5382. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5383. iwl3945_commit_rxon(priv);
  5384. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5385. iwl3945_setup_rxon_timing(priv);
  5386. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5387. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5388. if (rc)
  5389. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5390. "Attempting to continue.\n");
  5391. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5392. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5393. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5394. priv->assoc_id, priv->beacon_int);
  5395. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5396. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5397. else
  5398. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5399. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5400. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5401. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5402. else
  5403. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5404. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5405. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5406. }
  5407. iwl3945_commit_rxon(priv);
  5408. switch (priv->iw_mode) {
  5409. case IEEE80211_IF_TYPE_STA:
  5410. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5411. break;
  5412. case IEEE80211_IF_TYPE_IBSS:
  5413. /* clear out the station table */
  5414. iwl3945_clear_stations_table(priv);
  5415. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5416. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5417. iwl3945_sync_sta(priv, IWL_STA_ID,
  5418. (priv->band == IEEE80211_BAND_5GHZ) ?
  5419. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5420. CMD_ASYNC);
  5421. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5422. iwl3945_send_beacon_cmd(priv);
  5423. break;
  5424. default:
  5425. IWL_ERROR("%s Should not be called in %d mode\n",
  5426. __FUNCTION__, priv->iw_mode);
  5427. break;
  5428. }
  5429. iwl3945_sequence_reset(priv);
  5430. iwl3945_activate_qos(priv, 0);
  5431. /* we have just associated, don't start scan too early */
  5432. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5433. mutex_unlock(&priv->mutex);
  5434. }
  5435. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5436. {
  5437. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5438. if (!iwl3945_is_ready(priv))
  5439. return;
  5440. mutex_lock(&priv->mutex);
  5441. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5442. iwl3945_send_scan_abort(priv);
  5443. mutex_unlock(&priv->mutex);
  5444. }
  5445. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5446. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5447. {
  5448. struct iwl3945_priv *priv =
  5449. container_of(work, struct iwl3945_priv, scan_completed);
  5450. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5451. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5452. return;
  5453. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5454. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5455. ieee80211_scan_completed(priv->hw);
  5456. /* Since setting the TXPOWER may have been deferred while
  5457. * performing the scan, fire one off */
  5458. mutex_lock(&priv->mutex);
  5459. iwl3945_hw_reg_send_txpower(priv);
  5460. mutex_unlock(&priv->mutex);
  5461. }
  5462. /*****************************************************************************
  5463. *
  5464. * mac80211 entry point functions
  5465. *
  5466. *****************************************************************************/
  5467. #define UCODE_READY_TIMEOUT (2 * HZ)
  5468. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5469. {
  5470. struct iwl3945_priv *priv = hw->priv;
  5471. int ret;
  5472. IWL_DEBUG_MAC80211("enter\n");
  5473. if (pci_enable_device(priv->pci_dev)) {
  5474. IWL_ERROR("Fail to pci_enable_device\n");
  5475. return -ENODEV;
  5476. }
  5477. pci_restore_state(priv->pci_dev);
  5478. pci_enable_msi(priv->pci_dev);
  5479. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5480. DRV_NAME, priv);
  5481. if (ret) {
  5482. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5483. goto out_disable_msi;
  5484. }
  5485. /* we should be verifying the device is ready to be opened */
  5486. mutex_lock(&priv->mutex);
  5487. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5488. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5489. * ucode filename and max sizes are card-specific. */
  5490. if (!priv->ucode_code.len) {
  5491. ret = iwl3945_read_ucode(priv);
  5492. if (ret) {
  5493. IWL_ERROR("Could not read microcode: %d\n", ret);
  5494. mutex_unlock(&priv->mutex);
  5495. goto out_release_irq;
  5496. }
  5497. }
  5498. ret = __iwl3945_up(priv);
  5499. mutex_unlock(&priv->mutex);
  5500. if (ret)
  5501. goto out_release_irq;
  5502. IWL_DEBUG_INFO("Start UP work.\n");
  5503. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5504. return 0;
  5505. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5506. * mac80211 will not be run successfully. */
  5507. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5508. test_bit(STATUS_READY, &priv->status),
  5509. UCODE_READY_TIMEOUT);
  5510. if (!ret) {
  5511. if (!test_bit(STATUS_READY, &priv->status)) {
  5512. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5513. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5514. ret = -ETIMEDOUT;
  5515. goto out_release_irq;
  5516. }
  5517. }
  5518. priv->is_open = 1;
  5519. IWL_DEBUG_MAC80211("leave\n");
  5520. return 0;
  5521. out_release_irq:
  5522. free_irq(priv->pci_dev->irq, priv);
  5523. out_disable_msi:
  5524. pci_disable_msi(priv->pci_dev);
  5525. pci_disable_device(priv->pci_dev);
  5526. priv->is_open = 0;
  5527. IWL_DEBUG_MAC80211("leave - failed\n");
  5528. return ret;
  5529. }
  5530. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5531. {
  5532. struct iwl3945_priv *priv = hw->priv;
  5533. IWL_DEBUG_MAC80211("enter\n");
  5534. if (!priv->is_open) {
  5535. IWL_DEBUG_MAC80211("leave - skip\n");
  5536. return;
  5537. }
  5538. priv->is_open = 0;
  5539. if (iwl3945_is_ready_rf(priv)) {
  5540. /* stop mac, cancel any scan request and clear
  5541. * RXON_FILTER_ASSOC_MSK BIT
  5542. */
  5543. mutex_lock(&priv->mutex);
  5544. iwl3945_scan_cancel_timeout(priv, 100);
  5545. cancel_delayed_work(&priv->post_associate);
  5546. mutex_unlock(&priv->mutex);
  5547. }
  5548. iwl3945_down(priv);
  5549. flush_workqueue(priv->workqueue);
  5550. free_irq(priv->pci_dev->irq, priv);
  5551. pci_disable_msi(priv->pci_dev);
  5552. pci_save_state(priv->pci_dev);
  5553. pci_disable_device(priv->pci_dev);
  5554. IWL_DEBUG_MAC80211("leave\n");
  5555. }
  5556. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5557. {
  5558. struct iwl3945_priv *priv = hw->priv;
  5559. IWL_DEBUG_MAC80211("enter\n");
  5560. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5561. IWL_DEBUG_MAC80211("leave - monitor\n");
  5562. return -1;
  5563. }
  5564. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5565. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5566. if (iwl3945_tx_skb(priv, skb))
  5567. dev_kfree_skb_any(skb);
  5568. IWL_DEBUG_MAC80211("leave\n");
  5569. return 0;
  5570. }
  5571. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5572. struct ieee80211_if_init_conf *conf)
  5573. {
  5574. struct iwl3945_priv *priv = hw->priv;
  5575. unsigned long flags;
  5576. DECLARE_MAC_BUF(mac);
  5577. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5578. if (priv->vif) {
  5579. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5580. return -EOPNOTSUPP;
  5581. }
  5582. spin_lock_irqsave(&priv->lock, flags);
  5583. priv->vif = conf->vif;
  5584. spin_unlock_irqrestore(&priv->lock, flags);
  5585. mutex_lock(&priv->mutex);
  5586. if (conf->mac_addr) {
  5587. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5588. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5589. }
  5590. if (iwl3945_is_ready(priv))
  5591. iwl3945_set_mode(priv, conf->type);
  5592. mutex_unlock(&priv->mutex);
  5593. IWL_DEBUG_MAC80211("leave\n");
  5594. return 0;
  5595. }
  5596. /**
  5597. * iwl3945_mac_config - mac80211 config callback
  5598. *
  5599. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5600. * be set inappropriately and the driver currently sets the hardware up to
  5601. * use it whenever needed.
  5602. */
  5603. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5604. {
  5605. struct iwl3945_priv *priv = hw->priv;
  5606. const struct iwl3945_channel_info *ch_info;
  5607. unsigned long flags;
  5608. int ret = 0;
  5609. mutex_lock(&priv->mutex);
  5610. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5611. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5612. if (!iwl3945_is_ready(priv)) {
  5613. IWL_DEBUG_MAC80211("leave - not ready\n");
  5614. ret = -EIO;
  5615. goto out;
  5616. }
  5617. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5618. test_bit(STATUS_SCANNING, &priv->status))) {
  5619. IWL_DEBUG_MAC80211("leave - scanning\n");
  5620. set_bit(STATUS_CONF_PENDING, &priv->status);
  5621. mutex_unlock(&priv->mutex);
  5622. return 0;
  5623. }
  5624. spin_lock_irqsave(&priv->lock, flags);
  5625. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5626. conf->channel->hw_value);
  5627. if (!is_channel_valid(ch_info)) {
  5628. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5629. conf->channel->hw_value, conf->channel->band);
  5630. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5631. spin_unlock_irqrestore(&priv->lock, flags);
  5632. ret = -EINVAL;
  5633. goto out;
  5634. }
  5635. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5636. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5637. /* The list of supported rates and rate mask can be different
  5638. * for each phymode; since the phymode may have changed, reset
  5639. * the rate mask to what mac80211 lists */
  5640. iwl3945_set_rate(priv);
  5641. spin_unlock_irqrestore(&priv->lock, flags);
  5642. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5643. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5644. iwl3945_hw_channel_switch(priv, conf->channel);
  5645. goto out;
  5646. }
  5647. #endif
  5648. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5649. if (!conf->radio_enabled) {
  5650. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5651. goto out;
  5652. }
  5653. if (iwl3945_is_rfkill(priv)) {
  5654. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5655. ret = -EIO;
  5656. goto out;
  5657. }
  5658. iwl3945_set_rate(priv);
  5659. if (memcmp(&priv->active_rxon,
  5660. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5661. iwl3945_commit_rxon(priv);
  5662. else
  5663. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5664. IWL_DEBUG_MAC80211("leave\n");
  5665. out:
  5666. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5667. mutex_unlock(&priv->mutex);
  5668. return ret;
  5669. }
  5670. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5671. {
  5672. int rc = 0;
  5673. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5674. return;
  5675. /* The following should be done only at AP bring up */
  5676. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5677. /* RXON - unassoc (to set timing command) */
  5678. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5679. iwl3945_commit_rxon(priv);
  5680. /* RXON Timing */
  5681. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5682. iwl3945_setup_rxon_timing(priv);
  5683. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5684. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5685. if (rc)
  5686. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5687. "Attempting to continue.\n");
  5688. /* FIXME: what should be the assoc_id for AP? */
  5689. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5690. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5691. priv->staging_rxon.flags |=
  5692. RXON_FLG_SHORT_PREAMBLE_MSK;
  5693. else
  5694. priv->staging_rxon.flags &=
  5695. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5696. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5697. if (priv->assoc_capability &
  5698. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5699. priv->staging_rxon.flags |=
  5700. RXON_FLG_SHORT_SLOT_MSK;
  5701. else
  5702. priv->staging_rxon.flags &=
  5703. ~RXON_FLG_SHORT_SLOT_MSK;
  5704. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5705. priv->staging_rxon.flags &=
  5706. ~RXON_FLG_SHORT_SLOT_MSK;
  5707. }
  5708. /* restore RXON assoc */
  5709. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5710. iwl3945_commit_rxon(priv);
  5711. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5712. }
  5713. iwl3945_send_beacon_cmd(priv);
  5714. /* FIXME - we need to add code here to detect a totally new
  5715. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5716. * clear sta table, add BCAST sta... */
  5717. }
  5718. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5719. struct ieee80211_vif *vif,
  5720. struct ieee80211_if_conf *conf)
  5721. {
  5722. struct iwl3945_priv *priv = hw->priv;
  5723. DECLARE_MAC_BUF(mac);
  5724. unsigned long flags;
  5725. int rc;
  5726. if (conf == NULL)
  5727. return -EIO;
  5728. if (priv->vif != vif) {
  5729. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5730. return 0;
  5731. }
  5732. /* XXX: this MUST use conf->mac_addr */
  5733. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5734. (!conf->beacon || !conf->ssid_len)) {
  5735. IWL_DEBUG_MAC80211
  5736. ("Leaving in AP mode because HostAPD is not ready.\n");
  5737. return 0;
  5738. }
  5739. if (!iwl3945_is_alive(priv))
  5740. return -EAGAIN;
  5741. mutex_lock(&priv->mutex);
  5742. if (conf->bssid)
  5743. IWL_DEBUG_MAC80211("bssid: %s\n",
  5744. print_mac(mac, conf->bssid));
  5745. /*
  5746. * very dubious code was here; the probe filtering flag is never set:
  5747. *
  5748. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5749. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5750. */
  5751. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5752. if (!conf->bssid) {
  5753. conf->bssid = priv->mac_addr;
  5754. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5755. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5756. print_mac(mac, conf->bssid));
  5757. }
  5758. if (priv->ibss_beacon)
  5759. dev_kfree_skb(priv->ibss_beacon);
  5760. priv->ibss_beacon = conf->beacon;
  5761. }
  5762. if (iwl3945_is_rfkill(priv))
  5763. goto done;
  5764. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5765. !is_multicast_ether_addr(conf->bssid)) {
  5766. /* If there is currently a HW scan going on in the background
  5767. * then we need to cancel it else the RXON below will fail. */
  5768. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5769. IWL_WARNING("Aborted scan still in progress "
  5770. "after 100ms\n");
  5771. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5772. mutex_unlock(&priv->mutex);
  5773. return -EAGAIN;
  5774. }
  5775. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5776. /* TODO: Audit driver for usage of these members and see
  5777. * if mac80211 deprecates them (priv->bssid looks like it
  5778. * shouldn't be there, but I haven't scanned the IBSS code
  5779. * to verify) - jpk */
  5780. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5781. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5782. iwl3945_config_ap(priv);
  5783. else {
  5784. rc = iwl3945_commit_rxon(priv);
  5785. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5786. iwl3945_add_station(priv,
  5787. priv->active_rxon.bssid_addr, 1, 0);
  5788. }
  5789. } else {
  5790. iwl3945_scan_cancel_timeout(priv, 100);
  5791. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5792. iwl3945_commit_rxon(priv);
  5793. }
  5794. done:
  5795. spin_lock_irqsave(&priv->lock, flags);
  5796. if (!conf->ssid_len)
  5797. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5798. else
  5799. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5800. priv->essid_len = conf->ssid_len;
  5801. spin_unlock_irqrestore(&priv->lock, flags);
  5802. IWL_DEBUG_MAC80211("leave\n");
  5803. mutex_unlock(&priv->mutex);
  5804. return 0;
  5805. }
  5806. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5807. unsigned int changed_flags,
  5808. unsigned int *total_flags,
  5809. int mc_count, struct dev_addr_list *mc_list)
  5810. {
  5811. /*
  5812. * XXX: dummy
  5813. * see also iwl3945_connection_init_rx_config
  5814. */
  5815. struct iwl3945_priv *priv = hw->priv;
  5816. int new_flags = 0;
  5817. if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  5818. if (*total_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  5819. IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
  5820. IEEE80211_IF_TYPE_MNTR,
  5821. changed_flags, *total_flags);
  5822. /* queue work 'cuz mac80211 is holding a lock which
  5823. * prevents us from issuing (synchronous) f/w cmds */
  5824. queue_work(priv->workqueue, &priv->set_monitor);
  5825. new_flags &= FIF_PROMISC_IN_BSS |
  5826. FIF_OTHER_BSS |
  5827. FIF_ALLMULTI;
  5828. }
  5829. }
  5830. *total_flags = new_flags;
  5831. }
  5832. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5833. struct ieee80211_if_init_conf *conf)
  5834. {
  5835. struct iwl3945_priv *priv = hw->priv;
  5836. IWL_DEBUG_MAC80211("enter\n");
  5837. mutex_lock(&priv->mutex);
  5838. if (iwl3945_is_ready_rf(priv)) {
  5839. iwl3945_scan_cancel_timeout(priv, 100);
  5840. cancel_delayed_work(&priv->post_associate);
  5841. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5842. iwl3945_commit_rxon(priv);
  5843. }
  5844. if (priv->vif == conf->vif) {
  5845. priv->vif = NULL;
  5846. memset(priv->bssid, 0, ETH_ALEN);
  5847. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5848. priv->essid_len = 0;
  5849. }
  5850. mutex_unlock(&priv->mutex);
  5851. IWL_DEBUG_MAC80211("leave\n");
  5852. }
  5853. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5854. {
  5855. int rc = 0;
  5856. unsigned long flags;
  5857. struct iwl3945_priv *priv = hw->priv;
  5858. IWL_DEBUG_MAC80211("enter\n");
  5859. mutex_lock(&priv->mutex);
  5860. spin_lock_irqsave(&priv->lock, flags);
  5861. if (!iwl3945_is_ready_rf(priv)) {
  5862. rc = -EIO;
  5863. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5864. goto out_unlock;
  5865. }
  5866. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5867. rc = -EIO;
  5868. IWL_ERROR("ERROR: APs don't scan\n");
  5869. goto out_unlock;
  5870. }
  5871. /* we don't schedule scan within next_scan_jiffies period */
  5872. if (priv->next_scan_jiffies &&
  5873. time_after(priv->next_scan_jiffies, jiffies)) {
  5874. rc = -EAGAIN;
  5875. goto out_unlock;
  5876. }
  5877. /* if we just finished scan ask for delay for a broadcast scan */
  5878. if ((len == 0) && priv->last_scan_jiffies &&
  5879. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5880. jiffies)) {
  5881. rc = -EAGAIN;
  5882. goto out_unlock;
  5883. }
  5884. if (len) {
  5885. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5886. iwl3945_escape_essid(ssid, len), (int)len);
  5887. priv->one_direct_scan = 1;
  5888. priv->direct_ssid_len = (u8)
  5889. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5890. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5891. } else
  5892. priv->one_direct_scan = 0;
  5893. rc = iwl3945_scan_initiate(priv);
  5894. IWL_DEBUG_MAC80211("leave\n");
  5895. out_unlock:
  5896. spin_unlock_irqrestore(&priv->lock, flags);
  5897. mutex_unlock(&priv->mutex);
  5898. return rc;
  5899. }
  5900. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5901. const u8 *local_addr, const u8 *addr,
  5902. struct ieee80211_key_conf *key)
  5903. {
  5904. struct iwl3945_priv *priv = hw->priv;
  5905. int rc = 0;
  5906. u8 sta_id;
  5907. IWL_DEBUG_MAC80211("enter\n");
  5908. if (!iwl3945_param_hwcrypto) {
  5909. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5910. return -EOPNOTSUPP;
  5911. }
  5912. if (is_zero_ether_addr(addr))
  5913. /* only support pairwise keys */
  5914. return -EOPNOTSUPP;
  5915. sta_id = iwl3945_hw_find_station(priv, addr);
  5916. if (sta_id == IWL_INVALID_STATION) {
  5917. DECLARE_MAC_BUF(mac);
  5918. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5919. print_mac(mac, addr));
  5920. return -EINVAL;
  5921. }
  5922. mutex_lock(&priv->mutex);
  5923. iwl3945_scan_cancel_timeout(priv, 100);
  5924. switch (cmd) {
  5925. case SET_KEY:
  5926. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5927. if (!rc) {
  5928. iwl3945_set_rxon_hwcrypto(priv, 1);
  5929. iwl3945_commit_rxon(priv);
  5930. key->hw_key_idx = sta_id;
  5931. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5932. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5933. }
  5934. break;
  5935. case DISABLE_KEY:
  5936. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5937. if (!rc) {
  5938. iwl3945_set_rxon_hwcrypto(priv, 0);
  5939. iwl3945_commit_rxon(priv);
  5940. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5941. }
  5942. break;
  5943. default:
  5944. rc = -EINVAL;
  5945. }
  5946. IWL_DEBUG_MAC80211("leave\n");
  5947. mutex_unlock(&priv->mutex);
  5948. return rc;
  5949. }
  5950. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5951. const struct ieee80211_tx_queue_params *params)
  5952. {
  5953. struct iwl3945_priv *priv = hw->priv;
  5954. unsigned long flags;
  5955. int q;
  5956. IWL_DEBUG_MAC80211("enter\n");
  5957. if (!iwl3945_is_ready_rf(priv)) {
  5958. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5959. return -EIO;
  5960. }
  5961. if (queue >= AC_NUM) {
  5962. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5963. return 0;
  5964. }
  5965. if (!priv->qos_data.qos_enable) {
  5966. priv->qos_data.qos_active = 0;
  5967. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5968. return 0;
  5969. }
  5970. q = AC_NUM - 1 - queue;
  5971. spin_lock_irqsave(&priv->lock, flags);
  5972. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5973. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5974. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5975. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5976. cpu_to_le16((params->txop * 32));
  5977. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5978. priv->qos_data.qos_active = 1;
  5979. spin_unlock_irqrestore(&priv->lock, flags);
  5980. mutex_lock(&priv->mutex);
  5981. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5982. iwl3945_activate_qos(priv, 1);
  5983. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5984. iwl3945_activate_qos(priv, 0);
  5985. mutex_unlock(&priv->mutex);
  5986. IWL_DEBUG_MAC80211("leave\n");
  5987. return 0;
  5988. }
  5989. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5990. struct ieee80211_tx_queue_stats *stats)
  5991. {
  5992. struct iwl3945_priv *priv = hw->priv;
  5993. int i, avail;
  5994. struct iwl3945_tx_queue *txq;
  5995. struct iwl3945_queue *q;
  5996. unsigned long flags;
  5997. IWL_DEBUG_MAC80211("enter\n");
  5998. if (!iwl3945_is_ready_rf(priv)) {
  5999. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6000. return -EIO;
  6001. }
  6002. spin_lock_irqsave(&priv->lock, flags);
  6003. for (i = 0; i < AC_NUM; i++) {
  6004. txq = &priv->txq[i];
  6005. q = &txq->q;
  6006. avail = iwl3945_queue_space(q);
  6007. stats[i].len = q->n_window - avail;
  6008. stats[i].limit = q->n_window - q->high_mark;
  6009. stats[i].count = q->n_window;
  6010. }
  6011. spin_unlock_irqrestore(&priv->lock, flags);
  6012. IWL_DEBUG_MAC80211("leave\n");
  6013. return 0;
  6014. }
  6015. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6016. struct ieee80211_low_level_stats *stats)
  6017. {
  6018. IWL_DEBUG_MAC80211("enter\n");
  6019. IWL_DEBUG_MAC80211("leave\n");
  6020. return 0;
  6021. }
  6022. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6023. {
  6024. IWL_DEBUG_MAC80211("enter\n");
  6025. IWL_DEBUG_MAC80211("leave\n");
  6026. return 0;
  6027. }
  6028. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6029. {
  6030. struct iwl3945_priv *priv = hw->priv;
  6031. unsigned long flags;
  6032. mutex_lock(&priv->mutex);
  6033. IWL_DEBUG_MAC80211("enter\n");
  6034. iwl3945_reset_qos(priv);
  6035. cancel_delayed_work(&priv->post_associate);
  6036. spin_lock_irqsave(&priv->lock, flags);
  6037. priv->assoc_id = 0;
  6038. priv->assoc_capability = 0;
  6039. priv->call_post_assoc_from_beacon = 0;
  6040. /* new association get rid of ibss beacon skb */
  6041. if (priv->ibss_beacon)
  6042. dev_kfree_skb(priv->ibss_beacon);
  6043. priv->ibss_beacon = NULL;
  6044. priv->beacon_int = priv->hw->conf.beacon_int;
  6045. priv->timestamp1 = 0;
  6046. priv->timestamp0 = 0;
  6047. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6048. priv->beacon_int = 0;
  6049. spin_unlock_irqrestore(&priv->lock, flags);
  6050. if (!iwl3945_is_ready_rf(priv)) {
  6051. IWL_DEBUG_MAC80211("leave - not ready\n");
  6052. mutex_unlock(&priv->mutex);
  6053. return;
  6054. }
  6055. /* we are restarting association process
  6056. * clear RXON_FILTER_ASSOC_MSK bit
  6057. */
  6058. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6059. iwl3945_scan_cancel_timeout(priv, 100);
  6060. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6061. iwl3945_commit_rxon(priv);
  6062. }
  6063. /* Per mac80211.h: This is only used in IBSS mode... */
  6064. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6065. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6066. mutex_unlock(&priv->mutex);
  6067. return;
  6068. }
  6069. iwl3945_set_rate(priv);
  6070. mutex_unlock(&priv->mutex);
  6071. IWL_DEBUG_MAC80211("leave\n");
  6072. }
  6073. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  6074. {
  6075. struct iwl3945_priv *priv = hw->priv;
  6076. unsigned long flags;
  6077. mutex_lock(&priv->mutex);
  6078. IWL_DEBUG_MAC80211("enter\n");
  6079. if (!iwl3945_is_ready_rf(priv)) {
  6080. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6081. mutex_unlock(&priv->mutex);
  6082. return -EIO;
  6083. }
  6084. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6085. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6086. mutex_unlock(&priv->mutex);
  6087. return -EIO;
  6088. }
  6089. spin_lock_irqsave(&priv->lock, flags);
  6090. if (priv->ibss_beacon)
  6091. dev_kfree_skb(priv->ibss_beacon);
  6092. priv->ibss_beacon = skb;
  6093. priv->assoc_id = 0;
  6094. IWL_DEBUG_MAC80211("leave\n");
  6095. spin_unlock_irqrestore(&priv->lock, flags);
  6096. iwl3945_reset_qos(priv);
  6097. queue_work(priv->workqueue, &priv->post_associate.work);
  6098. mutex_unlock(&priv->mutex);
  6099. return 0;
  6100. }
  6101. /*****************************************************************************
  6102. *
  6103. * sysfs attributes
  6104. *
  6105. *****************************************************************************/
  6106. #ifdef CONFIG_IWL3945_DEBUG
  6107. /*
  6108. * The following adds a new attribute to the sysfs representation
  6109. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6110. * used for controlling the debug level.
  6111. *
  6112. * See the level definitions in iwl for details.
  6113. */
  6114. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6115. {
  6116. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6117. }
  6118. static ssize_t store_debug_level(struct device_driver *d,
  6119. const char *buf, size_t count)
  6120. {
  6121. char *p = (char *)buf;
  6122. u32 val;
  6123. val = simple_strtoul(p, &p, 0);
  6124. if (p == buf)
  6125. printk(KERN_INFO DRV_NAME
  6126. ": %s is not in hex or decimal form.\n", buf);
  6127. else
  6128. iwl3945_debug_level = val;
  6129. return strnlen(buf, count);
  6130. }
  6131. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6132. show_debug_level, store_debug_level);
  6133. #endif /* CONFIG_IWL3945_DEBUG */
  6134. static ssize_t show_rf_kill(struct device *d,
  6135. struct device_attribute *attr, char *buf)
  6136. {
  6137. /*
  6138. * 0 - RF kill not enabled
  6139. * 1 - SW based RF kill active (sysfs)
  6140. * 2 - HW based RF kill active
  6141. * 3 - Both HW and SW based RF kill active
  6142. */
  6143. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6144. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6145. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6146. return sprintf(buf, "%i\n", val);
  6147. }
  6148. static ssize_t store_rf_kill(struct device *d,
  6149. struct device_attribute *attr,
  6150. const char *buf, size_t count)
  6151. {
  6152. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6153. mutex_lock(&priv->mutex);
  6154. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6155. mutex_unlock(&priv->mutex);
  6156. return count;
  6157. }
  6158. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6159. static ssize_t show_temperature(struct device *d,
  6160. struct device_attribute *attr, char *buf)
  6161. {
  6162. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6163. if (!iwl3945_is_alive(priv))
  6164. return -EAGAIN;
  6165. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6166. }
  6167. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6168. static ssize_t show_rs_window(struct device *d,
  6169. struct device_attribute *attr,
  6170. char *buf)
  6171. {
  6172. struct iwl3945_priv *priv = d->driver_data;
  6173. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6174. }
  6175. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6176. static ssize_t show_tx_power(struct device *d,
  6177. struct device_attribute *attr, char *buf)
  6178. {
  6179. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6180. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6181. }
  6182. static ssize_t store_tx_power(struct device *d,
  6183. struct device_attribute *attr,
  6184. const char *buf, size_t count)
  6185. {
  6186. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6187. char *p = (char *)buf;
  6188. u32 val;
  6189. val = simple_strtoul(p, &p, 10);
  6190. if (p == buf)
  6191. printk(KERN_INFO DRV_NAME
  6192. ": %s is not in decimal form.\n", buf);
  6193. else
  6194. iwl3945_hw_reg_set_txpower(priv, val);
  6195. return count;
  6196. }
  6197. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6198. static ssize_t show_flags(struct device *d,
  6199. struct device_attribute *attr, char *buf)
  6200. {
  6201. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6202. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6203. }
  6204. static ssize_t store_flags(struct device *d,
  6205. struct device_attribute *attr,
  6206. const char *buf, size_t count)
  6207. {
  6208. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6209. u32 flags = simple_strtoul(buf, NULL, 0);
  6210. mutex_lock(&priv->mutex);
  6211. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6212. /* Cancel any currently running scans... */
  6213. if (iwl3945_scan_cancel_timeout(priv, 100))
  6214. IWL_WARNING("Could not cancel scan.\n");
  6215. else {
  6216. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6217. flags);
  6218. priv->staging_rxon.flags = cpu_to_le32(flags);
  6219. iwl3945_commit_rxon(priv);
  6220. }
  6221. }
  6222. mutex_unlock(&priv->mutex);
  6223. return count;
  6224. }
  6225. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6226. static ssize_t show_filter_flags(struct device *d,
  6227. struct device_attribute *attr, char *buf)
  6228. {
  6229. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6230. return sprintf(buf, "0x%04X\n",
  6231. le32_to_cpu(priv->active_rxon.filter_flags));
  6232. }
  6233. static ssize_t store_filter_flags(struct device *d,
  6234. struct device_attribute *attr,
  6235. const char *buf, size_t count)
  6236. {
  6237. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6238. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6239. mutex_lock(&priv->mutex);
  6240. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6241. /* Cancel any currently running scans... */
  6242. if (iwl3945_scan_cancel_timeout(priv, 100))
  6243. IWL_WARNING("Could not cancel scan.\n");
  6244. else {
  6245. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6246. "0x%04X\n", filter_flags);
  6247. priv->staging_rxon.filter_flags =
  6248. cpu_to_le32(filter_flags);
  6249. iwl3945_commit_rxon(priv);
  6250. }
  6251. }
  6252. mutex_unlock(&priv->mutex);
  6253. return count;
  6254. }
  6255. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6256. store_filter_flags);
  6257. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6258. static ssize_t show_measurement(struct device *d,
  6259. struct device_attribute *attr, char *buf)
  6260. {
  6261. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6262. struct iwl3945_spectrum_notification measure_report;
  6263. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6264. u8 *data = (u8 *) & measure_report;
  6265. unsigned long flags;
  6266. spin_lock_irqsave(&priv->lock, flags);
  6267. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6268. spin_unlock_irqrestore(&priv->lock, flags);
  6269. return 0;
  6270. }
  6271. memcpy(&measure_report, &priv->measure_report, size);
  6272. priv->measurement_status = 0;
  6273. spin_unlock_irqrestore(&priv->lock, flags);
  6274. while (size && (PAGE_SIZE - len)) {
  6275. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6276. PAGE_SIZE - len, 1);
  6277. len = strlen(buf);
  6278. if (PAGE_SIZE - len)
  6279. buf[len++] = '\n';
  6280. ofs += 16;
  6281. size -= min(size, 16U);
  6282. }
  6283. return len;
  6284. }
  6285. static ssize_t store_measurement(struct device *d,
  6286. struct device_attribute *attr,
  6287. const char *buf, size_t count)
  6288. {
  6289. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6290. struct ieee80211_measurement_params params = {
  6291. .channel = le16_to_cpu(priv->active_rxon.channel),
  6292. .start_time = cpu_to_le64(priv->last_tsf),
  6293. .duration = cpu_to_le16(1),
  6294. };
  6295. u8 type = IWL_MEASURE_BASIC;
  6296. u8 buffer[32];
  6297. u8 channel;
  6298. if (count) {
  6299. char *p = buffer;
  6300. strncpy(buffer, buf, min(sizeof(buffer), count));
  6301. channel = simple_strtoul(p, NULL, 0);
  6302. if (channel)
  6303. params.channel = channel;
  6304. p = buffer;
  6305. while (*p && *p != ' ')
  6306. p++;
  6307. if (*p)
  6308. type = simple_strtoul(p + 1, NULL, 0);
  6309. }
  6310. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6311. "channel %d (for '%s')\n", type, params.channel, buf);
  6312. iwl3945_get_measurement(priv, &params, type);
  6313. return count;
  6314. }
  6315. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6316. show_measurement, store_measurement);
  6317. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6318. static ssize_t store_retry_rate(struct device *d,
  6319. struct device_attribute *attr,
  6320. const char *buf, size_t count)
  6321. {
  6322. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6323. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6324. if (priv->retry_rate <= 0)
  6325. priv->retry_rate = 1;
  6326. return count;
  6327. }
  6328. static ssize_t show_retry_rate(struct device *d,
  6329. struct device_attribute *attr, char *buf)
  6330. {
  6331. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6332. return sprintf(buf, "%d", priv->retry_rate);
  6333. }
  6334. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6335. store_retry_rate);
  6336. static ssize_t store_power_level(struct device *d,
  6337. struct device_attribute *attr,
  6338. const char *buf, size_t count)
  6339. {
  6340. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6341. int rc;
  6342. int mode;
  6343. mode = simple_strtoul(buf, NULL, 0);
  6344. mutex_lock(&priv->mutex);
  6345. if (!iwl3945_is_ready(priv)) {
  6346. rc = -EAGAIN;
  6347. goto out;
  6348. }
  6349. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6350. mode = IWL_POWER_AC;
  6351. else
  6352. mode |= IWL_POWER_ENABLED;
  6353. if (mode != priv->power_mode) {
  6354. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6355. if (rc) {
  6356. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6357. goto out;
  6358. }
  6359. priv->power_mode = mode;
  6360. }
  6361. rc = count;
  6362. out:
  6363. mutex_unlock(&priv->mutex);
  6364. return rc;
  6365. }
  6366. #define MAX_WX_STRING 80
  6367. /* Values are in microsecond */
  6368. static const s32 timeout_duration[] = {
  6369. 350000,
  6370. 250000,
  6371. 75000,
  6372. 37000,
  6373. 25000,
  6374. };
  6375. static const s32 period_duration[] = {
  6376. 400000,
  6377. 700000,
  6378. 1000000,
  6379. 1000000,
  6380. 1000000
  6381. };
  6382. static ssize_t show_power_level(struct device *d,
  6383. struct device_attribute *attr, char *buf)
  6384. {
  6385. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6386. int level = IWL_POWER_LEVEL(priv->power_mode);
  6387. char *p = buf;
  6388. p += sprintf(p, "%d ", level);
  6389. switch (level) {
  6390. case IWL_POWER_MODE_CAM:
  6391. case IWL_POWER_AC:
  6392. p += sprintf(p, "(AC)");
  6393. break;
  6394. case IWL_POWER_BATTERY:
  6395. p += sprintf(p, "(BATTERY)");
  6396. break;
  6397. default:
  6398. p += sprintf(p,
  6399. "(Timeout %dms, Period %dms)",
  6400. timeout_duration[level - 1] / 1000,
  6401. period_duration[level - 1] / 1000);
  6402. }
  6403. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6404. p += sprintf(p, " OFF\n");
  6405. else
  6406. p += sprintf(p, " \n");
  6407. return (p - buf + 1);
  6408. }
  6409. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6410. store_power_level);
  6411. static ssize_t show_channels(struct device *d,
  6412. struct device_attribute *attr, char *buf)
  6413. {
  6414. /* all this shit doesn't belong into sysfs anyway */
  6415. return 0;
  6416. }
  6417. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6418. static ssize_t show_statistics(struct device *d,
  6419. struct device_attribute *attr, char *buf)
  6420. {
  6421. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6422. u32 size = sizeof(struct iwl3945_notif_statistics);
  6423. u32 len = 0, ofs = 0;
  6424. u8 *data = (u8 *) & priv->statistics;
  6425. int rc = 0;
  6426. if (!iwl3945_is_alive(priv))
  6427. return -EAGAIN;
  6428. mutex_lock(&priv->mutex);
  6429. rc = iwl3945_send_statistics_request(priv);
  6430. mutex_unlock(&priv->mutex);
  6431. if (rc) {
  6432. len = sprintf(buf,
  6433. "Error sending statistics request: 0x%08X\n", rc);
  6434. return len;
  6435. }
  6436. while (size && (PAGE_SIZE - len)) {
  6437. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6438. PAGE_SIZE - len, 1);
  6439. len = strlen(buf);
  6440. if (PAGE_SIZE - len)
  6441. buf[len++] = '\n';
  6442. ofs += 16;
  6443. size -= min(size, 16U);
  6444. }
  6445. return len;
  6446. }
  6447. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6448. static ssize_t show_antenna(struct device *d,
  6449. struct device_attribute *attr, char *buf)
  6450. {
  6451. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6452. if (!iwl3945_is_alive(priv))
  6453. return -EAGAIN;
  6454. return sprintf(buf, "%d\n", priv->antenna);
  6455. }
  6456. static ssize_t store_antenna(struct device *d,
  6457. struct device_attribute *attr,
  6458. const char *buf, size_t count)
  6459. {
  6460. int ant;
  6461. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6462. if (count == 0)
  6463. return 0;
  6464. if (sscanf(buf, "%1i", &ant) != 1) {
  6465. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6466. return count;
  6467. }
  6468. if ((ant >= 0) && (ant <= 2)) {
  6469. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6470. priv->antenna = (enum iwl3945_antenna)ant;
  6471. } else
  6472. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6473. return count;
  6474. }
  6475. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6476. static ssize_t show_status(struct device *d,
  6477. struct device_attribute *attr, char *buf)
  6478. {
  6479. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6480. if (!iwl3945_is_alive(priv))
  6481. return -EAGAIN;
  6482. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6483. }
  6484. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6485. static ssize_t dump_error_log(struct device *d,
  6486. struct device_attribute *attr,
  6487. const char *buf, size_t count)
  6488. {
  6489. char *p = (char *)buf;
  6490. if (p[0] == '1')
  6491. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6492. return strnlen(buf, count);
  6493. }
  6494. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6495. static ssize_t dump_event_log(struct device *d,
  6496. struct device_attribute *attr,
  6497. const char *buf, size_t count)
  6498. {
  6499. char *p = (char *)buf;
  6500. if (p[0] == '1')
  6501. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6502. return strnlen(buf, count);
  6503. }
  6504. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6505. /*****************************************************************************
  6506. *
  6507. * driver setup and teardown
  6508. *
  6509. *****************************************************************************/
  6510. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6511. {
  6512. priv->workqueue = create_workqueue(DRV_NAME);
  6513. init_waitqueue_head(&priv->wait_command_queue);
  6514. INIT_WORK(&priv->up, iwl3945_bg_up);
  6515. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6516. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6517. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6518. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6519. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6520. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6521. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6522. INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
  6523. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6524. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6525. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6526. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6527. iwl3945_hw_setup_deferred_work(priv);
  6528. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6529. iwl3945_irq_tasklet, (unsigned long)priv);
  6530. }
  6531. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6532. {
  6533. iwl3945_hw_cancel_deferred_work(priv);
  6534. cancel_delayed_work_sync(&priv->init_alive_start);
  6535. cancel_delayed_work(&priv->scan_check);
  6536. cancel_delayed_work(&priv->alive_start);
  6537. cancel_delayed_work(&priv->post_associate);
  6538. cancel_work_sync(&priv->beacon_update);
  6539. }
  6540. static struct attribute *iwl3945_sysfs_entries[] = {
  6541. &dev_attr_antenna.attr,
  6542. &dev_attr_channels.attr,
  6543. &dev_attr_dump_errors.attr,
  6544. &dev_attr_dump_events.attr,
  6545. &dev_attr_flags.attr,
  6546. &dev_attr_filter_flags.attr,
  6547. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6548. &dev_attr_measurement.attr,
  6549. #endif
  6550. &dev_attr_power_level.attr,
  6551. &dev_attr_retry_rate.attr,
  6552. &dev_attr_rf_kill.attr,
  6553. &dev_attr_rs_window.attr,
  6554. &dev_attr_statistics.attr,
  6555. &dev_attr_status.attr,
  6556. &dev_attr_temperature.attr,
  6557. &dev_attr_tx_power.attr,
  6558. NULL
  6559. };
  6560. static struct attribute_group iwl3945_attribute_group = {
  6561. .name = NULL, /* put in device directory */
  6562. .attrs = iwl3945_sysfs_entries,
  6563. };
  6564. static struct ieee80211_ops iwl3945_hw_ops = {
  6565. .tx = iwl3945_mac_tx,
  6566. .start = iwl3945_mac_start,
  6567. .stop = iwl3945_mac_stop,
  6568. .add_interface = iwl3945_mac_add_interface,
  6569. .remove_interface = iwl3945_mac_remove_interface,
  6570. .config = iwl3945_mac_config,
  6571. .config_interface = iwl3945_mac_config_interface,
  6572. .configure_filter = iwl3945_configure_filter,
  6573. .set_key = iwl3945_mac_set_key,
  6574. .get_stats = iwl3945_mac_get_stats,
  6575. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6576. .conf_tx = iwl3945_mac_conf_tx,
  6577. .get_tsf = iwl3945_mac_get_tsf,
  6578. .reset_tsf = iwl3945_mac_reset_tsf,
  6579. .beacon_update = iwl3945_mac_beacon_update,
  6580. .hw_scan = iwl3945_mac_hw_scan
  6581. };
  6582. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6583. {
  6584. int err = 0;
  6585. struct iwl3945_priv *priv;
  6586. struct ieee80211_hw *hw;
  6587. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6588. int i;
  6589. unsigned long flags;
  6590. DECLARE_MAC_BUF(mac);
  6591. /* Disabling hardware scan means that mac80211 will perform scans
  6592. * "the hard way", rather than using device's scan. */
  6593. if (iwl3945_param_disable_hw_scan) {
  6594. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6595. iwl3945_hw_ops.hw_scan = NULL;
  6596. }
  6597. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6598. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6599. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6600. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6601. err = -EINVAL;
  6602. goto out;
  6603. }
  6604. /* mac80211 allocates memory for this device instance, including
  6605. * space for this driver's private structure */
  6606. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6607. if (hw == NULL) {
  6608. IWL_ERROR("Can not allocate network device\n");
  6609. err = -ENOMEM;
  6610. goto out;
  6611. }
  6612. SET_IEEE80211_DEV(hw, &pdev->dev);
  6613. hw->rate_control_algorithm = "iwl-3945-rs";
  6614. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6615. priv = hw->priv;
  6616. priv->hw = hw;
  6617. priv->pci_dev = pdev;
  6618. priv->cfg = cfg;
  6619. /* Select antenna (may be helpful if only one antenna is connected) */
  6620. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6621. #ifdef CONFIG_IWL3945_DEBUG
  6622. iwl3945_debug_level = iwl3945_param_debug;
  6623. atomic_set(&priv->restrict_refcnt, 0);
  6624. #endif
  6625. priv->retry_rate = 1;
  6626. priv->ibss_beacon = NULL;
  6627. /* Tell mac80211 our characteristics */
  6628. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  6629. IEEE80211_HW_SIGNAL_DBM |
  6630. IEEE80211_HW_NOISE_DBM;
  6631. /* 4 EDCA QOS priorities */
  6632. hw->queues = 4;
  6633. spin_lock_init(&priv->lock);
  6634. spin_lock_init(&priv->power_data.lock);
  6635. spin_lock_init(&priv->sta_lock);
  6636. spin_lock_init(&priv->hcmd_lock);
  6637. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6638. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6639. INIT_LIST_HEAD(&priv->free_frames);
  6640. mutex_init(&priv->mutex);
  6641. if (pci_enable_device(pdev)) {
  6642. err = -ENODEV;
  6643. goto out_ieee80211_free_hw;
  6644. }
  6645. pci_set_master(pdev);
  6646. /* Clear the driver's (not device's) station table */
  6647. iwl3945_clear_stations_table(priv);
  6648. priv->data_retry_limit = -1;
  6649. priv->ieee_channels = NULL;
  6650. priv->ieee_rates = NULL;
  6651. priv->band = IEEE80211_BAND_2GHZ;
  6652. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6653. if (!err)
  6654. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6655. if (err) {
  6656. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6657. goto out_pci_disable_device;
  6658. }
  6659. pci_set_drvdata(pdev, priv);
  6660. err = pci_request_regions(pdev, DRV_NAME);
  6661. if (err)
  6662. goto out_pci_disable_device;
  6663. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6664. * PCI Tx retries from interfering with C3 CPU state */
  6665. pci_write_config_byte(pdev, 0x41, 0x00);
  6666. priv->hw_base = pci_iomap(pdev, 0, 0);
  6667. if (!priv->hw_base) {
  6668. err = -ENODEV;
  6669. goto out_pci_release_regions;
  6670. }
  6671. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6672. (unsigned long long) pci_resource_len(pdev, 0));
  6673. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6674. /* Initialize module parameter values here */
  6675. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6676. if (iwl3945_param_disable) {
  6677. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6678. IWL_DEBUG_INFO("Radio disabled.\n");
  6679. }
  6680. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6681. printk(KERN_INFO DRV_NAME
  6682. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6683. /* Device-specific setup */
  6684. if (iwl3945_hw_set_hw_setting(priv)) {
  6685. IWL_ERROR("failed to set hw settings\n");
  6686. goto out_iounmap;
  6687. }
  6688. if (iwl3945_param_qos_enable)
  6689. priv->qos_data.qos_enable = 1;
  6690. iwl3945_reset_qos(priv);
  6691. priv->qos_data.qos_active = 0;
  6692. priv->qos_data.qos_cap.val = 0;
  6693. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6694. iwl3945_setup_deferred_work(priv);
  6695. iwl3945_setup_rx_handlers(priv);
  6696. priv->rates_mask = IWL_RATES_MASK;
  6697. /* If power management is turned on, default to AC mode */
  6698. priv->power_mode = IWL_POWER_AC;
  6699. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6700. spin_lock_irqsave(&priv->lock, flags);
  6701. iwl3945_disable_interrupts(priv);
  6702. spin_unlock_irqrestore(&priv->lock, flags);
  6703. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6704. if (err) {
  6705. IWL_ERROR("failed to create sysfs device attributes\n");
  6706. goto out_release_irq;
  6707. }
  6708. /* nic init */
  6709. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6710. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6711. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6712. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6713. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6714. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6715. if (err < 0) {
  6716. IWL_DEBUG_INFO("Failed to init the card\n");
  6717. goto out_remove_sysfs;
  6718. }
  6719. /* Read the EEPROM */
  6720. err = iwl3945_eeprom_init(priv);
  6721. if (err) {
  6722. IWL_ERROR("Unable to init EEPROM\n");
  6723. goto out_remove_sysfs;
  6724. }
  6725. /* MAC Address location in EEPROM same for 3945/4965 */
  6726. get_eeprom_mac(priv, priv->mac_addr);
  6727. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6728. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6729. err = iwl3945_init_channel_map(priv);
  6730. if (err) {
  6731. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6732. goto out_remove_sysfs;
  6733. }
  6734. err = iwl3945_init_geos(priv);
  6735. if (err) {
  6736. IWL_ERROR("initializing geos failed: %d\n", err);
  6737. goto out_free_channel_map;
  6738. }
  6739. err = ieee80211_register_hw(priv->hw);
  6740. if (err) {
  6741. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6742. goto out_free_geos;
  6743. }
  6744. priv->hw->conf.beacon_int = 100;
  6745. priv->mac80211_registered = 1;
  6746. pci_save_state(pdev);
  6747. pci_disable_device(pdev);
  6748. return 0;
  6749. out_free_geos:
  6750. iwl3945_free_geos(priv);
  6751. out_free_channel_map:
  6752. iwl3945_free_channel_map(priv);
  6753. out_remove_sysfs:
  6754. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6755. out_release_irq:
  6756. destroy_workqueue(priv->workqueue);
  6757. priv->workqueue = NULL;
  6758. iwl3945_unset_hw_setting(priv);
  6759. out_iounmap:
  6760. pci_iounmap(pdev, priv->hw_base);
  6761. out_pci_release_regions:
  6762. pci_release_regions(pdev);
  6763. out_pci_disable_device:
  6764. pci_disable_device(pdev);
  6765. pci_set_drvdata(pdev, NULL);
  6766. out_ieee80211_free_hw:
  6767. ieee80211_free_hw(priv->hw);
  6768. out:
  6769. return err;
  6770. }
  6771. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6772. {
  6773. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6774. struct list_head *p, *q;
  6775. int i;
  6776. unsigned long flags;
  6777. if (!priv)
  6778. return;
  6779. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6780. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6781. iwl3945_down(priv);
  6782. /* make sure we flush any pending irq or
  6783. * tasklet for the driver
  6784. */
  6785. spin_lock_irqsave(&priv->lock, flags);
  6786. iwl3945_disable_interrupts(priv);
  6787. spin_unlock_irqrestore(&priv->lock, flags);
  6788. iwl_synchronize_irq(priv);
  6789. /* Free MAC hash list for ADHOC */
  6790. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  6791. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  6792. list_del(p);
  6793. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  6794. }
  6795. }
  6796. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6797. iwl3945_dealloc_ucode_pci(priv);
  6798. if (priv->rxq.bd)
  6799. iwl3945_rx_queue_free(priv, &priv->rxq);
  6800. iwl3945_hw_txq_ctx_free(priv);
  6801. iwl3945_unset_hw_setting(priv);
  6802. iwl3945_clear_stations_table(priv);
  6803. if (priv->mac80211_registered) {
  6804. ieee80211_unregister_hw(priv->hw);
  6805. }
  6806. /*netif_stop_queue(dev); */
  6807. flush_workqueue(priv->workqueue);
  6808. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6809. * priv->workqueue... so we can't take down the workqueue
  6810. * until now... */
  6811. destroy_workqueue(priv->workqueue);
  6812. priv->workqueue = NULL;
  6813. pci_iounmap(pdev, priv->hw_base);
  6814. pci_release_regions(pdev);
  6815. pci_disable_device(pdev);
  6816. pci_set_drvdata(pdev, NULL);
  6817. iwl3945_free_channel_map(priv);
  6818. iwl3945_free_geos(priv);
  6819. kfree(priv->scan);
  6820. if (priv->ibss_beacon)
  6821. dev_kfree_skb(priv->ibss_beacon);
  6822. ieee80211_free_hw(priv->hw);
  6823. }
  6824. #ifdef CONFIG_PM
  6825. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6826. {
  6827. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6828. if (priv->is_open) {
  6829. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6830. iwl3945_mac_stop(priv->hw);
  6831. priv->is_open = 1;
  6832. }
  6833. pci_set_power_state(pdev, PCI_D3hot);
  6834. return 0;
  6835. }
  6836. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6837. {
  6838. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6839. pci_set_power_state(pdev, PCI_D0);
  6840. if (priv->is_open)
  6841. iwl3945_mac_start(priv->hw);
  6842. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6843. return 0;
  6844. }
  6845. #endif /* CONFIG_PM */
  6846. /*****************************************************************************
  6847. *
  6848. * driver and module entry point
  6849. *
  6850. *****************************************************************************/
  6851. static struct pci_driver iwl3945_driver = {
  6852. .name = DRV_NAME,
  6853. .id_table = iwl3945_hw_card_ids,
  6854. .probe = iwl3945_pci_probe,
  6855. .remove = __devexit_p(iwl3945_pci_remove),
  6856. #ifdef CONFIG_PM
  6857. .suspend = iwl3945_pci_suspend,
  6858. .resume = iwl3945_pci_resume,
  6859. #endif
  6860. };
  6861. static int __init iwl3945_init(void)
  6862. {
  6863. int ret;
  6864. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6865. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6866. ret = iwl3945_rate_control_register();
  6867. if (ret) {
  6868. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6869. return ret;
  6870. }
  6871. ret = pci_register_driver(&iwl3945_driver);
  6872. if (ret) {
  6873. IWL_ERROR("Unable to initialize PCI module\n");
  6874. goto error_register;
  6875. }
  6876. #ifdef CONFIG_IWL3945_DEBUG
  6877. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6878. if (ret) {
  6879. IWL_ERROR("Unable to create driver sysfs file\n");
  6880. goto error_debug;
  6881. }
  6882. #endif
  6883. return ret;
  6884. #ifdef CONFIG_IWL3945_DEBUG
  6885. error_debug:
  6886. pci_unregister_driver(&iwl3945_driver);
  6887. #endif
  6888. error_register:
  6889. iwl3945_rate_control_unregister();
  6890. return ret;
  6891. }
  6892. static void __exit iwl3945_exit(void)
  6893. {
  6894. #ifdef CONFIG_IWL3945_DEBUG
  6895. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6896. #endif
  6897. pci_unregister_driver(&iwl3945_driver);
  6898. iwl3945_rate_control_unregister();
  6899. }
  6900. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6901. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6902. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6903. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6904. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6905. MODULE_PARM_DESC(hwcrypto,
  6906. "using hardware crypto engine (default 0 [software])\n");
  6907. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6908. MODULE_PARM_DESC(debug, "debug output mask");
  6909. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6910. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6911. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6912. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6913. /* QoS */
  6914. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6915. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6916. module_exit(iwl3945_exit);
  6917. module_init(iwl3945_init);