tg3.c 375 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2007 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/compiler.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/in.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/mii.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/ip.h>
  35. #include <linux/tcp.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/prefetch.h>
  38. #include <linux/dma-mapping.h>
  39. #include <net/checksum.h>
  40. #include <net/ip.h>
  41. #include <asm/system.h>
  42. #include <asm/io.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/uaccess.h>
  45. #ifdef CONFIG_SPARC
  46. #include <asm/idprom.h>
  47. #include <asm/prom.h>
  48. #endif
  49. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  50. #define TG3_VLAN_TAG_USED 1
  51. #else
  52. #define TG3_VLAN_TAG_USED 0
  53. #endif
  54. #define TG3_TSO_SUPPORT 1
  55. #include "tg3.h"
  56. #define DRV_MODULE_NAME "tg3"
  57. #define PFX DRV_MODULE_NAME ": "
  58. #define DRV_MODULE_VERSION "3.92"
  59. #define DRV_MODULE_RELDATE "May 2, 2008"
  60. #define TG3_DEF_MAC_MODE 0
  61. #define TG3_DEF_RX_MODE 0
  62. #define TG3_DEF_TX_MODE 0
  63. #define TG3_DEF_MSG_ENABLE \
  64. (NETIF_MSG_DRV | \
  65. NETIF_MSG_PROBE | \
  66. NETIF_MSG_LINK | \
  67. NETIF_MSG_TIMER | \
  68. NETIF_MSG_IFDOWN | \
  69. NETIF_MSG_IFUP | \
  70. NETIF_MSG_RX_ERR | \
  71. NETIF_MSG_TX_ERR)
  72. /* length of time before we decide the hardware is borked,
  73. * and dev->tx_timeout() should be called to fix the problem
  74. */
  75. #define TG3_TX_TIMEOUT (5 * HZ)
  76. /* hardware minimum and maximum for a single frame's data payload */
  77. #define TG3_MIN_MTU 60
  78. #define TG3_MAX_MTU(tp) \
  79. ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  80. /* These numbers seem to be hard coded in the NIC firmware somehow.
  81. * You can't change the ring sizes, but you can change where you place
  82. * them in the NIC onboard memory.
  83. */
  84. #define TG3_RX_RING_SIZE 512
  85. #define TG3_DEF_RX_RING_PENDING 200
  86. #define TG3_RX_JUMBO_RING_SIZE 256
  87. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  88. /* Do not place this n-ring entries value into the tp struct itself,
  89. * we really want to expose these constants to GCC so that modulo et
  90. * al. operations are done with shifts and masks instead of with
  91. * hw multiply/modulo instructions. Another solution would be to
  92. * replace things like '% foo' with '& (foo - 1)'.
  93. */
  94. #define TG3_RX_RCB_RING_SIZE(tp) \
  95. ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
  96. #define TG3_TX_RING_SIZE 512
  97. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  98. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  99. TG3_RX_RING_SIZE)
  100. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  101. TG3_RX_JUMBO_RING_SIZE)
  102. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  103. TG3_RX_RCB_RING_SIZE(tp))
  104. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  105. TG3_TX_RING_SIZE)
  106. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  107. #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
  108. #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
  109. /* minimum number of free TX descriptors required to wake up TX process */
  110. #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
  111. /* number of ETHTOOL_GSTATS u64's */
  112. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  113. #define TG3_NUM_TEST 6
  114. static char version[] __devinitdata =
  115. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  116. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  117. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  118. MODULE_LICENSE("GPL");
  119. MODULE_VERSION(DRV_MODULE_VERSION);
  120. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  121. module_param(tg3_debug, int, 0);
  122. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  123. static struct pci_device_id tg3_pci_tbl[] = {
  124. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  125. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  126. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  127. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  128. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  129. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  130. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  131. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  132. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  133. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  134. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  158. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  159. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  160. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  161. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  162. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  163. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  164. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  165. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  166. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  167. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  184. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  185. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  186. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  187. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  188. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  189. {}
  190. };
  191. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  192. static const struct {
  193. const char string[ETH_GSTRING_LEN];
  194. } ethtool_stats_keys[TG3_NUM_STATS] = {
  195. { "rx_octets" },
  196. { "rx_fragments" },
  197. { "rx_ucast_packets" },
  198. { "rx_mcast_packets" },
  199. { "rx_bcast_packets" },
  200. { "rx_fcs_errors" },
  201. { "rx_align_errors" },
  202. { "rx_xon_pause_rcvd" },
  203. { "rx_xoff_pause_rcvd" },
  204. { "rx_mac_ctrl_rcvd" },
  205. { "rx_xoff_entered" },
  206. { "rx_frame_too_long_errors" },
  207. { "rx_jabbers" },
  208. { "rx_undersize_packets" },
  209. { "rx_in_length_errors" },
  210. { "rx_out_length_errors" },
  211. { "rx_64_or_less_octet_packets" },
  212. { "rx_65_to_127_octet_packets" },
  213. { "rx_128_to_255_octet_packets" },
  214. { "rx_256_to_511_octet_packets" },
  215. { "rx_512_to_1023_octet_packets" },
  216. { "rx_1024_to_1522_octet_packets" },
  217. { "rx_1523_to_2047_octet_packets" },
  218. { "rx_2048_to_4095_octet_packets" },
  219. { "rx_4096_to_8191_octet_packets" },
  220. { "rx_8192_to_9022_octet_packets" },
  221. { "tx_octets" },
  222. { "tx_collisions" },
  223. { "tx_xon_sent" },
  224. { "tx_xoff_sent" },
  225. { "tx_flow_control" },
  226. { "tx_mac_errors" },
  227. { "tx_single_collisions" },
  228. { "tx_mult_collisions" },
  229. { "tx_deferred" },
  230. { "tx_excessive_collisions" },
  231. { "tx_late_collisions" },
  232. { "tx_collide_2times" },
  233. { "tx_collide_3times" },
  234. { "tx_collide_4times" },
  235. { "tx_collide_5times" },
  236. { "tx_collide_6times" },
  237. { "tx_collide_7times" },
  238. { "tx_collide_8times" },
  239. { "tx_collide_9times" },
  240. { "tx_collide_10times" },
  241. { "tx_collide_11times" },
  242. { "tx_collide_12times" },
  243. { "tx_collide_13times" },
  244. { "tx_collide_14times" },
  245. { "tx_collide_15times" },
  246. { "tx_ucast_packets" },
  247. { "tx_mcast_packets" },
  248. { "tx_bcast_packets" },
  249. { "tx_carrier_sense_errors" },
  250. { "tx_discards" },
  251. { "tx_errors" },
  252. { "dma_writeq_full" },
  253. { "dma_write_prioq_full" },
  254. { "rxbds_empty" },
  255. { "rx_discards" },
  256. { "rx_errors" },
  257. { "rx_threshold_hit" },
  258. { "dma_readq_full" },
  259. { "dma_read_prioq_full" },
  260. { "tx_comp_queue_full" },
  261. { "ring_set_send_prod_index" },
  262. { "ring_status_update" },
  263. { "nic_irqs" },
  264. { "nic_avoided_irqs" },
  265. { "nic_tx_threshold_hit" }
  266. };
  267. static const struct {
  268. const char string[ETH_GSTRING_LEN];
  269. } ethtool_test_keys[TG3_NUM_TEST] = {
  270. { "nvram test (online) " },
  271. { "link test (online) " },
  272. { "register test (offline)" },
  273. { "memory test (offline)" },
  274. { "loopback test (offline)" },
  275. { "interrupt test (offline)" },
  276. };
  277. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  278. {
  279. writel(val, tp->regs + off);
  280. }
  281. static u32 tg3_read32(struct tg3 *tp, u32 off)
  282. {
  283. return (readl(tp->regs + off));
  284. }
  285. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  286. {
  287. writel(val, tp->aperegs + off);
  288. }
  289. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  290. {
  291. return (readl(tp->aperegs + off));
  292. }
  293. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  294. {
  295. unsigned long flags;
  296. spin_lock_irqsave(&tp->indirect_lock, flags);
  297. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  298. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  299. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  300. }
  301. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  302. {
  303. writel(val, tp->regs + off);
  304. readl(tp->regs + off);
  305. }
  306. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  307. {
  308. unsigned long flags;
  309. u32 val;
  310. spin_lock_irqsave(&tp->indirect_lock, flags);
  311. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  312. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  313. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  314. return val;
  315. }
  316. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  317. {
  318. unsigned long flags;
  319. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  320. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  321. TG3_64BIT_REG_LOW, val);
  322. return;
  323. }
  324. if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
  325. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  326. TG3_64BIT_REG_LOW, val);
  327. return;
  328. }
  329. spin_lock_irqsave(&tp->indirect_lock, flags);
  330. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  331. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  332. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  333. /* In indirect mode when disabling interrupts, we also need
  334. * to clear the interrupt bit in the GRC local ctrl register.
  335. */
  336. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  337. (val == 0x1)) {
  338. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  339. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  340. }
  341. }
  342. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  343. {
  344. unsigned long flags;
  345. u32 val;
  346. spin_lock_irqsave(&tp->indirect_lock, flags);
  347. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  348. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  349. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  350. return val;
  351. }
  352. /* usec_wait specifies the wait time in usec when writing to certain registers
  353. * where it is unsafe to read back the register without some delay.
  354. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  355. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  356. */
  357. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  358. {
  359. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  360. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  361. /* Non-posted methods */
  362. tp->write32(tp, off, val);
  363. else {
  364. /* Posted method */
  365. tg3_write32(tp, off, val);
  366. if (usec_wait)
  367. udelay(usec_wait);
  368. tp->read32(tp, off);
  369. }
  370. /* Wait again after the read for the posted method to guarantee that
  371. * the wait time is met.
  372. */
  373. if (usec_wait)
  374. udelay(usec_wait);
  375. }
  376. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  377. {
  378. tp->write32_mbox(tp, off, val);
  379. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  380. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  381. tp->read32_mbox(tp, off);
  382. }
  383. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  384. {
  385. void __iomem *mbox = tp->regs + off;
  386. writel(val, mbox);
  387. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  388. writel(val, mbox);
  389. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  390. readl(mbox);
  391. }
  392. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  393. {
  394. return (readl(tp->regs + off + GRCMBOX_BASE));
  395. }
  396. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  397. {
  398. writel(val, tp->regs + off + GRCMBOX_BASE);
  399. }
  400. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  401. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  402. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  403. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  404. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  405. #define tw32(reg,val) tp->write32(tp, reg, val)
  406. #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
  407. #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
  408. #define tr32(reg) tp->read32(tp, reg)
  409. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  410. {
  411. unsigned long flags;
  412. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  413. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  414. return;
  415. spin_lock_irqsave(&tp->indirect_lock, flags);
  416. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  417. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  418. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  419. /* Always leave this as zero. */
  420. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  421. } else {
  422. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  423. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  424. /* Always leave this as zero. */
  425. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  426. }
  427. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  428. }
  429. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  430. {
  431. unsigned long flags;
  432. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  433. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  434. *val = 0;
  435. return;
  436. }
  437. spin_lock_irqsave(&tp->indirect_lock, flags);
  438. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  439. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  440. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  441. /* Always leave this as zero. */
  442. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  443. } else {
  444. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  445. *val = tr32(TG3PCI_MEM_WIN_DATA);
  446. /* Always leave this as zero. */
  447. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  448. }
  449. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  450. }
  451. static void tg3_ape_lock_init(struct tg3 *tp)
  452. {
  453. int i;
  454. /* Make sure the driver hasn't any stale locks. */
  455. for (i = 0; i < 8; i++)
  456. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
  457. APE_LOCK_GRANT_DRIVER);
  458. }
  459. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  460. {
  461. int i, off;
  462. int ret = 0;
  463. u32 status;
  464. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  465. return 0;
  466. switch (locknum) {
  467. case TG3_APE_LOCK_MEM:
  468. break;
  469. default:
  470. return -EINVAL;
  471. }
  472. off = 4 * locknum;
  473. tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
  474. /* Wait for up to 1 millisecond to acquire lock. */
  475. for (i = 0; i < 100; i++) {
  476. status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
  477. if (status == APE_LOCK_GRANT_DRIVER)
  478. break;
  479. udelay(10);
  480. }
  481. if (status != APE_LOCK_GRANT_DRIVER) {
  482. /* Revoke the lock request. */
  483. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
  484. APE_LOCK_GRANT_DRIVER);
  485. ret = -EBUSY;
  486. }
  487. return ret;
  488. }
  489. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  490. {
  491. int off;
  492. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  493. return;
  494. switch (locknum) {
  495. case TG3_APE_LOCK_MEM:
  496. break;
  497. default:
  498. return;
  499. }
  500. off = 4 * locknum;
  501. tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
  502. }
  503. static void tg3_disable_ints(struct tg3 *tp)
  504. {
  505. tw32(TG3PCI_MISC_HOST_CTRL,
  506. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  507. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  508. }
  509. static inline void tg3_cond_int(struct tg3 *tp)
  510. {
  511. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  512. (tp->hw_status->status & SD_STATUS_UPDATED))
  513. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  514. else
  515. tw32(HOSTCC_MODE, tp->coalesce_mode |
  516. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  517. }
  518. static void tg3_enable_ints(struct tg3 *tp)
  519. {
  520. tp->irq_sync = 0;
  521. wmb();
  522. tw32(TG3PCI_MISC_HOST_CTRL,
  523. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  524. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  525. (tp->last_tag << 24));
  526. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  527. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  528. (tp->last_tag << 24));
  529. tg3_cond_int(tp);
  530. }
  531. static inline unsigned int tg3_has_work(struct tg3 *tp)
  532. {
  533. struct tg3_hw_status *sblk = tp->hw_status;
  534. unsigned int work_exists = 0;
  535. /* check for phy events */
  536. if (!(tp->tg3_flags &
  537. (TG3_FLAG_USE_LINKCHG_REG |
  538. TG3_FLAG_POLL_SERDES))) {
  539. if (sblk->status & SD_STATUS_LINK_CHG)
  540. work_exists = 1;
  541. }
  542. /* check for RX/TX work to do */
  543. if (sblk->idx[0].tx_consumer != tp->tx_cons ||
  544. sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  545. work_exists = 1;
  546. return work_exists;
  547. }
  548. /* tg3_restart_ints
  549. * similar to tg3_enable_ints, but it accurately determines whether there
  550. * is new work pending and can return without flushing the PIO write
  551. * which reenables interrupts
  552. */
  553. static void tg3_restart_ints(struct tg3 *tp)
  554. {
  555. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  556. tp->last_tag << 24);
  557. mmiowb();
  558. /* When doing tagged status, this work check is unnecessary.
  559. * The last_tag we write above tells the chip which piece of
  560. * work we've completed.
  561. */
  562. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  563. tg3_has_work(tp))
  564. tw32(HOSTCC_MODE, tp->coalesce_mode |
  565. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  566. }
  567. static inline void tg3_netif_stop(struct tg3 *tp)
  568. {
  569. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  570. napi_disable(&tp->napi);
  571. netif_tx_disable(tp->dev);
  572. }
  573. static inline void tg3_netif_start(struct tg3 *tp)
  574. {
  575. netif_wake_queue(tp->dev);
  576. /* NOTE: unconditional netif_wake_queue is only appropriate
  577. * so long as all callers are assured to have free tx slots
  578. * (such as after tg3_init_hw)
  579. */
  580. napi_enable(&tp->napi);
  581. tp->hw_status->status |= SD_STATUS_UPDATED;
  582. tg3_enable_ints(tp);
  583. }
  584. static void tg3_switch_clocks(struct tg3 *tp)
  585. {
  586. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  587. u32 orig_clock_ctrl;
  588. if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  589. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  590. return;
  591. orig_clock_ctrl = clock_ctrl;
  592. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  593. CLOCK_CTRL_CLKRUN_OENABLE |
  594. 0x1f);
  595. tp->pci_clock_ctrl = clock_ctrl;
  596. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  597. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  598. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  599. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  600. }
  601. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  602. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  603. clock_ctrl |
  604. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  605. 40);
  606. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  607. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  608. 40);
  609. }
  610. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  611. }
  612. #define PHY_BUSY_LOOPS 5000
  613. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  614. {
  615. u32 frame_val;
  616. unsigned int loops;
  617. int ret;
  618. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  619. tw32_f(MAC_MI_MODE,
  620. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  621. udelay(80);
  622. }
  623. *val = 0x0;
  624. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  625. MI_COM_PHY_ADDR_MASK);
  626. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  627. MI_COM_REG_ADDR_MASK);
  628. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  629. tw32_f(MAC_MI_COM, frame_val);
  630. loops = PHY_BUSY_LOOPS;
  631. while (loops != 0) {
  632. udelay(10);
  633. frame_val = tr32(MAC_MI_COM);
  634. if ((frame_val & MI_COM_BUSY) == 0) {
  635. udelay(5);
  636. frame_val = tr32(MAC_MI_COM);
  637. break;
  638. }
  639. loops -= 1;
  640. }
  641. ret = -EBUSY;
  642. if (loops != 0) {
  643. *val = frame_val & MI_COM_DATA_MASK;
  644. ret = 0;
  645. }
  646. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  647. tw32_f(MAC_MI_MODE, tp->mi_mode);
  648. udelay(80);
  649. }
  650. return ret;
  651. }
  652. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  653. {
  654. u32 frame_val;
  655. unsigned int loops;
  656. int ret;
  657. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  658. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  659. return 0;
  660. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  661. tw32_f(MAC_MI_MODE,
  662. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  663. udelay(80);
  664. }
  665. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  666. MI_COM_PHY_ADDR_MASK);
  667. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  668. MI_COM_REG_ADDR_MASK);
  669. frame_val |= (val & MI_COM_DATA_MASK);
  670. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  671. tw32_f(MAC_MI_COM, frame_val);
  672. loops = PHY_BUSY_LOOPS;
  673. while (loops != 0) {
  674. udelay(10);
  675. frame_val = tr32(MAC_MI_COM);
  676. if ((frame_val & MI_COM_BUSY) == 0) {
  677. udelay(5);
  678. frame_val = tr32(MAC_MI_COM);
  679. break;
  680. }
  681. loops -= 1;
  682. }
  683. ret = -EBUSY;
  684. if (loops != 0)
  685. ret = 0;
  686. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  687. tw32_f(MAC_MI_MODE, tp->mi_mode);
  688. udelay(80);
  689. }
  690. return ret;
  691. }
  692. static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  693. {
  694. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  695. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  696. }
  697. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  698. {
  699. u32 phy;
  700. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  701. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  702. return;
  703. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  704. u32 ephy;
  705. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
  706. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  707. ephy | MII_TG3_EPHY_SHADOW_EN);
  708. if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
  709. if (enable)
  710. phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
  711. else
  712. phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
  713. tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
  714. }
  715. tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
  716. }
  717. } else {
  718. phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
  719. MII_TG3_AUXCTL_SHDWSEL_MISC;
  720. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
  721. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
  722. if (enable)
  723. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  724. else
  725. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  726. phy |= MII_TG3_AUXCTL_MISC_WREN;
  727. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  728. }
  729. }
  730. }
  731. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  732. {
  733. u32 val;
  734. if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
  735. return;
  736. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  737. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  738. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  739. (val | (1 << 15) | (1 << 4)));
  740. }
  741. static int tg3_bmcr_reset(struct tg3 *tp)
  742. {
  743. u32 phy_control;
  744. int limit, err;
  745. /* OK, reset it, and poll the BMCR_RESET bit until it
  746. * clears or we time out.
  747. */
  748. phy_control = BMCR_RESET;
  749. err = tg3_writephy(tp, MII_BMCR, phy_control);
  750. if (err != 0)
  751. return -EBUSY;
  752. limit = 5000;
  753. while (limit--) {
  754. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  755. if (err != 0)
  756. return -EBUSY;
  757. if ((phy_control & BMCR_RESET) == 0) {
  758. udelay(40);
  759. break;
  760. }
  761. udelay(10);
  762. }
  763. if (limit <= 0)
  764. return -EBUSY;
  765. return 0;
  766. }
  767. static void tg3_phy_apply_otp(struct tg3 *tp)
  768. {
  769. u32 otp, phy;
  770. if (!tp->phy_otp)
  771. return;
  772. otp = tp->phy_otp;
  773. /* Enable SM_DSP clock and tx 6dB coding. */
  774. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  775. MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
  776. MII_TG3_AUXCTL_ACTL_TX_6DB;
  777. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  778. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  779. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  780. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  781. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  782. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  783. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  784. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  785. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  786. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  787. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  788. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  789. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  790. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  791. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  792. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  793. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  794. /* Turn off SM_DSP clock. */
  795. phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
  796. MII_TG3_AUXCTL_ACTL_TX_6DB;
  797. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  798. }
  799. static int tg3_wait_macro_done(struct tg3 *tp)
  800. {
  801. int limit = 100;
  802. while (limit--) {
  803. u32 tmp32;
  804. if (!tg3_readphy(tp, 0x16, &tmp32)) {
  805. if ((tmp32 & 0x1000) == 0)
  806. break;
  807. }
  808. }
  809. if (limit <= 0)
  810. return -EBUSY;
  811. return 0;
  812. }
  813. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  814. {
  815. static const u32 test_pat[4][6] = {
  816. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  817. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  818. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  819. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  820. };
  821. int chan;
  822. for (chan = 0; chan < 4; chan++) {
  823. int i;
  824. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  825. (chan * 0x2000) | 0x0200);
  826. tg3_writephy(tp, 0x16, 0x0002);
  827. for (i = 0; i < 6; i++)
  828. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  829. test_pat[chan][i]);
  830. tg3_writephy(tp, 0x16, 0x0202);
  831. if (tg3_wait_macro_done(tp)) {
  832. *resetp = 1;
  833. return -EBUSY;
  834. }
  835. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  836. (chan * 0x2000) | 0x0200);
  837. tg3_writephy(tp, 0x16, 0x0082);
  838. if (tg3_wait_macro_done(tp)) {
  839. *resetp = 1;
  840. return -EBUSY;
  841. }
  842. tg3_writephy(tp, 0x16, 0x0802);
  843. if (tg3_wait_macro_done(tp)) {
  844. *resetp = 1;
  845. return -EBUSY;
  846. }
  847. for (i = 0; i < 6; i += 2) {
  848. u32 low, high;
  849. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  850. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  851. tg3_wait_macro_done(tp)) {
  852. *resetp = 1;
  853. return -EBUSY;
  854. }
  855. low &= 0x7fff;
  856. high &= 0x000f;
  857. if (low != test_pat[chan][i] ||
  858. high != test_pat[chan][i+1]) {
  859. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  860. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  861. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  862. return -EBUSY;
  863. }
  864. }
  865. }
  866. return 0;
  867. }
  868. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  869. {
  870. int chan;
  871. for (chan = 0; chan < 4; chan++) {
  872. int i;
  873. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  874. (chan * 0x2000) | 0x0200);
  875. tg3_writephy(tp, 0x16, 0x0002);
  876. for (i = 0; i < 6; i++)
  877. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  878. tg3_writephy(tp, 0x16, 0x0202);
  879. if (tg3_wait_macro_done(tp))
  880. return -EBUSY;
  881. }
  882. return 0;
  883. }
  884. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  885. {
  886. u32 reg32, phy9_orig;
  887. int retries, do_phy_reset, err;
  888. retries = 10;
  889. do_phy_reset = 1;
  890. do {
  891. if (do_phy_reset) {
  892. err = tg3_bmcr_reset(tp);
  893. if (err)
  894. return err;
  895. do_phy_reset = 0;
  896. }
  897. /* Disable transmitter and interrupt. */
  898. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  899. continue;
  900. reg32 |= 0x3000;
  901. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  902. /* Set full-duplex, 1000 mbps. */
  903. tg3_writephy(tp, MII_BMCR,
  904. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  905. /* Set to master mode. */
  906. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  907. continue;
  908. tg3_writephy(tp, MII_TG3_CTRL,
  909. (MII_TG3_CTRL_AS_MASTER |
  910. MII_TG3_CTRL_ENABLE_AS_MASTER));
  911. /* Enable SM_DSP_CLOCK and 6dB. */
  912. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  913. /* Block the PHY control access. */
  914. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  915. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
  916. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  917. if (!err)
  918. break;
  919. } while (--retries);
  920. err = tg3_phy_reset_chanpat(tp);
  921. if (err)
  922. return err;
  923. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  924. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
  925. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  926. tg3_writephy(tp, 0x16, 0x0000);
  927. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  928. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  929. /* Set Extended packet length bit for jumbo frames */
  930. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  931. }
  932. else {
  933. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  934. }
  935. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  936. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  937. reg32 &= ~0x3000;
  938. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  939. } else if (!err)
  940. err = -EBUSY;
  941. return err;
  942. }
  943. static void tg3_link_report(struct tg3 *);
  944. /* This will reset the tigon3 PHY if there is no valid
  945. * link unless the FORCE argument is non-zero.
  946. */
  947. static int tg3_phy_reset(struct tg3 *tp)
  948. {
  949. u32 cpmuctrl;
  950. u32 phy_status;
  951. int err;
  952. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  953. u32 val;
  954. val = tr32(GRC_MISC_CFG);
  955. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  956. udelay(40);
  957. }
  958. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  959. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  960. if (err != 0)
  961. return -EBUSY;
  962. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  963. netif_carrier_off(tp->dev);
  964. tg3_link_report(tp);
  965. }
  966. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  967. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  968. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  969. err = tg3_phy_reset_5703_4_5(tp);
  970. if (err)
  971. return err;
  972. goto out;
  973. }
  974. cpmuctrl = 0;
  975. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  976. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  977. cpmuctrl = tr32(TG3_CPMU_CTRL);
  978. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  979. tw32(TG3_CPMU_CTRL,
  980. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  981. }
  982. err = tg3_bmcr_reset(tp);
  983. if (err)
  984. return err;
  985. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  986. u32 phy;
  987. phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  988. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
  989. tw32(TG3_CPMU_CTRL, cpmuctrl);
  990. }
  991. if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
  992. u32 val;
  993. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  994. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  995. CPMU_LSPD_1000MB_MACCLK_12_5) {
  996. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  997. udelay(40);
  998. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  999. }
  1000. /* Disable GPHY autopowerdown. */
  1001. tg3_writephy(tp, MII_TG3_MISC_SHDW,
  1002. MII_TG3_MISC_SHDW_WREN |
  1003. MII_TG3_MISC_SHDW_APD_SEL |
  1004. MII_TG3_MISC_SHDW_APD_WKTM_84MS);
  1005. }
  1006. tg3_phy_apply_otp(tp);
  1007. out:
  1008. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
  1009. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1010. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1011. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  1012. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1013. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
  1014. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1015. }
  1016. if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
  1017. tg3_writephy(tp, 0x1c, 0x8d68);
  1018. tg3_writephy(tp, 0x1c, 0x8d68);
  1019. }
  1020. if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
  1021. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1022. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1023. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
  1024. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1025. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
  1026. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
  1027. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
  1028. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1029. }
  1030. else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
  1031. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  1032. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  1033. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
  1034. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  1035. tg3_writephy(tp, MII_TG3_TEST1,
  1036. MII_TG3_TEST1_TRIM_EN | 0x4);
  1037. } else
  1038. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  1039. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  1040. }
  1041. /* Set Extended packet length bit (bit 14) on all chips that */
  1042. /* support jumbo frames */
  1043. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1044. /* Cannot do read-modify-write on 5401 */
  1045. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1046. } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  1047. u32 phy_reg;
  1048. /* Set bit 14 with read-modify-write to preserve other bits */
  1049. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  1050. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  1051. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  1052. }
  1053. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  1054. * jumbo frames transmission.
  1055. */
  1056. if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  1057. u32 phy_reg;
  1058. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  1059. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1060. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  1061. }
  1062. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1063. /* adjust output voltage */
  1064. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
  1065. }
  1066. tg3_phy_toggle_automdix(tp, 1);
  1067. tg3_phy_set_wirespeed(tp);
  1068. return 0;
  1069. }
  1070. static void tg3_frob_aux_power(struct tg3 *tp)
  1071. {
  1072. struct tg3 *tp_peer = tp;
  1073. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
  1074. return;
  1075. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  1076. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  1077. struct net_device *dev_peer;
  1078. dev_peer = pci_get_drvdata(tp->pdev_peer);
  1079. /* remove_one() may have been run on the peer. */
  1080. if (!dev_peer)
  1081. tp_peer = tp;
  1082. else
  1083. tp_peer = netdev_priv(dev_peer);
  1084. }
  1085. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1086. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  1087. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  1088. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  1089. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1090. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1091. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1092. (GRC_LCLCTRL_GPIO_OE0 |
  1093. GRC_LCLCTRL_GPIO_OE1 |
  1094. GRC_LCLCTRL_GPIO_OE2 |
  1095. GRC_LCLCTRL_GPIO_OUTPUT0 |
  1096. GRC_LCLCTRL_GPIO_OUTPUT1),
  1097. 100);
  1098. } else {
  1099. u32 no_gpio2;
  1100. u32 grc_local_ctrl = 0;
  1101. if (tp_peer != tp &&
  1102. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1103. return;
  1104. /* Workaround to prevent overdrawing Amps. */
  1105. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1106. ASIC_REV_5714) {
  1107. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  1108. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1109. grc_local_ctrl, 100);
  1110. }
  1111. /* On 5753 and variants, GPIO2 cannot be used. */
  1112. no_gpio2 = tp->nic_sram_data_cfg &
  1113. NIC_SRAM_DATA_CFG_NO_GPIO2;
  1114. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  1115. GRC_LCLCTRL_GPIO_OE1 |
  1116. GRC_LCLCTRL_GPIO_OE2 |
  1117. GRC_LCLCTRL_GPIO_OUTPUT1 |
  1118. GRC_LCLCTRL_GPIO_OUTPUT2;
  1119. if (no_gpio2) {
  1120. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  1121. GRC_LCLCTRL_GPIO_OUTPUT2);
  1122. }
  1123. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1124. grc_local_ctrl, 100);
  1125. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  1126. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1127. grc_local_ctrl, 100);
  1128. if (!no_gpio2) {
  1129. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  1130. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1131. grc_local_ctrl, 100);
  1132. }
  1133. }
  1134. } else {
  1135. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  1136. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  1137. if (tp_peer != tp &&
  1138. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1139. return;
  1140. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1141. (GRC_LCLCTRL_GPIO_OE1 |
  1142. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1143. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1144. GRC_LCLCTRL_GPIO_OE1, 100);
  1145. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1146. (GRC_LCLCTRL_GPIO_OE1 |
  1147. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1148. }
  1149. }
  1150. }
  1151. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  1152. {
  1153. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  1154. return 1;
  1155. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
  1156. if (speed != SPEED_10)
  1157. return 1;
  1158. } else if (speed == SPEED_10)
  1159. return 1;
  1160. return 0;
  1161. }
  1162. static int tg3_setup_phy(struct tg3 *, int);
  1163. #define RESET_KIND_SHUTDOWN 0
  1164. #define RESET_KIND_INIT 1
  1165. #define RESET_KIND_SUSPEND 2
  1166. static void tg3_write_sig_post_reset(struct tg3 *, int);
  1167. static int tg3_halt_cpu(struct tg3 *, u32);
  1168. static int tg3_nvram_lock(struct tg3 *);
  1169. static void tg3_nvram_unlock(struct tg3 *);
  1170. static void tg3_power_down_phy(struct tg3 *tp)
  1171. {
  1172. u32 val;
  1173. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  1174. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1175. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1176. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1177. sg_dig_ctrl |=
  1178. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1179. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1180. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1181. }
  1182. return;
  1183. }
  1184. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1185. tg3_bmcr_reset(tp);
  1186. val = tr32(GRC_MISC_CFG);
  1187. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1188. udelay(40);
  1189. return;
  1190. } else {
  1191. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1192. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1193. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
  1194. }
  1195. /* The PHY should not be powered down on some chips because
  1196. * of bugs.
  1197. */
  1198. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1199. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1200. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1201. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1202. return;
  1203. if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
  1204. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  1205. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  1206. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  1207. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  1208. }
  1209. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1210. }
  1211. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  1212. {
  1213. u32 misc_host_ctrl;
  1214. u16 power_control, power_caps;
  1215. int pm = tp->pm_cap;
  1216. /* Make sure register accesses (indirect or otherwise)
  1217. * will function correctly.
  1218. */
  1219. pci_write_config_dword(tp->pdev,
  1220. TG3PCI_MISC_HOST_CTRL,
  1221. tp->misc_host_ctrl);
  1222. pci_read_config_word(tp->pdev,
  1223. pm + PCI_PM_CTRL,
  1224. &power_control);
  1225. power_control |= PCI_PM_CTRL_PME_STATUS;
  1226. power_control &= ~(PCI_PM_CTRL_STATE_MASK);
  1227. switch (state) {
  1228. case PCI_D0:
  1229. power_control |= 0;
  1230. pci_write_config_word(tp->pdev,
  1231. pm + PCI_PM_CTRL,
  1232. power_control);
  1233. udelay(100); /* Delay after power state change */
  1234. /* Switch out of Vaux if it is a NIC */
  1235. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  1236. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  1237. return 0;
  1238. case PCI_D1:
  1239. power_control |= 1;
  1240. break;
  1241. case PCI_D2:
  1242. power_control |= 2;
  1243. break;
  1244. case PCI_D3hot:
  1245. power_control |= 3;
  1246. break;
  1247. default:
  1248. printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
  1249. "requested.\n",
  1250. tp->dev->name, state);
  1251. return -EINVAL;
  1252. };
  1253. power_control |= PCI_PM_CTRL_PME_ENABLE;
  1254. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  1255. tw32(TG3PCI_MISC_HOST_CTRL,
  1256. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  1257. if (tp->link_config.phy_is_low_power == 0) {
  1258. tp->link_config.phy_is_low_power = 1;
  1259. tp->link_config.orig_speed = tp->link_config.speed;
  1260. tp->link_config.orig_duplex = tp->link_config.duplex;
  1261. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  1262. }
  1263. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  1264. tp->link_config.speed = SPEED_10;
  1265. tp->link_config.duplex = DUPLEX_HALF;
  1266. tp->link_config.autoneg = AUTONEG_ENABLE;
  1267. tg3_setup_phy(tp, 0);
  1268. }
  1269. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1270. u32 val;
  1271. val = tr32(GRC_VCPU_EXT_CTRL);
  1272. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  1273. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1274. int i;
  1275. u32 val;
  1276. for (i = 0; i < 200; i++) {
  1277. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  1278. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1279. break;
  1280. msleep(1);
  1281. }
  1282. }
  1283. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  1284. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  1285. WOL_DRV_STATE_SHUTDOWN |
  1286. WOL_DRV_WOL |
  1287. WOL_SET_MAGIC_PKT);
  1288. pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
  1289. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
  1290. u32 mac_mode;
  1291. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  1292. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  1293. udelay(40);
  1294. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  1295. mac_mode = MAC_MODE_PORT_MODE_GMII;
  1296. else
  1297. mac_mode = MAC_MODE_PORT_MODE_MII;
  1298. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  1299. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1300. ASIC_REV_5700) {
  1301. u32 speed = (tp->tg3_flags &
  1302. TG3_FLAG_WOL_SPEED_100MB) ?
  1303. SPEED_100 : SPEED_10;
  1304. if (tg3_5700_link_polarity(tp, speed))
  1305. mac_mode |= MAC_MODE_LINK_POLARITY;
  1306. else
  1307. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1308. }
  1309. } else {
  1310. mac_mode = MAC_MODE_PORT_MODE_TBI;
  1311. }
  1312. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  1313. tw32(MAC_LED_CTRL, tp->led_ctrl);
  1314. if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
  1315. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
  1316. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  1317. tw32_f(MAC_MODE, mac_mode);
  1318. udelay(100);
  1319. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  1320. udelay(10);
  1321. }
  1322. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  1323. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1324. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  1325. u32 base_val;
  1326. base_val = tp->pci_clock_ctrl;
  1327. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  1328. CLOCK_CTRL_TXCLK_DISABLE);
  1329. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  1330. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  1331. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1332. (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  1333. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  1334. /* do nothing */
  1335. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1336. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  1337. u32 newbits1, newbits2;
  1338. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1339. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1340. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  1341. CLOCK_CTRL_TXCLK_DISABLE |
  1342. CLOCK_CTRL_ALTCLK);
  1343. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1344. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  1345. newbits1 = CLOCK_CTRL_625_CORE;
  1346. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  1347. } else {
  1348. newbits1 = CLOCK_CTRL_ALTCLK;
  1349. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1350. }
  1351. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  1352. 40);
  1353. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  1354. 40);
  1355. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  1356. u32 newbits3;
  1357. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1358. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1359. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  1360. CLOCK_CTRL_TXCLK_DISABLE |
  1361. CLOCK_CTRL_44MHZ_CORE);
  1362. } else {
  1363. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  1364. }
  1365. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  1366. tp->pci_clock_ctrl | newbits3, 40);
  1367. }
  1368. }
  1369. if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  1370. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  1371. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  1372. tg3_power_down_phy(tp);
  1373. tg3_frob_aux_power(tp);
  1374. /* Workaround for unstable PLL clock */
  1375. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  1376. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  1377. u32 val = tr32(0x7d00);
  1378. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  1379. tw32(0x7d00, val);
  1380. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1381. int err;
  1382. err = tg3_nvram_lock(tp);
  1383. tg3_halt_cpu(tp, RX_CPU_BASE);
  1384. if (!err)
  1385. tg3_nvram_unlock(tp);
  1386. }
  1387. }
  1388. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  1389. /* Finally, set the new power state. */
  1390. pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
  1391. udelay(100); /* Delay after power state change */
  1392. return 0;
  1393. }
  1394. /* tp->lock is held. */
  1395. static void tg3_wait_for_event_ack(struct tg3 *tp)
  1396. {
  1397. int i;
  1398. /* Wait for up to 2.5 milliseconds */
  1399. for (i = 0; i < 250000; i++) {
  1400. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1401. break;
  1402. udelay(10);
  1403. }
  1404. }
  1405. /* tp->lock is held. */
  1406. static void tg3_ump_link_report(struct tg3 *tp)
  1407. {
  1408. u32 reg;
  1409. u32 val;
  1410. if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1411. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  1412. return;
  1413. tg3_wait_for_event_ack(tp);
  1414. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1415. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1416. val = 0;
  1417. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1418. val = reg << 16;
  1419. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1420. val |= (reg & 0xffff);
  1421. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
  1422. val = 0;
  1423. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1424. val = reg << 16;
  1425. if (!tg3_readphy(tp, MII_LPA, &reg))
  1426. val |= (reg & 0xffff);
  1427. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
  1428. val = 0;
  1429. if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
  1430. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1431. val = reg << 16;
  1432. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1433. val |= (reg & 0xffff);
  1434. }
  1435. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
  1436. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1437. val = reg << 16;
  1438. else
  1439. val = 0;
  1440. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
  1441. val = tr32(GRC_RX_CPU_EVENT);
  1442. val |= GRC_RX_CPU_DRIVER_EVENT;
  1443. tw32_f(GRC_RX_CPU_EVENT, val);
  1444. }
  1445. static void tg3_link_report(struct tg3 *tp)
  1446. {
  1447. if (!netif_carrier_ok(tp->dev)) {
  1448. if (netif_msg_link(tp))
  1449. printk(KERN_INFO PFX "%s: Link is down.\n",
  1450. tp->dev->name);
  1451. tg3_ump_link_report(tp);
  1452. } else if (netif_msg_link(tp)) {
  1453. printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
  1454. tp->dev->name,
  1455. (tp->link_config.active_speed == SPEED_1000 ?
  1456. 1000 :
  1457. (tp->link_config.active_speed == SPEED_100 ?
  1458. 100 : 10)),
  1459. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1460. "full" : "half"));
  1461. printk(KERN_INFO PFX
  1462. "%s: Flow control is %s for TX and %s for RX.\n",
  1463. tp->dev->name,
  1464. (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
  1465. "on" : "off",
  1466. (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
  1467. "on" : "off");
  1468. tg3_ump_link_report(tp);
  1469. }
  1470. }
  1471. static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
  1472. {
  1473. u16 miireg;
  1474. if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
  1475. miireg = ADVERTISE_PAUSE_CAP;
  1476. else if (flow_ctrl & TG3_FLOW_CTRL_TX)
  1477. miireg = ADVERTISE_PAUSE_ASYM;
  1478. else if (flow_ctrl & TG3_FLOW_CTRL_RX)
  1479. miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1480. else
  1481. miireg = 0;
  1482. return miireg;
  1483. }
  1484. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1485. {
  1486. u16 miireg;
  1487. if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
  1488. miireg = ADVERTISE_1000XPAUSE;
  1489. else if (flow_ctrl & TG3_FLOW_CTRL_TX)
  1490. miireg = ADVERTISE_1000XPSE_ASYM;
  1491. else if (flow_ctrl & TG3_FLOW_CTRL_RX)
  1492. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1493. else
  1494. miireg = 0;
  1495. return miireg;
  1496. }
  1497. static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
  1498. {
  1499. u8 cap = 0;
  1500. if (lcladv & ADVERTISE_PAUSE_CAP) {
  1501. if (lcladv & ADVERTISE_PAUSE_ASYM) {
  1502. if (rmtadv & LPA_PAUSE_CAP)
  1503. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1504. else if (rmtadv & LPA_PAUSE_ASYM)
  1505. cap = TG3_FLOW_CTRL_RX;
  1506. } else {
  1507. if (rmtadv & LPA_PAUSE_CAP)
  1508. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1509. }
  1510. } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
  1511. if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
  1512. cap = TG3_FLOW_CTRL_TX;
  1513. }
  1514. return cap;
  1515. }
  1516. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1517. {
  1518. u8 cap = 0;
  1519. if (lcladv & ADVERTISE_1000XPAUSE) {
  1520. if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1521. if (rmtadv & LPA_1000XPAUSE)
  1522. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1523. else if (rmtadv & LPA_1000XPAUSE_ASYM)
  1524. cap = TG3_FLOW_CTRL_RX;
  1525. } else {
  1526. if (rmtadv & LPA_1000XPAUSE)
  1527. cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  1528. }
  1529. } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
  1530. if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
  1531. cap = TG3_FLOW_CTRL_TX;
  1532. }
  1533. return cap;
  1534. }
  1535. static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
  1536. {
  1537. u8 new_tg3_flags = 0;
  1538. u32 old_rx_mode = tp->rx_mode;
  1539. u32 old_tx_mode = tp->tx_mode;
  1540. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  1541. (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
  1542. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  1543. new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv,
  1544. remote_adv);
  1545. else
  1546. new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv,
  1547. remote_adv);
  1548. } else {
  1549. new_tg3_flags = tp->link_config.flowctrl;
  1550. }
  1551. tp->link_config.active_flowctrl = new_tg3_flags;
  1552. if (new_tg3_flags & TG3_FLOW_CTRL_RX)
  1553. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1554. else
  1555. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1556. if (old_rx_mode != tp->rx_mode) {
  1557. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1558. }
  1559. if (new_tg3_flags & TG3_FLOW_CTRL_TX)
  1560. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1561. else
  1562. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1563. if (old_tx_mode != tp->tx_mode) {
  1564. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1565. }
  1566. }
  1567. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  1568. {
  1569. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  1570. case MII_TG3_AUX_STAT_10HALF:
  1571. *speed = SPEED_10;
  1572. *duplex = DUPLEX_HALF;
  1573. break;
  1574. case MII_TG3_AUX_STAT_10FULL:
  1575. *speed = SPEED_10;
  1576. *duplex = DUPLEX_FULL;
  1577. break;
  1578. case MII_TG3_AUX_STAT_100HALF:
  1579. *speed = SPEED_100;
  1580. *duplex = DUPLEX_HALF;
  1581. break;
  1582. case MII_TG3_AUX_STAT_100FULL:
  1583. *speed = SPEED_100;
  1584. *duplex = DUPLEX_FULL;
  1585. break;
  1586. case MII_TG3_AUX_STAT_1000HALF:
  1587. *speed = SPEED_1000;
  1588. *duplex = DUPLEX_HALF;
  1589. break;
  1590. case MII_TG3_AUX_STAT_1000FULL:
  1591. *speed = SPEED_1000;
  1592. *duplex = DUPLEX_FULL;
  1593. break;
  1594. default:
  1595. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1596. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  1597. SPEED_10;
  1598. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  1599. DUPLEX_HALF;
  1600. break;
  1601. }
  1602. *speed = SPEED_INVALID;
  1603. *duplex = DUPLEX_INVALID;
  1604. break;
  1605. };
  1606. }
  1607. static void tg3_phy_copper_begin(struct tg3 *tp)
  1608. {
  1609. u32 new_adv;
  1610. int i;
  1611. if (tp->link_config.phy_is_low_power) {
  1612. /* Entering low power mode. Disable gigabit and
  1613. * 100baseT advertisements.
  1614. */
  1615. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1616. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1617. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1618. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  1619. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  1620. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1621. } else if (tp->link_config.speed == SPEED_INVALID) {
  1622. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  1623. tp->link_config.advertising &=
  1624. ~(ADVERTISED_1000baseT_Half |
  1625. ADVERTISED_1000baseT_Full);
  1626. new_adv = ADVERTISE_CSMA;
  1627. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  1628. new_adv |= ADVERTISE_10HALF;
  1629. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  1630. new_adv |= ADVERTISE_10FULL;
  1631. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  1632. new_adv |= ADVERTISE_100HALF;
  1633. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  1634. new_adv |= ADVERTISE_100FULL;
  1635. new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  1636. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1637. if (tp->link_config.advertising &
  1638. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  1639. new_adv = 0;
  1640. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  1641. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  1642. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  1643. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  1644. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  1645. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1646. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  1647. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1648. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1649. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1650. } else {
  1651. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1652. }
  1653. } else {
  1654. new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  1655. new_adv |= ADVERTISE_CSMA;
  1656. /* Asking for a specific link mode. */
  1657. if (tp->link_config.speed == SPEED_1000) {
  1658. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1659. if (tp->link_config.duplex == DUPLEX_FULL)
  1660. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  1661. else
  1662. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  1663. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1664. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  1665. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1666. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1667. } else {
  1668. if (tp->link_config.speed == SPEED_100) {
  1669. if (tp->link_config.duplex == DUPLEX_FULL)
  1670. new_adv |= ADVERTISE_100FULL;
  1671. else
  1672. new_adv |= ADVERTISE_100HALF;
  1673. } else {
  1674. if (tp->link_config.duplex == DUPLEX_FULL)
  1675. new_adv |= ADVERTISE_10FULL;
  1676. else
  1677. new_adv |= ADVERTISE_10HALF;
  1678. }
  1679. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1680. new_adv = 0;
  1681. }
  1682. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1683. }
  1684. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  1685. tp->link_config.speed != SPEED_INVALID) {
  1686. u32 bmcr, orig_bmcr;
  1687. tp->link_config.active_speed = tp->link_config.speed;
  1688. tp->link_config.active_duplex = tp->link_config.duplex;
  1689. bmcr = 0;
  1690. switch (tp->link_config.speed) {
  1691. default:
  1692. case SPEED_10:
  1693. break;
  1694. case SPEED_100:
  1695. bmcr |= BMCR_SPEED100;
  1696. break;
  1697. case SPEED_1000:
  1698. bmcr |= TG3_BMCR_SPEED1000;
  1699. break;
  1700. };
  1701. if (tp->link_config.duplex == DUPLEX_FULL)
  1702. bmcr |= BMCR_FULLDPLX;
  1703. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  1704. (bmcr != orig_bmcr)) {
  1705. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  1706. for (i = 0; i < 1500; i++) {
  1707. u32 tmp;
  1708. udelay(10);
  1709. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  1710. tg3_readphy(tp, MII_BMSR, &tmp))
  1711. continue;
  1712. if (!(tmp & BMSR_LSTATUS)) {
  1713. udelay(40);
  1714. break;
  1715. }
  1716. }
  1717. tg3_writephy(tp, MII_BMCR, bmcr);
  1718. udelay(40);
  1719. }
  1720. } else {
  1721. tg3_writephy(tp, MII_BMCR,
  1722. BMCR_ANENABLE | BMCR_ANRESTART);
  1723. }
  1724. }
  1725. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  1726. {
  1727. int err;
  1728. /* Turn off tap power management. */
  1729. /* Set Extended packet length bit */
  1730. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1731. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
  1732. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
  1733. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
  1734. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
  1735. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1736. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
  1737. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1738. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
  1739. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1740. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
  1741. udelay(40);
  1742. return err;
  1743. }
  1744. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  1745. {
  1746. u32 adv_reg, all_mask = 0;
  1747. if (mask & ADVERTISED_10baseT_Half)
  1748. all_mask |= ADVERTISE_10HALF;
  1749. if (mask & ADVERTISED_10baseT_Full)
  1750. all_mask |= ADVERTISE_10FULL;
  1751. if (mask & ADVERTISED_100baseT_Half)
  1752. all_mask |= ADVERTISE_100HALF;
  1753. if (mask & ADVERTISED_100baseT_Full)
  1754. all_mask |= ADVERTISE_100FULL;
  1755. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  1756. return 0;
  1757. if ((adv_reg & all_mask) != all_mask)
  1758. return 0;
  1759. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  1760. u32 tg3_ctrl;
  1761. all_mask = 0;
  1762. if (mask & ADVERTISED_1000baseT_Half)
  1763. all_mask |= ADVERTISE_1000HALF;
  1764. if (mask & ADVERTISED_1000baseT_Full)
  1765. all_mask |= ADVERTISE_1000FULL;
  1766. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  1767. return 0;
  1768. if ((tg3_ctrl & all_mask) != all_mask)
  1769. return 0;
  1770. }
  1771. return 1;
  1772. }
  1773. static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
  1774. {
  1775. u32 curadv, reqadv;
  1776. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  1777. return 1;
  1778. curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  1779. reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
  1780. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  1781. if (curadv != reqadv)
  1782. return 0;
  1783. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
  1784. tg3_readphy(tp, MII_LPA, rmtadv);
  1785. } else {
  1786. /* Reprogram the advertisement register, even if it
  1787. * does not affect the current link. If the link
  1788. * gets renegotiated in the future, we can save an
  1789. * additional renegotiation cycle by advertising
  1790. * it correctly in the first place.
  1791. */
  1792. if (curadv != reqadv) {
  1793. *lcladv &= ~(ADVERTISE_PAUSE_CAP |
  1794. ADVERTISE_PAUSE_ASYM);
  1795. tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
  1796. }
  1797. }
  1798. return 1;
  1799. }
  1800. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  1801. {
  1802. int current_link_up;
  1803. u32 bmsr, dummy;
  1804. u32 lcl_adv, rmt_adv;
  1805. u16 current_speed;
  1806. u8 current_duplex;
  1807. int i, err;
  1808. tw32(MAC_EVENT, 0);
  1809. tw32_f(MAC_STATUS,
  1810. (MAC_STATUS_SYNC_CHANGED |
  1811. MAC_STATUS_CFG_CHANGED |
  1812. MAC_STATUS_MI_COMPLETION |
  1813. MAC_STATUS_LNKSTATE_CHANGED));
  1814. udelay(40);
  1815. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  1816. tw32_f(MAC_MI_MODE,
  1817. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  1818. udelay(80);
  1819. }
  1820. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  1821. /* Some third-party PHYs need to be reset on link going
  1822. * down.
  1823. */
  1824. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1825. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1826. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  1827. netif_carrier_ok(tp->dev)) {
  1828. tg3_readphy(tp, MII_BMSR, &bmsr);
  1829. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1830. !(bmsr & BMSR_LSTATUS))
  1831. force_reset = 1;
  1832. }
  1833. if (force_reset)
  1834. tg3_phy_reset(tp);
  1835. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1836. tg3_readphy(tp, MII_BMSR, &bmsr);
  1837. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  1838. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  1839. bmsr = 0;
  1840. if (!(bmsr & BMSR_LSTATUS)) {
  1841. err = tg3_init_5401phy_dsp(tp);
  1842. if (err)
  1843. return err;
  1844. tg3_readphy(tp, MII_BMSR, &bmsr);
  1845. for (i = 0; i < 1000; i++) {
  1846. udelay(10);
  1847. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1848. (bmsr & BMSR_LSTATUS)) {
  1849. udelay(40);
  1850. break;
  1851. }
  1852. }
  1853. if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
  1854. !(bmsr & BMSR_LSTATUS) &&
  1855. tp->link_config.active_speed == SPEED_1000) {
  1856. err = tg3_phy_reset(tp);
  1857. if (!err)
  1858. err = tg3_init_5401phy_dsp(tp);
  1859. if (err)
  1860. return err;
  1861. }
  1862. }
  1863. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1864. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  1865. /* 5701 {A0,B0} CRC bug workaround */
  1866. tg3_writephy(tp, 0x15, 0x0a75);
  1867. tg3_writephy(tp, 0x1c, 0x8c68);
  1868. tg3_writephy(tp, 0x1c, 0x8d68);
  1869. tg3_writephy(tp, 0x1c, 0x8c68);
  1870. }
  1871. /* Clear pending interrupts... */
  1872. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1873. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1874. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
  1875. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  1876. else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  1877. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  1878. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1879. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1880. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  1881. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1882. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  1883. else
  1884. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  1885. }
  1886. current_link_up = 0;
  1887. current_speed = SPEED_INVALID;
  1888. current_duplex = DUPLEX_INVALID;
  1889. if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
  1890. u32 val;
  1891. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  1892. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  1893. if (!(val & (1 << 10))) {
  1894. val |= (1 << 10);
  1895. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  1896. goto relink;
  1897. }
  1898. }
  1899. bmsr = 0;
  1900. for (i = 0; i < 100; i++) {
  1901. tg3_readphy(tp, MII_BMSR, &bmsr);
  1902. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1903. (bmsr & BMSR_LSTATUS))
  1904. break;
  1905. udelay(40);
  1906. }
  1907. if (bmsr & BMSR_LSTATUS) {
  1908. u32 aux_stat, bmcr;
  1909. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  1910. for (i = 0; i < 2000; i++) {
  1911. udelay(10);
  1912. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  1913. aux_stat)
  1914. break;
  1915. }
  1916. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  1917. &current_speed,
  1918. &current_duplex);
  1919. bmcr = 0;
  1920. for (i = 0; i < 200; i++) {
  1921. tg3_readphy(tp, MII_BMCR, &bmcr);
  1922. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  1923. continue;
  1924. if (bmcr && bmcr != 0x7fff)
  1925. break;
  1926. udelay(10);
  1927. }
  1928. lcl_adv = 0;
  1929. rmt_adv = 0;
  1930. tp->link_config.active_speed = current_speed;
  1931. tp->link_config.active_duplex = current_duplex;
  1932. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  1933. if ((bmcr & BMCR_ANENABLE) &&
  1934. tg3_copper_is_advertising_all(tp,
  1935. tp->link_config.advertising)) {
  1936. if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
  1937. &rmt_adv))
  1938. current_link_up = 1;
  1939. }
  1940. } else {
  1941. if (!(bmcr & BMCR_ANENABLE) &&
  1942. tp->link_config.speed == current_speed &&
  1943. tp->link_config.duplex == current_duplex &&
  1944. tp->link_config.flowctrl ==
  1945. tp->link_config.active_flowctrl) {
  1946. current_link_up = 1;
  1947. }
  1948. }
  1949. if (current_link_up == 1 &&
  1950. tp->link_config.active_duplex == DUPLEX_FULL)
  1951. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1952. }
  1953. relink:
  1954. if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
  1955. u32 tmp;
  1956. tg3_phy_copper_begin(tp);
  1957. tg3_readphy(tp, MII_BMSR, &tmp);
  1958. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  1959. (tmp & BMSR_LSTATUS))
  1960. current_link_up = 1;
  1961. }
  1962. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  1963. if (current_link_up == 1) {
  1964. if (tp->link_config.active_speed == SPEED_100 ||
  1965. tp->link_config.active_speed == SPEED_10)
  1966. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  1967. else
  1968. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1969. } else
  1970. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1971. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  1972. if (tp->link_config.active_duplex == DUPLEX_HALF)
  1973. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  1974. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  1975. if (current_link_up == 1 &&
  1976. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  1977. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  1978. else
  1979. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1980. }
  1981. /* ??? Without this setting Netgear GA302T PHY does not
  1982. * ??? send/receive packets...
  1983. */
  1984. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  1985. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  1986. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  1987. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1988. udelay(80);
  1989. }
  1990. tw32_f(MAC_MODE, tp->mac_mode);
  1991. udelay(40);
  1992. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  1993. /* Polled via timer. */
  1994. tw32_f(MAC_EVENT, 0);
  1995. } else {
  1996. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  1997. }
  1998. udelay(40);
  1999. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  2000. current_link_up == 1 &&
  2001. tp->link_config.active_speed == SPEED_1000 &&
  2002. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  2003. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  2004. udelay(120);
  2005. tw32_f(MAC_STATUS,
  2006. (MAC_STATUS_SYNC_CHANGED |
  2007. MAC_STATUS_CFG_CHANGED));
  2008. udelay(40);
  2009. tg3_write_mem(tp,
  2010. NIC_SRAM_FIRMWARE_MBOX,
  2011. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  2012. }
  2013. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2014. if (current_link_up)
  2015. netif_carrier_on(tp->dev);
  2016. else
  2017. netif_carrier_off(tp->dev);
  2018. tg3_link_report(tp);
  2019. }
  2020. return 0;
  2021. }
  2022. struct tg3_fiber_aneginfo {
  2023. int state;
  2024. #define ANEG_STATE_UNKNOWN 0
  2025. #define ANEG_STATE_AN_ENABLE 1
  2026. #define ANEG_STATE_RESTART_INIT 2
  2027. #define ANEG_STATE_RESTART 3
  2028. #define ANEG_STATE_DISABLE_LINK_OK 4
  2029. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  2030. #define ANEG_STATE_ABILITY_DETECT 6
  2031. #define ANEG_STATE_ACK_DETECT_INIT 7
  2032. #define ANEG_STATE_ACK_DETECT 8
  2033. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  2034. #define ANEG_STATE_COMPLETE_ACK 10
  2035. #define ANEG_STATE_IDLE_DETECT_INIT 11
  2036. #define ANEG_STATE_IDLE_DETECT 12
  2037. #define ANEG_STATE_LINK_OK 13
  2038. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  2039. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  2040. u32 flags;
  2041. #define MR_AN_ENABLE 0x00000001
  2042. #define MR_RESTART_AN 0x00000002
  2043. #define MR_AN_COMPLETE 0x00000004
  2044. #define MR_PAGE_RX 0x00000008
  2045. #define MR_NP_LOADED 0x00000010
  2046. #define MR_TOGGLE_TX 0x00000020
  2047. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  2048. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  2049. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  2050. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  2051. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  2052. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  2053. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  2054. #define MR_TOGGLE_RX 0x00002000
  2055. #define MR_NP_RX 0x00004000
  2056. #define MR_LINK_OK 0x80000000
  2057. unsigned long link_time, cur_time;
  2058. u32 ability_match_cfg;
  2059. int ability_match_count;
  2060. char ability_match, idle_match, ack_match;
  2061. u32 txconfig, rxconfig;
  2062. #define ANEG_CFG_NP 0x00000080
  2063. #define ANEG_CFG_ACK 0x00000040
  2064. #define ANEG_CFG_RF2 0x00000020
  2065. #define ANEG_CFG_RF1 0x00000010
  2066. #define ANEG_CFG_PS2 0x00000001
  2067. #define ANEG_CFG_PS1 0x00008000
  2068. #define ANEG_CFG_HD 0x00004000
  2069. #define ANEG_CFG_FD 0x00002000
  2070. #define ANEG_CFG_INVAL 0x00001f06
  2071. };
  2072. #define ANEG_OK 0
  2073. #define ANEG_DONE 1
  2074. #define ANEG_TIMER_ENAB 2
  2075. #define ANEG_FAILED -1
  2076. #define ANEG_STATE_SETTLE_TIME 10000
  2077. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  2078. struct tg3_fiber_aneginfo *ap)
  2079. {
  2080. u16 flowctrl;
  2081. unsigned long delta;
  2082. u32 rx_cfg_reg;
  2083. int ret;
  2084. if (ap->state == ANEG_STATE_UNKNOWN) {
  2085. ap->rxconfig = 0;
  2086. ap->link_time = 0;
  2087. ap->cur_time = 0;
  2088. ap->ability_match_cfg = 0;
  2089. ap->ability_match_count = 0;
  2090. ap->ability_match = 0;
  2091. ap->idle_match = 0;
  2092. ap->ack_match = 0;
  2093. }
  2094. ap->cur_time++;
  2095. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  2096. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  2097. if (rx_cfg_reg != ap->ability_match_cfg) {
  2098. ap->ability_match_cfg = rx_cfg_reg;
  2099. ap->ability_match = 0;
  2100. ap->ability_match_count = 0;
  2101. } else {
  2102. if (++ap->ability_match_count > 1) {
  2103. ap->ability_match = 1;
  2104. ap->ability_match_cfg = rx_cfg_reg;
  2105. }
  2106. }
  2107. if (rx_cfg_reg & ANEG_CFG_ACK)
  2108. ap->ack_match = 1;
  2109. else
  2110. ap->ack_match = 0;
  2111. ap->idle_match = 0;
  2112. } else {
  2113. ap->idle_match = 1;
  2114. ap->ability_match_cfg = 0;
  2115. ap->ability_match_count = 0;
  2116. ap->ability_match = 0;
  2117. ap->ack_match = 0;
  2118. rx_cfg_reg = 0;
  2119. }
  2120. ap->rxconfig = rx_cfg_reg;
  2121. ret = ANEG_OK;
  2122. switch(ap->state) {
  2123. case ANEG_STATE_UNKNOWN:
  2124. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  2125. ap->state = ANEG_STATE_AN_ENABLE;
  2126. /* fallthru */
  2127. case ANEG_STATE_AN_ENABLE:
  2128. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  2129. if (ap->flags & MR_AN_ENABLE) {
  2130. ap->link_time = 0;
  2131. ap->cur_time = 0;
  2132. ap->ability_match_cfg = 0;
  2133. ap->ability_match_count = 0;
  2134. ap->ability_match = 0;
  2135. ap->idle_match = 0;
  2136. ap->ack_match = 0;
  2137. ap->state = ANEG_STATE_RESTART_INIT;
  2138. } else {
  2139. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  2140. }
  2141. break;
  2142. case ANEG_STATE_RESTART_INIT:
  2143. ap->link_time = ap->cur_time;
  2144. ap->flags &= ~(MR_NP_LOADED);
  2145. ap->txconfig = 0;
  2146. tw32(MAC_TX_AUTO_NEG, 0);
  2147. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2148. tw32_f(MAC_MODE, tp->mac_mode);
  2149. udelay(40);
  2150. ret = ANEG_TIMER_ENAB;
  2151. ap->state = ANEG_STATE_RESTART;
  2152. /* fallthru */
  2153. case ANEG_STATE_RESTART:
  2154. delta = ap->cur_time - ap->link_time;
  2155. if (delta > ANEG_STATE_SETTLE_TIME) {
  2156. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  2157. } else {
  2158. ret = ANEG_TIMER_ENAB;
  2159. }
  2160. break;
  2161. case ANEG_STATE_DISABLE_LINK_OK:
  2162. ret = ANEG_DONE;
  2163. break;
  2164. case ANEG_STATE_ABILITY_DETECT_INIT:
  2165. ap->flags &= ~(MR_TOGGLE_TX);
  2166. ap->txconfig = ANEG_CFG_FD;
  2167. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2168. if (flowctrl & ADVERTISE_1000XPAUSE)
  2169. ap->txconfig |= ANEG_CFG_PS1;
  2170. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  2171. ap->txconfig |= ANEG_CFG_PS2;
  2172. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2173. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2174. tw32_f(MAC_MODE, tp->mac_mode);
  2175. udelay(40);
  2176. ap->state = ANEG_STATE_ABILITY_DETECT;
  2177. break;
  2178. case ANEG_STATE_ABILITY_DETECT:
  2179. if (ap->ability_match != 0 && ap->rxconfig != 0) {
  2180. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  2181. }
  2182. break;
  2183. case ANEG_STATE_ACK_DETECT_INIT:
  2184. ap->txconfig |= ANEG_CFG_ACK;
  2185. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  2186. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  2187. tw32_f(MAC_MODE, tp->mac_mode);
  2188. udelay(40);
  2189. ap->state = ANEG_STATE_ACK_DETECT;
  2190. /* fallthru */
  2191. case ANEG_STATE_ACK_DETECT:
  2192. if (ap->ack_match != 0) {
  2193. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  2194. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  2195. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  2196. } else {
  2197. ap->state = ANEG_STATE_AN_ENABLE;
  2198. }
  2199. } else if (ap->ability_match != 0 &&
  2200. ap->rxconfig == 0) {
  2201. ap->state = ANEG_STATE_AN_ENABLE;
  2202. }
  2203. break;
  2204. case ANEG_STATE_COMPLETE_ACK_INIT:
  2205. if (ap->rxconfig & ANEG_CFG_INVAL) {
  2206. ret = ANEG_FAILED;
  2207. break;
  2208. }
  2209. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  2210. MR_LP_ADV_HALF_DUPLEX |
  2211. MR_LP_ADV_SYM_PAUSE |
  2212. MR_LP_ADV_ASYM_PAUSE |
  2213. MR_LP_ADV_REMOTE_FAULT1 |
  2214. MR_LP_ADV_REMOTE_FAULT2 |
  2215. MR_LP_ADV_NEXT_PAGE |
  2216. MR_TOGGLE_RX |
  2217. MR_NP_RX);
  2218. if (ap->rxconfig & ANEG_CFG_FD)
  2219. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  2220. if (ap->rxconfig & ANEG_CFG_HD)
  2221. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  2222. if (ap->rxconfig & ANEG_CFG_PS1)
  2223. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  2224. if (ap->rxconfig & ANEG_CFG_PS2)
  2225. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  2226. if (ap->rxconfig & ANEG_CFG_RF1)
  2227. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  2228. if (ap->rxconfig & ANEG_CFG_RF2)
  2229. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  2230. if (ap->rxconfig & ANEG_CFG_NP)
  2231. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  2232. ap->link_time = ap->cur_time;
  2233. ap->flags ^= (MR_TOGGLE_TX);
  2234. if (ap->rxconfig & 0x0008)
  2235. ap->flags |= MR_TOGGLE_RX;
  2236. if (ap->rxconfig & ANEG_CFG_NP)
  2237. ap->flags |= MR_NP_RX;
  2238. ap->flags |= MR_PAGE_RX;
  2239. ap->state = ANEG_STATE_COMPLETE_ACK;
  2240. ret = ANEG_TIMER_ENAB;
  2241. break;
  2242. case ANEG_STATE_COMPLETE_ACK:
  2243. if (ap->ability_match != 0 &&
  2244. ap->rxconfig == 0) {
  2245. ap->state = ANEG_STATE_AN_ENABLE;
  2246. break;
  2247. }
  2248. delta = ap->cur_time - ap->link_time;
  2249. if (delta > ANEG_STATE_SETTLE_TIME) {
  2250. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  2251. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2252. } else {
  2253. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  2254. !(ap->flags & MR_NP_RX)) {
  2255. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2256. } else {
  2257. ret = ANEG_FAILED;
  2258. }
  2259. }
  2260. }
  2261. break;
  2262. case ANEG_STATE_IDLE_DETECT_INIT:
  2263. ap->link_time = ap->cur_time;
  2264. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2265. tw32_f(MAC_MODE, tp->mac_mode);
  2266. udelay(40);
  2267. ap->state = ANEG_STATE_IDLE_DETECT;
  2268. ret = ANEG_TIMER_ENAB;
  2269. break;
  2270. case ANEG_STATE_IDLE_DETECT:
  2271. if (ap->ability_match != 0 &&
  2272. ap->rxconfig == 0) {
  2273. ap->state = ANEG_STATE_AN_ENABLE;
  2274. break;
  2275. }
  2276. delta = ap->cur_time - ap->link_time;
  2277. if (delta > ANEG_STATE_SETTLE_TIME) {
  2278. /* XXX another gem from the Broadcom driver :( */
  2279. ap->state = ANEG_STATE_LINK_OK;
  2280. }
  2281. break;
  2282. case ANEG_STATE_LINK_OK:
  2283. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  2284. ret = ANEG_DONE;
  2285. break;
  2286. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  2287. /* ??? unimplemented */
  2288. break;
  2289. case ANEG_STATE_NEXT_PAGE_WAIT:
  2290. /* ??? unimplemented */
  2291. break;
  2292. default:
  2293. ret = ANEG_FAILED;
  2294. break;
  2295. };
  2296. return ret;
  2297. }
  2298. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  2299. {
  2300. int res = 0;
  2301. struct tg3_fiber_aneginfo aninfo;
  2302. int status = ANEG_FAILED;
  2303. unsigned int tick;
  2304. u32 tmp;
  2305. tw32_f(MAC_TX_AUTO_NEG, 0);
  2306. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  2307. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  2308. udelay(40);
  2309. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  2310. udelay(40);
  2311. memset(&aninfo, 0, sizeof(aninfo));
  2312. aninfo.flags |= MR_AN_ENABLE;
  2313. aninfo.state = ANEG_STATE_UNKNOWN;
  2314. aninfo.cur_time = 0;
  2315. tick = 0;
  2316. while (++tick < 195000) {
  2317. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  2318. if (status == ANEG_DONE || status == ANEG_FAILED)
  2319. break;
  2320. udelay(1);
  2321. }
  2322. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2323. tw32_f(MAC_MODE, tp->mac_mode);
  2324. udelay(40);
  2325. *txflags = aninfo.txconfig;
  2326. *rxflags = aninfo.flags;
  2327. if (status == ANEG_DONE &&
  2328. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  2329. MR_LP_ADV_FULL_DUPLEX)))
  2330. res = 1;
  2331. return res;
  2332. }
  2333. static void tg3_init_bcm8002(struct tg3 *tp)
  2334. {
  2335. u32 mac_status = tr32(MAC_STATUS);
  2336. int i;
  2337. /* Reset when initting first time or we have a link. */
  2338. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  2339. !(mac_status & MAC_STATUS_PCS_SYNCED))
  2340. return;
  2341. /* Set PLL lock range. */
  2342. tg3_writephy(tp, 0x16, 0x8007);
  2343. /* SW reset */
  2344. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  2345. /* Wait for reset to complete. */
  2346. /* XXX schedule_timeout() ... */
  2347. for (i = 0; i < 500; i++)
  2348. udelay(10);
  2349. /* Config mode; select PMA/Ch 1 regs. */
  2350. tg3_writephy(tp, 0x10, 0x8411);
  2351. /* Enable auto-lock and comdet, select txclk for tx. */
  2352. tg3_writephy(tp, 0x11, 0x0a10);
  2353. tg3_writephy(tp, 0x18, 0x00a0);
  2354. tg3_writephy(tp, 0x16, 0x41ff);
  2355. /* Assert and deassert POR. */
  2356. tg3_writephy(tp, 0x13, 0x0400);
  2357. udelay(40);
  2358. tg3_writephy(tp, 0x13, 0x0000);
  2359. tg3_writephy(tp, 0x11, 0x0a50);
  2360. udelay(40);
  2361. tg3_writephy(tp, 0x11, 0x0a10);
  2362. /* Wait for signal to stabilize */
  2363. /* XXX schedule_timeout() ... */
  2364. for (i = 0; i < 15000; i++)
  2365. udelay(10);
  2366. /* Deselect the channel register so we can read the PHYID
  2367. * later.
  2368. */
  2369. tg3_writephy(tp, 0x10, 0x8011);
  2370. }
  2371. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  2372. {
  2373. u16 flowctrl;
  2374. u32 sg_dig_ctrl, sg_dig_status;
  2375. u32 serdes_cfg, expected_sg_dig_ctrl;
  2376. int workaround, port_a;
  2377. int current_link_up;
  2378. serdes_cfg = 0;
  2379. expected_sg_dig_ctrl = 0;
  2380. workaround = 0;
  2381. port_a = 1;
  2382. current_link_up = 0;
  2383. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  2384. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  2385. workaround = 1;
  2386. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  2387. port_a = 0;
  2388. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  2389. /* preserve bits 20-23 for voltage regulator */
  2390. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  2391. }
  2392. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2393. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  2394. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  2395. if (workaround) {
  2396. u32 val = serdes_cfg;
  2397. if (port_a)
  2398. val |= 0xc010000;
  2399. else
  2400. val |= 0x4010000;
  2401. tw32_f(MAC_SERDES_CFG, val);
  2402. }
  2403. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  2404. }
  2405. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  2406. tg3_setup_flow_control(tp, 0, 0);
  2407. current_link_up = 1;
  2408. }
  2409. goto out;
  2410. }
  2411. /* Want auto-negotiation. */
  2412. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  2413. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2414. if (flowctrl & ADVERTISE_1000XPAUSE)
  2415. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  2416. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  2417. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  2418. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  2419. if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  2420. tp->serdes_counter &&
  2421. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  2422. MAC_STATUS_RCVD_CFG)) ==
  2423. MAC_STATUS_PCS_SYNCED)) {
  2424. tp->serdes_counter--;
  2425. current_link_up = 1;
  2426. goto out;
  2427. }
  2428. restart_autoneg:
  2429. if (workaround)
  2430. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  2431. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  2432. udelay(5);
  2433. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  2434. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2435. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2436. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  2437. MAC_STATUS_SIGNAL_DET)) {
  2438. sg_dig_status = tr32(SG_DIG_STATUS);
  2439. mac_status = tr32(MAC_STATUS);
  2440. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  2441. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  2442. u32 local_adv = 0, remote_adv = 0;
  2443. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  2444. local_adv |= ADVERTISE_1000XPAUSE;
  2445. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  2446. local_adv |= ADVERTISE_1000XPSE_ASYM;
  2447. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  2448. remote_adv |= LPA_1000XPAUSE;
  2449. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  2450. remote_adv |= LPA_1000XPAUSE_ASYM;
  2451. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2452. current_link_up = 1;
  2453. tp->serdes_counter = 0;
  2454. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2455. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  2456. if (tp->serdes_counter)
  2457. tp->serdes_counter--;
  2458. else {
  2459. if (workaround) {
  2460. u32 val = serdes_cfg;
  2461. if (port_a)
  2462. val |= 0xc010000;
  2463. else
  2464. val |= 0x4010000;
  2465. tw32_f(MAC_SERDES_CFG, val);
  2466. }
  2467. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  2468. udelay(40);
  2469. /* Link parallel detection - link is up */
  2470. /* only if we have PCS_SYNC and not */
  2471. /* receiving config code words */
  2472. mac_status = tr32(MAC_STATUS);
  2473. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  2474. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  2475. tg3_setup_flow_control(tp, 0, 0);
  2476. current_link_up = 1;
  2477. tp->tg3_flags2 |=
  2478. TG3_FLG2_PARALLEL_DETECT;
  2479. tp->serdes_counter =
  2480. SERDES_PARALLEL_DET_TIMEOUT;
  2481. } else
  2482. goto restart_autoneg;
  2483. }
  2484. }
  2485. } else {
  2486. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2487. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2488. }
  2489. out:
  2490. return current_link_up;
  2491. }
  2492. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  2493. {
  2494. int current_link_up = 0;
  2495. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  2496. goto out;
  2497. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2498. u32 txflags, rxflags;
  2499. int i;
  2500. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  2501. u32 local_adv = 0, remote_adv = 0;
  2502. if (txflags & ANEG_CFG_PS1)
  2503. local_adv |= ADVERTISE_1000XPAUSE;
  2504. if (txflags & ANEG_CFG_PS2)
  2505. local_adv |= ADVERTISE_1000XPSE_ASYM;
  2506. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  2507. remote_adv |= LPA_1000XPAUSE;
  2508. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  2509. remote_adv |= LPA_1000XPAUSE_ASYM;
  2510. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2511. current_link_up = 1;
  2512. }
  2513. for (i = 0; i < 30; i++) {
  2514. udelay(20);
  2515. tw32_f(MAC_STATUS,
  2516. (MAC_STATUS_SYNC_CHANGED |
  2517. MAC_STATUS_CFG_CHANGED));
  2518. udelay(40);
  2519. if ((tr32(MAC_STATUS) &
  2520. (MAC_STATUS_SYNC_CHANGED |
  2521. MAC_STATUS_CFG_CHANGED)) == 0)
  2522. break;
  2523. }
  2524. mac_status = tr32(MAC_STATUS);
  2525. if (current_link_up == 0 &&
  2526. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  2527. !(mac_status & MAC_STATUS_RCVD_CFG))
  2528. current_link_up = 1;
  2529. } else {
  2530. tg3_setup_flow_control(tp, 0, 0);
  2531. /* Forcing 1000FD link up. */
  2532. current_link_up = 1;
  2533. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  2534. udelay(40);
  2535. tw32_f(MAC_MODE, tp->mac_mode);
  2536. udelay(40);
  2537. }
  2538. out:
  2539. return current_link_up;
  2540. }
  2541. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  2542. {
  2543. u32 orig_pause_cfg;
  2544. u16 orig_active_speed;
  2545. u8 orig_active_duplex;
  2546. u32 mac_status;
  2547. int current_link_up;
  2548. int i;
  2549. orig_pause_cfg = tp->link_config.active_flowctrl;
  2550. orig_active_speed = tp->link_config.active_speed;
  2551. orig_active_duplex = tp->link_config.active_duplex;
  2552. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  2553. netif_carrier_ok(tp->dev) &&
  2554. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  2555. mac_status = tr32(MAC_STATUS);
  2556. mac_status &= (MAC_STATUS_PCS_SYNCED |
  2557. MAC_STATUS_SIGNAL_DET |
  2558. MAC_STATUS_CFG_CHANGED |
  2559. MAC_STATUS_RCVD_CFG);
  2560. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  2561. MAC_STATUS_SIGNAL_DET)) {
  2562. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2563. MAC_STATUS_CFG_CHANGED));
  2564. return 0;
  2565. }
  2566. }
  2567. tw32_f(MAC_TX_AUTO_NEG, 0);
  2568. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  2569. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  2570. tw32_f(MAC_MODE, tp->mac_mode);
  2571. udelay(40);
  2572. if (tp->phy_id == PHY_ID_BCM8002)
  2573. tg3_init_bcm8002(tp);
  2574. /* Enable link change event even when serdes polling. */
  2575. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2576. udelay(40);
  2577. current_link_up = 0;
  2578. mac_status = tr32(MAC_STATUS);
  2579. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  2580. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  2581. else
  2582. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  2583. tp->hw_status->status =
  2584. (SD_STATUS_UPDATED |
  2585. (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
  2586. for (i = 0; i < 100; i++) {
  2587. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2588. MAC_STATUS_CFG_CHANGED));
  2589. udelay(5);
  2590. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  2591. MAC_STATUS_CFG_CHANGED |
  2592. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  2593. break;
  2594. }
  2595. mac_status = tr32(MAC_STATUS);
  2596. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  2597. current_link_up = 0;
  2598. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  2599. tp->serdes_counter == 0) {
  2600. tw32_f(MAC_MODE, (tp->mac_mode |
  2601. MAC_MODE_SEND_CONFIGS));
  2602. udelay(1);
  2603. tw32_f(MAC_MODE, tp->mac_mode);
  2604. }
  2605. }
  2606. if (current_link_up == 1) {
  2607. tp->link_config.active_speed = SPEED_1000;
  2608. tp->link_config.active_duplex = DUPLEX_FULL;
  2609. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2610. LED_CTRL_LNKLED_OVERRIDE |
  2611. LED_CTRL_1000MBPS_ON));
  2612. } else {
  2613. tp->link_config.active_speed = SPEED_INVALID;
  2614. tp->link_config.active_duplex = DUPLEX_INVALID;
  2615. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2616. LED_CTRL_LNKLED_OVERRIDE |
  2617. LED_CTRL_TRAFFIC_OVERRIDE));
  2618. }
  2619. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2620. if (current_link_up)
  2621. netif_carrier_on(tp->dev);
  2622. else
  2623. netif_carrier_off(tp->dev);
  2624. tg3_link_report(tp);
  2625. } else {
  2626. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  2627. if (orig_pause_cfg != now_pause_cfg ||
  2628. orig_active_speed != tp->link_config.active_speed ||
  2629. orig_active_duplex != tp->link_config.active_duplex)
  2630. tg3_link_report(tp);
  2631. }
  2632. return 0;
  2633. }
  2634. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  2635. {
  2636. int current_link_up, err = 0;
  2637. u32 bmsr, bmcr;
  2638. u16 current_speed;
  2639. u8 current_duplex;
  2640. u32 local_adv, remote_adv;
  2641. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2642. tw32_f(MAC_MODE, tp->mac_mode);
  2643. udelay(40);
  2644. tw32(MAC_EVENT, 0);
  2645. tw32_f(MAC_STATUS,
  2646. (MAC_STATUS_SYNC_CHANGED |
  2647. MAC_STATUS_CFG_CHANGED |
  2648. MAC_STATUS_MI_COMPLETION |
  2649. MAC_STATUS_LNKSTATE_CHANGED));
  2650. udelay(40);
  2651. if (force_reset)
  2652. tg3_phy_reset(tp);
  2653. current_link_up = 0;
  2654. current_speed = SPEED_INVALID;
  2655. current_duplex = DUPLEX_INVALID;
  2656. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2657. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2658. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  2659. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2660. bmsr |= BMSR_LSTATUS;
  2661. else
  2662. bmsr &= ~BMSR_LSTATUS;
  2663. }
  2664. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  2665. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  2666. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  2667. tp->link_config.flowctrl == tp->link_config.active_flowctrl) {
  2668. /* do nothing, just check for link up at the end */
  2669. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2670. u32 adv, new_adv;
  2671. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2672. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  2673. ADVERTISE_1000XPAUSE |
  2674. ADVERTISE_1000XPSE_ASYM |
  2675. ADVERTISE_SLCT);
  2676. new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  2677. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2678. new_adv |= ADVERTISE_1000XHALF;
  2679. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2680. new_adv |= ADVERTISE_1000XFULL;
  2681. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  2682. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2683. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  2684. tg3_writephy(tp, MII_BMCR, bmcr);
  2685. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2686. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  2687. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2688. return err;
  2689. }
  2690. } else {
  2691. u32 new_bmcr;
  2692. bmcr &= ~BMCR_SPEED1000;
  2693. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  2694. if (tp->link_config.duplex == DUPLEX_FULL)
  2695. new_bmcr |= BMCR_FULLDPLX;
  2696. if (new_bmcr != bmcr) {
  2697. /* BMCR_SPEED1000 is a reserved bit that needs
  2698. * to be set on write.
  2699. */
  2700. new_bmcr |= BMCR_SPEED1000;
  2701. /* Force a linkdown */
  2702. if (netif_carrier_ok(tp->dev)) {
  2703. u32 adv;
  2704. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2705. adv &= ~(ADVERTISE_1000XFULL |
  2706. ADVERTISE_1000XHALF |
  2707. ADVERTISE_SLCT);
  2708. tg3_writephy(tp, MII_ADVERTISE, adv);
  2709. tg3_writephy(tp, MII_BMCR, bmcr |
  2710. BMCR_ANRESTART |
  2711. BMCR_ANENABLE);
  2712. udelay(10);
  2713. netif_carrier_off(tp->dev);
  2714. }
  2715. tg3_writephy(tp, MII_BMCR, new_bmcr);
  2716. bmcr = new_bmcr;
  2717. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2718. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2719. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2720. ASIC_REV_5714) {
  2721. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2722. bmsr |= BMSR_LSTATUS;
  2723. else
  2724. bmsr &= ~BMSR_LSTATUS;
  2725. }
  2726. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2727. }
  2728. }
  2729. if (bmsr & BMSR_LSTATUS) {
  2730. current_speed = SPEED_1000;
  2731. current_link_up = 1;
  2732. if (bmcr & BMCR_FULLDPLX)
  2733. current_duplex = DUPLEX_FULL;
  2734. else
  2735. current_duplex = DUPLEX_HALF;
  2736. local_adv = 0;
  2737. remote_adv = 0;
  2738. if (bmcr & BMCR_ANENABLE) {
  2739. u32 common;
  2740. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  2741. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  2742. common = local_adv & remote_adv;
  2743. if (common & (ADVERTISE_1000XHALF |
  2744. ADVERTISE_1000XFULL)) {
  2745. if (common & ADVERTISE_1000XFULL)
  2746. current_duplex = DUPLEX_FULL;
  2747. else
  2748. current_duplex = DUPLEX_HALF;
  2749. }
  2750. else
  2751. current_link_up = 0;
  2752. }
  2753. }
  2754. if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
  2755. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2756. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2757. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2758. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2759. tw32_f(MAC_MODE, tp->mac_mode);
  2760. udelay(40);
  2761. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2762. tp->link_config.active_speed = current_speed;
  2763. tp->link_config.active_duplex = current_duplex;
  2764. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2765. if (current_link_up)
  2766. netif_carrier_on(tp->dev);
  2767. else {
  2768. netif_carrier_off(tp->dev);
  2769. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2770. }
  2771. tg3_link_report(tp);
  2772. }
  2773. return err;
  2774. }
  2775. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  2776. {
  2777. if (tp->serdes_counter) {
  2778. /* Give autoneg time to complete. */
  2779. tp->serdes_counter--;
  2780. return;
  2781. }
  2782. if (!netif_carrier_ok(tp->dev) &&
  2783. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  2784. u32 bmcr;
  2785. tg3_readphy(tp, MII_BMCR, &bmcr);
  2786. if (bmcr & BMCR_ANENABLE) {
  2787. u32 phy1, phy2;
  2788. /* Select shadow register 0x1f */
  2789. tg3_writephy(tp, 0x1c, 0x7c00);
  2790. tg3_readphy(tp, 0x1c, &phy1);
  2791. /* Select expansion interrupt status register */
  2792. tg3_writephy(tp, 0x17, 0x0f01);
  2793. tg3_readphy(tp, 0x15, &phy2);
  2794. tg3_readphy(tp, 0x15, &phy2);
  2795. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  2796. /* We have signal detect and not receiving
  2797. * config code words, link is up by parallel
  2798. * detection.
  2799. */
  2800. bmcr &= ~BMCR_ANENABLE;
  2801. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  2802. tg3_writephy(tp, MII_BMCR, bmcr);
  2803. tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
  2804. }
  2805. }
  2806. }
  2807. else if (netif_carrier_ok(tp->dev) &&
  2808. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  2809. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2810. u32 phy2;
  2811. /* Select expansion interrupt status register */
  2812. tg3_writephy(tp, 0x17, 0x0f01);
  2813. tg3_readphy(tp, 0x15, &phy2);
  2814. if (phy2 & 0x20) {
  2815. u32 bmcr;
  2816. /* Config code words received, turn on autoneg. */
  2817. tg3_readphy(tp, MII_BMCR, &bmcr);
  2818. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  2819. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2820. }
  2821. }
  2822. }
  2823. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  2824. {
  2825. int err;
  2826. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  2827. err = tg3_setup_fiber_phy(tp, force_reset);
  2828. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  2829. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  2830. } else {
  2831. err = tg3_setup_copper_phy(tp, force_reset);
  2832. }
  2833. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
  2834. tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
  2835. u32 val, scale;
  2836. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  2837. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  2838. scale = 65;
  2839. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  2840. scale = 6;
  2841. else
  2842. scale = 12;
  2843. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  2844. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  2845. tw32(GRC_MISC_CFG, val);
  2846. }
  2847. if (tp->link_config.active_speed == SPEED_1000 &&
  2848. tp->link_config.active_duplex == DUPLEX_HALF)
  2849. tw32(MAC_TX_LENGTHS,
  2850. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2851. (6 << TX_LENGTHS_IPG_SHIFT) |
  2852. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2853. else
  2854. tw32(MAC_TX_LENGTHS,
  2855. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2856. (6 << TX_LENGTHS_IPG_SHIFT) |
  2857. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2858. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  2859. if (netif_carrier_ok(tp->dev)) {
  2860. tw32(HOSTCC_STAT_COAL_TICKS,
  2861. tp->coal.stats_block_coalesce_usecs);
  2862. } else {
  2863. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  2864. }
  2865. }
  2866. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
  2867. u32 val = tr32(PCIE_PWR_MGMT_THRESH);
  2868. if (!netif_carrier_ok(tp->dev))
  2869. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  2870. tp->pwrmgmt_thresh;
  2871. else
  2872. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  2873. tw32(PCIE_PWR_MGMT_THRESH, val);
  2874. }
  2875. return err;
  2876. }
  2877. /* This is called whenever we suspect that the system chipset is re-
  2878. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  2879. * is bogus tx completions. We try to recover by setting the
  2880. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  2881. * in the workqueue.
  2882. */
  2883. static void tg3_tx_recover(struct tg3 *tp)
  2884. {
  2885. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  2886. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  2887. printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
  2888. "mapped I/O cycles to the network device, attempting to "
  2889. "recover. Please report the problem to the driver maintainer "
  2890. "and include system chipset information.\n", tp->dev->name);
  2891. spin_lock(&tp->lock);
  2892. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  2893. spin_unlock(&tp->lock);
  2894. }
  2895. static inline u32 tg3_tx_avail(struct tg3 *tp)
  2896. {
  2897. smp_mb();
  2898. return (tp->tx_pending -
  2899. ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
  2900. }
  2901. /* Tigon3 never reports partial packet sends. So we do not
  2902. * need special logic to handle SKBs that have not had all
  2903. * of their frags sent yet, like SunGEM does.
  2904. */
  2905. static void tg3_tx(struct tg3 *tp)
  2906. {
  2907. u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
  2908. u32 sw_idx = tp->tx_cons;
  2909. while (sw_idx != hw_idx) {
  2910. struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
  2911. struct sk_buff *skb = ri->skb;
  2912. int i, tx_bug = 0;
  2913. if (unlikely(skb == NULL)) {
  2914. tg3_tx_recover(tp);
  2915. return;
  2916. }
  2917. pci_unmap_single(tp->pdev,
  2918. pci_unmap_addr(ri, mapping),
  2919. skb_headlen(skb),
  2920. PCI_DMA_TODEVICE);
  2921. ri->skb = NULL;
  2922. sw_idx = NEXT_TX(sw_idx);
  2923. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2924. ri = &tp->tx_buffers[sw_idx];
  2925. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  2926. tx_bug = 1;
  2927. pci_unmap_page(tp->pdev,
  2928. pci_unmap_addr(ri, mapping),
  2929. skb_shinfo(skb)->frags[i].size,
  2930. PCI_DMA_TODEVICE);
  2931. sw_idx = NEXT_TX(sw_idx);
  2932. }
  2933. dev_kfree_skb(skb);
  2934. if (unlikely(tx_bug)) {
  2935. tg3_tx_recover(tp);
  2936. return;
  2937. }
  2938. }
  2939. tp->tx_cons = sw_idx;
  2940. /* Need to make the tx_cons update visible to tg3_start_xmit()
  2941. * before checking for netif_queue_stopped(). Without the
  2942. * memory barrier, there is a small possibility that tg3_start_xmit()
  2943. * will miss it and cause the queue to be stopped forever.
  2944. */
  2945. smp_mb();
  2946. if (unlikely(netif_queue_stopped(tp->dev) &&
  2947. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
  2948. netif_tx_lock(tp->dev);
  2949. if (netif_queue_stopped(tp->dev) &&
  2950. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
  2951. netif_wake_queue(tp->dev);
  2952. netif_tx_unlock(tp->dev);
  2953. }
  2954. }
  2955. /* Returns size of skb allocated or < 0 on error.
  2956. *
  2957. * We only need to fill in the address because the other members
  2958. * of the RX descriptor are invariant, see tg3_init_rings.
  2959. *
  2960. * Note the purposeful assymetry of cpu vs. chip accesses. For
  2961. * posting buffers we only dirty the first cache line of the RX
  2962. * descriptor (containing the address). Whereas for the RX status
  2963. * buffers the cpu only reads the last cacheline of the RX descriptor
  2964. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  2965. */
  2966. static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
  2967. int src_idx, u32 dest_idx_unmasked)
  2968. {
  2969. struct tg3_rx_buffer_desc *desc;
  2970. struct ring_info *map, *src_map;
  2971. struct sk_buff *skb;
  2972. dma_addr_t mapping;
  2973. int skb_size, dest_idx;
  2974. src_map = NULL;
  2975. switch (opaque_key) {
  2976. case RXD_OPAQUE_RING_STD:
  2977. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2978. desc = &tp->rx_std[dest_idx];
  2979. map = &tp->rx_std_buffers[dest_idx];
  2980. if (src_idx >= 0)
  2981. src_map = &tp->rx_std_buffers[src_idx];
  2982. skb_size = tp->rx_pkt_buf_sz;
  2983. break;
  2984. case RXD_OPAQUE_RING_JUMBO:
  2985. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2986. desc = &tp->rx_jumbo[dest_idx];
  2987. map = &tp->rx_jumbo_buffers[dest_idx];
  2988. if (src_idx >= 0)
  2989. src_map = &tp->rx_jumbo_buffers[src_idx];
  2990. skb_size = RX_JUMBO_PKT_BUF_SZ;
  2991. break;
  2992. default:
  2993. return -EINVAL;
  2994. };
  2995. /* Do not overwrite any of the map or rp information
  2996. * until we are sure we can commit to a new buffer.
  2997. *
  2998. * Callers depend upon this behavior and assume that
  2999. * we leave everything unchanged if we fail.
  3000. */
  3001. skb = netdev_alloc_skb(tp->dev, skb_size);
  3002. if (skb == NULL)
  3003. return -ENOMEM;
  3004. skb_reserve(skb, tp->rx_offset);
  3005. mapping = pci_map_single(tp->pdev, skb->data,
  3006. skb_size - tp->rx_offset,
  3007. PCI_DMA_FROMDEVICE);
  3008. map->skb = skb;
  3009. pci_unmap_addr_set(map, mapping, mapping);
  3010. if (src_map != NULL)
  3011. src_map->skb = NULL;
  3012. desc->addr_hi = ((u64)mapping >> 32);
  3013. desc->addr_lo = ((u64)mapping & 0xffffffff);
  3014. return skb_size;
  3015. }
  3016. /* We only need to move over in the address because the other
  3017. * members of the RX descriptor are invariant. See notes above
  3018. * tg3_alloc_rx_skb for full details.
  3019. */
  3020. static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
  3021. int src_idx, u32 dest_idx_unmasked)
  3022. {
  3023. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  3024. struct ring_info *src_map, *dest_map;
  3025. int dest_idx;
  3026. switch (opaque_key) {
  3027. case RXD_OPAQUE_RING_STD:
  3028. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  3029. dest_desc = &tp->rx_std[dest_idx];
  3030. dest_map = &tp->rx_std_buffers[dest_idx];
  3031. src_desc = &tp->rx_std[src_idx];
  3032. src_map = &tp->rx_std_buffers[src_idx];
  3033. break;
  3034. case RXD_OPAQUE_RING_JUMBO:
  3035. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  3036. dest_desc = &tp->rx_jumbo[dest_idx];
  3037. dest_map = &tp->rx_jumbo_buffers[dest_idx];
  3038. src_desc = &tp->rx_jumbo[src_idx];
  3039. src_map = &tp->rx_jumbo_buffers[src_idx];
  3040. break;
  3041. default:
  3042. return;
  3043. };
  3044. dest_map->skb = src_map->skb;
  3045. pci_unmap_addr_set(dest_map, mapping,
  3046. pci_unmap_addr(src_map, mapping));
  3047. dest_desc->addr_hi = src_desc->addr_hi;
  3048. dest_desc->addr_lo = src_desc->addr_lo;
  3049. src_map->skb = NULL;
  3050. }
  3051. #if TG3_VLAN_TAG_USED
  3052. static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
  3053. {
  3054. return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
  3055. }
  3056. #endif
  3057. /* The RX ring scheme is composed of multiple rings which post fresh
  3058. * buffers to the chip, and one special ring the chip uses to report
  3059. * status back to the host.
  3060. *
  3061. * The special ring reports the status of received packets to the
  3062. * host. The chip does not write into the original descriptor the
  3063. * RX buffer was obtained from. The chip simply takes the original
  3064. * descriptor as provided by the host, updates the status and length
  3065. * field, then writes this into the next status ring entry.
  3066. *
  3067. * Each ring the host uses to post buffers to the chip is described
  3068. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  3069. * it is first placed into the on-chip ram. When the packet's length
  3070. * is known, it walks down the TG3_BDINFO entries to select the ring.
  3071. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  3072. * which is within the range of the new packet's length is chosen.
  3073. *
  3074. * The "separate ring for rx status" scheme may sound queer, but it makes
  3075. * sense from a cache coherency perspective. If only the host writes
  3076. * to the buffer post rings, and only the chip writes to the rx status
  3077. * rings, then cache lines never move beyond shared-modified state.
  3078. * If both the host and chip were to write into the same ring, cache line
  3079. * eviction could occur since both entities want it in an exclusive state.
  3080. */
  3081. static int tg3_rx(struct tg3 *tp, int budget)
  3082. {
  3083. u32 work_mask, rx_std_posted = 0;
  3084. u32 sw_idx = tp->rx_rcb_ptr;
  3085. u16 hw_idx;
  3086. int received;
  3087. hw_idx = tp->hw_status->idx[0].rx_producer;
  3088. /*
  3089. * We need to order the read of hw_idx and the read of
  3090. * the opaque cookie.
  3091. */
  3092. rmb();
  3093. work_mask = 0;
  3094. received = 0;
  3095. while (sw_idx != hw_idx && budget > 0) {
  3096. struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
  3097. unsigned int len;
  3098. struct sk_buff *skb;
  3099. dma_addr_t dma_addr;
  3100. u32 opaque_key, desc_idx, *post_ptr;
  3101. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  3102. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  3103. if (opaque_key == RXD_OPAQUE_RING_STD) {
  3104. dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
  3105. mapping);
  3106. skb = tp->rx_std_buffers[desc_idx].skb;
  3107. post_ptr = &tp->rx_std_ptr;
  3108. rx_std_posted++;
  3109. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  3110. dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
  3111. mapping);
  3112. skb = tp->rx_jumbo_buffers[desc_idx].skb;
  3113. post_ptr = &tp->rx_jumbo_ptr;
  3114. }
  3115. else {
  3116. goto next_pkt_nopost;
  3117. }
  3118. work_mask |= opaque_key;
  3119. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  3120. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  3121. drop_it:
  3122. tg3_recycle_rx(tp, opaque_key,
  3123. desc_idx, *post_ptr);
  3124. drop_it_no_recycle:
  3125. /* Other statistics kept track of by card. */
  3126. tp->net_stats.rx_dropped++;
  3127. goto next_pkt;
  3128. }
  3129. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
  3130. if (len > RX_COPY_THRESHOLD
  3131. && tp->rx_offset == 2
  3132. /* rx_offset != 2 iff this is a 5701 card running
  3133. * in PCI-X mode [see tg3_get_invariants()] */
  3134. ) {
  3135. int skb_size;
  3136. skb_size = tg3_alloc_rx_skb(tp, opaque_key,
  3137. desc_idx, *post_ptr);
  3138. if (skb_size < 0)
  3139. goto drop_it;
  3140. pci_unmap_single(tp->pdev, dma_addr,
  3141. skb_size - tp->rx_offset,
  3142. PCI_DMA_FROMDEVICE);
  3143. skb_put(skb, len);
  3144. } else {
  3145. struct sk_buff *copy_skb;
  3146. tg3_recycle_rx(tp, opaque_key,
  3147. desc_idx, *post_ptr);
  3148. copy_skb = netdev_alloc_skb(tp->dev, len + 2);
  3149. if (copy_skb == NULL)
  3150. goto drop_it_no_recycle;
  3151. skb_reserve(copy_skb, 2);
  3152. skb_put(copy_skb, len);
  3153. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3154. skb_copy_from_linear_data(skb, copy_skb->data, len);
  3155. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  3156. /* We'll reuse the original ring buffer. */
  3157. skb = copy_skb;
  3158. }
  3159. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  3160. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  3161. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  3162. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  3163. skb->ip_summed = CHECKSUM_UNNECESSARY;
  3164. else
  3165. skb->ip_summed = CHECKSUM_NONE;
  3166. skb->protocol = eth_type_trans(skb, tp->dev);
  3167. #if TG3_VLAN_TAG_USED
  3168. if (tp->vlgrp != NULL &&
  3169. desc->type_flags & RXD_FLAG_VLAN) {
  3170. tg3_vlan_rx(tp, skb,
  3171. desc->err_vlan & RXD_VLAN_MASK);
  3172. } else
  3173. #endif
  3174. netif_receive_skb(skb);
  3175. tp->dev->last_rx = jiffies;
  3176. received++;
  3177. budget--;
  3178. next_pkt:
  3179. (*post_ptr)++;
  3180. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  3181. u32 idx = *post_ptr % TG3_RX_RING_SIZE;
  3182. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
  3183. TG3_64BIT_REG_LOW, idx);
  3184. work_mask &= ~RXD_OPAQUE_RING_STD;
  3185. rx_std_posted = 0;
  3186. }
  3187. next_pkt_nopost:
  3188. sw_idx++;
  3189. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  3190. /* Refresh hw_idx to see if there is new work */
  3191. if (sw_idx == hw_idx) {
  3192. hw_idx = tp->hw_status->idx[0].rx_producer;
  3193. rmb();
  3194. }
  3195. }
  3196. /* ACK the status ring. */
  3197. tp->rx_rcb_ptr = sw_idx;
  3198. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
  3199. /* Refill RX ring(s). */
  3200. if (work_mask & RXD_OPAQUE_RING_STD) {
  3201. sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
  3202. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  3203. sw_idx);
  3204. }
  3205. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  3206. sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
  3207. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  3208. sw_idx);
  3209. }
  3210. mmiowb();
  3211. return received;
  3212. }
  3213. static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
  3214. {
  3215. struct tg3_hw_status *sblk = tp->hw_status;
  3216. /* handle link change and other phy events */
  3217. if (!(tp->tg3_flags &
  3218. (TG3_FLAG_USE_LINKCHG_REG |
  3219. TG3_FLAG_POLL_SERDES))) {
  3220. if (sblk->status & SD_STATUS_LINK_CHG) {
  3221. sblk->status = SD_STATUS_UPDATED |
  3222. (sblk->status & ~SD_STATUS_LINK_CHG);
  3223. spin_lock(&tp->lock);
  3224. tg3_setup_phy(tp, 0);
  3225. spin_unlock(&tp->lock);
  3226. }
  3227. }
  3228. /* run TX completion thread */
  3229. if (sblk->idx[0].tx_consumer != tp->tx_cons) {
  3230. tg3_tx(tp);
  3231. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  3232. return work_done;
  3233. }
  3234. /* run RX thread, within the bounds set by NAPI.
  3235. * All RX "locking" is done by ensuring outside
  3236. * code synchronizes with tg3->napi.poll()
  3237. */
  3238. if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  3239. work_done += tg3_rx(tp, budget - work_done);
  3240. return work_done;
  3241. }
  3242. static int tg3_poll(struct napi_struct *napi, int budget)
  3243. {
  3244. struct tg3 *tp = container_of(napi, struct tg3, napi);
  3245. int work_done = 0;
  3246. struct tg3_hw_status *sblk = tp->hw_status;
  3247. while (1) {
  3248. work_done = tg3_poll_work(tp, work_done, budget);
  3249. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
  3250. goto tx_recovery;
  3251. if (unlikely(work_done >= budget))
  3252. break;
  3253. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  3254. /* tp->last_tag is used in tg3_restart_ints() below
  3255. * to tell the hw how much work has been processed,
  3256. * so we must read it before checking for more work.
  3257. */
  3258. tp->last_tag = sblk->status_tag;
  3259. rmb();
  3260. } else
  3261. sblk->status &= ~SD_STATUS_UPDATED;
  3262. if (likely(!tg3_has_work(tp))) {
  3263. netif_rx_complete(tp->dev, napi);
  3264. tg3_restart_ints(tp);
  3265. break;
  3266. }
  3267. }
  3268. return work_done;
  3269. tx_recovery:
  3270. /* work_done is guaranteed to be less than budget. */
  3271. netif_rx_complete(tp->dev, napi);
  3272. schedule_work(&tp->reset_task);
  3273. return work_done;
  3274. }
  3275. static void tg3_irq_quiesce(struct tg3 *tp)
  3276. {
  3277. BUG_ON(tp->irq_sync);
  3278. tp->irq_sync = 1;
  3279. smp_mb();
  3280. synchronize_irq(tp->pdev->irq);
  3281. }
  3282. static inline int tg3_irq_sync(struct tg3 *tp)
  3283. {
  3284. return tp->irq_sync;
  3285. }
  3286. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  3287. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  3288. * with as well. Most of the time, this is not necessary except when
  3289. * shutting down the device.
  3290. */
  3291. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  3292. {
  3293. spin_lock_bh(&tp->lock);
  3294. if (irq_sync)
  3295. tg3_irq_quiesce(tp);
  3296. }
  3297. static inline void tg3_full_unlock(struct tg3 *tp)
  3298. {
  3299. spin_unlock_bh(&tp->lock);
  3300. }
  3301. /* One-shot MSI handler - Chip automatically disables interrupt
  3302. * after sending MSI so driver doesn't have to do it.
  3303. */
  3304. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  3305. {
  3306. struct net_device *dev = dev_id;
  3307. struct tg3 *tp = netdev_priv(dev);
  3308. prefetch(tp->hw_status);
  3309. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3310. if (likely(!tg3_irq_sync(tp)))
  3311. netif_rx_schedule(dev, &tp->napi);
  3312. return IRQ_HANDLED;
  3313. }
  3314. /* MSI ISR - No need to check for interrupt sharing and no need to
  3315. * flush status block and interrupt mailbox. PCI ordering rules
  3316. * guarantee that MSI will arrive after the status block.
  3317. */
  3318. static irqreturn_t tg3_msi(int irq, void *dev_id)
  3319. {
  3320. struct net_device *dev = dev_id;
  3321. struct tg3 *tp = netdev_priv(dev);
  3322. prefetch(tp->hw_status);
  3323. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3324. /*
  3325. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3326. * chip-internal interrupt pending events.
  3327. * Writing non-zero to intr-mbox-0 additional tells the
  3328. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3329. * event coalescing.
  3330. */
  3331. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3332. if (likely(!tg3_irq_sync(tp)))
  3333. netif_rx_schedule(dev, &tp->napi);
  3334. return IRQ_RETVAL(1);
  3335. }
  3336. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  3337. {
  3338. struct net_device *dev = dev_id;
  3339. struct tg3 *tp = netdev_priv(dev);
  3340. struct tg3_hw_status *sblk = tp->hw_status;
  3341. unsigned int handled = 1;
  3342. /* In INTx mode, it is possible for the interrupt to arrive at
  3343. * the CPU before the status block posted prior to the interrupt.
  3344. * Reading the PCI State register will confirm whether the
  3345. * interrupt is ours and will flush the status block.
  3346. */
  3347. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  3348. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3349. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3350. handled = 0;
  3351. goto out;
  3352. }
  3353. }
  3354. /*
  3355. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3356. * chip-internal interrupt pending events.
  3357. * Writing non-zero to intr-mbox-0 additional tells the
  3358. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3359. * event coalescing.
  3360. *
  3361. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3362. * spurious interrupts. The flush impacts performance but
  3363. * excessive spurious interrupts can be worse in some cases.
  3364. */
  3365. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3366. if (tg3_irq_sync(tp))
  3367. goto out;
  3368. sblk->status &= ~SD_STATUS_UPDATED;
  3369. if (likely(tg3_has_work(tp))) {
  3370. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3371. netif_rx_schedule(dev, &tp->napi);
  3372. } else {
  3373. /* No work, shared interrupt perhaps? re-enable
  3374. * interrupts, and flush that PCI write
  3375. */
  3376. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  3377. 0x00000000);
  3378. }
  3379. out:
  3380. return IRQ_RETVAL(handled);
  3381. }
  3382. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  3383. {
  3384. struct net_device *dev = dev_id;
  3385. struct tg3 *tp = netdev_priv(dev);
  3386. struct tg3_hw_status *sblk = tp->hw_status;
  3387. unsigned int handled = 1;
  3388. /* In INTx mode, it is possible for the interrupt to arrive at
  3389. * the CPU before the status block posted prior to the interrupt.
  3390. * Reading the PCI State register will confirm whether the
  3391. * interrupt is ours and will flush the status block.
  3392. */
  3393. if (unlikely(sblk->status_tag == tp->last_tag)) {
  3394. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3395. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3396. handled = 0;
  3397. goto out;
  3398. }
  3399. }
  3400. /*
  3401. * writing any value to intr-mbox-0 clears PCI INTA# and
  3402. * chip-internal interrupt pending events.
  3403. * writing non-zero to intr-mbox-0 additional tells the
  3404. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3405. * event coalescing.
  3406. *
  3407. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3408. * spurious interrupts. The flush impacts performance but
  3409. * excessive spurious interrupts can be worse in some cases.
  3410. */
  3411. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3412. if (tg3_irq_sync(tp))
  3413. goto out;
  3414. if (netif_rx_schedule_prep(dev, &tp->napi)) {
  3415. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3416. /* Update last_tag to mark that this status has been
  3417. * seen. Because interrupt may be shared, we may be
  3418. * racing with tg3_poll(), so only update last_tag
  3419. * if tg3_poll() is not scheduled.
  3420. */
  3421. tp->last_tag = sblk->status_tag;
  3422. __netif_rx_schedule(dev, &tp->napi);
  3423. }
  3424. out:
  3425. return IRQ_RETVAL(handled);
  3426. }
  3427. /* ISR for interrupt test */
  3428. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  3429. {
  3430. struct net_device *dev = dev_id;
  3431. struct tg3 *tp = netdev_priv(dev);
  3432. struct tg3_hw_status *sblk = tp->hw_status;
  3433. if ((sblk->status & SD_STATUS_UPDATED) ||
  3434. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3435. tg3_disable_ints(tp);
  3436. return IRQ_RETVAL(1);
  3437. }
  3438. return IRQ_RETVAL(0);
  3439. }
  3440. static int tg3_init_hw(struct tg3 *, int);
  3441. static int tg3_halt(struct tg3 *, int, int);
  3442. /* Restart hardware after configuration changes, self-test, etc.
  3443. * Invoked with tp->lock held.
  3444. */
  3445. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  3446. __releases(tp->lock)
  3447. __acquires(tp->lock)
  3448. {
  3449. int err;
  3450. err = tg3_init_hw(tp, reset_phy);
  3451. if (err) {
  3452. printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
  3453. "aborting.\n", tp->dev->name);
  3454. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3455. tg3_full_unlock(tp);
  3456. del_timer_sync(&tp->timer);
  3457. tp->irq_sync = 0;
  3458. napi_enable(&tp->napi);
  3459. dev_close(tp->dev);
  3460. tg3_full_lock(tp, 0);
  3461. }
  3462. return err;
  3463. }
  3464. #ifdef CONFIG_NET_POLL_CONTROLLER
  3465. static void tg3_poll_controller(struct net_device *dev)
  3466. {
  3467. struct tg3 *tp = netdev_priv(dev);
  3468. tg3_interrupt(tp->pdev->irq, dev);
  3469. }
  3470. #endif
  3471. static void tg3_reset_task(struct work_struct *work)
  3472. {
  3473. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  3474. unsigned int restart_timer;
  3475. tg3_full_lock(tp, 0);
  3476. if (!netif_running(tp->dev)) {
  3477. tg3_full_unlock(tp);
  3478. return;
  3479. }
  3480. tg3_full_unlock(tp);
  3481. tg3_netif_stop(tp);
  3482. tg3_full_lock(tp, 1);
  3483. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  3484. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  3485. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  3486. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  3487. tp->write32_rx_mbox = tg3_write_flush_reg32;
  3488. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  3489. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  3490. }
  3491. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  3492. if (tg3_init_hw(tp, 1))
  3493. goto out;
  3494. tg3_netif_start(tp);
  3495. if (restart_timer)
  3496. mod_timer(&tp->timer, jiffies + 1);
  3497. out:
  3498. tg3_full_unlock(tp);
  3499. }
  3500. static void tg3_dump_short_state(struct tg3 *tp)
  3501. {
  3502. printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  3503. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  3504. printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  3505. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  3506. }
  3507. static void tg3_tx_timeout(struct net_device *dev)
  3508. {
  3509. struct tg3 *tp = netdev_priv(dev);
  3510. if (netif_msg_tx_err(tp)) {
  3511. printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  3512. dev->name);
  3513. tg3_dump_short_state(tp);
  3514. }
  3515. schedule_work(&tp->reset_task);
  3516. }
  3517. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  3518. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  3519. {
  3520. u32 base = (u32) mapping & 0xffffffff;
  3521. return ((base > 0xffffdcc0) &&
  3522. (base + len + 8 < base));
  3523. }
  3524. /* Test for DMA addresses > 40-bit */
  3525. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  3526. int len)
  3527. {
  3528. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  3529. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  3530. return (((u64) mapping + len) > DMA_40BIT_MASK);
  3531. return 0;
  3532. #else
  3533. return 0;
  3534. #endif
  3535. }
  3536. static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
  3537. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  3538. static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
  3539. u32 last_plus_one, u32 *start,
  3540. u32 base_flags, u32 mss)
  3541. {
  3542. struct sk_buff *new_skb;
  3543. dma_addr_t new_addr = 0;
  3544. u32 entry = *start;
  3545. int i, ret = 0;
  3546. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  3547. new_skb = skb_copy(skb, GFP_ATOMIC);
  3548. else {
  3549. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  3550. new_skb = skb_copy_expand(skb,
  3551. skb_headroom(skb) + more_headroom,
  3552. skb_tailroom(skb), GFP_ATOMIC);
  3553. }
  3554. if (!new_skb) {
  3555. ret = -1;
  3556. } else {
  3557. /* New SKB is guaranteed to be linear. */
  3558. entry = *start;
  3559. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  3560. PCI_DMA_TODEVICE);
  3561. /* Make sure new skb does not cross any 4G boundaries.
  3562. * Drop the packet if it does.
  3563. */
  3564. if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
  3565. ret = -1;
  3566. dev_kfree_skb(new_skb);
  3567. new_skb = NULL;
  3568. } else {
  3569. tg3_set_txd(tp, entry, new_addr, new_skb->len,
  3570. base_flags, 1 | (mss << 1));
  3571. *start = NEXT_TX(entry);
  3572. }
  3573. }
  3574. /* Now clean up the sw ring entries. */
  3575. i = 0;
  3576. while (entry != last_plus_one) {
  3577. int len;
  3578. if (i == 0)
  3579. len = skb_headlen(skb);
  3580. else
  3581. len = skb_shinfo(skb)->frags[i-1].size;
  3582. pci_unmap_single(tp->pdev,
  3583. pci_unmap_addr(&tp->tx_buffers[entry], mapping),
  3584. len, PCI_DMA_TODEVICE);
  3585. if (i == 0) {
  3586. tp->tx_buffers[entry].skb = new_skb;
  3587. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
  3588. } else {
  3589. tp->tx_buffers[entry].skb = NULL;
  3590. }
  3591. entry = NEXT_TX(entry);
  3592. i++;
  3593. }
  3594. dev_kfree_skb(skb);
  3595. return ret;
  3596. }
  3597. static void tg3_set_txd(struct tg3 *tp, int entry,
  3598. dma_addr_t mapping, int len, u32 flags,
  3599. u32 mss_and_is_end)
  3600. {
  3601. struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  3602. int is_end = (mss_and_is_end & 0x1);
  3603. u32 mss = (mss_and_is_end >> 1);
  3604. u32 vlan_tag = 0;
  3605. if (is_end)
  3606. flags |= TXD_FLAG_END;
  3607. if (flags & TXD_FLAG_VLAN) {
  3608. vlan_tag = flags >> 16;
  3609. flags &= 0xffff;
  3610. }
  3611. vlan_tag |= (mss << TXD_MSS_SHIFT);
  3612. txd->addr_hi = ((u64) mapping >> 32);
  3613. txd->addr_lo = ((u64) mapping & 0xffffffff);
  3614. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  3615. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  3616. }
  3617. /* hard_start_xmit for devices that don't have any bugs and
  3618. * support TG3_FLG2_HW_TSO_2 only.
  3619. */
  3620. static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  3621. {
  3622. struct tg3 *tp = netdev_priv(dev);
  3623. dma_addr_t mapping;
  3624. u32 len, entry, base_flags, mss;
  3625. len = skb_headlen(skb);
  3626. /* We are running in BH disabled context with netif_tx_lock
  3627. * and TX reclaim runs via tp->napi.poll inside of a software
  3628. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3629. * no IRQ context deadlocks to worry about either. Rejoice!
  3630. */
  3631. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3632. if (!netif_queue_stopped(dev)) {
  3633. netif_stop_queue(dev);
  3634. /* This is a hard error, log it. */
  3635. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3636. "queue awake!\n", dev->name);
  3637. }
  3638. return NETDEV_TX_BUSY;
  3639. }
  3640. entry = tp->tx_prod;
  3641. base_flags = 0;
  3642. mss = 0;
  3643. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3644. int tcp_opt_len, ip_tcp_len;
  3645. if (skb_header_cloned(skb) &&
  3646. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3647. dev_kfree_skb(skb);
  3648. goto out_unlock;
  3649. }
  3650. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  3651. mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
  3652. else {
  3653. struct iphdr *iph = ip_hdr(skb);
  3654. tcp_opt_len = tcp_optlen(skb);
  3655. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3656. iph->check = 0;
  3657. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  3658. mss |= (ip_tcp_len + tcp_opt_len) << 9;
  3659. }
  3660. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3661. TXD_FLAG_CPU_POST_DMA);
  3662. tcp_hdr(skb)->check = 0;
  3663. }
  3664. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  3665. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3666. #if TG3_VLAN_TAG_USED
  3667. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3668. base_flags |= (TXD_FLAG_VLAN |
  3669. (vlan_tx_tag_get(skb) << 16));
  3670. #endif
  3671. /* Queue skb data, a.k.a. the main skb fragment. */
  3672. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3673. tp->tx_buffers[entry].skb = skb;
  3674. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3675. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3676. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3677. entry = NEXT_TX(entry);
  3678. /* Now loop through additional data fragments, and queue them. */
  3679. if (skb_shinfo(skb)->nr_frags > 0) {
  3680. unsigned int i, last;
  3681. last = skb_shinfo(skb)->nr_frags - 1;
  3682. for (i = 0; i <= last; i++) {
  3683. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3684. len = frag->size;
  3685. mapping = pci_map_page(tp->pdev,
  3686. frag->page,
  3687. frag->page_offset,
  3688. len, PCI_DMA_TODEVICE);
  3689. tp->tx_buffers[entry].skb = NULL;
  3690. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3691. tg3_set_txd(tp, entry, mapping, len,
  3692. base_flags, (i == last) | (mss << 1));
  3693. entry = NEXT_TX(entry);
  3694. }
  3695. }
  3696. /* Packets are ready, update Tx producer idx local and on card. */
  3697. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3698. tp->tx_prod = entry;
  3699. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3700. netif_stop_queue(dev);
  3701. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3702. netif_wake_queue(tp->dev);
  3703. }
  3704. out_unlock:
  3705. mmiowb();
  3706. dev->trans_start = jiffies;
  3707. return NETDEV_TX_OK;
  3708. }
  3709. static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
  3710. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  3711. * TSO header is greater than 80 bytes.
  3712. */
  3713. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  3714. {
  3715. struct sk_buff *segs, *nskb;
  3716. /* Estimate the number of fragments in the worst case */
  3717. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
  3718. netif_stop_queue(tp->dev);
  3719. if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
  3720. return NETDEV_TX_BUSY;
  3721. netif_wake_queue(tp->dev);
  3722. }
  3723. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  3724. if (IS_ERR(segs))
  3725. goto tg3_tso_bug_end;
  3726. do {
  3727. nskb = segs;
  3728. segs = segs->next;
  3729. nskb->next = NULL;
  3730. tg3_start_xmit_dma_bug(nskb, tp->dev);
  3731. } while (segs);
  3732. tg3_tso_bug_end:
  3733. dev_kfree_skb(skb);
  3734. return NETDEV_TX_OK;
  3735. }
  3736. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  3737. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  3738. */
  3739. static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
  3740. {
  3741. struct tg3 *tp = netdev_priv(dev);
  3742. dma_addr_t mapping;
  3743. u32 len, entry, base_flags, mss;
  3744. int would_hit_hwbug;
  3745. len = skb_headlen(skb);
  3746. /* We are running in BH disabled context with netif_tx_lock
  3747. * and TX reclaim runs via tp->napi.poll inside of a software
  3748. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3749. * no IRQ context deadlocks to worry about either. Rejoice!
  3750. */
  3751. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3752. if (!netif_queue_stopped(dev)) {
  3753. netif_stop_queue(dev);
  3754. /* This is a hard error, log it. */
  3755. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3756. "queue awake!\n", dev->name);
  3757. }
  3758. return NETDEV_TX_BUSY;
  3759. }
  3760. entry = tp->tx_prod;
  3761. base_flags = 0;
  3762. if (skb->ip_summed == CHECKSUM_PARTIAL)
  3763. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3764. mss = 0;
  3765. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3766. struct iphdr *iph;
  3767. int tcp_opt_len, ip_tcp_len, hdr_len;
  3768. if (skb_header_cloned(skb) &&
  3769. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3770. dev_kfree_skb(skb);
  3771. goto out_unlock;
  3772. }
  3773. tcp_opt_len = tcp_optlen(skb);
  3774. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3775. hdr_len = ip_tcp_len + tcp_opt_len;
  3776. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  3777. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  3778. return (tg3_tso_bug(tp, skb));
  3779. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3780. TXD_FLAG_CPU_POST_DMA);
  3781. iph = ip_hdr(skb);
  3782. iph->check = 0;
  3783. iph->tot_len = htons(mss + hdr_len);
  3784. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  3785. tcp_hdr(skb)->check = 0;
  3786. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  3787. } else
  3788. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  3789. iph->daddr, 0,
  3790. IPPROTO_TCP,
  3791. 0);
  3792. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  3793. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
  3794. if (tcp_opt_len || iph->ihl > 5) {
  3795. int tsflags;
  3796. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  3797. mss |= (tsflags << 11);
  3798. }
  3799. } else {
  3800. if (tcp_opt_len || iph->ihl > 5) {
  3801. int tsflags;
  3802. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  3803. base_flags |= tsflags << 12;
  3804. }
  3805. }
  3806. }
  3807. #if TG3_VLAN_TAG_USED
  3808. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3809. base_flags |= (TXD_FLAG_VLAN |
  3810. (vlan_tx_tag_get(skb) << 16));
  3811. #endif
  3812. /* Queue skb data, a.k.a. the main skb fragment. */
  3813. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3814. tp->tx_buffers[entry].skb = skb;
  3815. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3816. would_hit_hwbug = 0;
  3817. if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
  3818. would_hit_hwbug = 1;
  3819. else if (tg3_4g_overflow_test(mapping, len))
  3820. would_hit_hwbug = 1;
  3821. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3822. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3823. entry = NEXT_TX(entry);
  3824. /* Now loop through additional data fragments, and queue them. */
  3825. if (skb_shinfo(skb)->nr_frags > 0) {
  3826. unsigned int i, last;
  3827. last = skb_shinfo(skb)->nr_frags - 1;
  3828. for (i = 0; i <= last; i++) {
  3829. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3830. len = frag->size;
  3831. mapping = pci_map_page(tp->pdev,
  3832. frag->page,
  3833. frag->page_offset,
  3834. len, PCI_DMA_TODEVICE);
  3835. tp->tx_buffers[entry].skb = NULL;
  3836. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3837. if (tg3_4g_overflow_test(mapping, len))
  3838. would_hit_hwbug = 1;
  3839. if (tg3_40bit_overflow_test(tp, mapping, len))
  3840. would_hit_hwbug = 1;
  3841. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  3842. tg3_set_txd(tp, entry, mapping, len,
  3843. base_flags, (i == last)|(mss << 1));
  3844. else
  3845. tg3_set_txd(tp, entry, mapping, len,
  3846. base_flags, (i == last));
  3847. entry = NEXT_TX(entry);
  3848. }
  3849. }
  3850. if (would_hit_hwbug) {
  3851. u32 last_plus_one = entry;
  3852. u32 start;
  3853. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  3854. start &= (TG3_TX_RING_SIZE - 1);
  3855. /* If the workaround fails due to memory/mapping
  3856. * failure, silently drop this packet.
  3857. */
  3858. if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
  3859. &start, base_flags, mss))
  3860. goto out_unlock;
  3861. entry = start;
  3862. }
  3863. /* Packets are ready, update Tx producer idx local and on card. */
  3864. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3865. tp->tx_prod = entry;
  3866. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3867. netif_stop_queue(dev);
  3868. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3869. netif_wake_queue(tp->dev);
  3870. }
  3871. out_unlock:
  3872. mmiowb();
  3873. dev->trans_start = jiffies;
  3874. return NETDEV_TX_OK;
  3875. }
  3876. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  3877. int new_mtu)
  3878. {
  3879. dev->mtu = new_mtu;
  3880. if (new_mtu > ETH_DATA_LEN) {
  3881. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  3882. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  3883. ethtool_op_set_tso(dev, 0);
  3884. }
  3885. else
  3886. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  3887. } else {
  3888. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  3889. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  3890. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  3891. }
  3892. }
  3893. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  3894. {
  3895. struct tg3 *tp = netdev_priv(dev);
  3896. int err;
  3897. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  3898. return -EINVAL;
  3899. if (!netif_running(dev)) {
  3900. /* We'll just catch it later when the
  3901. * device is up'd.
  3902. */
  3903. tg3_set_mtu(dev, tp, new_mtu);
  3904. return 0;
  3905. }
  3906. tg3_netif_stop(tp);
  3907. tg3_full_lock(tp, 1);
  3908. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3909. tg3_set_mtu(dev, tp, new_mtu);
  3910. err = tg3_restart_hw(tp, 0);
  3911. if (!err)
  3912. tg3_netif_start(tp);
  3913. tg3_full_unlock(tp);
  3914. return err;
  3915. }
  3916. /* Free up pending packets in all rx/tx rings.
  3917. *
  3918. * The chip has been shut down and the driver detached from
  3919. * the networking, so no interrupts or new tx packets will
  3920. * end up in the driver. tp->{tx,}lock is not held and we are not
  3921. * in an interrupt context and thus may sleep.
  3922. */
  3923. static void tg3_free_rings(struct tg3 *tp)
  3924. {
  3925. struct ring_info *rxp;
  3926. int i;
  3927. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3928. rxp = &tp->rx_std_buffers[i];
  3929. if (rxp->skb == NULL)
  3930. continue;
  3931. pci_unmap_single(tp->pdev,
  3932. pci_unmap_addr(rxp, mapping),
  3933. tp->rx_pkt_buf_sz - tp->rx_offset,
  3934. PCI_DMA_FROMDEVICE);
  3935. dev_kfree_skb_any(rxp->skb);
  3936. rxp->skb = NULL;
  3937. }
  3938. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3939. rxp = &tp->rx_jumbo_buffers[i];
  3940. if (rxp->skb == NULL)
  3941. continue;
  3942. pci_unmap_single(tp->pdev,
  3943. pci_unmap_addr(rxp, mapping),
  3944. RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
  3945. PCI_DMA_FROMDEVICE);
  3946. dev_kfree_skb_any(rxp->skb);
  3947. rxp->skb = NULL;
  3948. }
  3949. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  3950. struct tx_ring_info *txp;
  3951. struct sk_buff *skb;
  3952. int j;
  3953. txp = &tp->tx_buffers[i];
  3954. skb = txp->skb;
  3955. if (skb == NULL) {
  3956. i++;
  3957. continue;
  3958. }
  3959. pci_unmap_single(tp->pdev,
  3960. pci_unmap_addr(txp, mapping),
  3961. skb_headlen(skb),
  3962. PCI_DMA_TODEVICE);
  3963. txp->skb = NULL;
  3964. i++;
  3965. for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
  3966. txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  3967. pci_unmap_page(tp->pdev,
  3968. pci_unmap_addr(txp, mapping),
  3969. skb_shinfo(skb)->frags[j].size,
  3970. PCI_DMA_TODEVICE);
  3971. i++;
  3972. }
  3973. dev_kfree_skb_any(skb);
  3974. }
  3975. }
  3976. /* Initialize tx/rx rings for packet processing.
  3977. *
  3978. * The chip has been shut down and the driver detached from
  3979. * the networking, so no interrupts or new tx packets will
  3980. * end up in the driver. tp->{tx,}lock are held and thus
  3981. * we may not sleep.
  3982. */
  3983. static int tg3_init_rings(struct tg3 *tp)
  3984. {
  3985. u32 i;
  3986. /* Free up all the SKBs. */
  3987. tg3_free_rings(tp);
  3988. /* Zero out all descriptors. */
  3989. memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  3990. memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  3991. memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  3992. memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  3993. tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
  3994. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  3995. (tp->dev->mtu > ETH_DATA_LEN))
  3996. tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
  3997. /* Initialize invariants of the rings, we only set this
  3998. * stuff once. This works because the card does not
  3999. * write into the rx buffer posting rings.
  4000. */
  4001. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  4002. struct tg3_rx_buffer_desc *rxd;
  4003. rxd = &tp->rx_std[i];
  4004. rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
  4005. << RXD_LEN_SHIFT;
  4006. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  4007. rxd->opaque = (RXD_OPAQUE_RING_STD |
  4008. (i << RXD_OPAQUE_INDEX_SHIFT));
  4009. }
  4010. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  4011. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  4012. struct tg3_rx_buffer_desc *rxd;
  4013. rxd = &tp->rx_jumbo[i];
  4014. rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
  4015. << RXD_LEN_SHIFT;
  4016. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  4017. RXD_FLAG_JUMBO;
  4018. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  4019. (i << RXD_OPAQUE_INDEX_SHIFT));
  4020. }
  4021. }
  4022. /* Now allocate fresh SKBs for each rx ring. */
  4023. for (i = 0; i < tp->rx_pending; i++) {
  4024. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
  4025. printk(KERN_WARNING PFX
  4026. "%s: Using a smaller RX standard ring, "
  4027. "only %d out of %d buffers were allocated "
  4028. "successfully.\n",
  4029. tp->dev->name, i, tp->rx_pending);
  4030. if (i == 0)
  4031. return -ENOMEM;
  4032. tp->rx_pending = i;
  4033. break;
  4034. }
  4035. }
  4036. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  4037. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  4038. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
  4039. -1, i) < 0) {
  4040. printk(KERN_WARNING PFX
  4041. "%s: Using a smaller RX jumbo ring, "
  4042. "only %d out of %d buffers were "
  4043. "allocated successfully.\n",
  4044. tp->dev->name, i, tp->rx_jumbo_pending);
  4045. if (i == 0) {
  4046. tg3_free_rings(tp);
  4047. return -ENOMEM;
  4048. }
  4049. tp->rx_jumbo_pending = i;
  4050. break;
  4051. }
  4052. }
  4053. }
  4054. return 0;
  4055. }
  4056. /*
  4057. * Must not be invoked with interrupt sources disabled and
  4058. * the hardware shutdown down.
  4059. */
  4060. static void tg3_free_consistent(struct tg3 *tp)
  4061. {
  4062. kfree(tp->rx_std_buffers);
  4063. tp->rx_std_buffers = NULL;
  4064. if (tp->rx_std) {
  4065. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  4066. tp->rx_std, tp->rx_std_mapping);
  4067. tp->rx_std = NULL;
  4068. }
  4069. if (tp->rx_jumbo) {
  4070. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  4071. tp->rx_jumbo, tp->rx_jumbo_mapping);
  4072. tp->rx_jumbo = NULL;
  4073. }
  4074. if (tp->rx_rcb) {
  4075. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  4076. tp->rx_rcb, tp->rx_rcb_mapping);
  4077. tp->rx_rcb = NULL;
  4078. }
  4079. if (tp->tx_ring) {
  4080. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  4081. tp->tx_ring, tp->tx_desc_mapping);
  4082. tp->tx_ring = NULL;
  4083. }
  4084. if (tp->hw_status) {
  4085. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  4086. tp->hw_status, tp->status_mapping);
  4087. tp->hw_status = NULL;
  4088. }
  4089. if (tp->hw_stats) {
  4090. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  4091. tp->hw_stats, tp->stats_mapping);
  4092. tp->hw_stats = NULL;
  4093. }
  4094. }
  4095. /*
  4096. * Must not be invoked with interrupt sources disabled and
  4097. * the hardware shutdown down. Can sleep.
  4098. */
  4099. static int tg3_alloc_consistent(struct tg3 *tp)
  4100. {
  4101. tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
  4102. (TG3_RX_RING_SIZE +
  4103. TG3_RX_JUMBO_RING_SIZE)) +
  4104. (sizeof(struct tx_ring_info) *
  4105. TG3_TX_RING_SIZE),
  4106. GFP_KERNEL);
  4107. if (!tp->rx_std_buffers)
  4108. return -ENOMEM;
  4109. tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
  4110. tp->tx_buffers = (struct tx_ring_info *)
  4111. &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
  4112. tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  4113. &tp->rx_std_mapping);
  4114. if (!tp->rx_std)
  4115. goto err_out;
  4116. tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  4117. &tp->rx_jumbo_mapping);
  4118. if (!tp->rx_jumbo)
  4119. goto err_out;
  4120. tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  4121. &tp->rx_rcb_mapping);
  4122. if (!tp->rx_rcb)
  4123. goto err_out;
  4124. tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
  4125. &tp->tx_desc_mapping);
  4126. if (!tp->tx_ring)
  4127. goto err_out;
  4128. tp->hw_status = pci_alloc_consistent(tp->pdev,
  4129. TG3_HW_STATUS_SIZE,
  4130. &tp->status_mapping);
  4131. if (!tp->hw_status)
  4132. goto err_out;
  4133. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  4134. sizeof(struct tg3_hw_stats),
  4135. &tp->stats_mapping);
  4136. if (!tp->hw_stats)
  4137. goto err_out;
  4138. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  4139. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  4140. return 0;
  4141. err_out:
  4142. tg3_free_consistent(tp);
  4143. return -ENOMEM;
  4144. }
  4145. #define MAX_WAIT_CNT 1000
  4146. /* To stop a block, clear the enable bit and poll till it
  4147. * clears. tp->lock is held.
  4148. */
  4149. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  4150. {
  4151. unsigned int i;
  4152. u32 val;
  4153. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  4154. switch (ofs) {
  4155. case RCVLSC_MODE:
  4156. case DMAC_MODE:
  4157. case MBFREE_MODE:
  4158. case BUFMGR_MODE:
  4159. case MEMARB_MODE:
  4160. /* We can't enable/disable these bits of the
  4161. * 5705/5750, just say success.
  4162. */
  4163. return 0;
  4164. default:
  4165. break;
  4166. };
  4167. }
  4168. val = tr32(ofs);
  4169. val &= ~enable_bit;
  4170. tw32_f(ofs, val);
  4171. for (i = 0; i < MAX_WAIT_CNT; i++) {
  4172. udelay(100);
  4173. val = tr32(ofs);
  4174. if ((val & enable_bit) == 0)
  4175. break;
  4176. }
  4177. if (i == MAX_WAIT_CNT && !silent) {
  4178. printk(KERN_ERR PFX "tg3_stop_block timed out, "
  4179. "ofs=%lx enable_bit=%x\n",
  4180. ofs, enable_bit);
  4181. return -ENODEV;
  4182. }
  4183. return 0;
  4184. }
  4185. /* tp->lock is held. */
  4186. static int tg3_abort_hw(struct tg3 *tp, int silent)
  4187. {
  4188. int i, err;
  4189. tg3_disable_ints(tp);
  4190. tp->rx_mode &= ~RX_MODE_ENABLE;
  4191. tw32_f(MAC_RX_MODE, tp->rx_mode);
  4192. udelay(10);
  4193. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  4194. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  4195. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  4196. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  4197. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  4198. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  4199. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  4200. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  4201. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  4202. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  4203. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  4204. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  4205. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  4206. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  4207. tw32_f(MAC_MODE, tp->mac_mode);
  4208. udelay(40);
  4209. tp->tx_mode &= ~TX_MODE_ENABLE;
  4210. tw32_f(MAC_TX_MODE, tp->tx_mode);
  4211. for (i = 0; i < MAX_WAIT_CNT; i++) {
  4212. udelay(100);
  4213. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  4214. break;
  4215. }
  4216. if (i >= MAX_WAIT_CNT) {
  4217. printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  4218. "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  4219. tp->dev->name, tr32(MAC_TX_MODE));
  4220. err |= -ENODEV;
  4221. }
  4222. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  4223. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  4224. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  4225. tw32(FTQ_RESET, 0xffffffff);
  4226. tw32(FTQ_RESET, 0x00000000);
  4227. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  4228. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  4229. if (tp->hw_status)
  4230. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  4231. if (tp->hw_stats)
  4232. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  4233. return err;
  4234. }
  4235. /* tp->lock is held. */
  4236. static int tg3_nvram_lock(struct tg3 *tp)
  4237. {
  4238. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  4239. int i;
  4240. if (tp->nvram_lock_cnt == 0) {
  4241. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  4242. for (i = 0; i < 8000; i++) {
  4243. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  4244. break;
  4245. udelay(20);
  4246. }
  4247. if (i == 8000) {
  4248. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  4249. return -ENODEV;
  4250. }
  4251. }
  4252. tp->nvram_lock_cnt++;
  4253. }
  4254. return 0;
  4255. }
  4256. /* tp->lock is held. */
  4257. static void tg3_nvram_unlock(struct tg3 *tp)
  4258. {
  4259. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  4260. if (tp->nvram_lock_cnt > 0)
  4261. tp->nvram_lock_cnt--;
  4262. if (tp->nvram_lock_cnt == 0)
  4263. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  4264. }
  4265. }
  4266. /* tp->lock is held. */
  4267. static void tg3_enable_nvram_access(struct tg3 *tp)
  4268. {
  4269. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  4270. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  4271. u32 nvaccess = tr32(NVRAM_ACCESS);
  4272. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  4273. }
  4274. }
  4275. /* tp->lock is held. */
  4276. static void tg3_disable_nvram_access(struct tg3 *tp)
  4277. {
  4278. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  4279. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  4280. u32 nvaccess = tr32(NVRAM_ACCESS);
  4281. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  4282. }
  4283. }
  4284. static void tg3_ape_send_event(struct tg3 *tp, u32 event)
  4285. {
  4286. int i;
  4287. u32 apedata;
  4288. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  4289. if (apedata != APE_SEG_SIG_MAGIC)
  4290. return;
  4291. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  4292. if (apedata != APE_FW_STATUS_READY)
  4293. return;
  4294. /* Wait for up to 1 millisecond for APE to service previous event. */
  4295. for (i = 0; i < 10; i++) {
  4296. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  4297. return;
  4298. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  4299. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  4300. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  4301. event | APE_EVENT_STATUS_EVENT_PENDING);
  4302. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  4303. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  4304. break;
  4305. udelay(100);
  4306. }
  4307. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  4308. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  4309. }
  4310. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  4311. {
  4312. u32 event;
  4313. u32 apedata;
  4314. if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  4315. return;
  4316. switch (kind) {
  4317. case RESET_KIND_INIT:
  4318. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  4319. APE_HOST_SEG_SIG_MAGIC);
  4320. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  4321. APE_HOST_SEG_LEN_MAGIC);
  4322. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  4323. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  4324. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  4325. APE_HOST_DRIVER_ID_MAGIC);
  4326. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  4327. APE_HOST_BEHAV_NO_PHYLOCK);
  4328. event = APE_EVENT_STATUS_STATE_START;
  4329. break;
  4330. case RESET_KIND_SHUTDOWN:
  4331. event = APE_EVENT_STATUS_STATE_UNLOAD;
  4332. break;
  4333. case RESET_KIND_SUSPEND:
  4334. event = APE_EVENT_STATUS_STATE_SUSPEND;
  4335. break;
  4336. default:
  4337. return;
  4338. }
  4339. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  4340. tg3_ape_send_event(tp, event);
  4341. }
  4342. /* tp->lock is held. */
  4343. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  4344. {
  4345. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  4346. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  4347. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  4348. switch (kind) {
  4349. case RESET_KIND_INIT:
  4350. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4351. DRV_STATE_START);
  4352. break;
  4353. case RESET_KIND_SHUTDOWN:
  4354. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4355. DRV_STATE_UNLOAD);
  4356. break;
  4357. case RESET_KIND_SUSPEND:
  4358. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4359. DRV_STATE_SUSPEND);
  4360. break;
  4361. default:
  4362. break;
  4363. };
  4364. }
  4365. if (kind == RESET_KIND_INIT ||
  4366. kind == RESET_KIND_SUSPEND)
  4367. tg3_ape_driver_state_change(tp, kind);
  4368. }
  4369. /* tp->lock is held. */
  4370. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  4371. {
  4372. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  4373. switch (kind) {
  4374. case RESET_KIND_INIT:
  4375. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4376. DRV_STATE_START_DONE);
  4377. break;
  4378. case RESET_KIND_SHUTDOWN:
  4379. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4380. DRV_STATE_UNLOAD_DONE);
  4381. break;
  4382. default:
  4383. break;
  4384. };
  4385. }
  4386. if (kind == RESET_KIND_SHUTDOWN)
  4387. tg3_ape_driver_state_change(tp, kind);
  4388. }
  4389. /* tp->lock is held. */
  4390. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  4391. {
  4392. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4393. switch (kind) {
  4394. case RESET_KIND_INIT:
  4395. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4396. DRV_STATE_START);
  4397. break;
  4398. case RESET_KIND_SHUTDOWN:
  4399. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4400. DRV_STATE_UNLOAD);
  4401. break;
  4402. case RESET_KIND_SUSPEND:
  4403. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4404. DRV_STATE_SUSPEND);
  4405. break;
  4406. default:
  4407. break;
  4408. };
  4409. }
  4410. }
  4411. static int tg3_poll_fw(struct tg3 *tp)
  4412. {
  4413. int i;
  4414. u32 val;
  4415. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4416. /* Wait up to 20ms for init done. */
  4417. for (i = 0; i < 200; i++) {
  4418. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  4419. return 0;
  4420. udelay(100);
  4421. }
  4422. return -ENODEV;
  4423. }
  4424. /* Wait for firmware initialization to complete. */
  4425. for (i = 0; i < 100000; i++) {
  4426. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  4427. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  4428. break;
  4429. udelay(10);
  4430. }
  4431. /* Chip might not be fitted with firmware. Some Sun onboard
  4432. * parts are configured like that. So don't signal the timeout
  4433. * of the above loop as an error, but do report the lack of
  4434. * running firmware once.
  4435. */
  4436. if (i >= 100000 &&
  4437. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  4438. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  4439. printk(KERN_INFO PFX "%s: No firmware running.\n",
  4440. tp->dev->name);
  4441. }
  4442. return 0;
  4443. }
  4444. /* Save PCI command register before chip reset */
  4445. static void tg3_save_pci_state(struct tg3 *tp)
  4446. {
  4447. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  4448. }
  4449. /* Restore PCI state after chip reset */
  4450. static void tg3_restore_pci_state(struct tg3 *tp)
  4451. {
  4452. u32 val;
  4453. /* Re-enable indirect register accesses. */
  4454. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  4455. tp->misc_host_ctrl);
  4456. /* Set MAX PCI retry to zero. */
  4457. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  4458. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  4459. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  4460. val |= PCISTATE_RETRY_SAME_DMA;
  4461. /* Allow reads and writes to the APE register and memory space. */
  4462. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  4463. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  4464. PCISTATE_ALLOW_APE_SHMEM_WR;
  4465. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  4466. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  4467. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  4468. pcie_set_readrq(tp->pdev, 4096);
  4469. else {
  4470. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  4471. tp->pci_cacheline_sz);
  4472. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  4473. tp->pci_lat_timer);
  4474. }
  4475. /* Make sure PCI-X relaxed ordering bit is clear. */
  4476. if (tp->pcix_cap) {
  4477. u16 pcix_cmd;
  4478. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  4479. &pcix_cmd);
  4480. pcix_cmd &= ~PCI_X_CMD_ERO;
  4481. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  4482. pcix_cmd);
  4483. }
  4484. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4485. /* Chip reset on 5780 will reset MSI enable bit,
  4486. * so need to restore it.
  4487. */
  4488. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  4489. u16 ctrl;
  4490. pci_read_config_word(tp->pdev,
  4491. tp->msi_cap + PCI_MSI_FLAGS,
  4492. &ctrl);
  4493. pci_write_config_word(tp->pdev,
  4494. tp->msi_cap + PCI_MSI_FLAGS,
  4495. ctrl | PCI_MSI_FLAGS_ENABLE);
  4496. val = tr32(MSGINT_MODE);
  4497. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  4498. }
  4499. }
  4500. }
  4501. static void tg3_stop_fw(struct tg3 *);
  4502. /* tp->lock is held. */
  4503. static int tg3_chip_reset(struct tg3 *tp)
  4504. {
  4505. u32 val;
  4506. void (*write_op)(struct tg3 *, u32, u32);
  4507. int err;
  4508. tg3_nvram_lock(tp);
  4509. /* No matching tg3_nvram_unlock() after this because
  4510. * chip reset below will undo the nvram lock.
  4511. */
  4512. tp->nvram_lock_cnt = 0;
  4513. /* GRC_MISC_CFG core clock reset will clear the memory
  4514. * enable bit in PCI register 4 and the MSI enable bit
  4515. * on some chips, so we save relevant registers here.
  4516. */
  4517. tg3_save_pci_state(tp);
  4518. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  4519. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  4520. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  4521. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  4522. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  4523. tw32(GRC_FASTBOOT_PC, 0);
  4524. /*
  4525. * We must avoid the readl() that normally takes place.
  4526. * It locks machines, causes machine checks, and other
  4527. * fun things. So, temporarily disable the 5701
  4528. * hardware workaround, while we do the reset.
  4529. */
  4530. write_op = tp->write32;
  4531. if (write_op == tg3_write_flush_reg32)
  4532. tp->write32 = tg3_write32;
  4533. /* Prevent the irq handler from reading or writing PCI registers
  4534. * during chip reset when the memory enable bit in the PCI command
  4535. * register may be cleared. The chip does not generate interrupt
  4536. * at this time, but the irq handler may still be called due to irq
  4537. * sharing or irqpoll.
  4538. */
  4539. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  4540. if (tp->hw_status) {
  4541. tp->hw_status->status = 0;
  4542. tp->hw_status->status_tag = 0;
  4543. }
  4544. tp->last_tag = 0;
  4545. smp_mb();
  4546. synchronize_irq(tp->pdev->irq);
  4547. /* do the reset */
  4548. val = GRC_MISC_CFG_CORECLK_RESET;
  4549. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4550. if (tr32(0x7e2c) == 0x60) {
  4551. tw32(0x7e2c, 0x20);
  4552. }
  4553. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4554. tw32(GRC_MISC_CFG, (1 << 29));
  4555. val |= (1 << 29);
  4556. }
  4557. }
  4558. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4559. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  4560. tw32(GRC_VCPU_EXT_CTRL,
  4561. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  4562. }
  4563. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4564. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  4565. tw32(GRC_MISC_CFG, val);
  4566. /* restore 5701 hardware bug workaround write method */
  4567. tp->write32 = write_op;
  4568. /* Unfortunately, we have to delay before the PCI read back.
  4569. * Some 575X chips even will not respond to a PCI cfg access
  4570. * when the reset command is given to the chip.
  4571. *
  4572. * How do these hardware designers expect things to work
  4573. * properly if the PCI write is posted for a long period
  4574. * of time? It is always necessary to have some method by
  4575. * which a register read back can occur to push the write
  4576. * out which does the reset.
  4577. *
  4578. * For most tg3 variants the trick below was working.
  4579. * Ho hum...
  4580. */
  4581. udelay(120);
  4582. /* Flush PCI posted writes. The normal MMIO registers
  4583. * are inaccessible at this time so this is the only
  4584. * way to make this reliably (actually, this is no longer
  4585. * the case, see above). I tried to use indirect
  4586. * register read/write but this upset some 5701 variants.
  4587. */
  4588. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  4589. udelay(120);
  4590. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4591. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  4592. int i;
  4593. u32 cfg_val;
  4594. /* Wait for link training to complete. */
  4595. for (i = 0; i < 5000; i++)
  4596. udelay(100);
  4597. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  4598. pci_write_config_dword(tp->pdev, 0xc4,
  4599. cfg_val | (1 << 15));
  4600. }
  4601. /* Set PCIE max payload size and clear error status. */
  4602. pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
  4603. }
  4604. tg3_restore_pci_state(tp);
  4605. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  4606. val = 0;
  4607. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  4608. val = tr32(MEMARB_MODE);
  4609. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  4610. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  4611. tg3_stop_fw(tp);
  4612. tw32(0x5000, 0x400);
  4613. }
  4614. tw32(GRC_MODE, tp->grc_mode);
  4615. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  4616. val = tr32(0xc4);
  4617. tw32(0xc4, val | (1 << 15));
  4618. }
  4619. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  4620. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4621. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  4622. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  4623. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  4624. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  4625. }
  4626. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  4627. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  4628. tw32_f(MAC_MODE, tp->mac_mode);
  4629. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  4630. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  4631. tw32_f(MAC_MODE, tp->mac_mode);
  4632. } else
  4633. tw32_f(MAC_MODE, 0);
  4634. udelay(40);
  4635. err = tg3_poll_fw(tp);
  4636. if (err)
  4637. return err;
  4638. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  4639. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4640. val = tr32(0x7c00);
  4641. tw32(0x7c00, val | (1 << 25));
  4642. }
  4643. /* Reprobe ASF enable state. */
  4644. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  4645. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  4646. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  4647. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  4648. u32 nic_cfg;
  4649. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  4650. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  4651. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  4652. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  4653. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  4654. }
  4655. }
  4656. return 0;
  4657. }
  4658. /* tp->lock is held. */
  4659. static void tg3_stop_fw(struct tg3 *tp)
  4660. {
  4661. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
  4662. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  4663. u32 val;
  4664. /* Wait for RX cpu to ACK the previous event. */
  4665. tg3_wait_for_event_ack(tp);
  4666. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  4667. val = tr32(GRC_RX_CPU_EVENT);
  4668. val |= GRC_RX_CPU_DRIVER_EVENT;
  4669. tw32(GRC_RX_CPU_EVENT, val);
  4670. /* Wait for RX cpu to ACK this event. */
  4671. tg3_wait_for_event_ack(tp);
  4672. }
  4673. }
  4674. /* tp->lock is held. */
  4675. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  4676. {
  4677. int err;
  4678. tg3_stop_fw(tp);
  4679. tg3_write_sig_pre_reset(tp, kind);
  4680. tg3_abort_hw(tp, silent);
  4681. err = tg3_chip_reset(tp);
  4682. tg3_write_sig_legacy(tp, kind);
  4683. tg3_write_sig_post_reset(tp, kind);
  4684. if (err)
  4685. return err;
  4686. return 0;
  4687. }
  4688. #define TG3_FW_RELEASE_MAJOR 0x0
  4689. #define TG3_FW_RELASE_MINOR 0x0
  4690. #define TG3_FW_RELEASE_FIX 0x0
  4691. #define TG3_FW_START_ADDR 0x08000000
  4692. #define TG3_FW_TEXT_ADDR 0x08000000
  4693. #define TG3_FW_TEXT_LEN 0x9c0
  4694. #define TG3_FW_RODATA_ADDR 0x080009c0
  4695. #define TG3_FW_RODATA_LEN 0x60
  4696. #define TG3_FW_DATA_ADDR 0x08000a40
  4697. #define TG3_FW_DATA_LEN 0x20
  4698. #define TG3_FW_SBSS_ADDR 0x08000a60
  4699. #define TG3_FW_SBSS_LEN 0xc
  4700. #define TG3_FW_BSS_ADDR 0x08000a70
  4701. #define TG3_FW_BSS_LEN 0x10
  4702. static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
  4703. 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  4704. 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
  4705. 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
  4706. 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
  4707. 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
  4708. 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
  4709. 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
  4710. 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
  4711. 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
  4712. 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
  4713. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
  4714. 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
  4715. 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  4716. 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
  4717. 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
  4718. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  4719. 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
  4720. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
  4721. 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
  4722. 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  4723. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
  4724. 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
  4725. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  4726. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4727. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4728. 0, 0, 0, 0, 0, 0,
  4729. 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
  4730. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4731. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4732. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4733. 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
  4734. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
  4735. 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
  4736. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
  4737. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4738. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4739. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
  4740. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4741. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4742. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4743. 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
  4744. 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
  4745. 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
  4746. 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
  4747. 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
  4748. 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
  4749. 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
  4750. 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
  4751. 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
  4752. 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
  4753. 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
  4754. 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
  4755. 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
  4756. 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
  4757. 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
  4758. 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
  4759. 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
  4760. 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
  4761. 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
  4762. 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
  4763. 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
  4764. 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
  4765. 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
  4766. 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
  4767. 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
  4768. 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
  4769. 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
  4770. 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
  4771. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
  4772. 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
  4773. 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
  4774. 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
  4775. 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
  4776. 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
  4777. 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
  4778. 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
  4779. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
  4780. 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
  4781. 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
  4782. 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
  4783. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
  4784. 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
  4785. 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
  4786. 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
  4787. 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
  4788. 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
  4789. 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
  4790. 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
  4791. 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
  4792. 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
  4793. 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
  4794. };
  4795. static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
  4796. 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
  4797. 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
  4798. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  4799. 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
  4800. 0x00000000
  4801. };
  4802. #if 0 /* All zeros, don't eat up space with it. */
  4803. u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  4804. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4805. 0x00000000, 0x00000000, 0x00000000, 0x00000000
  4806. };
  4807. #endif
  4808. #define RX_CPU_SCRATCH_BASE 0x30000
  4809. #define RX_CPU_SCRATCH_SIZE 0x04000
  4810. #define TX_CPU_SCRATCH_BASE 0x34000
  4811. #define TX_CPU_SCRATCH_SIZE 0x04000
  4812. /* tp->lock is held. */
  4813. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  4814. {
  4815. int i;
  4816. BUG_ON(offset == TX_CPU_BASE &&
  4817. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  4818. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4819. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  4820. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  4821. return 0;
  4822. }
  4823. if (offset == RX_CPU_BASE) {
  4824. for (i = 0; i < 10000; i++) {
  4825. tw32(offset + CPU_STATE, 0xffffffff);
  4826. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4827. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4828. break;
  4829. }
  4830. tw32(offset + CPU_STATE, 0xffffffff);
  4831. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  4832. udelay(10);
  4833. } else {
  4834. for (i = 0; i < 10000; i++) {
  4835. tw32(offset + CPU_STATE, 0xffffffff);
  4836. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4837. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4838. break;
  4839. }
  4840. }
  4841. if (i >= 10000) {
  4842. printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  4843. "and %s CPU\n",
  4844. tp->dev->name,
  4845. (offset == RX_CPU_BASE ? "RX" : "TX"));
  4846. return -ENODEV;
  4847. }
  4848. /* Clear firmware's nvram arbitration. */
  4849. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  4850. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  4851. return 0;
  4852. }
  4853. struct fw_info {
  4854. unsigned int text_base;
  4855. unsigned int text_len;
  4856. const u32 *text_data;
  4857. unsigned int rodata_base;
  4858. unsigned int rodata_len;
  4859. const u32 *rodata_data;
  4860. unsigned int data_base;
  4861. unsigned int data_len;
  4862. const u32 *data_data;
  4863. };
  4864. /* tp->lock is held. */
  4865. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  4866. int cpu_scratch_size, struct fw_info *info)
  4867. {
  4868. int err, lock_err, i;
  4869. void (*write_op)(struct tg3 *, u32, u32);
  4870. if (cpu_base == TX_CPU_BASE &&
  4871. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  4872. printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  4873. "TX cpu firmware on %s which is 5705.\n",
  4874. tp->dev->name);
  4875. return -EINVAL;
  4876. }
  4877. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4878. write_op = tg3_write_mem;
  4879. else
  4880. write_op = tg3_write_indirect_reg32;
  4881. /* It is possible that bootcode is still loading at this point.
  4882. * Get the nvram lock first before halting the cpu.
  4883. */
  4884. lock_err = tg3_nvram_lock(tp);
  4885. err = tg3_halt_cpu(tp, cpu_base);
  4886. if (!lock_err)
  4887. tg3_nvram_unlock(tp);
  4888. if (err)
  4889. goto out;
  4890. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  4891. write_op(tp, cpu_scratch_base + i, 0);
  4892. tw32(cpu_base + CPU_STATE, 0xffffffff);
  4893. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  4894. for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  4895. write_op(tp, (cpu_scratch_base +
  4896. (info->text_base & 0xffff) +
  4897. (i * sizeof(u32))),
  4898. (info->text_data ?
  4899. info->text_data[i] : 0));
  4900. for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  4901. write_op(tp, (cpu_scratch_base +
  4902. (info->rodata_base & 0xffff) +
  4903. (i * sizeof(u32))),
  4904. (info->rodata_data ?
  4905. info->rodata_data[i] : 0));
  4906. for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  4907. write_op(tp, (cpu_scratch_base +
  4908. (info->data_base & 0xffff) +
  4909. (i * sizeof(u32))),
  4910. (info->data_data ?
  4911. info->data_data[i] : 0));
  4912. err = 0;
  4913. out:
  4914. return err;
  4915. }
  4916. /* tp->lock is held. */
  4917. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  4918. {
  4919. struct fw_info info;
  4920. int err, i;
  4921. info.text_base = TG3_FW_TEXT_ADDR;
  4922. info.text_len = TG3_FW_TEXT_LEN;
  4923. info.text_data = &tg3FwText[0];
  4924. info.rodata_base = TG3_FW_RODATA_ADDR;
  4925. info.rodata_len = TG3_FW_RODATA_LEN;
  4926. info.rodata_data = &tg3FwRodata[0];
  4927. info.data_base = TG3_FW_DATA_ADDR;
  4928. info.data_len = TG3_FW_DATA_LEN;
  4929. info.data_data = NULL;
  4930. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  4931. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  4932. &info);
  4933. if (err)
  4934. return err;
  4935. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  4936. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  4937. &info);
  4938. if (err)
  4939. return err;
  4940. /* Now startup only the RX cpu. */
  4941. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4942. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4943. for (i = 0; i < 5; i++) {
  4944. if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
  4945. break;
  4946. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4947. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  4948. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4949. udelay(1000);
  4950. }
  4951. if (i >= 5) {
  4952. printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  4953. "to set RX CPU PC, is %08x should be %08x\n",
  4954. tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  4955. TG3_FW_TEXT_ADDR);
  4956. return -ENODEV;
  4957. }
  4958. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4959. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  4960. return 0;
  4961. }
  4962. #define TG3_TSO_FW_RELEASE_MAJOR 0x1
  4963. #define TG3_TSO_FW_RELASE_MINOR 0x6
  4964. #define TG3_TSO_FW_RELEASE_FIX 0x0
  4965. #define TG3_TSO_FW_START_ADDR 0x08000000
  4966. #define TG3_TSO_FW_TEXT_ADDR 0x08000000
  4967. #define TG3_TSO_FW_TEXT_LEN 0x1aa0
  4968. #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
  4969. #define TG3_TSO_FW_RODATA_LEN 0x60
  4970. #define TG3_TSO_FW_DATA_ADDR 0x08001b20
  4971. #define TG3_TSO_FW_DATA_LEN 0x30
  4972. #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
  4973. #define TG3_TSO_FW_SBSS_LEN 0x2c
  4974. #define TG3_TSO_FW_BSS_ADDR 0x08001b80
  4975. #define TG3_TSO_FW_BSS_LEN 0x894
  4976. static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
  4977. 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
  4978. 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
  4979. 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4980. 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
  4981. 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
  4982. 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
  4983. 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
  4984. 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
  4985. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
  4986. 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
  4987. 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
  4988. 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
  4989. 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
  4990. 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
  4991. 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
  4992. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
  4993. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
  4994. 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
  4995. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4996. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
  4997. 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
  4998. 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
  4999. 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
  5000. 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
  5001. 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
  5002. 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
  5003. 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
  5004. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
  5005. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
  5006. 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5007. 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  5008. 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
  5009. 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
  5010. 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
  5011. 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
  5012. 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
  5013. 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
  5014. 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
  5015. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  5016. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
  5017. 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
  5018. 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
  5019. 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
  5020. 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
  5021. 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
  5022. 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
  5023. 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
  5024. 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  5025. 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
  5026. 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  5027. 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
  5028. 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
  5029. 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
  5030. 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
  5031. 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
  5032. 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
  5033. 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
  5034. 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
  5035. 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
  5036. 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
  5037. 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
  5038. 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
  5039. 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
  5040. 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
  5041. 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
  5042. 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
  5043. 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
  5044. 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
  5045. 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
  5046. 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
  5047. 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
  5048. 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
  5049. 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
  5050. 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
  5051. 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
  5052. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
  5053. 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
  5054. 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
  5055. 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
  5056. 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
  5057. 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
  5058. 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
  5059. 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
  5060. 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
  5061. 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
  5062. 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
  5063. 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
  5064. 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
  5065. 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
  5066. 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
  5067. 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
  5068. 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
  5069. 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
  5070. 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
  5071. 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
  5072. 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
  5073. 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
  5074. 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
  5075. 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
  5076. 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
  5077. 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
  5078. 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
  5079. 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
  5080. 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
  5081. 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
  5082. 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
  5083. 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
  5084. 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
  5085. 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
  5086. 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
  5087. 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
  5088. 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
  5089. 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
  5090. 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
  5091. 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
  5092. 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
  5093. 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
  5094. 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
  5095. 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
  5096. 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
  5097. 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
  5098. 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
  5099. 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
  5100. 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
  5101. 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
  5102. 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
  5103. 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
  5104. 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
  5105. 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
  5106. 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
  5107. 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
  5108. 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
  5109. 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
  5110. 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  5111. 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
  5112. 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
  5113. 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
  5114. 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
  5115. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  5116. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
  5117. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
  5118. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
  5119. 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
  5120. 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
  5121. 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
  5122. 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
  5123. 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
  5124. 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
  5125. 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
  5126. 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
  5127. 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
  5128. 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
  5129. 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
  5130. 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
  5131. 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
  5132. 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
  5133. 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
  5134. 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
  5135. 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
  5136. 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
  5137. 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
  5138. 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
  5139. 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
  5140. 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
  5141. 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
  5142. 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
  5143. 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
  5144. 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
  5145. 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
  5146. 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
  5147. 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
  5148. 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
  5149. 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
  5150. 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
  5151. 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
  5152. 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
  5153. 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
  5154. 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
  5155. 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
  5156. 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
  5157. 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
  5158. 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
  5159. 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
  5160. 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
  5161. 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
  5162. 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
  5163. 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
  5164. 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
  5165. 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
  5166. 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
  5167. 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
  5168. 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
  5169. 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
  5170. 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
  5171. 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
  5172. 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
  5173. 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
  5174. 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
  5175. 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
  5176. 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
  5177. 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
  5178. 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
  5179. 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
  5180. 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
  5181. 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
  5182. 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
  5183. 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
  5184. 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
  5185. 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
  5186. 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
  5187. 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
  5188. 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
  5189. 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
  5190. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
  5191. 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
  5192. 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
  5193. 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
  5194. 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
  5195. 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
  5196. 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
  5197. 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  5198. 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
  5199. 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
  5200. 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
  5201. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
  5202. 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
  5203. 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
  5204. 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
  5205. 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
  5206. 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
  5207. 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
  5208. 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
  5209. 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
  5210. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
  5211. 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
  5212. 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
  5213. 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
  5214. 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  5215. 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
  5216. 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
  5217. 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  5218. 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  5219. 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  5220. 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  5221. 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
  5222. 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
  5223. 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  5224. 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
  5225. 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  5226. 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
  5227. 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
  5228. 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
  5229. 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
  5230. 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
  5231. 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
  5232. 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
  5233. 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
  5234. 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
  5235. 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
  5236. 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
  5237. 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
  5238. 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
  5239. 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
  5240. 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
  5241. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  5242. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
  5243. 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
  5244. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
  5245. 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
  5246. 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
  5247. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
  5248. 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
  5249. 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  5250. 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
  5251. 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
  5252. 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
  5253. 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
  5254. 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
  5255. 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
  5256. 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
  5257. 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
  5258. 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
  5259. 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
  5260. 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
  5261. };
  5262. static const u32 tg3TsoFwRodata[] = {
  5263. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5264. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
  5265. 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
  5266. 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
  5267. 0x00000000,
  5268. };
  5269. static const u32 tg3TsoFwData[] = {
  5270. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
  5271. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  5272. 0x00000000,
  5273. };
  5274. /* 5705 needs a special version of the TSO firmware. */
  5275. #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
  5276. #define TG3_TSO5_FW_RELASE_MINOR 0x2
  5277. #define TG3_TSO5_FW_RELEASE_FIX 0x0
  5278. #define TG3_TSO5_FW_START_ADDR 0x00010000
  5279. #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
  5280. #define TG3_TSO5_FW_TEXT_LEN 0xe90
  5281. #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
  5282. #define TG3_TSO5_FW_RODATA_LEN 0x50
  5283. #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
  5284. #define TG3_TSO5_FW_DATA_LEN 0x20
  5285. #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
  5286. #define TG3_TSO5_FW_SBSS_LEN 0x28
  5287. #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
  5288. #define TG3_TSO5_FW_BSS_LEN 0x88
  5289. static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
  5290. 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
  5291. 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
  5292. 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  5293. 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
  5294. 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
  5295. 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
  5296. 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5297. 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
  5298. 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
  5299. 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
  5300. 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
  5301. 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
  5302. 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
  5303. 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
  5304. 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
  5305. 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
  5306. 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
  5307. 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
  5308. 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
  5309. 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
  5310. 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
  5311. 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
  5312. 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
  5313. 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
  5314. 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
  5315. 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
  5316. 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
  5317. 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
  5318. 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
  5319. 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
  5320. 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  5321. 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
  5322. 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
  5323. 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
  5324. 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
  5325. 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
  5326. 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
  5327. 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
  5328. 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
  5329. 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
  5330. 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
  5331. 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
  5332. 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
  5333. 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
  5334. 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
  5335. 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
  5336. 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
  5337. 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
  5338. 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
  5339. 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
  5340. 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
  5341. 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
  5342. 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
  5343. 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
  5344. 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
  5345. 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
  5346. 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
  5347. 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
  5348. 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
  5349. 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
  5350. 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
  5351. 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
  5352. 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
  5353. 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
  5354. 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
  5355. 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
  5356. 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  5357. 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
  5358. 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
  5359. 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
  5360. 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
  5361. 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
  5362. 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
  5363. 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
  5364. 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
  5365. 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
  5366. 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
  5367. 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
  5368. 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
  5369. 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
  5370. 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
  5371. 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
  5372. 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
  5373. 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
  5374. 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
  5375. 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
  5376. 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
  5377. 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
  5378. 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
  5379. 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
  5380. 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
  5381. 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
  5382. 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
  5383. 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
  5384. 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
  5385. 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
  5386. 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
  5387. 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
  5388. 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
  5389. 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
  5390. 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
  5391. 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
  5392. 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
  5393. 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
  5394. 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
  5395. 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
  5396. 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5397. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5398. 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
  5399. 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
  5400. 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
  5401. 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
  5402. 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
  5403. 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
  5404. 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
  5405. 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
  5406. 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
  5407. 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5408. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5409. 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
  5410. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
  5411. 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  5412. 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
  5413. 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5414. 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
  5415. 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
  5416. 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
  5417. 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
  5418. 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
  5419. 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
  5420. 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
  5421. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
  5422. 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
  5423. 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
  5424. 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
  5425. 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
  5426. 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
  5427. 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
  5428. 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
  5429. 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
  5430. 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
  5431. 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
  5432. 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
  5433. 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
  5434. 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
  5435. 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
  5436. 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
  5437. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  5438. 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
  5439. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
  5440. 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
  5441. 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  5442. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
  5443. 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  5444. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  5445. 0x00000000, 0x00000000, 0x00000000,
  5446. };
  5447. static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
  5448. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5449. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
  5450. 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  5451. 0x00000000, 0x00000000, 0x00000000,
  5452. };
  5453. static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
  5454. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
  5455. 0x00000000, 0x00000000, 0x00000000,
  5456. };
  5457. /* tp->lock is held. */
  5458. static int tg3_load_tso_firmware(struct tg3 *tp)
  5459. {
  5460. struct fw_info info;
  5461. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  5462. int err, i;
  5463. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5464. return 0;
  5465. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5466. info.text_base = TG3_TSO5_FW_TEXT_ADDR;
  5467. info.text_len = TG3_TSO5_FW_TEXT_LEN;
  5468. info.text_data = &tg3Tso5FwText[0];
  5469. info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
  5470. info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
  5471. info.rodata_data = &tg3Tso5FwRodata[0];
  5472. info.data_base = TG3_TSO5_FW_DATA_ADDR;
  5473. info.data_len = TG3_TSO5_FW_DATA_LEN;
  5474. info.data_data = &tg3Tso5FwData[0];
  5475. cpu_base = RX_CPU_BASE;
  5476. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  5477. cpu_scratch_size = (info.text_len +
  5478. info.rodata_len +
  5479. info.data_len +
  5480. TG3_TSO5_FW_SBSS_LEN +
  5481. TG3_TSO5_FW_BSS_LEN);
  5482. } else {
  5483. info.text_base = TG3_TSO_FW_TEXT_ADDR;
  5484. info.text_len = TG3_TSO_FW_TEXT_LEN;
  5485. info.text_data = &tg3TsoFwText[0];
  5486. info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  5487. info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  5488. info.rodata_data = &tg3TsoFwRodata[0];
  5489. info.data_base = TG3_TSO_FW_DATA_ADDR;
  5490. info.data_len = TG3_TSO_FW_DATA_LEN;
  5491. info.data_data = &tg3TsoFwData[0];
  5492. cpu_base = TX_CPU_BASE;
  5493. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  5494. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  5495. }
  5496. err = tg3_load_firmware_cpu(tp, cpu_base,
  5497. cpu_scratch_base, cpu_scratch_size,
  5498. &info);
  5499. if (err)
  5500. return err;
  5501. /* Now startup the cpu. */
  5502. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5503. tw32_f(cpu_base + CPU_PC, info.text_base);
  5504. for (i = 0; i < 5; i++) {
  5505. if (tr32(cpu_base + CPU_PC) == info.text_base)
  5506. break;
  5507. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5508. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  5509. tw32_f(cpu_base + CPU_PC, info.text_base);
  5510. udelay(1000);
  5511. }
  5512. if (i >= 5) {
  5513. printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  5514. "to set CPU PC, is %08x should be %08x\n",
  5515. tp->dev->name, tr32(cpu_base + CPU_PC),
  5516. info.text_base);
  5517. return -ENODEV;
  5518. }
  5519. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5520. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  5521. return 0;
  5522. }
  5523. /* tp->lock is held. */
  5524. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  5525. {
  5526. u32 addr_high, addr_low;
  5527. int i;
  5528. addr_high = ((tp->dev->dev_addr[0] << 8) |
  5529. tp->dev->dev_addr[1]);
  5530. addr_low = ((tp->dev->dev_addr[2] << 24) |
  5531. (tp->dev->dev_addr[3] << 16) |
  5532. (tp->dev->dev_addr[4] << 8) |
  5533. (tp->dev->dev_addr[5] << 0));
  5534. for (i = 0; i < 4; i++) {
  5535. if (i == 1 && skip_mac_1)
  5536. continue;
  5537. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  5538. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  5539. }
  5540. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  5541. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5542. for (i = 0; i < 12; i++) {
  5543. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  5544. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  5545. }
  5546. }
  5547. addr_high = (tp->dev->dev_addr[0] +
  5548. tp->dev->dev_addr[1] +
  5549. tp->dev->dev_addr[2] +
  5550. tp->dev->dev_addr[3] +
  5551. tp->dev->dev_addr[4] +
  5552. tp->dev->dev_addr[5]) &
  5553. TX_BACKOFF_SEED_MASK;
  5554. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  5555. }
  5556. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  5557. {
  5558. struct tg3 *tp = netdev_priv(dev);
  5559. struct sockaddr *addr = p;
  5560. int err = 0, skip_mac_1 = 0;
  5561. if (!is_valid_ether_addr(addr->sa_data))
  5562. return -EINVAL;
  5563. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  5564. if (!netif_running(dev))
  5565. return 0;
  5566. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5567. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  5568. addr0_high = tr32(MAC_ADDR_0_HIGH);
  5569. addr0_low = tr32(MAC_ADDR_0_LOW);
  5570. addr1_high = tr32(MAC_ADDR_1_HIGH);
  5571. addr1_low = tr32(MAC_ADDR_1_LOW);
  5572. /* Skip MAC addr 1 if ASF is using it. */
  5573. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  5574. !(addr1_high == 0 && addr1_low == 0))
  5575. skip_mac_1 = 1;
  5576. }
  5577. spin_lock_bh(&tp->lock);
  5578. __tg3_set_mac_addr(tp, skip_mac_1);
  5579. spin_unlock_bh(&tp->lock);
  5580. return err;
  5581. }
  5582. /* tp->lock is held. */
  5583. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  5584. dma_addr_t mapping, u32 maxlen_flags,
  5585. u32 nic_addr)
  5586. {
  5587. tg3_write_mem(tp,
  5588. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  5589. ((u64) mapping >> 32));
  5590. tg3_write_mem(tp,
  5591. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  5592. ((u64) mapping & 0xffffffff));
  5593. tg3_write_mem(tp,
  5594. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  5595. maxlen_flags);
  5596. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5597. tg3_write_mem(tp,
  5598. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  5599. nic_addr);
  5600. }
  5601. static void __tg3_set_rx_mode(struct net_device *);
  5602. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  5603. {
  5604. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  5605. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  5606. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  5607. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  5608. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5609. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  5610. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  5611. }
  5612. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  5613. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  5614. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5615. u32 val = ec->stats_block_coalesce_usecs;
  5616. if (!netif_carrier_ok(tp->dev))
  5617. val = 0;
  5618. tw32(HOSTCC_STAT_COAL_TICKS, val);
  5619. }
  5620. }
  5621. /* tp->lock is held. */
  5622. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  5623. {
  5624. u32 val, rdmac_mode;
  5625. int i, err, limit;
  5626. tg3_disable_ints(tp);
  5627. tg3_stop_fw(tp);
  5628. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  5629. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  5630. tg3_abort_hw(tp, 1);
  5631. }
  5632. if (reset_phy)
  5633. tg3_phy_reset(tp);
  5634. err = tg3_chip_reset(tp);
  5635. if (err)
  5636. return err;
  5637. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  5638. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
  5639. tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
  5640. val = tr32(TG3_CPMU_CTRL);
  5641. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  5642. tw32(TG3_CPMU_CTRL, val);
  5643. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  5644. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  5645. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  5646. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  5647. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  5648. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  5649. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  5650. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  5651. val = tr32(TG3_CPMU_HST_ACC);
  5652. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  5653. val |= CPMU_HST_ACC_MACCLK_6_25;
  5654. tw32(TG3_CPMU_HST_ACC, val);
  5655. }
  5656. /* This works around an issue with Athlon chipsets on
  5657. * B3 tigon3 silicon. This bit has no effect on any
  5658. * other revision. But do not set this on PCI Express
  5659. * chips and don't even touch the clocks if the CPMU is present.
  5660. */
  5661. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
  5662. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  5663. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  5664. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  5665. }
  5666. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  5667. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  5668. val = tr32(TG3PCI_PCISTATE);
  5669. val |= PCISTATE_RETRY_SAME_DMA;
  5670. tw32(TG3PCI_PCISTATE, val);
  5671. }
  5672. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  5673. /* Allow reads and writes to the
  5674. * APE register and memory space.
  5675. */
  5676. val = tr32(TG3PCI_PCISTATE);
  5677. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  5678. PCISTATE_ALLOW_APE_SHMEM_WR;
  5679. tw32(TG3PCI_PCISTATE, val);
  5680. }
  5681. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  5682. /* Enable some hw fixes. */
  5683. val = tr32(TG3PCI_MSI_DATA);
  5684. val |= (1 << 26) | (1 << 28) | (1 << 29);
  5685. tw32(TG3PCI_MSI_DATA, val);
  5686. }
  5687. /* Descriptor ring init may make accesses to the
  5688. * NIC SRAM area to setup the TX descriptors, so we
  5689. * can only do this after the hardware has been
  5690. * successfully reset.
  5691. */
  5692. err = tg3_init_rings(tp);
  5693. if (err)
  5694. return err;
  5695. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  5696. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
  5697. /* This value is determined during the probe time DMA
  5698. * engine test, tg3_test_dma.
  5699. */
  5700. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  5701. }
  5702. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  5703. GRC_MODE_4X_NIC_SEND_RINGS |
  5704. GRC_MODE_NO_TX_PHDR_CSUM |
  5705. GRC_MODE_NO_RX_PHDR_CSUM);
  5706. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  5707. /* Pseudo-header checksum is done by hardware logic and not
  5708. * the offload processers, so make the chip do the pseudo-
  5709. * header checksums on receive. For transmit it is more
  5710. * convenient to do the pseudo-header checksum in software
  5711. * as Linux does that on transmit for us in all cases.
  5712. */
  5713. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  5714. tw32(GRC_MODE,
  5715. tp->grc_mode |
  5716. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  5717. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  5718. val = tr32(GRC_MISC_CFG);
  5719. val &= ~0xff;
  5720. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  5721. tw32(GRC_MISC_CFG, val);
  5722. /* Initialize MBUF/DESC pool. */
  5723. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5724. /* Do nothing. */
  5725. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  5726. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  5727. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  5728. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  5729. else
  5730. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  5731. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  5732. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  5733. }
  5734. else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5735. int fw_len;
  5736. fw_len = (TG3_TSO5_FW_TEXT_LEN +
  5737. TG3_TSO5_FW_RODATA_LEN +
  5738. TG3_TSO5_FW_DATA_LEN +
  5739. TG3_TSO5_FW_SBSS_LEN +
  5740. TG3_TSO5_FW_BSS_LEN);
  5741. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  5742. tw32(BUFMGR_MB_POOL_ADDR,
  5743. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  5744. tw32(BUFMGR_MB_POOL_SIZE,
  5745. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  5746. }
  5747. if (tp->dev->mtu <= ETH_DATA_LEN) {
  5748. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5749. tp->bufmgr_config.mbuf_read_dma_low_water);
  5750. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5751. tp->bufmgr_config.mbuf_mac_rx_low_water);
  5752. tw32(BUFMGR_MB_HIGH_WATER,
  5753. tp->bufmgr_config.mbuf_high_water);
  5754. } else {
  5755. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5756. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  5757. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5758. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  5759. tw32(BUFMGR_MB_HIGH_WATER,
  5760. tp->bufmgr_config.mbuf_high_water_jumbo);
  5761. }
  5762. tw32(BUFMGR_DMA_LOW_WATER,
  5763. tp->bufmgr_config.dma_low_water);
  5764. tw32(BUFMGR_DMA_HIGH_WATER,
  5765. tp->bufmgr_config.dma_high_water);
  5766. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  5767. for (i = 0; i < 2000; i++) {
  5768. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  5769. break;
  5770. udelay(10);
  5771. }
  5772. if (i >= 2000) {
  5773. printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  5774. tp->dev->name);
  5775. return -ENODEV;
  5776. }
  5777. /* Setup replenish threshold. */
  5778. val = tp->rx_pending / 8;
  5779. if (val == 0)
  5780. val = 1;
  5781. else if (val > tp->rx_std_max_post)
  5782. val = tp->rx_std_max_post;
  5783. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5784. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  5785. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  5786. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  5787. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  5788. }
  5789. tw32(RCVBDI_STD_THRESH, val);
  5790. /* Initialize TG3_BDINFO's at:
  5791. * RCVDBDI_STD_BD: standard eth size rx ring
  5792. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  5793. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  5794. *
  5795. * like so:
  5796. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  5797. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  5798. * ring attribute flags
  5799. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  5800. *
  5801. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  5802. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  5803. *
  5804. * The size of each ring is fixed in the firmware, but the location is
  5805. * configurable.
  5806. */
  5807. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5808. ((u64) tp->rx_std_mapping >> 32));
  5809. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5810. ((u64) tp->rx_std_mapping & 0xffffffff));
  5811. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  5812. NIC_SRAM_RX_BUFFER_DESC);
  5813. /* Don't even try to program the JUMBO/MINI buffer descriptor
  5814. * configs on 5705.
  5815. */
  5816. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  5817. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5818. RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
  5819. } else {
  5820. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5821. RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5822. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5823. BDINFO_FLAGS_DISABLED);
  5824. /* Setup replenish threshold. */
  5825. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  5826. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  5827. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5828. ((u64) tp->rx_jumbo_mapping >> 32));
  5829. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5830. ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  5831. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5832. RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5833. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  5834. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  5835. } else {
  5836. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5837. BDINFO_FLAGS_DISABLED);
  5838. }
  5839. }
  5840. /* There is only one send ring on 5705/5750, no need to explicitly
  5841. * disable the others.
  5842. */
  5843. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5844. /* Clear out send RCB ring in SRAM. */
  5845. for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  5846. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5847. BDINFO_FLAGS_DISABLED);
  5848. }
  5849. tp->tx_prod = 0;
  5850. tp->tx_cons = 0;
  5851. tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5852. tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5853. tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  5854. tp->tx_desc_mapping,
  5855. (TG3_TX_RING_SIZE <<
  5856. BDINFO_FLAGS_MAXLEN_SHIFT),
  5857. NIC_SRAM_TX_BUFFER_DESC);
  5858. /* There is only one receive return ring on 5705/5750, no need
  5859. * to explicitly disable the others.
  5860. */
  5861. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5862. for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
  5863. i += TG3_BDINFO_SIZE) {
  5864. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5865. BDINFO_FLAGS_DISABLED);
  5866. }
  5867. }
  5868. tp->rx_rcb_ptr = 0;
  5869. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5870. tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  5871. tp->rx_rcb_mapping,
  5872. (TG3_RX_RCB_RING_SIZE(tp) <<
  5873. BDINFO_FLAGS_MAXLEN_SHIFT),
  5874. 0);
  5875. tp->rx_std_ptr = tp->rx_pending;
  5876. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  5877. tp->rx_std_ptr);
  5878. tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  5879. tp->rx_jumbo_pending : 0;
  5880. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  5881. tp->rx_jumbo_ptr);
  5882. /* Initialize MAC address and backoff seed. */
  5883. __tg3_set_mac_addr(tp, 0);
  5884. /* MTU + ethernet header + FCS + optional VLAN tag */
  5885. tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
  5886. /* The slot time is changed by tg3_setup_phy if we
  5887. * run at gigabit with half duplex.
  5888. */
  5889. tw32(MAC_TX_LENGTHS,
  5890. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  5891. (6 << TX_LENGTHS_IPG_SHIFT) |
  5892. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  5893. /* Receive rules. */
  5894. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  5895. tw32(RCVLPC_CONFIG, 0x0181);
  5896. /* Calculate RDMAC_MODE setting early, we need it to determine
  5897. * the RCVLPC_STATE_ENABLE mask.
  5898. */
  5899. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  5900. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  5901. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  5902. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  5903. RDMAC_MODE_LNGREAD_ENAB);
  5904. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  5905. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  5906. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  5907. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  5908. /* If statement applies to 5705 and 5750 PCI devices only */
  5909. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5910. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5911. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  5912. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  5913. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5914. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  5915. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5916. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  5917. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5918. }
  5919. }
  5920. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  5921. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5922. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5923. rdmac_mode |= (1 << 27);
  5924. /* Receive/send statistics. */
  5925. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5926. val = tr32(RCVLPC_STATS_ENABLE);
  5927. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  5928. tw32(RCVLPC_STATS_ENABLE, val);
  5929. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  5930. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  5931. val = tr32(RCVLPC_STATS_ENABLE);
  5932. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  5933. tw32(RCVLPC_STATS_ENABLE, val);
  5934. } else {
  5935. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  5936. }
  5937. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  5938. tw32(SNDDATAI_STATSENAB, 0xffffff);
  5939. tw32(SNDDATAI_STATSCTRL,
  5940. (SNDDATAI_SCTRL_ENABLE |
  5941. SNDDATAI_SCTRL_FASTUPD));
  5942. /* Setup host coalescing engine. */
  5943. tw32(HOSTCC_MODE, 0);
  5944. for (i = 0; i < 2000; i++) {
  5945. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  5946. break;
  5947. udelay(10);
  5948. }
  5949. __tg3_set_coalesce(tp, &tp->coal);
  5950. /* set status block DMA address */
  5951. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5952. ((u64) tp->status_mapping >> 32));
  5953. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5954. ((u64) tp->status_mapping & 0xffffffff));
  5955. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5956. /* Status/statistics block address. See tg3_timer,
  5957. * the tg3_periodic_fetch_stats call there, and
  5958. * tg3_get_stats to see how this works for 5705/5750 chips.
  5959. */
  5960. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5961. ((u64) tp->stats_mapping >> 32));
  5962. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5963. ((u64) tp->stats_mapping & 0xffffffff));
  5964. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  5965. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  5966. }
  5967. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  5968. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  5969. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  5970. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5971. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  5972. /* Clear statistics/status block in chip, and status block in ram. */
  5973. for (i = NIC_SRAM_STATS_BLK;
  5974. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  5975. i += sizeof(u32)) {
  5976. tg3_write_mem(tp, i, 0);
  5977. udelay(40);
  5978. }
  5979. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  5980. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  5981. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  5982. /* reset to prevent losing 1st rx packet intermittently */
  5983. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5984. udelay(10);
  5985. }
  5986. tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  5987. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  5988. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5989. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  5990. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  5991. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  5992. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  5993. udelay(40);
  5994. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  5995. * If TG3_FLG2_IS_NIC is zero, we should read the
  5996. * register to preserve the GPIO settings for LOMs. The GPIOs,
  5997. * whether used as inputs or outputs, are set by boot code after
  5998. * reset.
  5999. */
  6000. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  6001. u32 gpio_mask;
  6002. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  6003. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  6004. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  6005. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  6006. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  6007. GRC_LCLCTRL_GPIO_OUTPUT3;
  6008. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  6009. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  6010. tp->grc_local_ctrl &= ~gpio_mask;
  6011. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  6012. /* GPIO1 must be driven high for eeprom write protect */
  6013. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  6014. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  6015. GRC_LCLCTRL_GPIO_OUTPUT1);
  6016. }
  6017. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6018. udelay(100);
  6019. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  6020. tp->last_tag = 0;
  6021. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  6022. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  6023. udelay(40);
  6024. }
  6025. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  6026. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  6027. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  6028. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  6029. WDMAC_MODE_LNGREAD_ENAB);
  6030. /* If statement applies to 5705 and 5750 PCI devices only */
  6031. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  6032. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  6033. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  6034. if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
  6035. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  6036. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  6037. /* nothing */
  6038. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  6039. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  6040. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  6041. val |= WDMAC_MODE_RX_ACCEL;
  6042. }
  6043. }
  6044. /* Enable host coalescing bug fix */
  6045. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
  6046. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
  6047. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
  6048. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761))
  6049. val |= (1 << 29);
  6050. tw32_f(WDMAC_MODE, val);
  6051. udelay(40);
  6052. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  6053. u16 pcix_cmd;
  6054. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6055. &pcix_cmd);
  6056. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  6057. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  6058. pcix_cmd |= PCI_X_CMD_READ_2K;
  6059. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  6060. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  6061. pcix_cmd |= PCI_X_CMD_READ_2K;
  6062. }
  6063. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6064. pcix_cmd);
  6065. }
  6066. tw32_f(RDMAC_MODE, rdmac_mode);
  6067. udelay(40);
  6068. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  6069. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  6070. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  6071. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  6072. tw32(SNDDATAC_MODE,
  6073. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  6074. else
  6075. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  6076. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  6077. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  6078. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  6079. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  6080. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  6081. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  6082. tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
  6083. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  6084. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  6085. err = tg3_load_5701_a0_firmware_fix(tp);
  6086. if (err)
  6087. return err;
  6088. }
  6089. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  6090. err = tg3_load_tso_firmware(tp);
  6091. if (err)
  6092. return err;
  6093. }
  6094. tp->tx_mode = TX_MODE_ENABLE;
  6095. tw32_f(MAC_TX_MODE, tp->tx_mode);
  6096. udelay(100);
  6097. tp->rx_mode = RX_MODE_ENABLE;
  6098. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  6099. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  6100. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  6101. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6102. udelay(10);
  6103. if (tp->link_config.phy_is_low_power) {
  6104. tp->link_config.phy_is_low_power = 0;
  6105. tp->link_config.speed = tp->link_config.orig_speed;
  6106. tp->link_config.duplex = tp->link_config.orig_duplex;
  6107. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  6108. }
  6109. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  6110. tw32_f(MAC_MI_MODE, tp->mi_mode);
  6111. udelay(80);
  6112. tw32(MAC_LED_CTRL, tp->led_ctrl);
  6113. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  6114. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  6115. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6116. udelay(10);
  6117. }
  6118. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6119. udelay(10);
  6120. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  6121. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  6122. !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
  6123. /* Set drive transmission level to 1.2V */
  6124. /* only if the signal pre-emphasis bit is not set */
  6125. val = tr32(MAC_SERDES_CFG);
  6126. val &= 0xfffff000;
  6127. val |= 0x880;
  6128. tw32(MAC_SERDES_CFG, val);
  6129. }
  6130. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  6131. tw32(MAC_SERDES_CFG, 0x616000);
  6132. }
  6133. /* Prevent chip from dropping frames when flow control
  6134. * is enabled.
  6135. */
  6136. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
  6137. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  6138. (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  6139. /* Use hardware link auto-negotiation */
  6140. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  6141. }
  6142. if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
  6143. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  6144. u32 tmp;
  6145. tmp = tr32(SERDES_RX_CTRL);
  6146. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  6147. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  6148. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  6149. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  6150. }
  6151. err = tg3_setup_phy(tp, 0);
  6152. if (err)
  6153. return err;
  6154. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6155. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
  6156. u32 tmp;
  6157. /* Clear CRC stats. */
  6158. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  6159. tg3_writephy(tp, MII_TG3_TEST1,
  6160. tmp | MII_TG3_TEST1_CRC_EN);
  6161. tg3_readphy(tp, 0x14, &tmp);
  6162. }
  6163. }
  6164. __tg3_set_rx_mode(tp->dev);
  6165. /* Initialize receive rules. */
  6166. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  6167. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6168. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  6169. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  6170. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  6171. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  6172. limit = 8;
  6173. else
  6174. limit = 16;
  6175. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  6176. limit -= 4;
  6177. switch (limit) {
  6178. case 16:
  6179. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  6180. case 15:
  6181. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  6182. case 14:
  6183. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  6184. case 13:
  6185. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  6186. case 12:
  6187. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  6188. case 11:
  6189. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  6190. case 10:
  6191. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  6192. case 9:
  6193. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  6194. case 8:
  6195. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  6196. case 7:
  6197. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  6198. case 6:
  6199. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  6200. case 5:
  6201. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  6202. case 4:
  6203. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  6204. case 3:
  6205. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  6206. case 2:
  6207. case 1:
  6208. default:
  6209. break;
  6210. };
  6211. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
  6212. /* Write our heartbeat update interval to APE. */
  6213. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  6214. APE_HOST_HEARTBEAT_INT_DISABLE);
  6215. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  6216. return 0;
  6217. }
  6218. /* Called at device open time to get the chip ready for
  6219. * packet processing. Invoked with tp->lock held.
  6220. */
  6221. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  6222. {
  6223. int err;
  6224. /* Force the chip into D0. */
  6225. err = tg3_set_power_state(tp, PCI_D0);
  6226. if (err)
  6227. goto out;
  6228. tg3_switch_clocks(tp);
  6229. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  6230. err = tg3_reset_hw(tp, reset_phy);
  6231. out:
  6232. return err;
  6233. }
  6234. #define TG3_STAT_ADD32(PSTAT, REG) \
  6235. do { u32 __val = tr32(REG); \
  6236. (PSTAT)->low += __val; \
  6237. if ((PSTAT)->low < __val) \
  6238. (PSTAT)->high += 1; \
  6239. } while (0)
  6240. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  6241. {
  6242. struct tg3_hw_stats *sp = tp->hw_stats;
  6243. if (!netif_carrier_ok(tp->dev))
  6244. return;
  6245. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  6246. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  6247. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  6248. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  6249. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  6250. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  6251. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  6252. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  6253. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  6254. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  6255. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  6256. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  6257. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  6258. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  6259. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  6260. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  6261. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  6262. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  6263. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  6264. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  6265. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  6266. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  6267. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  6268. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  6269. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  6270. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  6271. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  6272. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  6273. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  6274. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  6275. }
  6276. static void tg3_timer(unsigned long __opaque)
  6277. {
  6278. struct tg3 *tp = (struct tg3 *) __opaque;
  6279. if (tp->irq_sync)
  6280. goto restart_timer;
  6281. spin_lock(&tp->lock);
  6282. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6283. /* All of this garbage is because when using non-tagged
  6284. * IRQ status the mailbox/status_block protocol the chip
  6285. * uses with the cpu is race prone.
  6286. */
  6287. if (tp->hw_status->status & SD_STATUS_UPDATED) {
  6288. tw32(GRC_LOCAL_CTRL,
  6289. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  6290. } else {
  6291. tw32(HOSTCC_MODE, tp->coalesce_mode |
  6292. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  6293. }
  6294. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  6295. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  6296. spin_unlock(&tp->lock);
  6297. schedule_work(&tp->reset_task);
  6298. return;
  6299. }
  6300. }
  6301. /* This part only runs once per second. */
  6302. if (!--tp->timer_counter) {
  6303. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  6304. tg3_periodic_fetch_stats(tp);
  6305. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  6306. u32 mac_stat;
  6307. int phy_event;
  6308. mac_stat = tr32(MAC_STATUS);
  6309. phy_event = 0;
  6310. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  6311. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  6312. phy_event = 1;
  6313. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  6314. phy_event = 1;
  6315. if (phy_event)
  6316. tg3_setup_phy(tp, 0);
  6317. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  6318. u32 mac_stat = tr32(MAC_STATUS);
  6319. int need_setup = 0;
  6320. if (netif_carrier_ok(tp->dev) &&
  6321. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  6322. need_setup = 1;
  6323. }
  6324. if (! netif_carrier_ok(tp->dev) &&
  6325. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  6326. MAC_STATUS_SIGNAL_DET))) {
  6327. need_setup = 1;
  6328. }
  6329. if (need_setup) {
  6330. if (!tp->serdes_counter) {
  6331. tw32_f(MAC_MODE,
  6332. (tp->mac_mode &
  6333. ~MAC_MODE_PORT_MODE_MASK));
  6334. udelay(40);
  6335. tw32_f(MAC_MODE, tp->mac_mode);
  6336. udelay(40);
  6337. }
  6338. tg3_setup_phy(tp, 0);
  6339. }
  6340. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  6341. tg3_serdes_parallel_detect(tp);
  6342. tp->timer_counter = tp->timer_multiplier;
  6343. }
  6344. /* Heartbeat is only sent once every 2 seconds.
  6345. *
  6346. * The heartbeat is to tell the ASF firmware that the host
  6347. * driver is still alive. In the event that the OS crashes,
  6348. * ASF needs to reset the hardware to free up the FIFO space
  6349. * that may be filled with rx packets destined for the host.
  6350. * If the FIFO is full, ASF will no longer function properly.
  6351. *
  6352. * Unintended resets have been reported on real time kernels
  6353. * where the timer doesn't run on time. Netpoll will also have
  6354. * same problem.
  6355. *
  6356. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  6357. * to check the ring condition when the heartbeat is expiring
  6358. * before doing the reset. This will prevent most unintended
  6359. * resets.
  6360. */
  6361. if (!--tp->asf_counter) {
  6362. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  6363. u32 val;
  6364. tg3_wait_for_event_ack(tp);
  6365. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  6366. FWCMD_NICDRV_ALIVE3);
  6367. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  6368. /* 5 seconds timeout */
  6369. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
  6370. val = tr32(GRC_RX_CPU_EVENT);
  6371. val |= GRC_RX_CPU_DRIVER_EVENT;
  6372. tw32_f(GRC_RX_CPU_EVENT, val);
  6373. }
  6374. tp->asf_counter = tp->asf_multiplier;
  6375. }
  6376. spin_unlock(&tp->lock);
  6377. restart_timer:
  6378. tp->timer.expires = jiffies + tp->timer_offset;
  6379. add_timer(&tp->timer);
  6380. }
  6381. static int tg3_request_irq(struct tg3 *tp)
  6382. {
  6383. irq_handler_t fn;
  6384. unsigned long flags;
  6385. struct net_device *dev = tp->dev;
  6386. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6387. fn = tg3_msi;
  6388. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  6389. fn = tg3_msi_1shot;
  6390. flags = IRQF_SAMPLE_RANDOM;
  6391. } else {
  6392. fn = tg3_interrupt;
  6393. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6394. fn = tg3_interrupt_tagged;
  6395. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  6396. }
  6397. return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
  6398. }
  6399. static int tg3_test_interrupt(struct tg3 *tp)
  6400. {
  6401. struct net_device *dev = tp->dev;
  6402. int err, i, intr_ok = 0;
  6403. if (!netif_running(dev))
  6404. return -ENODEV;
  6405. tg3_disable_ints(tp);
  6406. free_irq(tp->pdev->irq, dev);
  6407. err = request_irq(tp->pdev->irq, tg3_test_isr,
  6408. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
  6409. if (err)
  6410. return err;
  6411. tp->hw_status->status &= ~SD_STATUS_UPDATED;
  6412. tg3_enable_ints(tp);
  6413. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  6414. HOSTCC_MODE_NOW);
  6415. for (i = 0; i < 5; i++) {
  6416. u32 int_mbox, misc_host_ctrl;
  6417. int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
  6418. TG3_64BIT_REG_LOW);
  6419. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  6420. if ((int_mbox != 0) ||
  6421. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  6422. intr_ok = 1;
  6423. break;
  6424. }
  6425. msleep(10);
  6426. }
  6427. tg3_disable_ints(tp);
  6428. free_irq(tp->pdev->irq, dev);
  6429. err = tg3_request_irq(tp);
  6430. if (err)
  6431. return err;
  6432. if (intr_ok)
  6433. return 0;
  6434. return -EIO;
  6435. }
  6436. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  6437. * successfully restored
  6438. */
  6439. static int tg3_test_msi(struct tg3 *tp)
  6440. {
  6441. struct net_device *dev = tp->dev;
  6442. int err;
  6443. u16 pci_cmd;
  6444. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  6445. return 0;
  6446. /* Turn off SERR reporting in case MSI terminates with Master
  6447. * Abort.
  6448. */
  6449. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  6450. pci_write_config_word(tp->pdev, PCI_COMMAND,
  6451. pci_cmd & ~PCI_COMMAND_SERR);
  6452. err = tg3_test_interrupt(tp);
  6453. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  6454. if (!err)
  6455. return 0;
  6456. /* other failures */
  6457. if (err != -EIO)
  6458. return err;
  6459. /* MSI test failed, go back to INTx mode */
  6460. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  6461. "switching to INTx mode. Please report this failure to "
  6462. "the PCI maintainer and include system chipset information.\n",
  6463. tp->dev->name);
  6464. free_irq(tp->pdev->irq, dev);
  6465. pci_disable_msi(tp->pdev);
  6466. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6467. err = tg3_request_irq(tp);
  6468. if (err)
  6469. return err;
  6470. /* Need to reset the chip because the MSI cycle may have terminated
  6471. * with Master Abort.
  6472. */
  6473. tg3_full_lock(tp, 1);
  6474. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6475. err = tg3_init_hw(tp, 1);
  6476. tg3_full_unlock(tp);
  6477. if (err)
  6478. free_irq(tp->pdev->irq, dev);
  6479. return err;
  6480. }
  6481. static int tg3_open(struct net_device *dev)
  6482. {
  6483. struct tg3 *tp = netdev_priv(dev);
  6484. int err;
  6485. netif_carrier_off(tp->dev);
  6486. tg3_full_lock(tp, 0);
  6487. err = tg3_set_power_state(tp, PCI_D0);
  6488. if (err) {
  6489. tg3_full_unlock(tp);
  6490. return err;
  6491. }
  6492. tg3_disable_ints(tp);
  6493. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6494. tg3_full_unlock(tp);
  6495. /* The placement of this call is tied
  6496. * to the setup and use of Host TX descriptors.
  6497. */
  6498. err = tg3_alloc_consistent(tp);
  6499. if (err)
  6500. return err;
  6501. if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
  6502. /* All MSI supporting chips should support tagged
  6503. * status. Assert that this is the case.
  6504. */
  6505. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6506. printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
  6507. "Not using MSI.\n", tp->dev->name);
  6508. } else if (pci_enable_msi(tp->pdev) == 0) {
  6509. u32 msi_mode;
  6510. msi_mode = tr32(MSGINT_MODE);
  6511. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  6512. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  6513. }
  6514. }
  6515. err = tg3_request_irq(tp);
  6516. if (err) {
  6517. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6518. pci_disable_msi(tp->pdev);
  6519. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6520. }
  6521. tg3_free_consistent(tp);
  6522. return err;
  6523. }
  6524. napi_enable(&tp->napi);
  6525. tg3_full_lock(tp, 0);
  6526. err = tg3_init_hw(tp, 1);
  6527. if (err) {
  6528. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6529. tg3_free_rings(tp);
  6530. } else {
  6531. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6532. tp->timer_offset = HZ;
  6533. else
  6534. tp->timer_offset = HZ / 10;
  6535. BUG_ON(tp->timer_offset > HZ);
  6536. tp->timer_counter = tp->timer_multiplier =
  6537. (HZ / tp->timer_offset);
  6538. tp->asf_counter = tp->asf_multiplier =
  6539. ((HZ / tp->timer_offset) * 2);
  6540. init_timer(&tp->timer);
  6541. tp->timer.expires = jiffies + tp->timer_offset;
  6542. tp->timer.data = (unsigned long) tp;
  6543. tp->timer.function = tg3_timer;
  6544. }
  6545. tg3_full_unlock(tp);
  6546. if (err) {
  6547. napi_disable(&tp->napi);
  6548. free_irq(tp->pdev->irq, dev);
  6549. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6550. pci_disable_msi(tp->pdev);
  6551. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6552. }
  6553. tg3_free_consistent(tp);
  6554. return err;
  6555. }
  6556. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6557. err = tg3_test_msi(tp);
  6558. if (err) {
  6559. tg3_full_lock(tp, 0);
  6560. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6561. pci_disable_msi(tp->pdev);
  6562. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6563. }
  6564. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6565. tg3_free_rings(tp);
  6566. tg3_free_consistent(tp);
  6567. tg3_full_unlock(tp);
  6568. napi_disable(&tp->napi);
  6569. return err;
  6570. }
  6571. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6572. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
  6573. u32 val = tr32(PCIE_TRANSACTION_CFG);
  6574. tw32(PCIE_TRANSACTION_CFG,
  6575. val | PCIE_TRANS_CFG_1SHOT_MSI);
  6576. }
  6577. }
  6578. }
  6579. tg3_full_lock(tp, 0);
  6580. add_timer(&tp->timer);
  6581. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  6582. tg3_enable_ints(tp);
  6583. tg3_full_unlock(tp);
  6584. netif_start_queue(dev);
  6585. return 0;
  6586. }
  6587. #if 0
  6588. /*static*/ void tg3_dump_state(struct tg3 *tp)
  6589. {
  6590. u32 val32, val32_2, val32_3, val32_4, val32_5;
  6591. u16 val16;
  6592. int i;
  6593. pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  6594. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  6595. printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  6596. val16, val32);
  6597. /* MAC block */
  6598. printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  6599. tr32(MAC_MODE), tr32(MAC_STATUS));
  6600. printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  6601. tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  6602. printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  6603. tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  6604. printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  6605. tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  6606. /* Send data initiator control block */
  6607. printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  6608. tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  6609. printk(" SNDDATAI_STATSCTRL[%08x]\n",
  6610. tr32(SNDDATAI_STATSCTRL));
  6611. /* Send data completion control block */
  6612. printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  6613. /* Send BD ring selector block */
  6614. printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  6615. tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  6616. /* Send BD initiator control block */
  6617. printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  6618. tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  6619. /* Send BD completion control block */
  6620. printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  6621. /* Receive list placement control block */
  6622. printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  6623. tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  6624. printk(" RCVLPC_STATSCTRL[%08x]\n",
  6625. tr32(RCVLPC_STATSCTRL));
  6626. /* Receive data and receive BD initiator control block */
  6627. printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  6628. tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  6629. /* Receive data completion control block */
  6630. printk("DEBUG: RCVDCC_MODE[%08x]\n",
  6631. tr32(RCVDCC_MODE));
  6632. /* Receive BD initiator control block */
  6633. printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  6634. tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  6635. /* Receive BD completion control block */
  6636. printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  6637. tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  6638. /* Receive list selector control block */
  6639. printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  6640. tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  6641. /* Mbuf cluster free block */
  6642. printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  6643. tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  6644. /* Host coalescing control block */
  6645. printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  6646. tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  6647. printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  6648. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6649. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6650. printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  6651. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6652. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6653. printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  6654. tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  6655. printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  6656. tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  6657. /* Memory arbiter control block */
  6658. printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  6659. tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  6660. /* Buffer manager control block */
  6661. printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  6662. tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  6663. printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  6664. tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  6665. printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  6666. "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  6667. tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  6668. tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  6669. /* Read DMA control block */
  6670. printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  6671. tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  6672. /* Write DMA control block */
  6673. printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  6674. tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  6675. /* DMA completion block */
  6676. printk("DEBUG: DMAC_MODE[%08x]\n",
  6677. tr32(DMAC_MODE));
  6678. /* GRC block */
  6679. printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  6680. tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  6681. printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  6682. tr32(GRC_LOCAL_CTRL));
  6683. /* TG3_BDINFOs */
  6684. printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  6685. tr32(RCVDBDI_JUMBO_BD + 0x0),
  6686. tr32(RCVDBDI_JUMBO_BD + 0x4),
  6687. tr32(RCVDBDI_JUMBO_BD + 0x8),
  6688. tr32(RCVDBDI_JUMBO_BD + 0xc));
  6689. printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  6690. tr32(RCVDBDI_STD_BD + 0x0),
  6691. tr32(RCVDBDI_STD_BD + 0x4),
  6692. tr32(RCVDBDI_STD_BD + 0x8),
  6693. tr32(RCVDBDI_STD_BD + 0xc));
  6694. printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  6695. tr32(RCVDBDI_MINI_BD + 0x0),
  6696. tr32(RCVDBDI_MINI_BD + 0x4),
  6697. tr32(RCVDBDI_MINI_BD + 0x8),
  6698. tr32(RCVDBDI_MINI_BD + 0xc));
  6699. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  6700. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  6701. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  6702. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  6703. printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  6704. val32, val32_2, val32_3, val32_4);
  6705. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  6706. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  6707. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  6708. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  6709. printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  6710. val32, val32_2, val32_3, val32_4);
  6711. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  6712. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  6713. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  6714. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  6715. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  6716. printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  6717. val32, val32_2, val32_3, val32_4, val32_5);
  6718. /* SW status block */
  6719. printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  6720. tp->hw_status->status,
  6721. tp->hw_status->status_tag,
  6722. tp->hw_status->rx_jumbo_consumer,
  6723. tp->hw_status->rx_consumer,
  6724. tp->hw_status->rx_mini_consumer,
  6725. tp->hw_status->idx[0].rx_producer,
  6726. tp->hw_status->idx[0].tx_consumer);
  6727. /* SW statistics block */
  6728. printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  6729. ((u32 *)tp->hw_stats)[0],
  6730. ((u32 *)tp->hw_stats)[1],
  6731. ((u32 *)tp->hw_stats)[2],
  6732. ((u32 *)tp->hw_stats)[3]);
  6733. /* Mailboxes */
  6734. printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  6735. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  6736. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  6737. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  6738. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  6739. /* NIC side send descriptors. */
  6740. for (i = 0; i < 6; i++) {
  6741. unsigned long txd;
  6742. txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  6743. + (i * sizeof(struct tg3_tx_buffer_desc));
  6744. printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  6745. i,
  6746. readl(txd + 0x0), readl(txd + 0x4),
  6747. readl(txd + 0x8), readl(txd + 0xc));
  6748. }
  6749. /* NIC side RX descriptors. */
  6750. for (i = 0; i < 6; i++) {
  6751. unsigned long rxd;
  6752. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  6753. + (i * sizeof(struct tg3_rx_buffer_desc));
  6754. printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  6755. i,
  6756. readl(rxd + 0x0), readl(rxd + 0x4),
  6757. readl(rxd + 0x8), readl(rxd + 0xc));
  6758. rxd += (4 * sizeof(u32));
  6759. printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  6760. i,
  6761. readl(rxd + 0x0), readl(rxd + 0x4),
  6762. readl(rxd + 0x8), readl(rxd + 0xc));
  6763. }
  6764. for (i = 0; i < 6; i++) {
  6765. unsigned long rxd;
  6766. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  6767. + (i * sizeof(struct tg3_rx_buffer_desc));
  6768. printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  6769. i,
  6770. readl(rxd + 0x0), readl(rxd + 0x4),
  6771. readl(rxd + 0x8), readl(rxd + 0xc));
  6772. rxd += (4 * sizeof(u32));
  6773. printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  6774. i,
  6775. readl(rxd + 0x0), readl(rxd + 0x4),
  6776. readl(rxd + 0x8), readl(rxd + 0xc));
  6777. }
  6778. }
  6779. #endif
  6780. static struct net_device_stats *tg3_get_stats(struct net_device *);
  6781. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  6782. static int tg3_close(struct net_device *dev)
  6783. {
  6784. struct tg3 *tp = netdev_priv(dev);
  6785. napi_disable(&tp->napi);
  6786. cancel_work_sync(&tp->reset_task);
  6787. netif_stop_queue(dev);
  6788. del_timer_sync(&tp->timer);
  6789. tg3_full_lock(tp, 1);
  6790. #if 0
  6791. tg3_dump_state(tp);
  6792. #endif
  6793. tg3_disable_ints(tp);
  6794. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6795. tg3_free_rings(tp);
  6796. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6797. tg3_full_unlock(tp);
  6798. free_irq(tp->pdev->irq, dev);
  6799. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6800. pci_disable_msi(tp->pdev);
  6801. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6802. }
  6803. memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  6804. sizeof(tp->net_stats_prev));
  6805. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  6806. sizeof(tp->estats_prev));
  6807. tg3_free_consistent(tp);
  6808. tg3_set_power_state(tp, PCI_D3hot);
  6809. netif_carrier_off(tp->dev);
  6810. return 0;
  6811. }
  6812. static inline unsigned long get_stat64(tg3_stat64_t *val)
  6813. {
  6814. unsigned long ret;
  6815. #if (BITS_PER_LONG == 32)
  6816. ret = val->low;
  6817. #else
  6818. ret = ((u64)val->high << 32) | ((u64)val->low);
  6819. #endif
  6820. return ret;
  6821. }
  6822. static unsigned long calc_crc_errors(struct tg3 *tp)
  6823. {
  6824. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6825. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6826. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  6827. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  6828. u32 val;
  6829. spin_lock_bh(&tp->lock);
  6830. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  6831. tg3_writephy(tp, MII_TG3_TEST1,
  6832. val | MII_TG3_TEST1_CRC_EN);
  6833. tg3_readphy(tp, 0x14, &val);
  6834. } else
  6835. val = 0;
  6836. spin_unlock_bh(&tp->lock);
  6837. tp->phy_crc_errors += val;
  6838. return tp->phy_crc_errors;
  6839. }
  6840. return get_stat64(&hw_stats->rx_fcs_errors);
  6841. }
  6842. #define ESTAT_ADD(member) \
  6843. estats->member = old_estats->member + \
  6844. get_stat64(&hw_stats->member)
  6845. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  6846. {
  6847. struct tg3_ethtool_stats *estats = &tp->estats;
  6848. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  6849. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6850. if (!hw_stats)
  6851. return old_estats;
  6852. ESTAT_ADD(rx_octets);
  6853. ESTAT_ADD(rx_fragments);
  6854. ESTAT_ADD(rx_ucast_packets);
  6855. ESTAT_ADD(rx_mcast_packets);
  6856. ESTAT_ADD(rx_bcast_packets);
  6857. ESTAT_ADD(rx_fcs_errors);
  6858. ESTAT_ADD(rx_align_errors);
  6859. ESTAT_ADD(rx_xon_pause_rcvd);
  6860. ESTAT_ADD(rx_xoff_pause_rcvd);
  6861. ESTAT_ADD(rx_mac_ctrl_rcvd);
  6862. ESTAT_ADD(rx_xoff_entered);
  6863. ESTAT_ADD(rx_frame_too_long_errors);
  6864. ESTAT_ADD(rx_jabbers);
  6865. ESTAT_ADD(rx_undersize_packets);
  6866. ESTAT_ADD(rx_in_length_errors);
  6867. ESTAT_ADD(rx_out_length_errors);
  6868. ESTAT_ADD(rx_64_or_less_octet_packets);
  6869. ESTAT_ADD(rx_65_to_127_octet_packets);
  6870. ESTAT_ADD(rx_128_to_255_octet_packets);
  6871. ESTAT_ADD(rx_256_to_511_octet_packets);
  6872. ESTAT_ADD(rx_512_to_1023_octet_packets);
  6873. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  6874. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  6875. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  6876. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  6877. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  6878. ESTAT_ADD(tx_octets);
  6879. ESTAT_ADD(tx_collisions);
  6880. ESTAT_ADD(tx_xon_sent);
  6881. ESTAT_ADD(tx_xoff_sent);
  6882. ESTAT_ADD(tx_flow_control);
  6883. ESTAT_ADD(tx_mac_errors);
  6884. ESTAT_ADD(tx_single_collisions);
  6885. ESTAT_ADD(tx_mult_collisions);
  6886. ESTAT_ADD(tx_deferred);
  6887. ESTAT_ADD(tx_excessive_collisions);
  6888. ESTAT_ADD(tx_late_collisions);
  6889. ESTAT_ADD(tx_collide_2times);
  6890. ESTAT_ADD(tx_collide_3times);
  6891. ESTAT_ADD(tx_collide_4times);
  6892. ESTAT_ADD(tx_collide_5times);
  6893. ESTAT_ADD(tx_collide_6times);
  6894. ESTAT_ADD(tx_collide_7times);
  6895. ESTAT_ADD(tx_collide_8times);
  6896. ESTAT_ADD(tx_collide_9times);
  6897. ESTAT_ADD(tx_collide_10times);
  6898. ESTAT_ADD(tx_collide_11times);
  6899. ESTAT_ADD(tx_collide_12times);
  6900. ESTAT_ADD(tx_collide_13times);
  6901. ESTAT_ADD(tx_collide_14times);
  6902. ESTAT_ADD(tx_collide_15times);
  6903. ESTAT_ADD(tx_ucast_packets);
  6904. ESTAT_ADD(tx_mcast_packets);
  6905. ESTAT_ADD(tx_bcast_packets);
  6906. ESTAT_ADD(tx_carrier_sense_errors);
  6907. ESTAT_ADD(tx_discards);
  6908. ESTAT_ADD(tx_errors);
  6909. ESTAT_ADD(dma_writeq_full);
  6910. ESTAT_ADD(dma_write_prioq_full);
  6911. ESTAT_ADD(rxbds_empty);
  6912. ESTAT_ADD(rx_discards);
  6913. ESTAT_ADD(rx_errors);
  6914. ESTAT_ADD(rx_threshold_hit);
  6915. ESTAT_ADD(dma_readq_full);
  6916. ESTAT_ADD(dma_read_prioq_full);
  6917. ESTAT_ADD(tx_comp_queue_full);
  6918. ESTAT_ADD(ring_set_send_prod_index);
  6919. ESTAT_ADD(ring_status_update);
  6920. ESTAT_ADD(nic_irqs);
  6921. ESTAT_ADD(nic_avoided_irqs);
  6922. ESTAT_ADD(nic_tx_threshold_hit);
  6923. return estats;
  6924. }
  6925. static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  6926. {
  6927. struct tg3 *tp = netdev_priv(dev);
  6928. struct net_device_stats *stats = &tp->net_stats;
  6929. struct net_device_stats *old_stats = &tp->net_stats_prev;
  6930. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6931. if (!hw_stats)
  6932. return old_stats;
  6933. stats->rx_packets = old_stats->rx_packets +
  6934. get_stat64(&hw_stats->rx_ucast_packets) +
  6935. get_stat64(&hw_stats->rx_mcast_packets) +
  6936. get_stat64(&hw_stats->rx_bcast_packets);
  6937. stats->tx_packets = old_stats->tx_packets +
  6938. get_stat64(&hw_stats->tx_ucast_packets) +
  6939. get_stat64(&hw_stats->tx_mcast_packets) +
  6940. get_stat64(&hw_stats->tx_bcast_packets);
  6941. stats->rx_bytes = old_stats->rx_bytes +
  6942. get_stat64(&hw_stats->rx_octets);
  6943. stats->tx_bytes = old_stats->tx_bytes +
  6944. get_stat64(&hw_stats->tx_octets);
  6945. stats->rx_errors = old_stats->rx_errors +
  6946. get_stat64(&hw_stats->rx_errors);
  6947. stats->tx_errors = old_stats->tx_errors +
  6948. get_stat64(&hw_stats->tx_errors) +
  6949. get_stat64(&hw_stats->tx_mac_errors) +
  6950. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  6951. get_stat64(&hw_stats->tx_discards);
  6952. stats->multicast = old_stats->multicast +
  6953. get_stat64(&hw_stats->rx_mcast_packets);
  6954. stats->collisions = old_stats->collisions +
  6955. get_stat64(&hw_stats->tx_collisions);
  6956. stats->rx_length_errors = old_stats->rx_length_errors +
  6957. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  6958. get_stat64(&hw_stats->rx_undersize_packets);
  6959. stats->rx_over_errors = old_stats->rx_over_errors +
  6960. get_stat64(&hw_stats->rxbds_empty);
  6961. stats->rx_frame_errors = old_stats->rx_frame_errors +
  6962. get_stat64(&hw_stats->rx_align_errors);
  6963. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  6964. get_stat64(&hw_stats->tx_discards);
  6965. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  6966. get_stat64(&hw_stats->tx_carrier_sense_errors);
  6967. stats->rx_crc_errors = old_stats->rx_crc_errors +
  6968. calc_crc_errors(tp);
  6969. stats->rx_missed_errors = old_stats->rx_missed_errors +
  6970. get_stat64(&hw_stats->rx_discards);
  6971. return stats;
  6972. }
  6973. static inline u32 calc_crc(unsigned char *buf, int len)
  6974. {
  6975. u32 reg;
  6976. u32 tmp;
  6977. int j, k;
  6978. reg = 0xffffffff;
  6979. for (j = 0; j < len; j++) {
  6980. reg ^= buf[j];
  6981. for (k = 0; k < 8; k++) {
  6982. tmp = reg & 0x01;
  6983. reg >>= 1;
  6984. if (tmp) {
  6985. reg ^= 0xedb88320;
  6986. }
  6987. }
  6988. }
  6989. return ~reg;
  6990. }
  6991. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  6992. {
  6993. /* accept or reject all multicast frames */
  6994. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  6995. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  6996. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  6997. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  6998. }
  6999. static void __tg3_set_rx_mode(struct net_device *dev)
  7000. {
  7001. struct tg3 *tp = netdev_priv(dev);
  7002. u32 rx_mode;
  7003. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7004. RX_MODE_KEEP_VLAN_TAG);
  7005. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7006. * flag clear.
  7007. */
  7008. #if TG3_VLAN_TAG_USED
  7009. if (!tp->vlgrp &&
  7010. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7011. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7012. #else
  7013. /* By definition, VLAN is disabled always in this
  7014. * case.
  7015. */
  7016. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  7017. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7018. #endif
  7019. if (dev->flags & IFF_PROMISC) {
  7020. /* Promiscuous mode. */
  7021. rx_mode |= RX_MODE_PROMISC;
  7022. } else if (dev->flags & IFF_ALLMULTI) {
  7023. /* Accept all multicast. */
  7024. tg3_set_multi (tp, 1);
  7025. } else if (dev->mc_count < 1) {
  7026. /* Reject all multicast. */
  7027. tg3_set_multi (tp, 0);
  7028. } else {
  7029. /* Accept one or more multicast(s). */
  7030. struct dev_mc_list *mclist;
  7031. unsigned int i;
  7032. u32 mc_filter[4] = { 0, };
  7033. u32 regidx;
  7034. u32 bit;
  7035. u32 crc;
  7036. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  7037. i++, mclist = mclist->next) {
  7038. crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  7039. bit = ~crc & 0x7f;
  7040. regidx = (bit & 0x60) >> 5;
  7041. bit &= 0x1f;
  7042. mc_filter[regidx] |= (1 << bit);
  7043. }
  7044. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7045. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7046. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7047. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7048. }
  7049. if (rx_mode != tp->rx_mode) {
  7050. tp->rx_mode = rx_mode;
  7051. tw32_f(MAC_RX_MODE, rx_mode);
  7052. udelay(10);
  7053. }
  7054. }
  7055. static void tg3_set_rx_mode(struct net_device *dev)
  7056. {
  7057. struct tg3 *tp = netdev_priv(dev);
  7058. if (!netif_running(dev))
  7059. return;
  7060. tg3_full_lock(tp, 0);
  7061. __tg3_set_rx_mode(dev);
  7062. tg3_full_unlock(tp);
  7063. }
  7064. #define TG3_REGDUMP_LEN (32 * 1024)
  7065. static int tg3_get_regs_len(struct net_device *dev)
  7066. {
  7067. return TG3_REGDUMP_LEN;
  7068. }
  7069. static void tg3_get_regs(struct net_device *dev,
  7070. struct ethtool_regs *regs, void *_p)
  7071. {
  7072. u32 *p = _p;
  7073. struct tg3 *tp = netdev_priv(dev);
  7074. u8 *orig_p = _p;
  7075. int i;
  7076. regs->version = 0;
  7077. memset(p, 0, TG3_REGDUMP_LEN);
  7078. if (tp->link_config.phy_is_low_power)
  7079. return;
  7080. tg3_full_lock(tp, 0);
  7081. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  7082. #define GET_REG32_LOOP(base,len) \
  7083. do { p = (u32 *)(orig_p + (base)); \
  7084. for (i = 0; i < len; i += 4) \
  7085. __GET_REG32((base) + i); \
  7086. } while (0)
  7087. #define GET_REG32_1(reg) \
  7088. do { p = (u32 *)(orig_p + (reg)); \
  7089. __GET_REG32((reg)); \
  7090. } while (0)
  7091. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  7092. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  7093. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  7094. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  7095. GET_REG32_1(SNDDATAC_MODE);
  7096. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  7097. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  7098. GET_REG32_1(SNDBDC_MODE);
  7099. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  7100. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  7101. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  7102. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  7103. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  7104. GET_REG32_1(RCVDCC_MODE);
  7105. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  7106. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  7107. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  7108. GET_REG32_1(MBFREE_MODE);
  7109. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  7110. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  7111. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  7112. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  7113. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  7114. GET_REG32_1(RX_CPU_MODE);
  7115. GET_REG32_1(RX_CPU_STATE);
  7116. GET_REG32_1(RX_CPU_PGMCTR);
  7117. GET_REG32_1(RX_CPU_HWBKPT);
  7118. GET_REG32_1(TX_CPU_MODE);
  7119. GET_REG32_1(TX_CPU_STATE);
  7120. GET_REG32_1(TX_CPU_PGMCTR);
  7121. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  7122. GET_REG32_LOOP(FTQ_RESET, 0x120);
  7123. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  7124. GET_REG32_1(DMAC_MODE);
  7125. GET_REG32_LOOP(GRC_MODE, 0x4c);
  7126. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  7127. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  7128. #undef __GET_REG32
  7129. #undef GET_REG32_LOOP
  7130. #undef GET_REG32_1
  7131. tg3_full_unlock(tp);
  7132. }
  7133. static int tg3_get_eeprom_len(struct net_device *dev)
  7134. {
  7135. struct tg3 *tp = netdev_priv(dev);
  7136. return tp->nvram_size;
  7137. }
  7138. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
  7139. static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
  7140. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
  7141. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7142. {
  7143. struct tg3 *tp = netdev_priv(dev);
  7144. int ret;
  7145. u8 *pd;
  7146. u32 i, offset, len, b_offset, b_count;
  7147. __le32 val;
  7148. if (tp->link_config.phy_is_low_power)
  7149. return -EAGAIN;
  7150. offset = eeprom->offset;
  7151. len = eeprom->len;
  7152. eeprom->len = 0;
  7153. eeprom->magic = TG3_EEPROM_MAGIC;
  7154. if (offset & 3) {
  7155. /* adjustments to start on required 4 byte boundary */
  7156. b_offset = offset & 3;
  7157. b_count = 4 - b_offset;
  7158. if (b_count > len) {
  7159. /* i.e. offset=1 len=2 */
  7160. b_count = len;
  7161. }
  7162. ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
  7163. if (ret)
  7164. return ret;
  7165. memcpy(data, ((char*)&val) + b_offset, b_count);
  7166. len -= b_count;
  7167. offset += b_count;
  7168. eeprom->len += b_count;
  7169. }
  7170. /* read bytes upto the last 4 byte boundary */
  7171. pd = &data[eeprom->len];
  7172. for (i = 0; i < (len - (len & 3)); i += 4) {
  7173. ret = tg3_nvram_read_le(tp, offset + i, &val);
  7174. if (ret) {
  7175. eeprom->len += i;
  7176. return ret;
  7177. }
  7178. memcpy(pd + i, &val, 4);
  7179. }
  7180. eeprom->len += i;
  7181. if (len & 3) {
  7182. /* read last bytes not ending on 4 byte boundary */
  7183. pd = &data[eeprom->len];
  7184. b_count = len & 3;
  7185. b_offset = offset + len - b_count;
  7186. ret = tg3_nvram_read_le(tp, b_offset, &val);
  7187. if (ret)
  7188. return ret;
  7189. memcpy(pd, &val, b_count);
  7190. eeprom->len += b_count;
  7191. }
  7192. return 0;
  7193. }
  7194. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  7195. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  7196. {
  7197. struct tg3 *tp = netdev_priv(dev);
  7198. int ret;
  7199. u32 offset, len, b_offset, odd_len;
  7200. u8 *buf;
  7201. __le32 start, end;
  7202. if (tp->link_config.phy_is_low_power)
  7203. return -EAGAIN;
  7204. if (eeprom->magic != TG3_EEPROM_MAGIC)
  7205. return -EINVAL;
  7206. offset = eeprom->offset;
  7207. len = eeprom->len;
  7208. if ((b_offset = (offset & 3))) {
  7209. /* adjustments to start on required 4 byte boundary */
  7210. ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
  7211. if (ret)
  7212. return ret;
  7213. len += b_offset;
  7214. offset &= ~3;
  7215. if (len < 4)
  7216. len = 4;
  7217. }
  7218. odd_len = 0;
  7219. if (len & 3) {
  7220. /* adjustments to end on required 4 byte boundary */
  7221. odd_len = 1;
  7222. len = (len + 3) & ~3;
  7223. ret = tg3_nvram_read_le(tp, offset+len-4, &end);
  7224. if (ret)
  7225. return ret;
  7226. }
  7227. buf = data;
  7228. if (b_offset || odd_len) {
  7229. buf = kmalloc(len, GFP_KERNEL);
  7230. if (!buf)
  7231. return -ENOMEM;
  7232. if (b_offset)
  7233. memcpy(buf, &start, 4);
  7234. if (odd_len)
  7235. memcpy(buf+len-4, &end, 4);
  7236. memcpy(buf + b_offset, data, eeprom->len);
  7237. }
  7238. ret = tg3_nvram_write_block(tp, offset, len, buf);
  7239. if (buf != data)
  7240. kfree(buf);
  7241. return ret;
  7242. }
  7243. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  7244. {
  7245. struct tg3 *tp = netdev_priv(dev);
  7246. cmd->supported = (SUPPORTED_Autoneg);
  7247. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  7248. cmd->supported |= (SUPPORTED_1000baseT_Half |
  7249. SUPPORTED_1000baseT_Full);
  7250. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  7251. cmd->supported |= (SUPPORTED_100baseT_Half |
  7252. SUPPORTED_100baseT_Full |
  7253. SUPPORTED_10baseT_Half |
  7254. SUPPORTED_10baseT_Full |
  7255. SUPPORTED_TP);
  7256. cmd->port = PORT_TP;
  7257. } else {
  7258. cmd->supported |= SUPPORTED_FIBRE;
  7259. cmd->port = PORT_FIBRE;
  7260. }
  7261. cmd->advertising = tp->link_config.advertising;
  7262. if (netif_running(dev)) {
  7263. cmd->speed = tp->link_config.active_speed;
  7264. cmd->duplex = tp->link_config.active_duplex;
  7265. }
  7266. cmd->phy_address = PHY_ADDR;
  7267. cmd->transceiver = 0;
  7268. cmd->autoneg = tp->link_config.autoneg;
  7269. cmd->maxtxpkt = 0;
  7270. cmd->maxrxpkt = 0;
  7271. return 0;
  7272. }
  7273. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  7274. {
  7275. struct tg3 *tp = netdev_priv(dev);
  7276. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
  7277. /* These are the only valid advertisement bits allowed. */
  7278. if (cmd->autoneg == AUTONEG_ENABLE &&
  7279. (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
  7280. ADVERTISED_1000baseT_Full |
  7281. ADVERTISED_Autoneg |
  7282. ADVERTISED_FIBRE)))
  7283. return -EINVAL;
  7284. /* Fiber can only do SPEED_1000. */
  7285. else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  7286. (cmd->speed != SPEED_1000))
  7287. return -EINVAL;
  7288. /* Copper cannot force SPEED_1000. */
  7289. } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  7290. (cmd->speed == SPEED_1000))
  7291. return -EINVAL;
  7292. else if ((cmd->speed == SPEED_1000) &&
  7293. (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
  7294. return -EINVAL;
  7295. tg3_full_lock(tp, 0);
  7296. tp->link_config.autoneg = cmd->autoneg;
  7297. if (cmd->autoneg == AUTONEG_ENABLE) {
  7298. tp->link_config.advertising = (cmd->advertising |
  7299. ADVERTISED_Autoneg);
  7300. tp->link_config.speed = SPEED_INVALID;
  7301. tp->link_config.duplex = DUPLEX_INVALID;
  7302. } else {
  7303. tp->link_config.advertising = 0;
  7304. tp->link_config.speed = cmd->speed;
  7305. tp->link_config.duplex = cmd->duplex;
  7306. }
  7307. tp->link_config.orig_speed = tp->link_config.speed;
  7308. tp->link_config.orig_duplex = tp->link_config.duplex;
  7309. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  7310. if (netif_running(dev))
  7311. tg3_setup_phy(tp, 1);
  7312. tg3_full_unlock(tp);
  7313. return 0;
  7314. }
  7315. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  7316. {
  7317. struct tg3 *tp = netdev_priv(dev);
  7318. strcpy(info->driver, DRV_MODULE_NAME);
  7319. strcpy(info->version, DRV_MODULE_VERSION);
  7320. strcpy(info->fw_version, tp->fw_ver);
  7321. strcpy(info->bus_info, pci_name(tp->pdev));
  7322. }
  7323. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  7324. {
  7325. struct tg3 *tp = netdev_priv(dev);
  7326. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  7327. wol->supported = WAKE_MAGIC;
  7328. else
  7329. wol->supported = 0;
  7330. wol->wolopts = 0;
  7331. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  7332. wol->wolopts = WAKE_MAGIC;
  7333. memset(&wol->sopass, 0, sizeof(wol->sopass));
  7334. }
  7335. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  7336. {
  7337. struct tg3 *tp = netdev_priv(dev);
  7338. if (wol->wolopts & ~WAKE_MAGIC)
  7339. return -EINVAL;
  7340. if ((wol->wolopts & WAKE_MAGIC) &&
  7341. !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
  7342. return -EINVAL;
  7343. spin_lock_bh(&tp->lock);
  7344. if (wol->wolopts & WAKE_MAGIC)
  7345. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  7346. else
  7347. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  7348. spin_unlock_bh(&tp->lock);
  7349. return 0;
  7350. }
  7351. static u32 tg3_get_msglevel(struct net_device *dev)
  7352. {
  7353. struct tg3 *tp = netdev_priv(dev);
  7354. return tp->msg_enable;
  7355. }
  7356. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  7357. {
  7358. struct tg3 *tp = netdev_priv(dev);
  7359. tp->msg_enable = value;
  7360. }
  7361. static int tg3_set_tso(struct net_device *dev, u32 value)
  7362. {
  7363. struct tg3 *tp = netdev_priv(dev);
  7364. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  7365. if (value)
  7366. return -EINVAL;
  7367. return 0;
  7368. }
  7369. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  7370. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
  7371. if (value) {
  7372. dev->features |= NETIF_F_TSO6;
  7373. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  7374. dev->features |= NETIF_F_TSO_ECN;
  7375. } else
  7376. dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
  7377. }
  7378. return ethtool_op_set_tso(dev, value);
  7379. }
  7380. static int tg3_nway_reset(struct net_device *dev)
  7381. {
  7382. struct tg3 *tp = netdev_priv(dev);
  7383. u32 bmcr;
  7384. int r;
  7385. if (!netif_running(dev))
  7386. return -EAGAIN;
  7387. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7388. return -EINVAL;
  7389. spin_lock_bh(&tp->lock);
  7390. r = -EINVAL;
  7391. tg3_readphy(tp, MII_BMCR, &bmcr);
  7392. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  7393. ((bmcr & BMCR_ANENABLE) ||
  7394. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
  7395. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  7396. BMCR_ANENABLE);
  7397. r = 0;
  7398. }
  7399. spin_unlock_bh(&tp->lock);
  7400. return r;
  7401. }
  7402. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  7403. {
  7404. struct tg3 *tp = netdev_priv(dev);
  7405. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  7406. ering->rx_mini_max_pending = 0;
  7407. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  7408. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  7409. else
  7410. ering->rx_jumbo_max_pending = 0;
  7411. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  7412. ering->rx_pending = tp->rx_pending;
  7413. ering->rx_mini_pending = 0;
  7414. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  7415. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  7416. else
  7417. ering->rx_jumbo_pending = 0;
  7418. ering->tx_pending = tp->tx_pending;
  7419. }
  7420. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  7421. {
  7422. struct tg3 *tp = netdev_priv(dev);
  7423. int irq_sync = 0, err = 0;
  7424. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  7425. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  7426. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  7427. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  7428. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  7429. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  7430. return -EINVAL;
  7431. if (netif_running(dev)) {
  7432. tg3_netif_stop(tp);
  7433. irq_sync = 1;
  7434. }
  7435. tg3_full_lock(tp, irq_sync);
  7436. tp->rx_pending = ering->rx_pending;
  7437. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  7438. tp->rx_pending > 63)
  7439. tp->rx_pending = 63;
  7440. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  7441. tp->tx_pending = ering->tx_pending;
  7442. if (netif_running(dev)) {
  7443. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7444. err = tg3_restart_hw(tp, 1);
  7445. if (!err)
  7446. tg3_netif_start(tp);
  7447. }
  7448. tg3_full_unlock(tp);
  7449. return err;
  7450. }
  7451. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7452. {
  7453. struct tg3 *tp = netdev_priv(dev);
  7454. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  7455. if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
  7456. epause->rx_pause = 1;
  7457. else
  7458. epause->rx_pause = 0;
  7459. if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
  7460. epause->tx_pause = 1;
  7461. else
  7462. epause->tx_pause = 0;
  7463. }
  7464. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7465. {
  7466. struct tg3 *tp = netdev_priv(dev);
  7467. int irq_sync = 0, err = 0;
  7468. if (netif_running(dev)) {
  7469. tg3_netif_stop(tp);
  7470. irq_sync = 1;
  7471. }
  7472. tg3_full_lock(tp, irq_sync);
  7473. if (epause->autoneg)
  7474. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  7475. else
  7476. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  7477. if (epause->rx_pause)
  7478. tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
  7479. else
  7480. tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
  7481. if (epause->tx_pause)
  7482. tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
  7483. else
  7484. tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
  7485. if (netif_running(dev)) {
  7486. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7487. err = tg3_restart_hw(tp, 1);
  7488. if (!err)
  7489. tg3_netif_start(tp);
  7490. }
  7491. tg3_full_unlock(tp);
  7492. return err;
  7493. }
  7494. static u32 tg3_get_rx_csum(struct net_device *dev)
  7495. {
  7496. struct tg3 *tp = netdev_priv(dev);
  7497. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  7498. }
  7499. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  7500. {
  7501. struct tg3 *tp = netdev_priv(dev);
  7502. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7503. if (data != 0)
  7504. return -EINVAL;
  7505. return 0;
  7506. }
  7507. spin_lock_bh(&tp->lock);
  7508. if (data)
  7509. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  7510. else
  7511. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  7512. spin_unlock_bh(&tp->lock);
  7513. return 0;
  7514. }
  7515. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  7516. {
  7517. struct tg3 *tp = netdev_priv(dev);
  7518. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7519. if (data != 0)
  7520. return -EINVAL;
  7521. return 0;
  7522. }
  7523. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7524. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  7525. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  7526. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  7527. ethtool_op_set_tx_ipv6_csum(dev, data);
  7528. else
  7529. ethtool_op_set_tx_csum(dev, data);
  7530. return 0;
  7531. }
  7532. static int tg3_get_sset_count (struct net_device *dev, int sset)
  7533. {
  7534. switch (sset) {
  7535. case ETH_SS_TEST:
  7536. return TG3_NUM_TEST;
  7537. case ETH_SS_STATS:
  7538. return TG3_NUM_STATS;
  7539. default:
  7540. return -EOPNOTSUPP;
  7541. }
  7542. }
  7543. static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
  7544. {
  7545. switch (stringset) {
  7546. case ETH_SS_STATS:
  7547. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  7548. break;
  7549. case ETH_SS_TEST:
  7550. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  7551. break;
  7552. default:
  7553. WARN_ON(1); /* we need a WARN() */
  7554. break;
  7555. }
  7556. }
  7557. static int tg3_phys_id(struct net_device *dev, u32 data)
  7558. {
  7559. struct tg3 *tp = netdev_priv(dev);
  7560. int i;
  7561. if (!netif_running(tp->dev))
  7562. return -EAGAIN;
  7563. if (data == 0)
  7564. data = UINT_MAX / 2;
  7565. for (i = 0; i < (data * 2); i++) {
  7566. if ((i % 2) == 0)
  7567. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7568. LED_CTRL_1000MBPS_ON |
  7569. LED_CTRL_100MBPS_ON |
  7570. LED_CTRL_10MBPS_ON |
  7571. LED_CTRL_TRAFFIC_OVERRIDE |
  7572. LED_CTRL_TRAFFIC_BLINK |
  7573. LED_CTRL_TRAFFIC_LED);
  7574. else
  7575. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7576. LED_CTRL_TRAFFIC_OVERRIDE);
  7577. if (msleep_interruptible(500))
  7578. break;
  7579. }
  7580. tw32(MAC_LED_CTRL, tp->led_ctrl);
  7581. return 0;
  7582. }
  7583. static void tg3_get_ethtool_stats (struct net_device *dev,
  7584. struct ethtool_stats *estats, u64 *tmp_stats)
  7585. {
  7586. struct tg3 *tp = netdev_priv(dev);
  7587. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  7588. }
  7589. #define NVRAM_TEST_SIZE 0x100
  7590. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  7591. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  7592. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  7593. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  7594. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  7595. static int tg3_test_nvram(struct tg3 *tp)
  7596. {
  7597. u32 csum, magic;
  7598. __le32 *buf;
  7599. int i, j, k, err = 0, size;
  7600. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7601. return -EIO;
  7602. if (magic == TG3_EEPROM_MAGIC)
  7603. size = NVRAM_TEST_SIZE;
  7604. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  7605. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  7606. TG3_EEPROM_SB_FORMAT_1) {
  7607. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  7608. case TG3_EEPROM_SB_REVISION_0:
  7609. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  7610. break;
  7611. case TG3_EEPROM_SB_REVISION_2:
  7612. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  7613. break;
  7614. case TG3_EEPROM_SB_REVISION_3:
  7615. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  7616. break;
  7617. default:
  7618. return 0;
  7619. }
  7620. } else
  7621. return 0;
  7622. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  7623. size = NVRAM_SELFBOOT_HW_SIZE;
  7624. else
  7625. return -EIO;
  7626. buf = kmalloc(size, GFP_KERNEL);
  7627. if (buf == NULL)
  7628. return -ENOMEM;
  7629. err = -EIO;
  7630. for (i = 0, j = 0; i < size; i += 4, j++) {
  7631. if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
  7632. break;
  7633. }
  7634. if (i < size)
  7635. goto out;
  7636. /* Selfboot format */
  7637. magic = swab32(le32_to_cpu(buf[0]));
  7638. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  7639. TG3_EEPROM_MAGIC_FW) {
  7640. u8 *buf8 = (u8 *) buf, csum8 = 0;
  7641. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  7642. TG3_EEPROM_SB_REVISION_2) {
  7643. /* For rev 2, the csum doesn't include the MBA. */
  7644. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  7645. csum8 += buf8[i];
  7646. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  7647. csum8 += buf8[i];
  7648. } else {
  7649. for (i = 0; i < size; i++)
  7650. csum8 += buf8[i];
  7651. }
  7652. if (csum8 == 0) {
  7653. err = 0;
  7654. goto out;
  7655. }
  7656. err = -EIO;
  7657. goto out;
  7658. }
  7659. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  7660. TG3_EEPROM_MAGIC_HW) {
  7661. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  7662. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  7663. u8 *buf8 = (u8 *) buf;
  7664. /* Separate the parity bits and the data bytes. */
  7665. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  7666. if ((i == 0) || (i == 8)) {
  7667. int l;
  7668. u8 msk;
  7669. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  7670. parity[k++] = buf8[i] & msk;
  7671. i++;
  7672. }
  7673. else if (i == 16) {
  7674. int l;
  7675. u8 msk;
  7676. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  7677. parity[k++] = buf8[i] & msk;
  7678. i++;
  7679. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  7680. parity[k++] = buf8[i] & msk;
  7681. i++;
  7682. }
  7683. data[j++] = buf8[i];
  7684. }
  7685. err = -EIO;
  7686. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  7687. u8 hw8 = hweight8(data[i]);
  7688. if ((hw8 & 0x1) && parity[i])
  7689. goto out;
  7690. else if (!(hw8 & 0x1) && !parity[i])
  7691. goto out;
  7692. }
  7693. err = 0;
  7694. goto out;
  7695. }
  7696. /* Bootstrap checksum at offset 0x10 */
  7697. csum = calc_crc((unsigned char *) buf, 0x10);
  7698. if(csum != le32_to_cpu(buf[0x10/4]))
  7699. goto out;
  7700. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  7701. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  7702. if (csum != le32_to_cpu(buf[0xfc/4]))
  7703. goto out;
  7704. err = 0;
  7705. out:
  7706. kfree(buf);
  7707. return err;
  7708. }
  7709. #define TG3_SERDES_TIMEOUT_SEC 2
  7710. #define TG3_COPPER_TIMEOUT_SEC 6
  7711. static int tg3_test_link(struct tg3 *tp)
  7712. {
  7713. int i, max;
  7714. if (!netif_running(tp->dev))
  7715. return -ENODEV;
  7716. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  7717. max = TG3_SERDES_TIMEOUT_SEC;
  7718. else
  7719. max = TG3_COPPER_TIMEOUT_SEC;
  7720. for (i = 0; i < max; i++) {
  7721. if (netif_carrier_ok(tp->dev))
  7722. return 0;
  7723. if (msleep_interruptible(1000))
  7724. break;
  7725. }
  7726. return -EIO;
  7727. }
  7728. /* Only test the commonly used registers */
  7729. static int tg3_test_registers(struct tg3 *tp)
  7730. {
  7731. int i, is_5705, is_5750;
  7732. u32 offset, read_mask, write_mask, val, save_val, read_val;
  7733. static struct {
  7734. u16 offset;
  7735. u16 flags;
  7736. #define TG3_FL_5705 0x1
  7737. #define TG3_FL_NOT_5705 0x2
  7738. #define TG3_FL_NOT_5788 0x4
  7739. #define TG3_FL_NOT_5750 0x8
  7740. u32 read_mask;
  7741. u32 write_mask;
  7742. } reg_tbl[] = {
  7743. /* MAC Control Registers */
  7744. { MAC_MODE, TG3_FL_NOT_5705,
  7745. 0x00000000, 0x00ef6f8c },
  7746. { MAC_MODE, TG3_FL_5705,
  7747. 0x00000000, 0x01ef6b8c },
  7748. { MAC_STATUS, TG3_FL_NOT_5705,
  7749. 0x03800107, 0x00000000 },
  7750. { MAC_STATUS, TG3_FL_5705,
  7751. 0x03800100, 0x00000000 },
  7752. { MAC_ADDR_0_HIGH, 0x0000,
  7753. 0x00000000, 0x0000ffff },
  7754. { MAC_ADDR_0_LOW, 0x0000,
  7755. 0x00000000, 0xffffffff },
  7756. { MAC_RX_MTU_SIZE, 0x0000,
  7757. 0x00000000, 0x0000ffff },
  7758. { MAC_TX_MODE, 0x0000,
  7759. 0x00000000, 0x00000070 },
  7760. { MAC_TX_LENGTHS, 0x0000,
  7761. 0x00000000, 0x00003fff },
  7762. { MAC_RX_MODE, TG3_FL_NOT_5705,
  7763. 0x00000000, 0x000007fc },
  7764. { MAC_RX_MODE, TG3_FL_5705,
  7765. 0x00000000, 0x000007dc },
  7766. { MAC_HASH_REG_0, 0x0000,
  7767. 0x00000000, 0xffffffff },
  7768. { MAC_HASH_REG_1, 0x0000,
  7769. 0x00000000, 0xffffffff },
  7770. { MAC_HASH_REG_2, 0x0000,
  7771. 0x00000000, 0xffffffff },
  7772. { MAC_HASH_REG_3, 0x0000,
  7773. 0x00000000, 0xffffffff },
  7774. /* Receive Data and Receive BD Initiator Control Registers. */
  7775. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  7776. 0x00000000, 0xffffffff },
  7777. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  7778. 0x00000000, 0xffffffff },
  7779. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  7780. 0x00000000, 0x00000003 },
  7781. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  7782. 0x00000000, 0xffffffff },
  7783. { RCVDBDI_STD_BD+0, 0x0000,
  7784. 0x00000000, 0xffffffff },
  7785. { RCVDBDI_STD_BD+4, 0x0000,
  7786. 0x00000000, 0xffffffff },
  7787. { RCVDBDI_STD_BD+8, 0x0000,
  7788. 0x00000000, 0xffff0002 },
  7789. { RCVDBDI_STD_BD+0xc, 0x0000,
  7790. 0x00000000, 0xffffffff },
  7791. /* Receive BD Initiator Control Registers. */
  7792. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  7793. 0x00000000, 0xffffffff },
  7794. { RCVBDI_STD_THRESH, TG3_FL_5705,
  7795. 0x00000000, 0x000003ff },
  7796. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  7797. 0x00000000, 0xffffffff },
  7798. /* Host Coalescing Control Registers. */
  7799. { HOSTCC_MODE, TG3_FL_NOT_5705,
  7800. 0x00000000, 0x00000004 },
  7801. { HOSTCC_MODE, TG3_FL_5705,
  7802. 0x00000000, 0x000000f6 },
  7803. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  7804. 0x00000000, 0xffffffff },
  7805. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  7806. 0x00000000, 0x000003ff },
  7807. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  7808. 0x00000000, 0xffffffff },
  7809. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  7810. 0x00000000, 0x000003ff },
  7811. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  7812. 0x00000000, 0xffffffff },
  7813. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7814. 0x00000000, 0x000000ff },
  7815. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  7816. 0x00000000, 0xffffffff },
  7817. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7818. 0x00000000, 0x000000ff },
  7819. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7820. 0x00000000, 0xffffffff },
  7821. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7822. 0x00000000, 0xffffffff },
  7823. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7824. 0x00000000, 0xffffffff },
  7825. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7826. 0x00000000, 0x000000ff },
  7827. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7828. 0x00000000, 0xffffffff },
  7829. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7830. 0x00000000, 0x000000ff },
  7831. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  7832. 0x00000000, 0xffffffff },
  7833. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  7834. 0x00000000, 0xffffffff },
  7835. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  7836. 0x00000000, 0xffffffff },
  7837. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  7838. 0x00000000, 0xffffffff },
  7839. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  7840. 0x00000000, 0xffffffff },
  7841. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  7842. 0xffffffff, 0x00000000 },
  7843. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  7844. 0xffffffff, 0x00000000 },
  7845. /* Buffer Manager Control Registers. */
  7846. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  7847. 0x00000000, 0x007fff80 },
  7848. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  7849. 0x00000000, 0x007fffff },
  7850. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  7851. 0x00000000, 0x0000003f },
  7852. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  7853. 0x00000000, 0x000001ff },
  7854. { BUFMGR_MB_HIGH_WATER, 0x0000,
  7855. 0x00000000, 0x000001ff },
  7856. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  7857. 0xffffffff, 0x00000000 },
  7858. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  7859. 0xffffffff, 0x00000000 },
  7860. /* Mailbox Registers */
  7861. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  7862. 0x00000000, 0x000001ff },
  7863. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  7864. 0x00000000, 0x000001ff },
  7865. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  7866. 0x00000000, 0x000007ff },
  7867. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  7868. 0x00000000, 0x000001ff },
  7869. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  7870. };
  7871. is_5705 = is_5750 = 0;
  7872. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7873. is_5705 = 1;
  7874. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  7875. is_5750 = 1;
  7876. }
  7877. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  7878. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  7879. continue;
  7880. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  7881. continue;
  7882. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  7883. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  7884. continue;
  7885. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  7886. continue;
  7887. offset = (u32) reg_tbl[i].offset;
  7888. read_mask = reg_tbl[i].read_mask;
  7889. write_mask = reg_tbl[i].write_mask;
  7890. /* Save the original register content */
  7891. save_val = tr32(offset);
  7892. /* Determine the read-only value. */
  7893. read_val = save_val & read_mask;
  7894. /* Write zero to the register, then make sure the read-only bits
  7895. * are not changed and the read/write bits are all zeros.
  7896. */
  7897. tw32(offset, 0);
  7898. val = tr32(offset);
  7899. /* Test the read-only and read/write bits. */
  7900. if (((val & read_mask) != read_val) || (val & write_mask))
  7901. goto out;
  7902. /* Write ones to all the bits defined by RdMask and WrMask, then
  7903. * make sure the read-only bits are not changed and the
  7904. * read/write bits are all ones.
  7905. */
  7906. tw32(offset, read_mask | write_mask);
  7907. val = tr32(offset);
  7908. /* Test the read-only bits. */
  7909. if ((val & read_mask) != read_val)
  7910. goto out;
  7911. /* Test the read/write bits. */
  7912. if ((val & write_mask) != write_mask)
  7913. goto out;
  7914. tw32(offset, save_val);
  7915. }
  7916. return 0;
  7917. out:
  7918. if (netif_msg_hw(tp))
  7919. printk(KERN_ERR PFX "Register test failed at offset %x\n",
  7920. offset);
  7921. tw32(offset, save_val);
  7922. return -EIO;
  7923. }
  7924. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  7925. {
  7926. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  7927. int i;
  7928. u32 j;
  7929. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  7930. for (j = 0; j < len; j += 4) {
  7931. u32 val;
  7932. tg3_write_mem(tp, offset + j, test_pattern[i]);
  7933. tg3_read_mem(tp, offset + j, &val);
  7934. if (val != test_pattern[i])
  7935. return -EIO;
  7936. }
  7937. }
  7938. return 0;
  7939. }
  7940. static int tg3_test_memory(struct tg3 *tp)
  7941. {
  7942. static struct mem_entry {
  7943. u32 offset;
  7944. u32 len;
  7945. } mem_tbl_570x[] = {
  7946. { 0x00000000, 0x00b50},
  7947. { 0x00002000, 0x1c000},
  7948. { 0xffffffff, 0x00000}
  7949. }, mem_tbl_5705[] = {
  7950. { 0x00000100, 0x0000c},
  7951. { 0x00000200, 0x00008},
  7952. { 0x00004000, 0x00800},
  7953. { 0x00006000, 0x01000},
  7954. { 0x00008000, 0x02000},
  7955. { 0x00010000, 0x0e000},
  7956. { 0xffffffff, 0x00000}
  7957. }, mem_tbl_5755[] = {
  7958. { 0x00000200, 0x00008},
  7959. { 0x00004000, 0x00800},
  7960. { 0x00006000, 0x00800},
  7961. { 0x00008000, 0x02000},
  7962. { 0x00010000, 0x0c000},
  7963. { 0xffffffff, 0x00000}
  7964. }, mem_tbl_5906[] = {
  7965. { 0x00000200, 0x00008},
  7966. { 0x00004000, 0x00400},
  7967. { 0x00006000, 0x00400},
  7968. { 0x00008000, 0x01000},
  7969. { 0x00010000, 0x01000},
  7970. { 0xffffffff, 0x00000}
  7971. };
  7972. struct mem_entry *mem_tbl;
  7973. int err = 0;
  7974. int i;
  7975. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7976. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7977. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  7978. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  7979. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  7980. mem_tbl = mem_tbl_5755;
  7981. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  7982. mem_tbl = mem_tbl_5906;
  7983. else
  7984. mem_tbl = mem_tbl_5705;
  7985. } else
  7986. mem_tbl = mem_tbl_570x;
  7987. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  7988. if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
  7989. mem_tbl[i].len)) != 0)
  7990. break;
  7991. }
  7992. return err;
  7993. }
  7994. #define TG3_MAC_LOOPBACK 0
  7995. #define TG3_PHY_LOOPBACK 1
  7996. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  7997. {
  7998. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  7999. u32 desc_idx;
  8000. struct sk_buff *skb, *rx_skb;
  8001. u8 *tx_data;
  8002. dma_addr_t map;
  8003. int num_pkts, tx_len, rx_len, i, err;
  8004. struct tg3_rx_buffer_desc *desc;
  8005. if (loopback_mode == TG3_MAC_LOOPBACK) {
  8006. /* HW errata - mac loopback fails in some cases on 5780.
  8007. * Normal traffic and PHY loopback are not affected by
  8008. * errata.
  8009. */
  8010. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  8011. return 0;
  8012. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  8013. MAC_MODE_PORT_INT_LPBACK;
  8014. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  8015. mac_mode |= MAC_MODE_LINK_POLARITY;
  8016. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  8017. mac_mode |= MAC_MODE_PORT_MODE_MII;
  8018. else
  8019. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  8020. tw32(MAC_MODE, mac_mode);
  8021. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  8022. u32 val;
  8023. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8024. u32 phytest;
  8025. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
  8026. u32 phy;
  8027. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  8028. phytest | MII_TG3_EPHY_SHADOW_EN);
  8029. if (!tg3_readphy(tp, 0x1b, &phy))
  8030. tg3_writephy(tp, 0x1b, phy & ~0x20);
  8031. tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
  8032. }
  8033. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  8034. } else
  8035. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  8036. tg3_phy_toggle_automdix(tp, 0);
  8037. tg3_writephy(tp, MII_BMCR, val);
  8038. udelay(40);
  8039. mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  8040. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8041. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
  8042. mac_mode |= MAC_MODE_PORT_MODE_MII;
  8043. } else
  8044. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  8045. /* reset to prevent losing 1st rx packet intermittently */
  8046. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  8047. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8048. udelay(10);
  8049. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8050. }
  8051. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  8052. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
  8053. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  8054. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
  8055. mac_mode |= MAC_MODE_LINK_POLARITY;
  8056. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  8057. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  8058. }
  8059. tw32(MAC_MODE, mac_mode);
  8060. }
  8061. else
  8062. return -EINVAL;
  8063. err = -EIO;
  8064. tx_len = 1514;
  8065. skb = netdev_alloc_skb(tp->dev, tx_len);
  8066. if (!skb)
  8067. return -ENOMEM;
  8068. tx_data = skb_put(skb, tx_len);
  8069. memcpy(tx_data, tp->dev->dev_addr, 6);
  8070. memset(tx_data + 6, 0x0, 8);
  8071. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  8072. for (i = 14; i < tx_len; i++)
  8073. tx_data[i] = (u8) (i & 0xff);
  8074. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  8075. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8076. HOSTCC_MODE_NOW);
  8077. udelay(10);
  8078. rx_start_idx = tp->hw_status->idx[0].rx_producer;
  8079. num_pkts = 0;
  8080. tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
  8081. tp->tx_prod++;
  8082. num_pkts++;
  8083. tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
  8084. tp->tx_prod);
  8085. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
  8086. udelay(10);
  8087. /* 250 usec to allow enough time on some 10/100 Mbps devices. */
  8088. for (i = 0; i < 25; i++) {
  8089. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8090. HOSTCC_MODE_NOW);
  8091. udelay(10);
  8092. tx_idx = tp->hw_status->idx[0].tx_consumer;
  8093. rx_idx = tp->hw_status->idx[0].rx_producer;
  8094. if ((tx_idx == tp->tx_prod) &&
  8095. (rx_idx == (rx_start_idx + num_pkts)))
  8096. break;
  8097. }
  8098. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  8099. dev_kfree_skb(skb);
  8100. if (tx_idx != tp->tx_prod)
  8101. goto out;
  8102. if (rx_idx != rx_start_idx + num_pkts)
  8103. goto out;
  8104. desc = &tp->rx_rcb[rx_start_idx];
  8105. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  8106. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  8107. if (opaque_key != RXD_OPAQUE_RING_STD)
  8108. goto out;
  8109. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  8110. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  8111. goto out;
  8112. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  8113. if (rx_len != tx_len)
  8114. goto out;
  8115. rx_skb = tp->rx_std_buffers[desc_idx].skb;
  8116. map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
  8117. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  8118. for (i = 14; i < tx_len; i++) {
  8119. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  8120. goto out;
  8121. }
  8122. err = 0;
  8123. /* tg3_free_rings will unmap and free the rx_skb */
  8124. out:
  8125. return err;
  8126. }
  8127. #define TG3_MAC_LOOPBACK_FAILED 1
  8128. #define TG3_PHY_LOOPBACK_FAILED 2
  8129. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  8130. TG3_PHY_LOOPBACK_FAILED)
  8131. static int tg3_test_loopback(struct tg3 *tp)
  8132. {
  8133. int err = 0;
  8134. u32 cpmuctrl = 0;
  8135. if (!netif_running(tp->dev))
  8136. return TG3_LOOPBACK_FAILED;
  8137. err = tg3_reset_hw(tp, 1);
  8138. if (err)
  8139. return TG3_LOOPBACK_FAILED;
  8140. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  8141. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  8142. int i;
  8143. u32 status;
  8144. tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
  8145. /* Wait for up to 40 microseconds to acquire lock. */
  8146. for (i = 0; i < 4; i++) {
  8147. status = tr32(TG3_CPMU_MUTEX_GNT);
  8148. if (status == CPMU_MUTEX_GNT_DRIVER)
  8149. break;
  8150. udelay(10);
  8151. }
  8152. if (status != CPMU_MUTEX_GNT_DRIVER)
  8153. return TG3_LOOPBACK_FAILED;
  8154. /* Turn off link-based power management. */
  8155. cpmuctrl = tr32(TG3_CPMU_CTRL);
  8156. tw32(TG3_CPMU_CTRL,
  8157. cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
  8158. CPMU_CTRL_LINK_AWARE_MODE));
  8159. }
  8160. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  8161. err |= TG3_MAC_LOOPBACK_FAILED;
  8162. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  8163. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  8164. tw32(TG3_CPMU_CTRL, cpmuctrl);
  8165. /* Release the mutex */
  8166. tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
  8167. }
  8168. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  8169. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  8170. err |= TG3_PHY_LOOPBACK_FAILED;
  8171. }
  8172. return err;
  8173. }
  8174. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  8175. u64 *data)
  8176. {
  8177. struct tg3 *tp = netdev_priv(dev);
  8178. if (tp->link_config.phy_is_low_power)
  8179. tg3_set_power_state(tp, PCI_D0);
  8180. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  8181. if (tg3_test_nvram(tp) != 0) {
  8182. etest->flags |= ETH_TEST_FL_FAILED;
  8183. data[0] = 1;
  8184. }
  8185. if (tg3_test_link(tp) != 0) {
  8186. etest->flags |= ETH_TEST_FL_FAILED;
  8187. data[1] = 1;
  8188. }
  8189. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  8190. int err, irq_sync = 0;
  8191. if (netif_running(dev)) {
  8192. tg3_netif_stop(tp);
  8193. irq_sync = 1;
  8194. }
  8195. tg3_full_lock(tp, irq_sync);
  8196. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  8197. err = tg3_nvram_lock(tp);
  8198. tg3_halt_cpu(tp, RX_CPU_BASE);
  8199. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  8200. tg3_halt_cpu(tp, TX_CPU_BASE);
  8201. if (!err)
  8202. tg3_nvram_unlock(tp);
  8203. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  8204. tg3_phy_reset(tp);
  8205. if (tg3_test_registers(tp) != 0) {
  8206. etest->flags |= ETH_TEST_FL_FAILED;
  8207. data[2] = 1;
  8208. }
  8209. if (tg3_test_memory(tp) != 0) {
  8210. etest->flags |= ETH_TEST_FL_FAILED;
  8211. data[3] = 1;
  8212. }
  8213. if ((data[4] = tg3_test_loopback(tp)) != 0)
  8214. etest->flags |= ETH_TEST_FL_FAILED;
  8215. tg3_full_unlock(tp);
  8216. if (tg3_test_interrupt(tp) != 0) {
  8217. etest->flags |= ETH_TEST_FL_FAILED;
  8218. data[5] = 1;
  8219. }
  8220. tg3_full_lock(tp, 0);
  8221. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8222. if (netif_running(dev)) {
  8223. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  8224. if (!tg3_restart_hw(tp, 1))
  8225. tg3_netif_start(tp);
  8226. }
  8227. tg3_full_unlock(tp);
  8228. }
  8229. if (tp->link_config.phy_is_low_power)
  8230. tg3_set_power_state(tp, PCI_D3hot);
  8231. }
  8232. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  8233. {
  8234. struct mii_ioctl_data *data = if_mii(ifr);
  8235. struct tg3 *tp = netdev_priv(dev);
  8236. int err;
  8237. switch(cmd) {
  8238. case SIOCGMIIPHY:
  8239. data->phy_id = PHY_ADDR;
  8240. /* fallthru */
  8241. case SIOCGMIIREG: {
  8242. u32 mii_regval;
  8243. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  8244. break; /* We have no PHY */
  8245. if (tp->link_config.phy_is_low_power)
  8246. return -EAGAIN;
  8247. spin_lock_bh(&tp->lock);
  8248. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  8249. spin_unlock_bh(&tp->lock);
  8250. data->val_out = mii_regval;
  8251. return err;
  8252. }
  8253. case SIOCSMIIREG:
  8254. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  8255. break; /* We have no PHY */
  8256. if (!capable(CAP_NET_ADMIN))
  8257. return -EPERM;
  8258. if (tp->link_config.phy_is_low_power)
  8259. return -EAGAIN;
  8260. spin_lock_bh(&tp->lock);
  8261. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  8262. spin_unlock_bh(&tp->lock);
  8263. return err;
  8264. default:
  8265. /* do nothing */
  8266. break;
  8267. }
  8268. return -EOPNOTSUPP;
  8269. }
  8270. #if TG3_VLAN_TAG_USED
  8271. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  8272. {
  8273. struct tg3 *tp = netdev_priv(dev);
  8274. if (netif_running(dev))
  8275. tg3_netif_stop(tp);
  8276. tg3_full_lock(tp, 0);
  8277. tp->vlgrp = grp;
  8278. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  8279. __tg3_set_rx_mode(dev);
  8280. if (netif_running(dev))
  8281. tg3_netif_start(tp);
  8282. tg3_full_unlock(tp);
  8283. }
  8284. #endif
  8285. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  8286. {
  8287. struct tg3 *tp = netdev_priv(dev);
  8288. memcpy(ec, &tp->coal, sizeof(*ec));
  8289. return 0;
  8290. }
  8291. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  8292. {
  8293. struct tg3 *tp = netdev_priv(dev);
  8294. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  8295. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  8296. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  8297. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  8298. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  8299. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  8300. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  8301. }
  8302. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  8303. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  8304. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  8305. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  8306. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  8307. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  8308. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  8309. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  8310. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  8311. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  8312. return -EINVAL;
  8313. /* No rx interrupts will be generated if both are zero */
  8314. if ((ec->rx_coalesce_usecs == 0) &&
  8315. (ec->rx_max_coalesced_frames == 0))
  8316. return -EINVAL;
  8317. /* No tx interrupts will be generated if both are zero */
  8318. if ((ec->tx_coalesce_usecs == 0) &&
  8319. (ec->tx_max_coalesced_frames == 0))
  8320. return -EINVAL;
  8321. /* Only copy relevant parameters, ignore all others. */
  8322. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  8323. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  8324. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  8325. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  8326. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  8327. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  8328. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  8329. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  8330. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  8331. if (netif_running(dev)) {
  8332. tg3_full_lock(tp, 0);
  8333. __tg3_set_coalesce(tp, &tp->coal);
  8334. tg3_full_unlock(tp);
  8335. }
  8336. return 0;
  8337. }
  8338. static const struct ethtool_ops tg3_ethtool_ops = {
  8339. .get_settings = tg3_get_settings,
  8340. .set_settings = tg3_set_settings,
  8341. .get_drvinfo = tg3_get_drvinfo,
  8342. .get_regs_len = tg3_get_regs_len,
  8343. .get_regs = tg3_get_regs,
  8344. .get_wol = tg3_get_wol,
  8345. .set_wol = tg3_set_wol,
  8346. .get_msglevel = tg3_get_msglevel,
  8347. .set_msglevel = tg3_set_msglevel,
  8348. .nway_reset = tg3_nway_reset,
  8349. .get_link = ethtool_op_get_link,
  8350. .get_eeprom_len = tg3_get_eeprom_len,
  8351. .get_eeprom = tg3_get_eeprom,
  8352. .set_eeprom = tg3_set_eeprom,
  8353. .get_ringparam = tg3_get_ringparam,
  8354. .set_ringparam = tg3_set_ringparam,
  8355. .get_pauseparam = tg3_get_pauseparam,
  8356. .set_pauseparam = tg3_set_pauseparam,
  8357. .get_rx_csum = tg3_get_rx_csum,
  8358. .set_rx_csum = tg3_set_rx_csum,
  8359. .set_tx_csum = tg3_set_tx_csum,
  8360. .set_sg = ethtool_op_set_sg,
  8361. .set_tso = tg3_set_tso,
  8362. .self_test = tg3_self_test,
  8363. .get_strings = tg3_get_strings,
  8364. .phys_id = tg3_phys_id,
  8365. .get_ethtool_stats = tg3_get_ethtool_stats,
  8366. .get_coalesce = tg3_get_coalesce,
  8367. .set_coalesce = tg3_set_coalesce,
  8368. .get_sset_count = tg3_get_sset_count,
  8369. };
  8370. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  8371. {
  8372. u32 cursize, val, magic;
  8373. tp->nvram_size = EEPROM_CHIP_SIZE;
  8374. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  8375. return;
  8376. if ((magic != TG3_EEPROM_MAGIC) &&
  8377. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  8378. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  8379. return;
  8380. /*
  8381. * Size the chip by reading offsets at increasing powers of two.
  8382. * When we encounter our validation signature, we know the addressing
  8383. * has wrapped around, and thus have our chip size.
  8384. */
  8385. cursize = 0x10;
  8386. while (cursize < tp->nvram_size) {
  8387. if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
  8388. return;
  8389. if (val == magic)
  8390. break;
  8391. cursize <<= 1;
  8392. }
  8393. tp->nvram_size = cursize;
  8394. }
  8395. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  8396. {
  8397. u32 val;
  8398. if (tg3_nvram_read_swab(tp, 0, &val) != 0)
  8399. return;
  8400. /* Selfboot format */
  8401. if (val != TG3_EEPROM_MAGIC) {
  8402. tg3_get_eeprom_size(tp);
  8403. return;
  8404. }
  8405. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  8406. if (val != 0) {
  8407. tp->nvram_size = (val >> 16) * 1024;
  8408. return;
  8409. }
  8410. }
  8411. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  8412. }
  8413. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  8414. {
  8415. u32 nvcfg1;
  8416. nvcfg1 = tr32(NVRAM_CFG1);
  8417. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  8418. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8419. }
  8420. else {
  8421. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8422. tw32(NVRAM_CFG1, nvcfg1);
  8423. }
  8424. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  8425. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  8426. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  8427. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  8428. tp->nvram_jedecnum = JEDEC_ATMEL;
  8429. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  8430. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8431. break;
  8432. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  8433. tp->nvram_jedecnum = JEDEC_ATMEL;
  8434. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  8435. break;
  8436. case FLASH_VENDOR_ATMEL_EEPROM:
  8437. tp->nvram_jedecnum = JEDEC_ATMEL;
  8438. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8439. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8440. break;
  8441. case FLASH_VENDOR_ST:
  8442. tp->nvram_jedecnum = JEDEC_ST;
  8443. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  8444. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8445. break;
  8446. case FLASH_VENDOR_SAIFUN:
  8447. tp->nvram_jedecnum = JEDEC_SAIFUN;
  8448. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  8449. break;
  8450. case FLASH_VENDOR_SST_SMALL:
  8451. case FLASH_VENDOR_SST_LARGE:
  8452. tp->nvram_jedecnum = JEDEC_SST;
  8453. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  8454. break;
  8455. }
  8456. }
  8457. else {
  8458. tp->nvram_jedecnum = JEDEC_ATMEL;
  8459. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  8460. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8461. }
  8462. }
  8463. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  8464. {
  8465. u32 nvcfg1;
  8466. nvcfg1 = tr32(NVRAM_CFG1);
  8467. /* NVRAM protection for TPM */
  8468. if (nvcfg1 & (1 << 27))
  8469. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8470. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8471. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  8472. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  8473. tp->nvram_jedecnum = JEDEC_ATMEL;
  8474. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8475. break;
  8476. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8477. tp->nvram_jedecnum = JEDEC_ATMEL;
  8478. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8479. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8480. break;
  8481. case FLASH_5752VENDOR_ST_M45PE10:
  8482. case FLASH_5752VENDOR_ST_M45PE20:
  8483. case FLASH_5752VENDOR_ST_M45PE40:
  8484. tp->nvram_jedecnum = JEDEC_ST;
  8485. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8486. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8487. break;
  8488. }
  8489. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  8490. switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  8491. case FLASH_5752PAGE_SIZE_256:
  8492. tp->nvram_pagesize = 256;
  8493. break;
  8494. case FLASH_5752PAGE_SIZE_512:
  8495. tp->nvram_pagesize = 512;
  8496. break;
  8497. case FLASH_5752PAGE_SIZE_1K:
  8498. tp->nvram_pagesize = 1024;
  8499. break;
  8500. case FLASH_5752PAGE_SIZE_2K:
  8501. tp->nvram_pagesize = 2048;
  8502. break;
  8503. case FLASH_5752PAGE_SIZE_4K:
  8504. tp->nvram_pagesize = 4096;
  8505. break;
  8506. case FLASH_5752PAGE_SIZE_264:
  8507. tp->nvram_pagesize = 264;
  8508. break;
  8509. }
  8510. }
  8511. else {
  8512. /* For eeprom, set pagesize to maximum eeprom size */
  8513. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8514. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8515. tw32(NVRAM_CFG1, nvcfg1);
  8516. }
  8517. }
  8518. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  8519. {
  8520. u32 nvcfg1, protect = 0;
  8521. nvcfg1 = tr32(NVRAM_CFG1);
  8522. /* NVRAM protection for TPM */
  8523. if (nvcfg1 & (1 << 27)) {
  8524. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8525. protect = 1;
  8526. }
  8527. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  8528. switch (nvcfg1) {
  8529. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8530. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8531. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8532. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  8533. tp->nvram_jedecnum = JEDEC_ATMEL;
  8534. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8535. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8536. tp->nvram_pagesize = 264;
  8537. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  8538. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  8539. tp->nvram_size = (protect ? 0x3e200 :
  8540. TG3_NVRAM_SIZE_512KB);
  8541. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  8542. tp->nvram_size = (protect ? 0x1f200 :
  8543. TG3_NVRAM_SIZE_256KB);
  8544. else
  8545. tp->nvram_size = (protect ? 0x1f200 :
  8546. TG3_NVRAM_SIZE_128KB);
  8547. break;
  8548. case FLASH_5752VENDOR_ST_M45PE10:
  8549. case FLASH_5752VENDOR_ST_M45PE20:
  8550. case FLASH_5752VENDOR_ST_M45PE40:
  8551. tp->nvram_jedecnum = JEDEC_ST;
  8552. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8553. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8554. tp->nvram_pagesize = 256;
  8555. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  8556. tp->nvram_size = (protect ?
  8557. TG3_NVRAM_SIZE_64KB :
  8558. TG3_NVRAM_SIZE_128KB);
  8559. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  8560. tp->nvram_size = (protect ?
  8561. TG3_NVRAM_SIZE_64KB :
  8562. TG3_NVRAM_SIZE_256KB);
  8563. else
  8564. tp->nvram_size = (protect ?
  8565. TG3_NVRAM_SIZE_128KB :
  8566. TG3_NVRAM_SIZE_512KB);
  8567. break;
  8568. }
  8569. }
  8570. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  8571. {
  8572. u32 nvcfg1;
  8573. nvcfg1 = tr32(NVRAM_CFG1);
  8574. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8575. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  8576. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  8577. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  8578. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  8579. tp->nvram_jedecnum = JEDEC_ATMEL;
  8580. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8581. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8582. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8583. tw32(NVRAM_CFG1, nvcfg1);
  8584. break;
  8585. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8586. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8587. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8588. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8589. tp->nvram_jedecnum = JEDEC_ATMEL;
  8590. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8591. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8592. tp->nvram_pagesize = 264;
  8593. break;
  8594. case FLASH_5752VENDOR_ST_M45PE10:
  8595. case FLASH_5752VENDOR_ST_M45PE20:
  8596. case FLASH_5752VENDOR_ST_M45PE40:
  8597. tp->nvram_jedecnum = JEDEC_ST;
  8598. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8599. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8600. tp->nvram_pagesize = 256;
  8601. break;
  8602. }
  8603. }
  8604. static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
  8605. {
  8606. u32 nvcfg1, protect = 0;
  8607. nvcfg1 = tr32(NVRAM_CFG1);
  8608. /* NVRAM protection for TPM */
  8609. if (nvcfg1 & (1 << 27)) {
  8610. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8611. protect = 1;
  8612. }
  8613. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  8614. switch (nvcfg1) {
  8615. case FLASH_5761VENDOR_ATMEL_ADB021D:
  8616. case FLASH_5761VENDOR_ATMEL_ADB041D:
  8617. case FLASH_5761VENDOR_ATMEL_ADB081D:
  8618. case FLASH_5761VENDOR_ATMEL_ADB161D:
  8619. case FLASH_5761VENDOR_ATMEL_MDB021D:
  8620. case FLASH_5761VENDOR_ATMEL_MDB041D:
  8621. case FLASH_5761VENDOR_ATMEL_MDB081D:
  8622. case FLASH_5761VENDOR_ATMEL_MDB161D:
  8623. tp->nvram_jedecnum = JEDEC_ATMEL;
  8624. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8625. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8626. tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
  8627. tp->nvram_pagesize = 256;
  8628. break;
  8629. case FLASH_5761VENDOR_ST_A_M45PE20:
  8630. case FLASH_5761VENDOR_ST_A_M45PE40:
  8631. case FLASH_5761VENDOR_ST_A_M45PE80:
  8632. case FLASH_5761VENDOR_ST_A_M45PE16:
  8633. case FLASH_5761VENDOR_ST_M_M45PE20:
  8634. case FLASH_5761VENDOR_ST_M_M45PE40:
  8635. case FLASH_5761VENDOR_ST_M_M45PE80:
  8636. case FLASH_5761VENDOR_ST_M_M45PE16:
  8637. tp->nvram_jedecnum = JEDEC_ST;
  8638. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8639. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8640. tp->nvram_pagesize = 256;
  8641. break;
  8642. }
  8643. if (protect) {
  8644. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  8645. } else {
  8646. switch (nvcfg1) {
  8647. case FLASH_5761VENDOR_ATMEL_ADB161D:
  8648. case FLASH_5761VENDOR_ATMEL_MDB161D:
  8649. case FLASH_5761VENDOR_ST_A_M45PE16:
  8650. case FLASH_5761VENDOR_ST_M_M45PE16:
  8651. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  8652. break;
  8653. case FLASH_5761VENDOR_ATMEL_ADB081D:
  8654. case FLASH_5761VENDOR_ATMEL_MDB081D:
  8655. case FLASH_5761VENDOR_ST_A_M45PE80:
  8656. case FLASH_5761VENDOR_ST_M_M45PE80:
  8657. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  8658. break;
  8659. case FLASH_5761VENDOR_ATMEL_ADB041D:
  8660. case FLASH_5761VENDOR_ATMEL_MDB041D:
  8661. case FLASH_5761VENDOR_ST_A_M45PE40:
  8662. case FLASH_5761VENDOR_ST_M_M45PE40:
  8663. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  8664. break;
  8665. case FLASH_5761VENDOR_ATMEL_ADB021D:
  8666. case FLASH_5761VENDOR_ATMEL_MDB021D:
  8667. case FLASH_5761VENDOR_ST_A_M45PE20:
  8668. case FLASH_5761VENDOR_ST_M_M45PE20:
  8669. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  8670. break;
  8671. }
  8672. }
  8673. }
  8674. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  8675. {
  8676. tp->nvram_jedecnum = JEDEC_ATMEL;
  8677. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8678. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8679. }
  8680. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  8681. static void __devinit tg3_nvram_init(struct tg3 *tp)
  8682. {
  8683. tw32_f(GRC_EEPROM_ADDR,
  8684. (EEPROM_ADDR_FSM_RESET |
  8685. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  8686. EEPROM_ADDR_CLKPERD_SHIFT)));
  8687. msleep(1);
  8688. /* Enable seeprom accesses. */
  8689. tw32_f(GRC_LOCAL_CTRL,
  8690. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  8691. udelay(100);
  8692. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  8693. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  8694. tp->tg3_flags |= TG3_FLAG_NVRAM;
  8695. if (tg3_nvram_lock(tp)) {
  8696. printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
  8697. "tg3_nvram_init failed.\n", tp->dev->name);
  8698. return;
  8699. }
  8700. tg3_enable_nvram_access(tp);
  8701. tp->nvram_size = 0;
  8702. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  8703. tg3_get_5752_nvram_info(tp);
  8704. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  8705. tg3_get_5755_nvram_info(tp);
  8706. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  8707. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  8708. tg3_get_5787_nvram_info(tp);
  8709. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  8710. tg3_get_5761_nvram_info(tp);
  8711. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8712. tg3_get_5906_nvram_info(tp);
  8713. else
  8714. tg3_get_nvram_info(tp);
  8715. if (tp->nvram_size == 0)
  8716. tg3_get_nvram_size(tp);
  8717. tg3_disable_nvram_access(tp);
  8718. tg3_nvram_unlock(tp);
  8719. } else {
  8720. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  8721. tg3_get_eeprom_size(tp);
  8722. }
  8723. }
  8724. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  8725. u32 offset, u32 *val)
  8726. {
  8727. u32 tmp;
  8728. int i;
  8729. if (offset > EEPROM_ADDR_ADDR_MASK ||
  8730. (offset % 4) != 0)
  8731. return -EINVAL;
  8732. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  8733. EEPROM_ADDR_DEVID_MASK |
  8734. EEPROM_ADDR_READ);
  8735. tw32(GRC_EEPROM_ADDR,
  8736. tmp |
  8737. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8738. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  8739. EEPROM_ADDR_ADDR_MASK) |
  8740. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  8741. for (i = 0; i < 1000; i++) {
  8742. tmp = tr32(GRC_EEPROM_ADDR);
  8743. if (tmp & EEPROM_ADDR_COMPLETE)
  8744. break;
  8745. msleep(1);
  8746. }
  8747. if (!(tmp & EEPROM_ADDR_COMPLETE))
  8748. return -EBUSY;
  8749. *val = tr32(GRC_EEPROM_DATA);
  8750. return 0;
  8751. }
  8752. #define NVRAM_CMD_TIMEOUT 10000
  8753. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  8754. {
  8755. int i;
  8756. tw32(NVRAM_CMD, nvram_cmd);
  8757. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  8758. udelay(10);
  8759. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  8760. udelay(10);
  8761. break;
  8762. }
  8763. }
  8764. if (i == NVRAM_CMD_TIMEOUT) {
  8765. return -EBUSY;
  8766. }
  8767. return 0;
  8768. }
  8769. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  8770. {
  8771. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8772. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8773. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8774. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  8775. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8776. addr = ((addr / tp->nvram_pagesize) <<
  8777. ATMEL_AT45DB0X1B_PAGE_POS) +
  8778. (addr % tp->nvram_pagesize);
  8779. return addr;
  8780. }
  8781. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  8782. {
  8783. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8784. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8785. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8786. !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
  8787. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8788. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  8789. tp->nvram_pagesize) +
  8790. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  8791. return addr;
  8792. }
  8793. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  8794. {
  8795. int ret;
  8796. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  8797. return tg3_nvram_read_using_eeprom(tp, offset, val);
  8798. offset = tg3_nvram_phys_addr(tp, offset);
  8799. if (offset > NVRAM_ADDR_MSK)
  8800. return -EINVAL;
  8801. ret = tg3_nvram_lock(tp);
  8802. if (ret)
  8803. return ret;
  8804. tg3_enable_nvram_access(tp);
  8805. tw32(NVRAM_ADDR, offset);
  8806. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  8807. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  8808. if (ret == 0)
  8809. *val = swab32(tr32(NVRAM_RDDATA));
  8810. tg3_disable_nvram_access(tp);
  8811. tg3_nvram_unlock(tp);
  8812. return ret;
  8813. }
  8814. static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
  8815. {
  8816. u32 v;
  8817. int res = tg3_nvram_read(tp, offset, &v);
  8818. if (!res)
  8819. *val = cpu_to_le32(v);
  8820. return res;
  8821. }
  8822. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
  8823. {
  8824. int err;
  8825. u32 tmp;
  8826. err = tg3_nvram_read(tp, offset, &tmp);
  8827. *val = swab32(tmp);
  8828. return err;
  8829. }
  8830. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  8831. u32 offset, u32 len, u8 *buf)
  8832. {
  8833. int i, j, rc = 0;
  8834. u32 val;
  8835. for (i = 0; i < len; i += 4) {
  8836. u32 addr;
  8837. __le32 data;
  8838. addr = offset + i;
  8839. memcpy(&data, buf + i, 4);
  8840. tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
  8841. val = tr32(GRC_EEPROM_ADDR);
  8842. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  8843. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  8844. EEPROM_ADDR_READ);
  8845. tw32(GRC_EEPROM_ADDR, val |
  8846. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8847. (addr & EEPROM_ADDR_ADDR_MASK) |
  8848. EEPROM_ADDR_START |
  8849. EEPROM_ADDR_WRITE);
  8850. for (j = 0; j < 1000; j++) {
  8851. val = tr32(GRC_EEPROM_ADDR);
  8852. if (val & EEPROM_ADDR_COMPLETE)
  8853. break;
  8854. msleep(1);
  8855. }
  8856. if (!(val & EEPROM_ADDR_COMPLETE)) {
  8857. rc = -EBUSY;
  8858. break;
  8859. }
  8860. }
  8861. return rc;
  8862. }
  8863. /* offset and length are dword aligned */
  8864. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  8865. u8 *buf)
  8866. {
  8867. int ret = 0;
  8868. u32 pagesize = tp->nvram_pagesize;
  8869. u32 pagemask = pagesize - 1;
  8870. u32 nvram_cmd;
  8871. u8 *tmp;
  8872. tmp = kmalloc(pagesize, GFP_KERNEL);
  8873. if (tmp == NULL)
  8874. return -ENOMEM;
  8875. while (len) {
  8876. int j;
  8877. u32 phy_addr, page_off, size;
  8878. phy_addr = offset & ~pagemask;
  8879. for (j = 0; j < pagesize; j += 4) {
  8880. if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
  8881. (__le32 *) (tmp + j))))
  8882. break;
  8883. }
  8884. if (ret)
  8885. break;
  8886. page_off = offset & pagemask;
  8887. size = pagesize;
  8888. if (len < size)
  8889. size = len;
  8890. len -= size;
  8891. memcpy(tmp + page_off, buf, size);
  8892. offset = offset + (pagesize - page_off);
  8893. tg3_enable_nvram_access(tp);
  8894. /*
  8895. * Before we can erase the flash page, we need
  8896. * to issue a special "write enable" command.
  8897. */
  8898. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8899. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8900. break;
  8901. /* Erase the target page */
  8902. tw32(NVRAM_ADDR, phy_addr);
  8903. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  8904. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  8905. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8906. break;
  8907. /* Issue another write enable to start the write. */
  8908. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8909. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8910. break;
  8911. for (j = 0; j < pagesize; j += 4) {
  8912. __be32 data;
  8913. data = *((__be32 *) (tmp + j));
  8914. /* swab32(le32_to_cpu(data)), actually */
  8915. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  8916. tw32(NVRAM_ADDR, phy_addr + j);
  8917. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  8918. NVRAM_CMD_WR;
  8919. if (j == 0)
  8920. nvram_cmd |= NVRAM_CMD_FIRST;
  8921. else if (j == (pagesize - 4))
  8922. nvram_cmd |= NVRAM_CMD_LAST;
  8923. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8924. break;
  8925. }
  8926. if (ret)
  8927. break;
  8928. }
  8929. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8930. tg3_nvram_exec_cmd(tp, nvram_cmd);
  8931. kfree(tmp);
  8932. return ret;
  8933. }
  8934. /* offset and length are dword aligned */
  8935. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  8936. u8 *buf)
  8937. {
  8938. int i, ret = 0;
  8939. for (i = 0; i < len; i += 4, offset += 4) {
  8940. u32 page_off, phy_addr, nvram_cmd;
  8941. __be32 data;
  8942. memcpy(&data, buf + i, 4);
  8943. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  8944. page_off = offset % tp->nvram_pagesize;
  8945. phy_addr = tg3_nvram_phys_addr(tp, offset);
  8946. tw32(NVRAM_ADDR, phy_addr);
  8947. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  8948. if ((page_off == 0) || (i == 0))
  8949. nvram_cmd |= NVRAM_CMD_FIRST;
  8950. if (page_off == (tp->nvram_pagesize - 4))
  8951. nvram_cmd |= NVRAM_CMD_LAST;
  8952. if (i == (len - 4))
  8953. nvram_cmd |= NVRAM_CMD_LAST;
  8954. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
  8955. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
  8956. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
  8957. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
  8958. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
  8959. (tp->nvram_jedecnum == JEDEC_ST) &&
  8960. (nvram_cmd & NVRAM_CMD_FIRST)) {
  8961. if ((ret = tg3_nvram_exec_cmd(tp,
  8962. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  8963. NVRAM_CMD_DONE)))
  8964. break;
  8965. }
  8966. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8967. /* We always do complete word writes to eeprom. */
  8968. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  8969. }
  8970. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8971. break;
  8972. }
  8973. return ret;
  8974. }
  8975. /* offset and length are dword aligned */
  8976. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  8977. {
  8978. int ret;
  8979. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8980. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  8981. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  8982. udelay(40);
  8983. }
  8984. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  8985. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  8986. }
  8987. else {
  8988. u32 grc_mode;
  8989. ret = tg3_nvram_lock(tp);
  8990. if (ret)
  8991. return ret;
  8992. tg3_enable_nvram_access(tp);
  8993. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  8994. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
  8995. tw32(NVRAM_WRITE1, 0x406);
  8996. grc_mode = tr32(GRC_MODE);
  8997. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  8998. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  8999. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  9000. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  9001. buf);
  9002. }
  9003. else {
  9004. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  9005. buf);
  9006. }
  9007. grc_mode = tr32(GRC_MODE);
  9008. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  9009. tg3_disable_nvram_access(tp);
  9010. tg3_nvram_unlock(tp);
  9011. }
  9012. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  9013. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  9014. udelay(40);
  9015. }
  9016. return ret;
  9017. }
  9018. struct subsys_tbl_ent {
  9019. u16 subsys_vendor, subsys_devid;
  9020. u32 phy_id;
  9021. };
  9022. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  9023. /* Broadcom boards. */
  9024. { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  9025. { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  9026. { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  9027. { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
  9028. { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  9029. { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  9030. { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
  9031. { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  9032. { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  9033. { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
  9034. { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
  9035. /* 3com boards. */
  9036. { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  9037. { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  9038. { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
  9039. { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  9040. { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  9041. /* DELL boards. */
  9042. { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  9043. { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  9044. { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  9045. { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  9046. /* Compaq boards. */
  9047. { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  9048. { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  9049. { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
  9050. { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  9051. { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
  9052. /* IBM boards. */
  9053. { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
  9054. };
  9055. static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
  9056. {
  9057. int i;
  9058. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  9059. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  9060. tp->pdev->subsystem_vendor) &&
  9061. (subsys_id_to_phy_id[i].subsys_devid ==
  9062. tp->pdev->subsystem_device))
  9063. return &subsys_id_to_phy_id[i];
  9064. }
  9065. return NULL;
  9066. }
  9067. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  9068. {
  9069. u32 val;
  9070. u16 pmcsr;
  9071. /* On some early chips the SRAM cannot be accessed in D3hot state,
  9072. * so need make sure we're in D0.
  9073. */
  9074. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  9075. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  9076. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  9077. msleep(1);
  9078. /* Make sure register accesses (indirect or otherwise)
  9079. * will function correctly.
  9080. */
  9081. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9082. tp->misc_host_ctrl);
  9083. /* The memory arbiter has to be enabled in order for SRAM accesses
  9084. * to succeed. Normally on powerup the tg3 chip firmware will make
  9085. * sure it is enabled, but other entities such as system netboot
  9086. * code might disable it.
  9087. */
  9088. val = tr32(MEMARB_MODE);
  9089. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  9090. tp->phy_id = PHY_ID_INVALID;
  9091. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9092. /* Assume an onboard device and WOL capable by default. */
  9093. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
  9094. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9095. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  9096. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  9097. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  9098. }
  9099. val = tr32(VCPU_CFGSHDW);
  9100. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  9101. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  9102. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  9103. (val & VCPU_CFGSHDW_WOL_MAGPKT))
  9104. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  9105. return;
  9106. }
  9107. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  9108. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  9109. u32 nic_cfg, led_cfg;
  9110. u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
  9111. int eeprom_phy_serdes = 0;
  9112. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  9113. tp->nic_sram_data_cfg = nic_cfg;
  9114. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  9115. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  9116. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  9117. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  9118. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  9119. (ver > 0) && (ver < 0x100))
  9120. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  9121. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  9122. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  9123. eeprom_phy_serdes = 1;
  9124. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  9125. if (nic_phy_id != 0) {
  9126. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  9127. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  9128. eeprom_phy_id = (id1 >> 16) << 10;
  9129. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  9130. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  9131. } else
  9132. eeprom_phy_id = 0;
  9133. tp->phy_id = eeprom_phy_id;
  9134. if (eeprom_phy_serdes) {
  9135. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  9136. tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
  9137. else
  9138. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  9139. }
  9140. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  9141. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  9142. SHASTA_EXT_LED_MODE_MASK);
  9143. else
  9144. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  9145. switch (led_cfg) {
  9146. default:
  9147. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  9148. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9149. break;
  9150. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  9151. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  9152. break;
  9153. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  9154. tp->led_ctrl = LED_CTRL_MODE_MAC;
  9155. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  9156. * read on some older 5700/5701 bootcode.
  9157. */
  9158. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9159. ASIC_REV_5700 ||
  9160. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9161. ASIC_REV_5701)
  9162. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9163. break;
  9164. case SHASTA_EXT_LED_SHARED:
  9165. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  9166. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  9167. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  9168. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  9169. LED_CTRL_MODE_PHY_2);
  9170. break;
  9171. case SHASTA_EXT_LED_MAC:
  9172. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  9173. break;
  9174. case SHASTA_EXT_LED_COMBO:
  9175. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  9176. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  9177. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  9178. LED_CTRL_MODE_PHY_2);
  9179. break;
  9180. };
  9181. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9182. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  9183. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  9184. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  9185. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
  9186. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  9187. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  9188. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  9189. if ((tp->pdev->subsystem_vendor ==
  9190. PCI_VENDOR_ID_ARIMA) &&
  9191. (tp->pdev->subsystem_device == 0x205a ||
  9192. tp->pdev->subsystem_device == 0x2063))
  9193. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  9194. } else {
  9195. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  9196. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  9197. }
  9198. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  9199. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  9200. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  9201. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  9202. }
  9203. if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
  9204. tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
  9205. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
  9206. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  9207. tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
  9208. if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
  9209. nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
  9210. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  9211. if (cfg2 & (1 << 17))
  9212. tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
  9213. /* serdes signal pre-emphasis in register 0x590 set by */
  9214. /* bootcode if bit 18 is set */
  9215. if (cfg2 & (1 << 18))
  9216. tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
  9217. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9218. u32 cfg3;
  9219. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  9220. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  9221. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  9222. }
  9223. }
  9224. }
  9225. static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  9226. {
  9227. int i;
  9228. u32 val;
  9229. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  9230. tw32(OTP_CTRL, cmd);
  9231. /* Wait for up to 1 ms for command to execute. */
  9232. for (i = 0; i < 100; i++) {
  9233. val = tr32(OTP_STATUS);
  9234. if (val & OTP_STATUS_CMD_DONE)
  9235. break;
  9236. udelay(10);
  9237. }
  9238. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  9239. }
  9240. /* Read the gphy configuration from the OTP region of the chip. The gphy
  9241. * configuration is a 32-bit value that straddles the alignment boundary.
  9242. * We do two 32-bit reads and then shift and merge the results.
  9243. */
  9244. static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
  9245. {
  9246. u32 bhalf_otp, thalf_otp;
  9247. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  9248. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  9249. return 0;
  9250. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  9251. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  9252. return 0;
  9253. thalf_otp = tr32(OTP_READ_DATA);
  9254. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  9255. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  9256. return 0;
  9257. bhalf_otp = tr32(OTP_READ_DATA);
  9258. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  9259. }
  9260. static int __devinit tg3_phy_probe(struct tg3 *tp)
  9261. {
  9262. u32 hw_phy_id_1, hw_phy_id_2;
  9263. u32 hw_phy_id, hw_phy_id_masked;
  9264. int err;
  9265. /* Reading the PHY ID register can conflict with ASF
  9266. * firwmare access to the PHY hardware.
  9267. */
  9268. err = 0;
  9269. if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  9270. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
  9271. hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
  9272. } else {
  9273. /* Now read the physical PHY_ID from the chip and verify
  9274. * that it is sane. If it doesn't look good, we fall back
  9275. * to either the hard-coded table based PHY_ID and failing
  9276. * that the value found in the eeprom area.
  9277. */
  9278. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  9279. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  9280. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  9281. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  9282. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  9283. hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  9284. }
  9285. if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  9286. tp->phy_id = hw_phy_id;
  9287. if (hw_phy_id_masked == PHY_ID_BCM8002)
  9288. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  9289. else
  9290. tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
  9291. } else {
  9292. if (tp->phy_id != PHY_ID_INVALID) {
  9293. /* Do nothing, phy ID already set up in
  9294. * tg3_get_eeprom_hw_cfg().
  9295. */
  9296. } else {
  9297. struct subsys_tbl_ent *p;
  9298. /* No eeprom signature? Try the hardcoded
  9299. * subsys device table.
  9300. */
  9301. p = lookup_by_subsys(tp);
  9302. if (!p)
  9303. return -ENODEV;
  9304. tp->phy_id = p->phy_id;
  9305. if (!tp->phy_id ||
  9306. tp->phy_id == PHY_ID_BCM8002)
  9307. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  9308. }
  9309. }
  9310. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
  9311. !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
  9312. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  9313. u32 bmsr, adv_reg, tg3_ctrl, mask;
  9314. tg3_readphy(tp, MII_BMSR, &bmsr);
  9315. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  9316. (bmsr & BMSR_LSTATUS))
  9317. goto skip_phy_reset;
  9318. err = tg3_phy_reset(tp);
  9319. if (err)
  9320. return err;
  9321. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  9322. ADVERTISE_100HALF | ADVERTISE_100FULL |
  9323. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  9324. tg3_ctrl = 0;
  9325. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  9326. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  9327. MII_TG3_CTRL_ADV_1000_FULL);
  9328. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  9329. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  9330. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  9331. MII_TG3_CTRL_ENABLE_AS_MASTER);
  9332. }
  9333. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  9334. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  9335. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  9336. if (!tg3_copper_is_advertising_all(tp, mask)) {
  9337. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  9338. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  9339. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  9340. tg3_writephy(tp, MII_BMCR,
  9341. BMCR_ANENABLE | BMCR_ANRESTART);
  9342. }
  9343. tg3_phy_set_wirespeed(tp);
  9344. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  9345. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  9346. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  9347. }
  9348. skip_phy_reset:
  9349. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  9350. err = tg3_init_5401phy_dsp(tp);
  9351. if (err)
  9352. return err;
  9353. }
  9354. if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  9355. err = tg3_init_5401phy_dsp(tp);
  9356. }
  9357. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  9358. tp->link_config.advertising =
  9359. (ADVERTISED_1000baseT_Half |
  9360. ADVERTISED_1000baseT_Full |
  9361. ADVERTISED_Autoneg |
  9362. ADVERTISED_FIBRE);
  9363. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  9364. tp->link_config.advertising &=
  9365. ~(ADVERTISED_1000baseT_Half |
  9366. ADVERTISED_1000baseT_Full);
  9367. return err;
  9368. }
  9369. static void __devinit tg3_read_partno(struct tg3 *tp)
  9370. {
  9371. unsigned char vpd_data[256];
  9372. unsigned int i;
  9373. u32 magic;
  9374. if (tg3_nvram_read_swab(tp, 0x0, &magic))
  9375. goto out_not_found;
  9376. if (magic == TG3_EEPROM_MAGIC) {
  9377. for (i = 0; i < 256; i += 4) {
  9378. u32 tmp;
  9379. if (tg3_nvram_read(tp, 0x100 + i, &tmp))
  9380. goto out_not_found;
  9381. vpd_data[i + 0] = ((tmp >> 0) & 0xff);
  9382. vpd_data[i + 1] = ((tmp >> 8) & 0xff);
  9383. vpd_data[i + 2] = ((tmp >> 16) & 0xff);
  9384. vpd_data[i + 3] = ((tmp >> 24) & 0xff);
  9385. }
  9386. } else {
  9387. int vpd_cap;
  9388. vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
  9389. for (i = 0; i < 256; i += 4) {
  9390. u32 tmp, j = 0;
  9391. __le32 v;
  9392. u16 tmp16;
  9393. pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
  9394. i);
  9395. while (j++ < 100) {
  9396. pci_read_config_word(tp->pdev, vpd_cap +
  9397. PCI_VPD_ADDR, &tmp16);
  9398. if (tmp16 & 0x8000)
  9399. break;
  9400. msleep(1);
  9401. }
  9402. if (!(tmp16 & 0x8000))
  9403. goto out_not_found;
  9404. pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
  9405. &tmp);
  9406. v = cpu_to_le32(tmp);
  9407. memcpy(&vpd_data[i], &v, 4);
  9408. }
  9409. }
  9410. /* Now parse and find the part number. */
  9411. for (i = 0; i < 254; ) {
  9412. unsigned char val = vpd_data[i];
  9413. unsigned int block_end;
  9414. if (val == 0x82 || val == 0x91) {
  9415. i = (i + 3 +
  9416. (vpd_data[i + 1] +
  9417. (vpd_data[i + 2] << 8)));
  9418. continue;
  9419. }
  9420. if (val != 0x90)
  9421. goto out_not_found;
  9422. block_end = (i + 3 +
  9423. (vpd_data[i + 1] +
  9424. (vpd_data[i + 2] << 8)));
  9425. i += 3;
  9426. if (block_end > 256)
  9427. goto out_not_found;
  9428. while (i < (block_end - 2)) {
  9429. if (vpd_data[i + 0] == 'P' &&
  9430. vpd_data[i + 1] == 'N') {
  9431. int partno_len = vpd_data[i + 2];
  9432. i += 3;
  9433. if (partno_len > 24 || (partno_len + i) > 256)
  9434. goto out_not_found;
  9435. memcpy(tp->board_part_number,
  9436. &vpd_data[i], partno_len);
  9437. /* Success. */
  9438. return;
  9439. }
  9440. i += 3 + vpd_data[i + 2];
  9441. }
  9442. /* Part number not found. */
  9443. goto out_not_found;
  9444. }
  9445. out_not_found:
  9446. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9447. strcpy(tp->board_part_number, "BCM95906");
  9448. else
  9449. strcpy(tp->board_part_number, "none");
  9450. }
  9451. static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  9452. {
  9453. u32 val;
  9454. if (tg3_nvram_read_swab(tp, offset, &val) ||
  9455. (val & 0xfc000000) != 0x0c000000 ||
  9456. tg3_nvram_read_swab(tp, offset + 4, &val) ||
  9457. val != 0)
  9458. return 0;
  9459. return 1;
  9460. }
  9461. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  9462. {
  9463. u32 val, offset, start;
  9464. u32 ver_offset;
  9465. int i, bcnt;
  9466. if (tg3_nvram_read_swab(tp, 0, &val))
  9467. return;
  9468. if (val != TG3_EEPROM_MAGIC)
  9469. return;
  9470. if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
  9471. tg3_nvram_read_swab(tp, 0x4, &start))
  9472. return;
  9473. offset = tg3_nvram_logical_addr(tp, offset);
  9474. if (!tg3_fw_img_is_valid(tp, offset) ||
  9475. tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
  9476. return;
  9477. offset = offset + ver_offset - start;
  9478. for (i = 0; i < 16; i += 4) {
  9479. __le32 v;
  9480. if (tg3_nvram_read_le(tp, offset + i, &v))
  9481. return;
  9482. memcpy(tp->fw_ver + i, &v, 4);
  9483. }
  9484. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
  9485. (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
  9486. return;
  9487. for (offset = TG3_NVM_DIR_START;
  9488. offset < TG3_NVM_DIR_END;
  9489. offset += TG3_NVM_DIRENT_SIZE) {
  9490. if (tg3_nvram_read_swab(tp, offset, &val))
  9491. return;
  9492. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  9493. break;
  9494. }
  9495. if (offset == TG3_NVM_DIR_END)
  9496. return;
  9497. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  9498. start = 0x08000000;
  9499. else if (tg3_nvram_read_swab(tp, offset - 4, &start))
  9500. return;
  9501. if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
  9502. !tg3_fw_img_is_valid(tp, offset) ||
  9503. tg3_nvram_read_swab(tp, offset + 8, &val))
  9504. return;
  9505. offset += val - start;
  9506. bcnt = strlen(tp->fw_ver);
  9507. tp->fw_ver[bcnt++] = ',';
  9508. tp->fw_ver[bcnt++] = ' ';
  9509. for (i = 0; i < 4; i++) {
  9510. __le32 v;
  9511. if (tg3_nvram_read_le(tp, offset, &v))
  9512. return;
  9513. offset += sizeof(v);
  9514. if (bcnt > TG3_VER_SIZE - sizeof(v)) {
  9515. memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
  9516. break;
  9517. }
  9518. memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
  9519. bcnt += sizeof(v);
  9520. }
  9521. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  9522. }
  9523. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  9524. static int __devinit tg3_get_invariants(struct tg3 *tp)
  9525. {
  9526. static struct pci_device_id write_reorder_chipsets[] = {
  9527. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  9528. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  9529. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  9530. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  9531. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  9532. PCI_DEVICE_ID_VIA_8385_0) },
  9533. { },
  9534. };
  9535. u32 misc_ctrl_reg;
  9536. u32 cacheline_sz_reg;
  9537. u32 pci_state_reg, grc_misc_cfg;
  9538. u32 val;
  9539. u16 pci_cmd;
  9540. int err, pcie_cap;
  9541. /* Force memory write invalidate off. If we leave it on,
  9542. * then on 5700_BX chips we have to enable a workaround.
  9543. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  9544. * to match the cacheline size. The Broadcom driver have this
  9545. * workaround but turns MWI off all the times so never uses
  9546. * it. This seems to suggest that the workaround is insufficient.
  9547. */
  9548. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9549. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  9550. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9551. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  9552. * has the register indirect write enable bit set before
  9553. * we try to access any of the MMIO registers. It is also
  9554. * critical that the PCI-X hw workaround situation is decided
  9555. * before that as well.
  9556. */
  9557. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9558. &misc_ctrl_reg);
  9559. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  9560. MISC_HOST_CTRL_CHIPREV_SHIFT);
  9561. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
  9562. u32 prod_id_asic_rev;
  9563. pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
  9564. &prod_id_asic_rev);
  9565. tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
  9566. }
  9567. /* Wrong chip ID in 5752 A0. This code can be removed later
  9568. * as A0 is not in production.
  9569. */
  9570. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  9571. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  9572. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  9573. * we need to disable memory and use config. cycles
  9574. * only to access all registers. The 5702/03 chips
  9575. * can mistakenly decode the special cycles from the
  9576. * ICH chipsets as memory write cycles, causing corruption
  9577. * of register and memory space. Only certain ICH bridges
  9578. * will drive special cycles with non-zero data during the
  9579. * address phase which can fall within the 5703's address
  9580. * range. This is not an ICH bug as the PCI spec allows
  9581. * non-zero address during special cycles. However, only
  9582. * these ICH bridges are known to drive non-zero addresses
  9583. * during special cycles.
  9584. *
  9585. * Since special cycles do not cross PCI bridges, we only
  9586. * enable this workaround if the 5703 is on the secondary
  9587. * bus of these ICH bridges.
  9588. */
  9589. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  9590. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  9591. static struct tg3_dev_id {
  9592. u32 vendor;
  9593. u32 device;
  9594. u32 rev;
  9595. } ich_chipsets[] = {
  9596. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  9597. PCI_ANY_ID },
  9598. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  9599. PCI_ANY_ID },
  9600. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  9601. 0xa },
  9602. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  9603. PCI_ANY_ID },
  9604. { },
  9605. };
  9606. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  9607. struct pci_dev *bridge = NULL;
  9608. while (pci_id->vendor != 0) {
  9609. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  9610. bridge);
  9611. if (!bridge) {
  9612. pci_id++;
  9613. continue;
  9614. }
  9615. if (pci_id->rev != PCI_ANY_ID) {
  9616. if (bridge->revision > pci_id->rev)
  9617. continue;
  9618. }
  9619. if (bridge->subordinate &&
  9620. (bridge->subordinate->number ==
  9621. tp->pdev->bus->number)) {
  9622. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  9623. pci_dev_put(bridge);
  9624. break;
  9625. }
  9626. }
  9627. }
  9628. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  9629. static struct tg3_dev_id {
  9630. u32 vendor;
  9631. u32 device;
  9632. } bridge_chipsets[] = {
  9633. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  9634. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  9635. { },
  9636. };
  9637. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  9638. struct pci_dev *bridge = NULL;
  9639. while (pci_id->vendor != 0) {
  9640. bridge = pci_get_device(pci_id->vendor,
  9641. pci_id->device,
  9642. bridge);
  9643. if (!bridge) {
  9644. pci_id++;
  9645. continue;
  9646. }
  9647. if (bridge->subordinate &&
  9648. (bridge->subordinate->number <=
  9649. tp->pdev->bus->number) &&
  9650. (bridge->subordinate->subordinate >=
  9651. tp->pdev->bus->number)) {
  9652. tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
  9653. pci_dev_put(bridge);
  9654. break;
  9655. }
  9656. }
  9657. }
  9658. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  9659. * DMA addresses > 40-bit. This bridge may have other additional
  9660. * 57xx devices behind it in some 4-port NIC designs for example.
  9661. * Any tg3 device found behind the bridge will also need the 40-bit
  9662. * DMA workaround.
  9663. */
  9664. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  9665. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  9666. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  9667. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  9668. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  9669. }
  9670. else {
  9671. struct pci_dev *bridge = NULL;
  9672. do {
  9673. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  9674. PCI_DEVICE_ID_SERVERWORKS_EPB,
  9675. bridge);
  9676. if (bridge && bridge->subordinate &&
  9677. (bridge->subordinate->number <=
  9678. tp->pdev->bus->number) &&
  9679. (bridge->subordinate->subordinate >=
  9680. tp->pdev->bus->number)) {
  9681. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  9682. pci_dev_put(bridge);
  9683. break;
  9684. }
  9685. } while (bridge);
  9686. }
  9687. /* Initialize misc host control in PCI block. */
  9688. tp->misc_host_ctrl |= (misc_ctrl_reg &
  9689. MISC_HOST_CTRL_CHIPREV);
  9690. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9691. tp->misc_host_ctrl);
  9692. pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  9693. &cacheline_sz_reg);
  9694. tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
  9695. tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
  9696. tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
  9697. tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
  9698. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  9699. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
  9700. tp->pdev_peer = tg3_find_peer(tp);
  9701. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  9702. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  9703. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9704. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9705. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9706. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  9707. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  9708. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  9709. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  9710. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  9711. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  9712. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  9713. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  9714. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
  9715. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  9716. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  9717. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  9718. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  9719. tp->pdev_peer == tp->pdev))
  9720. tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
  9721. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9722. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9723. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9724. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  9725. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9726. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  9727. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  9728. } else {
  9729. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  9730. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9731. ASIC_REV_5750 &&
  9732. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  9733. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  9734. }
  9735. }
  9736. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
  9737. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
  9738. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  9739. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
  9740. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
  9741. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  9742. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
  9743. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9744. tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
  9745. pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  9746. if (pcie_cap != 0) {
  9747. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  9748. pcie_set_readrq(tp->pdev, 4096);
  9749. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9750. u16 lnkctl;
  9751. pci_read_config_word(tp->pdev,
  9752. pcie_cap + PCI_EXP_LNKCTL,
  9753. &lnkctl);
  9754. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
  9755. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  9756. }
  9757. }
  9758. /* If we have an AMD 762 or VIA K8T800 chipset, write
  9759. * reordering to the mailbox registers done by the host
  9760. * controller can cause major troubles. We read back from
  9761. * every mailbox register write to force the writes to be
  9762. * posted to the chip in order.
  9763. */
  9764. if (pci_dev_present(write_reorder_chipsets) &&
  9765. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  9766. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  9767. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  9768. tp->pci_lat_timer < 64) {
  9769. tp->pci_lat_timer = 64;
  9770. cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
  9771. cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
  9772. cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
  9773. cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
  9774. pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  9775. cacheline_sz_reg);
  9776. }
  9777. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  9778. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9779. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  9780. if (!tp->pcix_cap) {
  9781. printk(KERN_ERR PFX "Cannot find PCI-X "
  9782. "capability, aborting.\n");
  9783. return -EIO;
  9784. }
  9785. }
  9786. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9787. &pci_state_reg);
  9788. if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
  9789. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  9790. /* If this is a 5700 BX chipset, and we are in PCI-X
  9791. * mode, enable register write workaround.
  9792. *
  9793. * The workaround is to use indirect register accesses
  9794. * for all chip writes not to mailbox registers.
  9795. */
  9796. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  9797. u32 pm_reg;
  9798. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  9799. /* The chip can have it's power management PCI config
  9800. * space registers clobbered due to this bug.
  9801. * So explicitly force the chip into D0 here.
  9802. */
  9803. pci_read_config_dword(tp->pdev,
  9804. tp->pm_cap + PCI_PM_CTRL,
  9805. &pm_reg);
  9806. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  9807. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  9808. pci_write_config_dword(tp->pdev,
  9809. tp->pm_cap + PCI_PM_CTRL,
  9810. pm_reg);
  9811. /* Also, force SERR#/PERR# in PCI command. */
  9812. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9813. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  9814. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9815. }
  9816. }
  9817. /* 5700 BX chips need to have their TX producer index mailboxes
  9818. * written twice to workaround a bug.
  9819. */
  9820. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
  9821. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  9822. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  9823. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  9824. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  9825. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  9826. /* Chip-specific fixup from Broadcom driver */
  9827. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  9828. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  9829. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  9830. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  9831. }
  9832. /* Default fast path register access methods */
  9833. tp->read32 = tg3_read32;
  9834. tp->write32 = tg3_write32;
  9835. tp->read32_mbox = tg3_read32;
  9836. tp->write32_mbox = tg3_write32;
  9837. tp->write32_tx_mbox = tg3_write32;
  9838. tp->write32_rx_mbox = tg3_write32;
  9839. /* Various workaround register access methods */
  9840. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  9841. tp->write32 = tg3_write_indirect_reg32;
  9842. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  9843. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  9844. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  9845. /*
  9846. * Back to back register writes can cause problems on these
  9847. * chips, the workaround is to read back all reg writes
  9848. * except those to mailbox regs.
  9849. *
  9850. * See tg3_write_indirect_reg32().
  9851. */
  9852. tp->write32 = tg3_write_flush_reg32;
  9853. }
  9854. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  9855. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  9856. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  9857. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  9858. tp->write32_rx_mbox = tg3_write_flush_reg32;
  9859. }
  9860. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  9861. tp->read32 = tg3_read_indirect_reg32;
  9862. tp->write32 = tg3_write_indirect_reg32;
  9863. tp->read32_mbox = tg3_read_indirect_mbox;
  9864. tp->write32_mbox = tg3_write_indirect_mbox;
  9865. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  9866. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  9867. iounmap(tp->regs);
  9868. tp->regs = NULL;
  9869. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9870. pci_cmd &= ~PCI_COMMAND_MEMORY;
  9871. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9872. }
  9873. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9874. tp->read32_mbox = tg3_read32_mbox_5906;
  9875. tp->write32_mbox = tg3_write32_mbox_5906;
  9876. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  9877. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  9878. }
  9879. if (tp->write32 == tg3_write_indirect_reg32 ||
  9880. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9881. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9882. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  9883. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  9884. /* Get eeprom hw config before calling tg3_set_power_state().
  9885. * In particular, the TG3_FLG2_IS_NIC flag must be
  9886. * determined before calling tg3_set_power_state() so that
  9887. * we know whether or not to switch out of Vaux power.
  9888. * When the flag is set, it means that GPIO1 is used for eeprom
  9889. * write protect and also implies that it is a LOM where GPIOs
  9890. * are not used to switch power.
  9891. */
  9892. tg3_get_eeprom_hw_cfg(tp);
  9893. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  9894. /* Allow reads and writes to the
  9895. * APE register and memory space.
  9896. */
  9897. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  9898. PCISTATE_ALLOW_APE_SHMEM_WR;
  9899. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9900. pci_state_reg);
  9901. }
  9902. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9903. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  9904. tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
  9905. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
  9906. tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
  9907. tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
  9908. tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
  9909. tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
  9910. }
  9911. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  9912. * GPIO1 driven high will bring 5700's external PHY out of reset.
  9913. * It is also used as eeprom write protect on LOMs.
  9914. */
  9915. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  9916. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9917. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  9918. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  9919. GRC_LCLCTRL_GPIO_OUTPUT1);
  9920. /* Unused GPIO3 must be driven as output on 5752 because there
  9921. * are no pull-up resistors on unused GPIO pins.
  9922. */
  9923. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9924. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  9925. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9926. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  9927. /* Force the chip into D0. */
  9928. err = tg3_set_power_state(tp, PCI_D0);
  9929. if (err) {
  9930. printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  9931. pci_name(tp->pdev));
  9932. return err;
  9933. }
  9934. /* 5700 B0 chips do not support checksumming correctly due
  9935. * to hardware bugs.
  9936. */
  9937. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  9938. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  9939. /* Derive initial jumbo mode from MTU assigned in
  9940. * ether_setup() via the alloc_etherdev() call
  9941. */
  9942. if (tp->dev->mtu > ETH_DATA_LEN &&
  9943. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  9944. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  9945. /* Determine WakeOnLan speed to use. */
  9946. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9947. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  9948. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  9949. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  9950. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  9951. } else {
  9952. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  9953. }
  9954. /* A few boards don't want Ethernet@WireSpeed phy feature */
  9955. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9956. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  9957. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  9958. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  9959. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
  9960. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  9961. tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  9962. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  9963. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  9964. tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
  9965. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  9966. tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
  9967. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9968. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9969. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9970. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9971. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
  9972. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  9973. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  9974. tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
  9975. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  9976. tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
  9977. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9978. tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
  9979. }
  9980. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
  9981. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
  9982. tp->phy_otp = tg3_read_otp_phycfg(tp);
  9983. if (tp->phy_otp == 0)
  9984. tp->phy_otp = TG3_OTP_DEFAULT;
  9985. }
  9986. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9987. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  9988. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  9989. else
  9990. tp->mi_mode = MAC_MI_MODE_BASE;
  9991. tp->coalesce_mode = 0;
  9992. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  9993. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  9994. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  9995. /* Initialize MAC MI mode, polling disabled. */
  9996. tw32_f(MAC_MI_MODE, tp->mi_mode);
  9997. udelay(80);
  9998. /* Initialize data/descriptor byte/word swapping. */
  9999. val = tr32(GRC_MODE);
  10000. val &= GRC_MODE_HOST_STACKUP;
  10001. tw32(GRC_MODE, val | tp->grc_mode);
  10002. tg3_switch_clocks(tp);
  10003. /* Clear this out for sanity. */
  10004. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  10005. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  10006. &pci_state_reg);
  10007. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  10008. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  10009. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  10010. if (chiprevid == CHIPREV_ID_5701_A0 ||
  10011. chiprevid == CHIPREV_ID_5701_B0 ||
  10012. chiprevid == CHIPREV_ID_5701_B2 ||
  10013. chiprevid == CHIPREV_ID_5701_B5) {
  10014. void __iomem *sram_base;
  10015. /* Write some dummy words into the SRAM status block
  10016. * area, see if it reads back correctly. If the return
  10017. * value is bad, force enable the PCIX workaround.
  10018. */
  10019. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  10020. writel(0x00000000, sram_base);
  10021. writel(0x00000000, sram_base + 4);
  10022. writel(0xffffffff, sram_base + 4);
  10023. if (readl(sram_base) != 0x00000000)
  10024. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  10025. }
  10026. }
  10027. udelay(50);
  10028. tg3_nvram_init(tp);
  10029. grc_misc_cfg = tr32(GRC_MISC_CFG);
  10030. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  10031. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  10032. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  10033. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  10034. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  10035. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  10036. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  10037. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  10038. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  10039. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  10040. HOSTCC_MODE_CLRTICK_TXBD);
  10041. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  10042. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  10043. tp->misc_host_ctrl);
  10044. }
  10045. /* these are limited to 10/100 only */
  10046. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  10047. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  10048. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  10049. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  10050. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  10051. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  10052. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  10053. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  10054. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  10055. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  10056. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  10057. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10058. tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  10059. err = tg3_phy_probe(tp);
  10060. if (err) {
  10061. printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  10062. pci_name(tp->pdev), err);
  10063. /* ... but do not return immediately ... */
  10064. }
  10065. tg3_read_partno(tp);
  10066. tg3_read_fw_ver(tp);
  10067. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  10068. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  10069. } else {
  10070. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  10071. tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  10072. else
  10073. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  10074. }
  10075. /* 5700 {AX,BX} chips have a broken status block link
  10076. * change bit implementation, so we must use the
  10077. * status register in those cases.
  10078. */
  10079. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  10080. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  10081. else
  10082. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  10083. /* The led_ctrl is set during tg3_phy_probe, here we might
  10084. * have to force the link status polling mechanism based
  10085. * upon subsystem IDs.
  10086. */
  10087. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  10088. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  10089. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  10090. tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  10091. TG3_FLAG_USE_LINKCHG_REG);
  10092. }
  10093. /* For all SERDES we poll the MAC status register. */
  10094. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  10095. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  10096. else
  10097. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  10098. /* All chips before 5787 can get confused if TX buffers
  10099. * straddle the 4GB address boundary in some cases.
  10100. */
  10101. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10102. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10103. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10104. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
  10105. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10106. tp->dev->hard_start_xmit = tg3_start_xmit;
  10107. else
  10108. tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
  10109. tp->rx_offset = 2;
  10110. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  10111. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  10112. tp->rx_offset = 0;
  10113. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  10114. /* Increment the rx prod index on the rx std ring by at most
  10115. * 8 for these chips to workaround hw errata.
  10116. */
  10117. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  10118. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  10119. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  10120. tp->rx_std_max_post = 8;
  10121. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
  10122. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  10123. PCIE_PWR_MGMT_L1_THRESH_MSK;
  10124. return err;
  10125. }
  10126. #ifdef CONFIG_SPARC
  10127. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  10128. {
  10129. struct net_device *dev = tp->dev;
  10130. struct pci_dev *pdev = tp->pdev;
  10131. struct device_node *dp = pci_device_to_OF_node(pdev);
  10132. const unsigned char *addr;
  10133. int len;
  10134. addr = of_get_property(dp, "local-mac-address", &len);
  10135. if (addr && len == 6) {
  10136. memcpy(dev->dev_addr, addr, 6);
  10137. memcpy(dev->perm_addr, dev->dev_addr, 6);
  10138. return 0;
  10139. }
  10140. return -ENODEV;
  10141. }
  10142. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  10143. {
  10144. struct net_device *dev = tp->dev;
  10145. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  10146. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  10147. return 0;
  10148. }
  10149. #endif
  10150. static int __devinit tg3_get_device_address(struct tg3 *tp)
  10151. {
  10152. struct net_device *dev = tp->dev;
  10153. u32 hi, lo, mac_offset;
  10154. int addr_ok = 0;
  10155. #ifdef CONFIG_SPARC
  10156. if (!tg3_get_macaddr_sparc(tp))
  10157. return 0;
  10158. #endif
  10159. mac_offset = 0x7c;
  10160. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  10161. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  10162. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  10163. mac_offset = 0xcc;
  10164. if (tg3_nvram_lock(tp))
  10165. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  10166. else
  10167. tg3_nvram_unlock(tp);
  10168. }
  10169. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  10170. mac_offset = 0x10;
  10171. /* First try to get it from MAC address mailbox. */
  10172. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  10173. if ((hi >> 16) == 0x484b) {
  10174. dev->dev_addr[0] = (hi >> 8) & 0xff;
  10175. dev->dev_addr[1] = (hi >> 0) & 0xff;
  10176. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  10177. dev->dev_addr[2] = (lo >> 24) & 0xff;
  10178. dev->dev_addr[3] = (lo >> 16) & 0xff;
  10179. dev->dev_addr[4] = (lo >> 8) & 0xff;
  10180. dev->dev_addr[5] = (lo >> 0) & 0xff;
  10181. /* Some old bootcode may report a 0 MAC address in SRAM */
  10182. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  10183. }
  10184. if (!addr_ok) {
  10185. /* Next, try NVRAM. */
  10186. if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  10187. !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  10188. dev->dev_addr[0] = ((hi >> 16) & 0xff);
  10189. dev->dev_addr[1] = ((hi >> 24) & 0xff);
  10190. dev->dev_addr[2] = ((lo >> 0) & 0xff);
  10191. dev->dev_addr[3] = ((lo >> 8) & 0xff);
  10192. dev->dev_addr[4] = ((lo >> 16) & 0xff);
  10193. dev->dev_addr[5] = ((lo >> 24) & 0xff);
  10194. }
  10195. /* Finally just fetch it out of the MAC control regs. */
  10196. else {
  10197. hi = tr32(MAC_ADDR_0_HIGH);
  10198. lo = tr32(MAC_ADDR_0_LOW);
  10199. dev->dev_addr[5] = lo & 0xff;
  10200. dev->dev_addr[4] = (lo >> 8) & 0xff;
  10201. dev->dev_addr[3] = (lo >> 16) & 0xff;
  10202. dev->dev_addr[2] = (lo >> 24) & 0xff;
  10203. dev->dev_addr[1] = hi & 0xff;
  10204. dev->dev_addr[0] = (hi >> 8) & 0xff;
  10205. }
  10206. }
  10207. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  10208. #ifdef CONFIG_SPARC
  10209. if (!tg3_get_default_macaddr_sparc(tp))
  10210. return 0;
  10211. #endif
  10212. return -EINVAL;
  10213. }
  10214. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  10215. return 0;
  10216. }
  10217. #define BOUNDARY_SINGLE_CACHELINE 1
  10218. #define BOUNDARY_MULTI_CACHELINE 2
  10219. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  10220. {
  10221. int cacheline_size;
  10222. u8 byte;
  10223. int goal;
  10224. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  10225. if (byte == 0)
  10226. cacheline_size = 1024;
  10227. else
  10228. cacheline_size = (int) byte * 4;
  10229. /* On 5703 and later chips, the boundary bits have no
  10230. * effect.
  10231. */
  10232. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10233. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  10234. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  10235. goto out;
  10236. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  10237. goal = BOUNDARY_MULTI_CACHELINE;
  10238. #else
  10239. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  10240. goal = BOUNDARY_SINGLE_CACHELINE;
  10241. #else
  10242. goal = 0;
  10243. #endif
  10244. #endif
  10245. if (!goal)
  10246. goto out;
  10247. /* PCI controllers on most RISC systems tend to disconnect
  10248. * when a device tries to burst across a cache-line boundary.
  10249. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  10250. *
  10251. * Unfortunately, for PCI-E there are only limited
  10252. * write-side controls for this, and thus for reads
  10253. * we will still get the disconnects. We'll also waste
  10254. * these PCI cycles for both read and write for chips
  10255. * other than 5700 and 5701 which do not implement the
  10256. * boundary bits.
  10257. */
  10258. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  10259. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  10260. switch (cacheline_size) {
  10261. case 16:
  10262. case 32:
  10263. case 64:
  10264. case 128:
  10265. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10266. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  10267. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  10268. } else {
  10269. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  10270. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  10271. }
  10272. break;
  10273. case 256:
  10274. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  10275. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  10276. break;
  10277. default:
  10278. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  10279. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  10280. break;
  10281. };
  10282. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  10283. switch (cacheline_size) {
  10284. case 16:
  10285. case 32:
  10286. case 64:
  10287. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10288. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  10289. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  10290. break;
  10291. }
  10292. /* fallthrough */
  10293. case 128:
  10294. default:
  10295. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  10296. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  10297. break;
  10298. };
  10299. } else {
  10300. switch (cacheline_size) {
  10301. case 16:
  10302. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10303. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  10304. DMA_RWCTRL_WRITE_BNDRY_16);
  10305. break;
  10306. }
  10307. /* fallthrough */
  10308. case 32:
  10309. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10310. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  10311. DMA_RWCTRL_WRITE_BNDRY_32);
  10312. break;
  10313. }
  10314. /* fallthrough */
  10315. case 64:
  10316. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10317. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  10318. DMA_RWCTRL_WRITE_BNDRY_64);
  10319. break;
  10320. }
  10321. /* fallthrough */
  10322. case 128:
  10323. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  10324. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  10325. DMA_RWCTRL_WRITE_BNDRY_128);
  10326. break;
  10327. }
  10328. /* fallthrough */
  10329. case 256:
  10330. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  10331. DMA_RWCTRL_WRITE_BNDRY_256);
  10332. break;
  10333. case 512:
  10334. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  10335. DMA_RWCTRL_WRITE_BNDRY_512);
  10336. break;
  10337. case 1024:
  10338. default:
  10339. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  10340. DMA_RWCTRL_WRITE_BNDRY_1024);
  10341. break;
  10342. };
  10343. }
  10344. out:
  10345. return val;
  10346. }
  10347. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  10348. {
  10349. struct tg3_internal_buffer_desc test_desc;
  10350. u32 sram_dma_descs;
  10351. int i, ret;
  10352. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  10353. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  10354. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  10355. tw32(RDMAC_STATUS, 0);
  10356. tw32(WDMAC_STATUS, 0);
  10357. tw32(BUFMGR_MODE, 0);
  10358. tw32(FTQ_RESET, 0);
  10359. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  10360. test_desc.addr_lo = buf_dma & 0xffffffff;
  10361. test_desc.nic_mbuf = 0x00002100;
  10362. test_desc.len = size;
  10363. /*
  10364. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  10365. * the *second* time the tg3 driver was getting loaded after an
  10366. * initial scan.
  10367. *
  10368. * Broadcom tells me:
  10369. * ...the DMA engine is connected to the GRC block and a DMA
  10370. * reset may affect the GRC block in some unpredictable way...
  10371. * The behavior of resets to individual blocks has not been tested.
  10372. *
  10373. * Broadcom noted the GRC reset will also reset all sub-components.
  10374. */
  10375. if (to_device) {
  10376. test_desc.cqid_sqid = (13 << 8) | 2;
  10377. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  10378. udelay(40);
  10379. } else {
  10380. test_desc.cqid_sqid = (16 << 8) | 7;
  10381. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  10382. udelay(40);
  10383. }
  10384. test_desc.flags = 0x00000005;
  10385. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  10386. u32 val;
  10387. val = *(((u32 *)&test_desc) + i);
  10388. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  10389. sram_dma_descs + (i * sizeof(u32)));
  10390. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  10391. }
  10392. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  10393. if (to_device) {
  10394. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  10395. } else {
  10396. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  10397. }
  10398. ret = -ENODEV;
  10399. for (i = 0; i < 40; i++) {
  10400. u32 val;
  10401. if (to_device)
  10402. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  10403. else
  10404. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  10405. if ((val & 0xffff) == sram_dma_descs) {
  10406. ret = 0;
  10407. break;
  10408. }
  10409. udelay(100);
  10410. }
  10411. return ret;
  10412. }
  10413. #define TEST_BUFFER_SIZE 0x2000
  10414. static int __devinit tg3_test_dma(struct tg3 *tp)
  10415. {
  10416. dma_addr_t buf_dma;
  10417. u32 *buf, saved_dma_rwctrl;
  10418. int ret;
  10419. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  10420. if (!buf) {
  10421. ret = -ENOMEM;
  10422. goto out_nofree;
  10423. }
  10424. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  10425. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  10426. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  10427. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  10428. /* DMA read watermark not used on PCIE */
  10429. tp->dma_rwctrl |= 0x00180000;
  10430. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  10431. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  10432. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  10433. tp->dma_rwctrl |= 0x003f0000;
  10434. else
  10435. tp->dma_rwctrl |= 0x003f000f;
  10436. } else {
  10437. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  10438. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  10439. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  10440. u32 read_water = 0x7;
  10441. /* If the 5704 is behind the EPB bridge, we can
  10442. * do the less restrictive ONE_DMA workaround for
  10443. * better performance.
  10444. */
  10445. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  10446. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  10447. tp->dma_rwctrl |= 0x8000;
  10448. else if (ccval == 0x6 || ccval == 0x7)
  10449. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  10450. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  10451. read_water = 4;
  10452. /* Set bit 23 to enable PCIX hw bug fix */
  10453. tp->dma_rwctrl |=
  10454. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  10455. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  10456. (1 << 23);
  10457. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  10458. /* 5780 always in PCIX mode */
  10459. tp->dma_rwctrl |= 0x00144000;
  10460. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  10461. /* 5714 always in PCIX mode */
  10462. tp->dma_rwctrl |= 0x00148000;
  10463. } else {
  10464. tp->dma_rwctrl |= 0x001b000f;
  10465. }
  10466. }
  10467. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  10468. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  10469. tp->dma_rwctrl &= 0xfffffff0;
  10470. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10471. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  10472. /* Remove this if it causes problems for some boards. */
  10473. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  10474. /* On 5700/5701 chips, we need to set this bit.
  10475. * Otherwise the chip will issue cacheline transactions
  10476. * to streamable DMA memory with not all the byte
  10477. * enables turned on. This is an error on several
  10478. * RISC PCI controllers, in particular sparc64.
  10479. *
  10480. * On 5703/5704 chips, this bit has been reassigned
  10481. * a different meaning. In particular, it is used
  10482. * on those chips to enable a PCI-X workaround.
  10483. */
  10484. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  10485. }
  10486. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  10487. #if 0
  10488. /* Unneeded, already done by tg3_get_invariants. */
  10489. tg3_switch_clocks(tp);
  10490. #endif
  10491. ret = 0;
  10492. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  10493. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  10494. goto out;
  10495. /* It is best to perform DMA test with maximum write burst size
  10496. * to expose the 5700/5701 write DMA bug.
  10497. */
  10498. saved_dma_rwctrl = tp->dma_rwctrl;
  10499. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  10500. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  10501. while (1) {
  10502. u32 *p = buf, i;
  10503. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  10504. p[i] = i;
  10505. /* Send the buffer to the chip. */
  10506. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  10507. if (ret) {
  10508. printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
  10509. break;
  10510. }
  10511. #if 0
  10512. /* validate data reached card RAM correctly. */
  10513. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  10514. u32 val;
  10515. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  10516. if (le32_to_cpu(val) != p[i]) {
  10517. printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
  10518. /* ret = -ENODEV here? */
  10519. }
  10520. p[i] = 0;
  10521. }
  10522. #endif
  10523. /* Now read it back. */
  10524. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  10525. if (ret) {
  10526. printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
  10527. break;
  10528. }
  10529. /* Verify it. */
  10530. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  10531. if (p[i] == i)
  10532. continue;
  10533. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  10534. DMA_RWCTRL_WRITE_BNDRY_16) {
  10535. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  10536. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  10537. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  10538. break;
  10539. } else {
  10540. printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
  10541. ret = -ENODEV;
  10542. goto out;
  10543. }
  10544. }
  10545. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  10546. /* Success. */
  10547. ret = 0;
  10548. break;
  10549. }
  10550. }
  10551. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  10552. DMA_RWCTRL_WRITE_BNDRY_16) {
  10553. static struct pci_device_id dma_wait_state_chipsets[] = {
  10554. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  10555. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  10556. { },
  10557. };
  10558. /* DMA test passed without adjusting DMA boundary,
  10559. * now look for chipsets that are known to expose the
  10560. * DMA bug without failing the test.
  10561. */
  10562. if (pci_dev_present(dma_wait_state_chipsets)) {
  10563. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  10564. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  10565. }
  10566. else
  10567. /* Safe to use the calculated DMA boundary. */
  10568. tp->dma_rwctrl = saved_dma_rwctrl;
  10569. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  10570. }
  10571. out:
  10572. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  10573. out_nofree:
  10574. return ret;
  10575. }
  10576. static void __devinit tg3_init_link_config(struct tg3 *tp)
  10577. {
  10578. tp->link_config.advertising =
  10579. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  10580. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  10581. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  10582. ADVERTISED_Autoneg | ADVERTISED_MII);
  10583. tp->link_config.speed = SPEED_INVALID;
  10584. tp->link_config.duplex = DUPLEX_INVALID;
  10585. tp->link_config.autoneg = AUTONEG_ENABLE;
  10586. tp->link_config.active_speed = SPEED_INVALID;
  10587. tp->link_config.active_duplex = DUPLEX_INVALID;
  10588. tp->link_config.phy_is_low_power = 0;
  10589. tp->link_config.orig_speed = SPEED_INVALID;
  10590. tp->link_config.orig_duplex = DUPLEX_INVALID;
  10591. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  10592. }
  10593. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  10594. {
  10595. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  10596. tp->bufmgr_config.mbuf_read_dma_low_water =
  10597. DEFAULT_MB_RDMA_LOW_WATER_5705;
  10598. tp->bufmgr_config.mbuf_mac_rx_low_water =
  10599. DEFAULT_MB_MACRX_LOW_WATER_5705;
  10600. tp->bufmgr_config.mbuf_high_water =
  10601. DEFAULT_MB_HIGH_WATER_5705;
  10602. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  10603. tp->bufmgr_config.mbuf_mac_rx_low_water =
  10604. DEFAULT_MB_MACRX_LOW_WATER_5906;
  10605. tp->bufmgr_config.mbuf_high_water =
  10606. DEFAULT_MB_HIGH_WATER_5906;
  10607. }
  10608. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  10609. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  10610. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  10611. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  10612. tp->bufmgr_config.mbuf_high_water_jumbo =
  10613. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  10614. } else {
  10615. tp->bufmgr_config.mbuf_read_dma_low_water =
  10616. DEFAULT_MB_RDMA_LOW_WATER;
  10617. tp->bufmgr_config.mbuf_mac_rx_low_water =
  10618. DEFAULT_MB_MACRX_LOW_WATER;
  10619. tp->bufmgr_config.mbuf_high_water =
  10620. DEFAULT_MB_HIGH_WATER;
  10621. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  10622. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  10623. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  10624. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  10625. tp->bufmgr_config.mbuf_high_water_jumbo =
  10626. DEFAULT_MB_HIGH_WATER_JUMBO;
  10627. }
  10628. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  10629. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  10630. }
  10631. static char * __devinit tg3_phy_string(struct tg3 *tp)
  10632. {
  10633. switch (tp->phy_id & PHY_ID_MASK) {
  10634. case PHY_ID_BCM5400: return "5400";
  10635. case PHY_ID_BCM5401: return "5401";
  10636. case PHY_ID_BCM5411: return "5411";
  10637. case PHY_ID_BCM5701: return "5701";
  10638. case PHY_ID_BCM5703: return "5703";
  10639. case PHY_ID_BCM5704: return "5704";
  10640. case PHY_ID_BCM5705: return "5705";
  10641. case PHY_ID_BCM5750: return "5750";
  10642. case PHY_ID_BCM5752: return "5752";
  10643. case PHY_ID_BCM5714: return "5714";
  10644. case PHY_ID_BCM5780: return "5780";
  10645. case PHY_ID_BCM5755: return "5755";
  10646. case PHY_ID_BCM5787: return "5787";
  10647. case PHY_ID_BCM5784: return "5784";
  10648. case PHY_ID_BCM5756: return "5722/5756";
  10649. case PHY_ID_BCM5906: return "5906";
  10650. case PHY_ID_BCM5761: return "5761";
  10651. case PHY_ID_BCM8002: return "8002/serdes";
  10652. case 0: return "serdes";
  10653. default: return "unknown";
  10654. };
  10655. }
  10656. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  10657. {
  10658. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  10659. strcpy(str, "PCI Express");
  10660. return str;
  10661. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  10662. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  10663. strcpy(str, "PCIX:");
  10664. if ((clock_ctrl == 7) ||
  10665. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  10666. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  10667. strcat(str, "133MHz");
  10668. else if (clock_ctrl == 0)
  10669. strcat(str, "33MHz");
  10670. else if (clock_ctrl == 2)
  10671. strcat(str, "50MHz");
  10672. else if (clock_ctrl == 4)
  10673. strcat(str, "66MHz");
  10674. else if (clock_ctrl == 6)
  10675. strcat(str, "100MHz");
  10676. } else {
  10677. strcpy(str, "PCI:");
  10678. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  10679. strcat(str, "66MHz");
  10680. else
  10681. strcat(str, "33MHz");
  10682. }
  10683. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  10684. strcat(str, ":32-bit");
  10685. else
  10686. strcat(str, ":64-bit");
  10687. return str;
  10688. }
  10689. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  10690. {
  10691. struct pci_dev *peer;
  10692. unsigned int func, devnr = tp->pdev->devfn & ~7;
  10693. for (func = 0; func < 8; func++) {
  10694. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  10695. if (peer && peer != tp->pdev)
  10696. break;
  10697. pci_dev_put(peer);
  10698. }
  10699. /* 5704 can be configured in single-port mode, set peer to
  10700. * tp->pdev in that case.
  10701. */
  10702. if (!peer) {
  10703. peer = tp->pdev;
  10704. return peer;
  10705. }
  10706. /*
  10707. * We don't need to keep the refcount elevated; there's no way
  10708. * to remove one half of this device without removing the other
  10709. */
  10710. pci_dev_put(peer);
  10711. return peer;
  10712. }
  10713. static void __devinit tg3_init_coal(struct tg3 *tp)
  10714. {
  10715. struct ethtool_coalesce *ec = &tp->coal;
  10716. memset(ec, 0, sizeof(*ec));
  10717. ec->cmd = ETHTOOL_GCOALESCE;
  10718. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  10719. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  10720. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  10721. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  10722. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  10723. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  10724. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  10725. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  10726. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  10727. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  10728. HOSTCC_MODE_CLRTICK_TXBD)) {
  10729. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  10730. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  10731. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  10732. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  10733. }
  10734. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  10735. ec->rx_coalesce_usecs_irq = 0;
  10736. ec->tx_coalesce_usecs_irq = 0;
  10737. ec->stats_block_coalesce_usecs = 0;
  10738. }
  10739. }
  10740. static int __devinit tg3_init_one(struct pci_dev *pdev,
  10741. const struct pci_device_id *ent)
  10742. {
  10743. static int tg3_version_printed = 0;
  10744. resource_size_t tg3reg_base;
  10745. unsigned long tg3reg_len;
  10746. struct net_device *dev;
  10747. struct tg3 *tp;
  10748. int err, pm_cap;
  10749. char str[40];
  10750. u64 dma_mask, persist_dma_mask;
  10751. DECLARE_MAC_BUF(mac);
  10752. if (tg3_version_printed++ == 0)
  10753. printk(KERN_INFO "%s", version);
  10754. err = pci_enable_device(pdev);
  10755. if (err) {
  10756. printk(KERN_ERR PFX "Cannot enable PCI device, "
  10757. "aborting.\n");
  10758. return err;
  10759. }
  10760. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  10761. printk(KERN_ERR PFX "Cannot find proper PCI device "
  10762. "base address, aborting.\n");
  10763. err = -ENODEV;
  10764. goto err_out_disable_pdev;
  10765. }
  10766. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  10767. if (err) {
  10768. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  10769. "aborting.\n");
  10770. goto err_out_disable_pdev;
  10771. }
  10772. pci_set_master(pdev);
  10773. /* Find power-management capability. */
  10774. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  10775. if (pm_cap == 0) {
  10776. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  10777. "aborting.\n");
  10778. err = -EIO;
  10779. goto err_out_free_res;
  10780. }
  10781. tg3reg_base = pci_resource_start(pdev, 0);
  10782. tg3reg_len = pci_resource_len(pdev, 0);
  10783. dev = alloc_etherdev(sizeof(*tp));
  10784. if (!dev) {
  10785. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  10786. err = -ENOMEM;
  10787. goto err_out_free_res;
  10788. }
  10789. SET_NETDEV_DEV(dev, &pdev->dev);
  10790. #if TG3_VLAN_TAG_USED
  10791. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  10792. dev->vlan_rx_register = tg3_vlan_rx_register;
  10793. #endif
  10794. tp = netdev_priv(dev);
  10795. tp->pdev = pdev;
  10796. tp->dev = dev;
  10797. tp->pm_cap = pm_cap;
  10798. tp->mac_mode = TG3_DEF_MAC_MODE;
  10799. tp->rx_mode = TG3_DEF_RX_MODE;
  10800. tp->tx_mode = TG3_DEF_TX_MODE;
  10801. if (tg3_debug > 0)
  10802. tp->msg_enable = tg3_debug;
  10803. else
  10804. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  10805. /* The word/byte swap controls here control register access byte
  10806. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  10807. * setting below.
  10808. */
  10809. tp->misc_host_ctrl =
  10810. MISC_HOST_CTRL_MASK_PCI_INT |
  10811. MISC_HOST_CTRL_WORD_SWAP |
  10812. MISC_HOST_CTRL_INDIR_ACCESS |
  10813. MISC_HOST_CTRL_PCISTATE_RW;
  10814. /* The NONFRM (non-frame) byte/word swap controls take effect
  10815. * on descriptor entries, anything which isn't packet data.
  10816. *
  10817. * The StrongARM chips on the board (one for tx, one for rx)
  10818. * are running in big-endian mode.
  10819. */
  10820. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  10821. GRC_MODE_WSWAP_NONFRM_DATA);
  10822. #ifdef __BIG_ENDIAN
  10823. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  10824. #endif
  10825. spin_lock_init(&tp->lock);
  10826. spin_lock_init(&tp->indirect_lock);
  10827. INIT_WORK(&tp->reset_task, tg3_reset_task);
  10828. tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
  10829. if (!tp->regs) {
  10830. printk(KERN_ERR PFX "Cannot map device registers, "
  10831. "aborting.\n");
  10832. err = -ENOMEM;
  10833. goto err_out_free_dev;
  10834. }
  10835. tg3_init_link_config(tp);
  10836. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  10837. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  10838. tp->tx_pending = TG3_DEF_TX_RING_PENDING;
  10839. dev->open = tg3_open;
  10840. dev->stop = tg3_close;
  10841. dev->get_stats = tg3_get_stats;
  10842. dev->set_multicast_list = tg3_set_rx_mode;
  10843. dev->set_mac_address = tg3_set_mac_addr;
  10844. dev->do_ioctl = tg3_ioctl;
  10845. dev->tx_timeout = tg3_tx_timeout;
  10846. netif_napi_add(dev, &tp->napi, tg3_poll, 64);
  10847. dev->ethtool_ops = &tg3_ethtool_ops;
  10848. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  10849. dev->change_mtu = tg3_change_mtu;
  10850. dev->irq = pdev->irq;
  10851. #ifdef CONFIG_NET_POLL_CONTROLLER
  10852. dev->poll_controller = tg3_poll_controller;
  10853. #endif
  10854. err = tg3_get_invariants(tp);
  10855. if (err) {
  10856. printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  10857. "aborting.\n");
  10858. goto err_out_iounmap;
  10859. }
  10860. /* The EPB bridge inside 5714, 5715, and 5780 and any
  10861. * device behind the EPB cannot support DMA addresses > 40-bit.
  10862. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  10863. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  10864. * do DMA address check in tg3_start_xmit().
  10865. */
  10866. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  10867. persist_dma_mask = dma_mask = DMA_32BIT_MASK;
  10868. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  10869. persist_dma_mask = dma_mask = DMA_40BIT_MASK;
  10870. #ifdef CONFIG_HIGHMEM
  10871. dma_mask = DMA_64BIT_MASK;
  10872. #endif
  10873. } else
  10874. persist_dma_mask = dma_mask = DMA_64BIT_MASK;
  10875. /* Configure DMA attributes. */
  10876. if (dma_mask > DMA_32BIT_MASK) {
  10877. err = pci_set_dma_mask(pdev, dma_mask);
  10878. if (!err) {
  10879. dev->features |= NETIF_F_HIGHDMA;
  10880. err = pci_set_consistent_dma_mask(pdev,
  10881. persist_dma_mask);
  10882. if (err < 0) {
  10883. printk(KERN_ERR PFX "Unable to obtain 64 bit "
  10884. "DMA for consistent allocations\n");
  10885. goto err_out_iounmap;
  10886. }
  10887. }
  10888. }
  10889. if (err || dma_mask == DMA_32BIT_MASK) {
  10890. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  10891. if (err) {
  10892. printk(KERN_ERR PFX "No usable DMA configuration, "
  10893. "aborting.\n");
  10894. goto err_out_iounmap;
  10895. }
  10896. }
  10897. tg3_init_bufmgr_config(tp);
  10898. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10899. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  10900. }
  10901. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10902. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  10903. tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
  10904. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10905. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  10906. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  10907. } else {
  10908. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
  10909. }
  10910. /* TSO is on by default on chips that support hardware TSO.
  10911. * Firmware TSO on older chips gives lower performance, so it
  10912. * is off by default, but can be enabled using ethtool.
  10913. */
  10914. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10915. dev->features |= NETIF_F_TSO;
  10916. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  10917. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
  10918. dev->features |= NETIF_F_TSO6;
  10919. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  10920. dev->features |= NETIF_F_TSO_ECN;
  10921. }
  10922. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  10923. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  10924. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  10925. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  10926. tp->rx_pending = 63;
  10927. }
  10928. err = tg3_get_device_address(tp);
  10929. if (err) {
  10930. printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  10931. "aborting.\n");
  10932. goto err_out_iounmap;
  10933. }
  10934. if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
  10935. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  10936. printk(KERN_ERR PFX "Cannot find proper PCI device "
  10937. "base address for APE, aborting.\n");
  10938. err = -ENODEV;
  10939. goto err_out_iounmap;
  10940. }
  10941. tg3reg_base = pci_resource_start(pdev, 2);
  10942. tg3reg_len = pci_resource_len(pdev, 2);
  10943. tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
  10944. if (!tp->aperegs) {
  10945. printk(KERN_ERR PFX "Cannot map APE registers, "
  10946. "aborting.\n");
  10947. err = -ENOMEM;
  10948. goto err_out_iounmap;
  10949. }
  10950. tg3_ape_lock_init(tp);
  10951. }
  10952. /*
  10953. * Reset chip in case UNDI or EFI driver did not shutdown
  10954. * DMA self test will enable WDMAC and we'll see (spurious)
  10955. * pending DMA on the PCI bus at that point.
  10956. */
  10957. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  10958. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  10959. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  10960. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10961. }
  10962. err = tg3_test_dma(tp);
  10963. if (err) {
  10964. printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  10965. goto err_out_apeunmap;
  10966. }
  10967. /* Tigon3 can do ipv4 only... and some chips have buggy
  10968. * checksumming.
  10969. */
  10970. if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
  10971. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  10972. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10973. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10974. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  10975. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
  10976. dev->features |= NETIF_F_IPV6_CSUM;
  10977. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  10978. } else
  10979. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  10980. /* flow control autonegotiation is default behavior */
  10981. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  10982. tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
  10983. tg3_init_coal(tp);
  10984. pci_set_drvdata(pdev, dev);
  10985. err = register_netdev(dev);
  10986. if (err) {
  10987. printk(KERN_ERR PFX "Cannot register net device, "
  10988. "aborting.\n");
  10989. goto err_out_apeunmap;
  10990. }
  10991. printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
  10992. "(%s) %s Ethernet %s\n",
  10993. dev->name,
  10994. tp->board_part_number,
  10995. tp->pci_chip_rev_id,
  10996. tg3_phy_string(tp),
  10997. tg3_bus_string(tp, str),
  10998. ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
  10999. ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
  11000. "10/100/1000Base-T")),
  11001. print_mac(mac, dev->dev_addr));
  11002. printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
  11003. "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
  11004. dev->name,
  11005. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  11006. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  11007. (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
  11008. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  11009. (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
  11010. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  11011. printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  11012. dev->name, tp->dma_rwctrl,
  11013. (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
  11014. (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
  11015. return 0;
  11016. err_out_apeunmap:
  11017. if (tp->aperegs) {
  11018. iounmap(tp->aperegs);
  11019. tp->aperegs = NULL;
  11020. }
  11021. err_out_iounmap:
  11022. if (tp->regs) {
  11023. iounmap(tp->regs);
  11024. tp->regs = NULL;
  11025. }
  11026. err_out_free_dev:
  11027. free_netdev(dev);
  11028. err_out_free_res:
  11029. pci_release_regions(pdev);
  11030. err_out_disable_pdev:
  11031. pci_disable_device(pdev);
  11032. pci_set_drvdata(pdev, NULL);
  11033. return err;
  11034. }
  11035. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  11036. {
  11037. struct net_device *dev = pci_get_drvdata(pdev);
  11038. if (dev) {
  11039. struct tg3 *tp = netdev_priv(dev);
  11040. flush_scheduled_work();
  11041. unregister_netdev(dev);
  11042. if (tp->aperegs) {
  11043. iounmap(tp->aperegs);
  11044. tp->aperegs = NULL;
  11045. }
  11046. if (tp->regs) {
  11047. iounmap(tp->regs);
  11048. tp->regs = NULL;
  11049. }
  11050. free_netdev(dev);
  11051. pci_release_regions(pdev);
  11052. pci_disable_device(pdev);
  11053. pci_set_drvdata(pdev, NULL);
  11054. }
  11055. }
  11056. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  11057. {
  11058. struct net_device *dev = pci_get_drvdata(pdev);
  11059. struct tg3 *tp = netdev_priv(dev);
  11060. int err;
  11061. /* PCI register 4 needs to be saved whether netif_running() or not.
  11062. * MSI address and data need to be saved if using MSI and
  11063. * netif_running().
  11064. */
  11065. pci_save_state(pdev);
  11066. if (!netif_running(dev))
  11067. return 0;
  11068. flush_scheduled_work();
  11069. tg3_netif_stop(tp);
  11070. del_timer_sync(&tp->timer);
  11071. tg3_full_lock(tp, 1);
  11072. tg3_disable_ints(tp);
  11073. tg3_full_unlock(tp);
  11074. netif_device_detach(dev);
  11075. tg3_full_lock(tp, 0);
  11076. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  11077. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  11078. tg3_full_unlock(tp);
  11079. err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
  11080. if (err) {
  11081. tg3_full_lock(tp, 0);
  11082. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  11083. if (tg3_restart_hw(tp, 1))
  11084. goto out;
  11085. tp->timer.expires = jiffies + tp->timer_offset;
  11086. add_timer(&tp->timer);
  11087. netif_device_attach(dev);
  11088. tg3_netif_start(tp);
  11089. out:
  11090. tg3_full_unlock(tp);
  11091. }
  11092. return err;
  11093. }
  11094. static int tg3_resume(struct pci_dev *pdev)
  11095. {
  11096. struct net_device *dev = pci_get_drvdata(pdev);
  11097. struct tg3 *tp = netdev_priv(dev);
  11098. int err;
  11099. pci_restore_state(tp->pdev);
  11100. if (!netif_running(dev))
  11101. return 0;
  11102. err = tg3_set_power_state(tp, PCI_D0);
  11103. if (err)
  11104. return err;
  11105. netif_device_attach(dev);
  11106. tg3_full_lock(tp, 0);
  11107. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  11108. err = tg3_restart_hw(tp, 1);
  11109. if (err)
  11110. goto out;
  11111. tp->timer.expires = jiffies + tp->timer_offset;
  11112. add_timer(&tp->timer);
  11113. tg3_netif_start(tp);
  11114. out:
  11115. tg3_full_unlock(tp);
  11116. return err;
  11117. }
  11118. static struct pci_driver tg3_driver = {
  11119. .name = DRV_MODULE_NAME,
  11120. .id_table = tg3_pci_tbl,
  11121. .probe = tg3_init_one,
  11122. .remove = __devexit_p(tg3_remove_one),
  11123. .suspend = tg3_suspend,
  11124. .resume = tg3_resume
  11125. };
  11126. static int __init tg3_init(void)
  11127. {
  11128. return pci_register_driver(&tg3_driver);
  11129. }
  11130. static void __exit tg3_cleanup(void)
  11131. {
  11132. pci_unregister_driver(&tg3_driver);
  11133. }
  11134. module_init(tg3_init);
  11135. module_exit(tg3_cleanup);