smc91x.h 40 KB

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  1. /*------------------------------------------------------------------------
  2. . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
  3. .
  4. . Copyright (C) 1996 by Erik Stahlman
  5. . Copyright (C) 2001 Standard Microsystems Corporation
  6. . Developed by Simple Network Magic Corporation
  7. . Copyright (C) 2003 Monta Vista Software, Inc.
  8. . Unified SMC91x driver by Nicolas Pitre
  9. .
  10. . This program is free software; you can redistribute it and/or modify
  11. . it under the terms of the GNU General Public License as published by
  12. . the Free Software Foundation; either version 2 of the License, or
  13. . (at your option) any later version.
  14. .
  15. . This program is distributed in the hope that it will be useful,
  16. . but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. . GNU General Public License for more details.
  19. .
  20. . You should have received a copy of the GNU General Public License
  21. . along with this program; if not, write to the Free Software
  22. . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. .
  24. . Information contained in this file was obtained from the LAN91C111
  25. . manual from SMC. To get a copy, if you really want one, you can find
  26. . information under www.smsc.com.
  27. .
  28. . Authors
  29. . Erik Stahlman <erik@vt.edu>
  30. . Daris A Nevil <dnevil@snmc.com>
  31. . Nicolas Pitre <nico@cam.org>
  32. .
  33. ---------------------------------------------------------------------------*/
  34. #ifndef _SMC91X_H_
  35. #define _SMC91X_H_
  36. #include <linux/smc91x.h>
  37. /*
  38. * Define your architecture specific bus configuration parameters here.
  39. */
  40. #if defined(CONFIG_ARCH_LUBBOCK)
  41. /* We can only do 16-bit reads and writes in the static memory space. */
  42. #define SMC_CAN_USE_8BIT 0
  43. #define SMC_CAN_USE_16BIT 1
  44. #define SMC_CAN_USE_32BIT 0
  45. #define SMC_NOWAIT 1
  46. /* The first two address lines aren't connected... */
  47. #define SMC_IO_SHIFT 2
  48. #define SMC_inw(a, r) readw((a) + (r))
  49. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  50. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  51. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  52. #define SMC_IRQ_FLAGS (-1) /* from resource */
  53. #elif defined(CONFIG_BLACKFIN)
  54. #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
  55. #define RPC_LSA_DEFAULT RPC_LED_100_10
  56. #define RPC_LSB_DEFAULT RPC_LED_TX_RX
  57. # if defined (CONFIG_BFIN561_EZKIT)
  58. #define SMC_CAN_USE_8BIT 0
  59. #define SMC_CAN_USE_16BIT 1
  60. #define SMC_CAN_USE_32BIT 1
  61. #define SMC_IO_SHIFT 0
  62. #define SMC_NOWAIT 1
  63. #define SMC_USE_BFIN_DMA 0
  64. #define SMC_inw(a, r) readw((a) + (r))
  65. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  66. #define SMC_inl(a, r) readl((a) + (r))
  67. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  68. #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
  69. #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
  70. # else
  71. #define SMC_CAN_USE_8BIT 0
  72. #define SMC_CAN_USE_16BIT 1
  73. #define SMC_CAN_USE_32BIT 0
  74. #define SMC_IO_SHIFT 0
  75. #define SMC_NOWAIT 1
  76. #define SMC_USE_BFIN_DMA 0
  77. #define SMC_inw(a, r) readw((a) + (r))
  78. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  79. #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
  80. #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
  81. # endif
  82. /* check if the mac in reg is valid */
  83. #define SMC_GET_MAC_ADDR(addr) \
  84. do { \
  85. unsigned int __v; \
  86. __v = SMC_inw(ioaddr, ADDR0_REG); \
  87. addr[0] = __v; addr[1] = __v >> 8; \
  88. __v = SMC_inw(ioaddr, ADDR1_REG); \
  89. addr[2] = __v; addr[3] = __v >> 8; \
  90. __v = SMC_inw(ioaddr, ADDR2_REG); \
  91. addr[4] = __v; addr[5] = __v >> 8; \
  92. if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
  93. random_ether_addr(addr); \
  94. } \
  95. } while (0)
  96. #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
  97. /* We can only do 16-bit reads and writes in the static memory space. */
  98. #define SMC_CAN_USE_8BIT 0
  99. #define SMC_CAN_USE_16BIT 1
  100. #define SMC_CAN_USE_32BIT 0
  101. #define SMC_NOWAIT 1
  102. #define SMC_IO_SHIFT 0
  103. #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
  104. #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
  105. #define SMC_insw(a, r, p, l) \
  106. do { \
  107. unsigned long __port = (a) + (r); \
  108. u16 *__p = (u16 *)(p); \
  109. int __l = (l); \
  110. insw(__port, __p, __l); \
  111. while (__l > 0) { \
  112. *__p = swab16(*__p); \
  113. __p++; \
  114. __l--; \
  115. } \
  116. } while (0)
  117. #define SMC_outsw(a, r, p, l) \
  118. do { \
  119. unsigned long __port = (a) + (r); \
  120. u16 *__p = (u16 *)(p); \
  121. int __l = (l); \
  122. while (__l > 0) { \
  123. /* Believe it or not, the swab isn't needed. */ \
  124. outw( /* swab16 */ (*__p++), __port); \
  125. __l--; \
  126. } \
  127. } while (0)
  128. #define SMC_IRQ_FLAGS (0)
  129. #elif defined(CONFIG_SA1100_PLEB)
  130. /* We can only do 16-bit reads and writes in the static memory space. */
  131. #define SMC_CAN_USE_8BIT 1
  132. #define SMC_CAN_USE_16BIT 1
  133. #define SMC_CAN_USE_32BIT 0
  134. #define SMC_IO_SHIFT 0
  135. #define SMC_NOWAIT 1
  136. #define SMC_inb(a, r) readb((a) + (r))
  137. #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
  138. #define SMC_inw(a, r) readw((a) + (r))
  139. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  140. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  141. #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
  142. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  143. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  144. #define SMC_IRQ_FLAGS (-1)
  145. #elif defined(CONFIG_SA1100_ASSABET)
  146. #include <asm/arch/neponset.h>
  147. /* We can only do 8-bit reads and writes in the static memory space. */
  148. #define SMC_CAN_USE_8BIT 1
  149. #define SMC_CAN_USE_16BIT 0
  150. #define SMC_CAN_USE_32BIT 0
  151. #define SMC_NOWAIT 1
  152. /* The first two address lines aren't connected... */
  153. #define SMC_IO_SHIFT 2
  154. #define SMC_inb(a, r) readb((a) + (r))
  155. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  156. #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
  157. #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
  158. #define SMC_IRQ_FLAGS (-1) /* from resource */
  159. #elif defined(CONFIG_MACH_LOGICPD_PXA270)
  160. #define SMC_CAN_USE_8BIT 0
  161. #define SMC_CAN_USE_16BIT 1
  162. #define SMC_CAN_USE_32BIT 0
  163. #define SMC_IO_SHIFT 0
  164. #define SMC_NOWAIT 1
  165. #define SMC_inw(a, r) readw((a) + (r))
  166. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  167. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  168. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  169. #elif defined(CONFIG_ARCH_INNOKOM) || \
  170. defined(CONFIG_MACH_MAINSTONE) || \
  171. defined(CONFIG_ARCH_PXA_IDP) || \
  172. defined(CONFIG_ARCH_RAMSES) || \
  173. defined(CONFIG_ARCH_PCM027)
  174. #define SMC_CAN_USE_8BIT 1
  175. #define SMC_CAN_USE_16BIT 1
  176. #define SMC_CAN_USE_32BIT 1
  177. #define SMC_IO_SHIFT 0
  178. #define SMC_NOWAIT 1
  179. #define SMC_USE_PXA_DMA 1
  180. #define SMC_inb(a, r) readb((a) + (r))
  181. #define SMC_inw(a, r) readw((a) + (r))
  182. #define SMC_inl(a, r) readl((a) + (r))
  183. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  184. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  185. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  186. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  187. #define SMC_IRQ_FLAGS (-1) /* from resource */
  188. /* We actually can't write halfwords properly if not word aligned */
  189. static inline void
  190. SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  191. {
  192. if (reg & 2) {
  193. unsigned int v = val << 16;
  194. v |= readl(ioaddr + (reg & ~2)) & 0xffff;
  195. writel(v, ioaddr + (reg & ~2));
  196. } else {
  197. writew(val, ioaddr + reg);
  198. }
  199. }
  200. #elif defined(CONFIG_MACH_ZYLONITE)
  201. #define SMC_CAN_USE_8BIT 1
  202. #define SMC_CAN_USE_16BIT 1
  203. #define SMC_CAN_USE_32BIT 0
  204. #define SMC_IO_SHIFT 0
  205. #define SMC_NOWAIT 1
  206. #define SMC_USE_PXA_DMA 1
  207. #define SMC_inb(a, r) readb((a) + (r))
  208. #define SMC_inw(a, r) readw((a) + (r))
  209. #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
  210. #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
  211. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  212. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  213. #define SMC_IRQ_FLAGS (-1) /* from resource */
  214. #elif defined(CONFIG_ARCH_OMAP)
  215. /* We can only do 16-bit reads and writes in the static memory space. */
  216. #define SMC_CAN_USE_8BIT 0
  217. #define SMC_CAN_USE_16BIT 1
  218. #define SMC_CAN_USE_32BIT 0
  219. #define SMC_IO_SHIFT 0
  220. #define SMC_NOWAIT 1
  221. #define SMC_inw(a, r) readw((a) + (r))
  222. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  223. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  224. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  225. #define SMC_IRQ_FLAGS (-1) /* from resource */
  226. #elif defined(CONFIG_SH_SH4202_MICRODEV)
  227. #define SMC_CAN_USE_8BIT 0
  228. #define SMC_CAN_USE_16BIT 1
  229. #define SMC_CAN_USE_32BIT 0
  230. #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
  231. #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
  232. #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
  233. #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
  234. #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
  235. #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
  236. #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
  237. #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
  238. #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
  239. #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
  240. #define SMC_IRQ_FLAGS (0)
  241. #elif defined(CONFIG_ISA)
  242. #define SMC_CAN_USE_8BIT 1
  243. #define SMC_CAN_USE_16BIT 1
  244. #define SMC_CAN_USE_32BIT 0
  245. #define SMC_inb(a, r) inb((a) + (r))
  246. #define SMC_inw(a, r) inw((a) + (r))
  247. #define SMC_outb(v, a, r) outb(v, (a) + (r))
  248. #define SMC_outw(v, a, r) outw(v, (a) + (r))
  249. #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
  250. #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
  251. #elif defined(CONFIG_M32R)
  252. #define SMC_CAN_USE_8BIT 0
  253. #define SMC_CAN_USE_16BIT 1
  254. #define SMC_CAN_USE_32BIT 0
  255. #define SMC_inb(a, r) inb(((u32)a) + (r))
  256. #define SMC_inw(a, r) inw(((u32)a) + (r))
  257. #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
  258. #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
  259. #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
  260. #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
  261. #define SMC_IRQ_FLAGS (0)
  262. #define RPC_LSA_DEFAULT RPC_LED_TX_RX
  263. #define RPC_LSB_DEFAULT RPC_LED_100_10
  264. #elif defined(CONFIG_MACH_LPD79520) \
  265. || defined(CONFIG_MACH_LPD7A400) \
  266. || defined(CONFIG_MACH_LPD7A404)
  267. /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
  268. * way that the CPU handles chip selects and the way that the SMC chip
  269. * expects the chip select to operate. Refer to
  270. * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
  271. * IOBARRIER is a byte, in order that we read the least-common
  272. * denominator. It would be wasteful to read 32 bits from an 8-bit
  273. * accessible region.
  274. *
  275. * There is no explicit protection against interrupts intervening
  276. * between the writew and the IOBARRIER. In SMC ISR there is a
  277. * preamble that performs an IOBARRIER in the extremely unlikely event
  278. * that the driver interrupts itself between a writew to the chip an
  279. * the IOBARRIER that follows *and* the cache is large enough that the
  280. * first off-chip access while handing the interrupt is to the SMC
  281. * chip. Other devices in the same address space as the SMC chip must
  282. * be aware of the potential for trouble and perform a similar
  283. * IOBARRIER on entry to their ISR.
  284. */
  285. #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
  286. #define SMC_CAN_USE_8BIT 0
  287. #define SMC_CAN_USE_16BIT 1
  288. #define SMC_CAN_USE_32BIT 0
  289. #define SMC_NOWAIT 0
  290. #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
  291. #define SMC_inw(a,r)\
  292. ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
  293. #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
  294. #define SMC_insw LPD7_SMC_insw
  295. static inline void LPD7_SMC_insw (unsigned char* a, int r,
  296. unsigned char* p, int l)
  297. {
  298. unsigned short* ps = (unsigned short*) p;
  299. while (l-- > 0) {
  300. *ps++ = readw (a + r);
  301. LPD7X_IOBARRIER;
  302. }
  303. }
  304. #define SMC_outsw LPD7_SMC_outsw
  305. static inline void LPD7_SMC_outsw (unsigned char* a, int r,
  306. unsigned char* p, int l)
  307. {
  308. unsigned short* ps = (unsigned short*) p;
  309. while (l-- > 0) {
  310. writew (*ps++, a + r);
  311. LPD7X_IOBARRIER;
  312. }
  313. }
  314. #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
  315. #define RPC_LSA_DEFAULT RPC_LED_TX_RX
  316. #define RPC_LSB_DEFAULT RPC_LED_100_10
  317. #elif defined(CONFIG_SOC_AU1X00)
  318. #include <au1xxx.h>
  319. /* We can only do 16-bit reads and writes in the static memory space. */
  320. #define SMC_CAN_USE_8BIT 0
  321. #define SMC_CAN_USE_16BIT 1
  322. #define SMC_CAN_USE_32BIT 0
  323. #define SMC_IO_SHIFT 0
  324. #define SMC_NOWAIT 1
  325. #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
  326. #define SMC_insw(a, r, p, l) \
  327. do { \
  328. unsigned long _a = (unsigned long)((a) + (r)); \
  329. int _l = (l); \
  330. u16 *_p = (u16 *)(p); \
  331. while (_l-- > 0) \
  332. *_p++ = au_readw(_a); \
  333. } while(0)
  334. #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
  335. #define SMC_outsw(a, r, p, l) \
  336. do { \
  337. unsigned long _a = (unsigned long)((a) + (r)); \
  338. int _l = (l); \
  339. const u16 *_p = (const u16 *)(p); \
  340. while (_l-- > 0) \
  341. au_writew(*_p++ , _a); \
  342. } while(0)
  343. #define SMC_IRQ_FLAGS (0)
  344. #elif defined(CONFIG_ARCH_VERSATILE)
  345. #define SMC_CAN_USE_8BIT 1
  346. #define SMC_CAN_USE_16BIT 1
  347. #define SMC_CAN_USE_32BIT 1
  348. #define SMC_NOWAIT 1
  349. #define SMC_inb(a, r) readb((a) + (r))
  350. #define SMC_inw(a, r) readw((a) + (r))
  351. #define SMC_inl(a, r) readl((a) + (r))
  352. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  353. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  354. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  355. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  356. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  357. #define SMC_IRQ_FLAGS (-1) /* from resource */
  358. #elif defined(CONFIG_MN10300)
  359. /*
  360. * MN10300/AM33 configuration
  361. */
  362. #include <asm/unit/smc91111.h>
  363. #else
  364. /*
  365. * Default configuration
  366. */
  367. #define SMC_CAN_USE_8BIT 1
  368. #define SMC_CAN_USE_16BIT 1
  369. #define SMC_CAN_USE_32BIT 1
  370. #define SMC_NOWAIT 1
  371. #define SMC_inb(a, r) readb((a) + (r))
  372. #define SMC_inw(a, r) readw((a) + (r))
  373. #define SMC_inl(a, r) readl((a) + (r))
  374. #define SMC_outb(v, a, r) writeb(v, (a) + (r))
  375. #define SMC_outw(v, a, r) writew(v, (a) + (r))
  376. #define SMC_outl(v, a, r) writel(v, (a) + (r))
  377. #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
  378. #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
  379. #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
  380. #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
  381. #define RPC_LSA_DEFAULT RPC_LED_100_10
  382. #define RPC_LSB_DEFAULT RPC_LED_TX_RX
  383. #define SMC_DYNAMIC_BUS_CONFIG
  384. #endif
  385. /* store this information for the driver.. */
  386. struct smc_local {
  387. /*
  388. * If I have to wait until memory is available to send a
  389. * packet, I will store the skbuff here, until I get the
  390. * desired memory. Then, I'll send it out and free it.
  391. */
  392. struct sk_buff *pending_tx_skb;
  393. struct tasklet_struct tx_task;
  394. /* version/revision of the SMC91x chip */
  395. int version;
  396. /* Contains the current active transmission mode */
  397. int tcr_cur_mode;
  398. /* Contains the current active receive mode */
  399. int rcr_cur_mode;
  400. /* Contains the current active receive/phy mode */
  401. int rpc_cur_mode;
  402. int ctl_rfduplx;
  403. int ctl_rspeed;
  404. u32 msg_enable;
  405. u32 phy_type;
  406. struct mii_if_info mii;
  407. /* work queue */
  408. struct work_struct phy_configure;
  409. struct net_device *dev;
  410. int work_pending;
  411. spinlock_t lock;
  412. #ifdef SMC_USE_PXA_DMA
  413. /* DMA needs the physical address of the chip */
  414. u_long physaddr;
  415. struct device *device;
  416. #endif
  417. void __iomem *base;
  418. void __iomem *datacs;
  419. struct smc91x_platdata cfg;
  420. };
  421. #ifdef SMC_DYNAMIC_BUS_CONFIG
  422. #define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
  423. #define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
  424. #define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
  425. #else
  426. #define SMC_8BIT(p) SMC_CAN_USE_8BIT
  427. #define SMC_16BIT(p) SMC_CAN_USE_16BIT
  428. #define SMC_32BIT(p) SMC_CAN_USE_32BIT
  429. #endif
  430. #ifdef SMC_USE_PXA_DMA
  431. /*
  432. * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
  433. * always happening in irq context so no need to worry about races. TX is
  434. * different and probably not worth it for that reason, and not as critical
  435. * as RX which can overrun memory and lose packets.
  436. */
  437. #include <linux/dma-mapping.h>
  438. #include <asm/dma.h>
  439. #include <asm/arch/pxa-regs.h>
  440. #ifdef SMC_insl
  441. #undef SMC_insl
  442. #define SMC_insl(a, r, p, l) \
  443. smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
  444. static inline void
  445. smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
  446. u_char *buf, int len)
  447. {
  448. u_long physaddr = lp->physaddr;
  449. dma_addr_t dmabuf;
  450. /* fallback if no DMA available */
  451. if (dma == (unsigned char)-1) {
  452. readsl(ioaddr + reg, buf, len);
  453. return;
  454. }
  455. /* 64 bit alignment is required for memory to memory DMA */
  456. if ((long)buf & 4) {
  457. *((u32 *)buf) = SMC_inl(ioaddr, reg);
  458. buf += 4;
  459. len--;
  460. }
  461. len *= 4;
  462. dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
  463. DCSR(dma) = DCSR_NODESC;
  464. DTADR(dma) = dmabuf;
  465. DSADR(dma) = physaddr + reg;
  466. DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
  467. DCMD_WIDTH4 | (DCMD_LENGTH & len));
  468. DCSR(dma) = DCSR_NODESC | DCSR_RUN;
  469. while (!(DCSR(dma) & DCSR_STOPSTATE))
  470. cpu_relax();
  471. DCSR(dma) = 0;
  472. dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
  473. }
  474. #endif
  475. #ifdef SMC_insw
  476. #undef SMC_insw
  477. #define SMC_insw(a, r, p, l) \
  478. smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
  479. static inline void
  480. smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
  481. u_char *buf, int len)
  482. {
  483. u_long physaddr = lp->physaddr;
  484. dma_addr_t dmabuf;
  485. /* fallback if no DMA available */
  486. if (dma == (unsigned char)-1) {
  487. readsw(ioaddr + reg, buf, len);
  488. return;
  489. }
  490. /* 64 bit alignment is required for memory to memory DMA */
  491. while ((long)buf & 6) {
  492. *((u16 *)buf) = SMC_inw(ioaddr, reg);
  493. buf += 2;
  494. len--;
  495. }
  496. len *= 2;
  497. dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
  498. DCSR(dma) = DCSR_NODESC;
  499. DTADR(dma) = dmabuf;
  500. DSADR(dma) = physaddr + reg;
  501. DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
  502. DCMD_WIDTH2 | (DCMD_LENGTH & len));
  503. DCSR(dma) = DCSR_NODESC | DCSR_RUN;
  504. while (!(DCSR(dma) & DCSR_STOPSTATE))
  505. cpu_relax();
  506. DCSR(dma) = 0;
  507. dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
  508. }
  509. #endif
  510. static void
  511. smc_pxa_dma_irq(int dma, void *dummy)
  512. {
  513. DCSR(dma) = 0;
  514. }
  515. #endif /* SMC_USE_PXA_DMA */
  516. /*
  517. * Everything a particular hardware setup needs should have been defined
  518. * at this point. Add stubs for the undefined cases, mainly to avoid
  519. * compilation warnings since they'll be optimized away, or to prevent buggy
  520. * use of them.
  521. */
  522. #if ! SMC_CAN_USE_32BIT
  523. #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
  524. #define SMC_outl(x, ioaddr, reg) BUG()
  525. #define SMC_insl(a, r, p, l) BUG()
  526. #define SMC_outsl(a, r, p, l) BUG()
  527. #endif
  528. #if !defined(SMC_insl) || !defined(SMC_outsl)
  529. #define SMC_insl(a, r, p, l) BUG()
  530. #define SMC_outsl(a, r, p, l) BUG()
  531. #endif
  532. #if ! SMC_CAN_USE_16BIT
  533. /*
  534. * Any 16-bit access is performed with two 8-bit accesses if the hardware
  535. * can't do it directly. Most registers are 16-bit so those are mandatory.
  536. */
  537. #define SMC_outw(x, ioaddr, reg) \
  538. do { \
  539. unsigned int __val16 = (x); \
  540. SMC_outb( __val16, ioaddr, reg ); \
  541. SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
  542. } while (0)
  543. #define SMC_inw(ioaddr, reg) \
  544. ({ \
  545. unsigned int __val16; \
  546. __val16 = SMC_inb( ioaddr, reg ); \
  547. __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
  548. __val16; \
  549. })
  550. #define SMC_insw(a, r, p, l) BUG()
  551. #define SMC_outsw(a, r, p, l) BUG()
  552. #endif
  553. #if !defined(SMC_insw) || !defined(SMC_outsw)
  554. #define SMC_insw(a, r, p, l) BUG()
  555. #define SMC_outsw(a, r, p, l) BUG()
  556. #endif
  557. #if ! SMC_CAN_USE_8BIT
  558. #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
  559. #define SMC_outb(x, ioaddr, reg) BUG()
  560. #define SMC_insb(a, r, p, l) BUG()
  561. #define SMC_outsb(a, r, p, l) BUG()
  562. #endif
  563. #if !defined(SMC_insb) || !defined(SMC_outsb)
  564. #define SMC_insb(a, r, p, l) BUG()
  565. #define SMC_outsb(a, r, p, l) BUG()
  566. #endif
  567. #ifndef SMC_CAN_USE_DATACS
  568. #define SMC_CAN_USE_DATACS 0
  569. #endif
  570. #ifndef SMC_IO_SHIFT
  571. #define SMC_IO_SHIFT 0
  572. #endif
  573. #ifndef SMC_IRQ_FLAGS
  574. #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
  575. #endif
  576. #ifndef SMC_INTERRUPT_PREAMBLE
  577. #define SMC_INTERRUPT_PREAMBLE
  578. #endif
  579. /* Because of bank switching, the LAN91x uses only 16 I/O ports */
  580. #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
  581. #define SMC_DATA_EXTENT (4)
  582. /*
  583. . Bank Select Register:
  584. .
  585. . yyyy yyyy 0000 00xx
  586. . xx = bank number
  587. . yyyy yyyy = 0x33, for identification purposes.
  588. */
  589. #define BANK_SELECT (14 << SMC_IO_SHIFT)
  590. // Transmit Control Register
  591. /* BANK 0 */
  592. #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
  593. #define TCR_ENABLE 0x0001 // When 1 we can transmit
  594. #define TCR_LOOP 0x0002 // Controls output pin LBK
  595. #define TCR_FORCOL 0x0004 // When 1 will force a collision
  596. #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
  597. #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
  598. #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
  599. #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
  600. #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
  601. #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
  602. #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
  603. #define TCR_CLEAR 0 /* do NOTHING */
  604. /* the default settings for the TCR register : */
  605. #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
  606. // EPH Status Register
  607. /* BANK 0 */
  608. #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
  609. #define ES_TX_SUC 0x0001 // Last TX was successful
  610. #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
  611. #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
  612. #define ES_LTX_MULT 0x0008 // Last tx was a multicast
  613. #define ES_16COL 0x0010 // 16 Collisions Reached
  614. #define ES_SQET 0x0020 // Signal Quality Error Test
  615. #define ES_LTXBRD 0x0040 // Last tx was a broadcast
  616. #define ES_TXDEFR 0x0080 // Transmit Deferred
  617. #define ES_LATCOL 0x0200 // Late collision detected on last tx
  618. #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
  619. #define ES_EXC_DEF 0x0800 // Excessive Deferral
  620. #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
  621. #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
  622. #define ES_TXUNRN 0x8000 // Tx Underrun
  623. // Receive Control Register
  624. /* BANK 0 */
  625. #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
  626. #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
  627. #define RCR_PRMS 0x0002 // Enable promiscuous mode
  628. #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
  629. #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
  630. #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
  631. #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
  632. #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
  633. #define RCR_SOFTRST 0x8000 // resets the chip
  634. /* the normal settings for the RCR register : */
  635. #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
  636. #define RCR_CLEAR 0x0 // set it to a base state
  637. // Counter Register
  638. /* BANK 0 */
  639. #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
  640. // Memory Information Register
  641. /* BANK 0 */
  642. #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
  643. // Receive/Phy Control Register
  644. /* BANK 0 */
  645. #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
  646. #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
  647. #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
  648. #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
  649. #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
  650. #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
  651. #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
  652. #define RPC_LED_RES (0x01) // LED = Reserved
  653. #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
  654. #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
  655. #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
  656. #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
  657. #define RPC_LED_TX (0x06) // LED = TX packet occurred
  658. #define RPC_LED_RX (0x07) // LED = RX packet occurred
  659. #ifndef RPC_LSA_DEFAULT
  660. #define RPC_LSA_DEFAULT RPC_LED_100
  661. #endif
  662. #ifndef RPC_LSB_DEFAULT
  663. #define RPC_LSB_DEFAULT RPC_LED_FD
  664. #endif
  665. #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
  666. /* Bank 0 0x0C is reserved */
  667. // Bank Select Register
  668. /* All Banks */
  669. #define BSR_REG 0x000E
  670. // Configuration Reg
  671. /* BANK 1 */
  672. #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
  673. #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
  674. #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
  675. #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
  676. #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
  677. // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
  678. #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
  679. // Base Address Register
  680. /* BANK 1 */
  681. #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
  682. // Individual Address Registers
  683. /* BANK 1 */
  684. #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
  685. #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
  686. #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
  687. // General Purpose Register
  688. /* BANK 1 */
  689. #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
  690. // Control Register
  691. /* BANK 1 */
  692. #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
  693. #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
  694. #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
  695. #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
  696. #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
  697. #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
  698. #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
  699. #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
  700. #define CTL_STORE 0x0001 // When set stores registers into EEPROM
  701. // MMU Command Register
  702. /* BANK 2 */
  703. #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
  704. #define MC_BUSY 1 // When 1 the last release has not completed
  705. #define MC_NOP (0<<5) // No Op
  706. #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
  707. #define MC_RESET (2<<5) // Reset MMU to initial state
  708. #define MC_REMOVE (3<<5) // Remove the current rx packet
  709. #define MC_RELEASE (4<<5) // Remove and release the current rx packet
  710. #define MC_FREEPKT (5<<5) // Release packet in PNR register
  711. #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
  712. #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
  713. // Packet Number Register
  714. /* BANK 2 */
  715. #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
  716. // Allocation Result Register
  717. /* BANK 2 */
  718. #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
  719. #define AR_FAILED 0x80 // Alocation Failed
  720. // TX FIFO Ports Register
  721. /* BANK 2 */
  722. #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
  723. #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
  724. // RX FIFO Ports Register
  725. /* BANK 2 */
  726. #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
  727. #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
  728. #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
  729. // Pointer Register
  730. /* BANK 2 */
  731. #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
  732. #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
  733. #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
  734. #define PTR_READ 0x2000 // When 1 the operation is a read
  735. // Data Register
  736. /* BANK 2 */
  737. #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
  738. // Interrupt Status/Acknowledge Register
  739. /* BANK 2 */
  740. #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
  741. // Interrupt Mask Register
  742. /* BANK 2 */
  743. #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
  744. #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
  745. #define IM_ERCV_INT 0x40 // Early Receive Interrupt
  746. #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
  747. #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
  748. #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
  749. #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
  750. #define IM_TX_INT 0x02 // Transmit Interrupt
  751. #define IM_RCV_INT 0x01 // Receive Interrupt
  752. // Multicast Table Registers
  753. /* BANK 3 */
  754. #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
  755. #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
  756. #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
  757. #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
  758. // Management Interface Register (MII)
  759. /* BANK 3 */
  760. #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
  761. #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
  762. #define MII_MDOE 0x0008 // MII Output Enable
  763. #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
  764. #define MII_MDI 0x0002 // MII Input, pin MDI
  765. #define MII_MDO 0x0001 // MII Output, pin MDO
  766. // Revision Register
  767. /* BANK 3 */
  768. /* ( hi: chip id low: rev # ) */
  769. #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
  770. // Early RCV Register
  771. /* BANK 3 */
  772. /* this is NOT on SMC9192 */
  773. #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
  774. #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
  775. #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
  776. // External Register
  777. /* BANK 7 */
  778. #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
  779. #define CHIP_9192 3
  780. #define CHIP_9194 4
  781. #define CHIP_9195 5
  782. #define CHIP_9196 6
  783. #define CHIP_91100 7
  784. #define CHIP_91100FD 8
  785. #define CHIP_91111FD 9
  786. static const char * chip_ids[ 16 ] = {
  787. NULL, NULL, NULL,
  788. /* 3 */ "SMC91C90/91C92",
  789. /* 4 */ "SMC91C94",
  790. /* 5 */ "SMC91C95",
  791. /* 6 */ "SMC91C96",
  792. /* 7 */ "SMC91C100",
  793. /* 8 */ "SMC91C100FD",
  794. /* 9 */ "SMC91C11xFD",
  795. NULL, NULL, NULL,
  796. NULL, NULL, NULL};
  797. /*
  798. . Receive status bits
  799. */
  800. #define RS_ALGNERR 0x8000
  801. #define RS_BRODCAST 0x4000
  802. #define RS_BADCRC 0x2000
  803. #define RS_ODDFRAME 0x1000
  804. #define RS_TOOLONG 0x0800
  805. #define RS_TOOSHORT 0x0400
  806. #define RS_MULTICAST 0x0001
  807. #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
  808. /*
  809. * PHY IDs
  810. * LAN83C183 == LAN91C111 Internal PHY
  811. */
  812. #define PHY_LAN83C183 0x0016f840
  813. #define PHY_LAN83C180 0x02821c50
  814. /*
  815. * PHY Register Addresses (LAN91C111 Internal PHY)
  816. *
  817. * Generic PHY registers can be found in <linux/mii.h>
  818. *
  819. * These phy registers are specific to our on-board phy.
  820. */
  821. // PHY Configuration Register 1
  822. #define PHY_CFG1_REG 0x10
  823. #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
  824. #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
  825. #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
  826. #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
  827. #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
  828. #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
  829. #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
  830. #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
  831. #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
  832. #define PHY_CFG1_TLVL_MASK 0x003C
  833. #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
  834. // PHY Configuration Register 2
  835. #define PHY_CFG2_REG 0x11
  836. #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
  837. #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
  838. #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
  839. #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
  840. // PHY Status Output (and Interrupt status) Register
  841. #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
  842. #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
  843. #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
  844. #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
  845. #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
  846. #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
  847. #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
  848. #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
  849. #define PHY_INT_JAB 0x0100 // 1=Jabber detected
  850. #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
  851. #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
  852. // PHY Interrupt/Status Mask Register
  853. #define PHY_MASK_REG 0x13 // Interrupt Mask
  854. // Uses the same bit definitions as PHY_INT_REG
  855. /*
  856. * SMC91C96 ethernet config and status registers.
  857. * These are in the "attribute" space.
  858. */
  859. #define ECOR 0x8000
  860. #define ECOR_RESET 0x80
  861. #define ECOR_LEVEL_IRQ 0x40
  862. #define ECOR_WR_ATTRIB 0x04
  863. #define ECOR_ENABLE 0x01
  864. #define ECSR 0x8002
  865. #define ECSR_IOIS8 0x20
  866. #define ECSR_PWRDWN 0x04
  867. #define ECSR_INT 0x02
  868. #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
  869. /*
  870. * Macros to abstract register access according to the data bus
  871. * capabilities. Please use those and not the in/out primitives.
  872. * Note: the following macros do *not* select the bank -- this must
  873. * be done separately as needed in the main code. The SMC_REG() macro
  874. * only uses the bank argument for debugging purposes (when enabled).
  875. *
  876. * Note: despite inline functions being safer, everything leading to this
  877. * should preferably be macros to let BUG() display the line number in
  878. * the core source code since we're interested in the top call site
  879. * not in any inline function location.
  880. */
  881. #if SMC_DEBUG > 0
  882. #define SMC_REG(lp, reg, bank) \
  883. ({ \
  884. int __b = SMC_CURRENT_BANK(lp); \
  885. if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
  886. printk( "%s: bank reg screwed (0x%04x)\n", \
  887. CARDNAME, __b ); \
  888. BUG(); \
  889. } \
  890. reg<<SMC_IO_SHIFT; \
  891. })
  892. #else
  893. #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
  894. #endif
  895. /*
  896. * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
  897. * aligned to a 32 bit boundary. I tell you that does exist!
  898. * Fortunately the affected register accesses can be easily worked around
  899. * since we can write zeroes to the preceeding 16 bits without adverse
  900. * effects and use a 32-bit access.
  901. *
  902. * Enforce it on any 32-bit capable setup for now.
  903. */
  904. #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
  905. #define SMC_GET_PN(lp) \
  906. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
  907. : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
  908. #define SMC_SET_PN(lp, x) \
  909. do { \
  910. if (SMC_MUST_ALIGN_WRITE(lp)) \
  911. SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
  912. else if (SMC_8BIT(lp)) \
  913. SMC_outb(x, ioaddr, PN_REG(lp)); \
  914. else \
  915. SMC_outw(x, ioaddr, PN_REG(lp)); \
  916. } while (0)
  917. #define SMC_GET_AR(lp) \
  918. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
  919. : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
  920. #define SMC_GET_TXFIFO(lp) \
  921. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
  922. : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
  923. #define SMC_GET_RXFIFO(lp) \
  924. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
  925. : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
  926. #define SMC_GET_INT(lp) \
  927. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
  928. : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
  929. #define SMC_ACK_INT(lp, x) \
  930. do { \
  931. if (SMC_8BIT(lp)) \
  932. SMC_outb(x, ioaddr, INT_REG(lp)); \
  933. else { \
  934. unsigned long __flags; \
  935. int __mask; \
  936. local_irq_save(__flags); \
  937. __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
  938. SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
  939. local_irq_restore(__flags); \
  940. } \
  941. } while (0)
  942. #define SMC_GET_INT_MASK(lp) \
  943. (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
  944. : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
  945. #define SMC_SET_INT_MASK(lp, x) \
  946. do { \
  947. if (SMC_8BIT(lp)) \
  948. SMC_outb(x, ioaddr, IM_REG(lp)); \
  949. else \
  950. SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
  951. } while (0)
  952. #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
  953. #define SMC_SELECT_BANK(lp, x) \
  954. do { \
  955. if (SMC_MUST_ALIGN_WRITE(lp)) \
  956. SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
  957. else \
  958. SMC_outw(x, ioaddr, BANK_SELECT); \
  959. } while (0)
  960. #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
  961. #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
  962. #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
  963. #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
  964. #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
  965. #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
  966. #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
  967. #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
  968. #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
  969. #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
  970. #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
  971. #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
  972. #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
  973. #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
  974. #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
  975. #define SMC_SET_PTR(lp, x) \
  976. do { \
  977. if (SMC_MUST_ALIGN_WRITE(lp)) \
  978. SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
  979. else \
  980. SMC_outw(x, ioaddr, PTR_REG(lp)); \
  981. } while (0)
  982. #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
  983. #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
  984. #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
  985. #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
  986. #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
  987. #define SMC_SET_RPC(lp, x) \
  988. do { \
  989. if (SMC_MUST_ALIGN_WRITE(lp)) \
  990. SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
  991. else \
  992. SMC_outw(x, ioaddr, RPC_REG(lp)); \
  993. } while (0)
  994. #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
  995. #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
  996. #ifndef SMC_GET_MAC_ADDR
  997. #define SMC_GET_MAC_ADDR(lp, addr) \
  998. do { \
  999. unsigned int __v; \
  1000. __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
  1001. addr[0] = __v; addr[1] = __v >> 8; \
  1002. __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
  1003. addr[2] = __v; addr[3] = __v >> 8; \
  1004. __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
  1005. addr[4] = __v; addr[5] = __v >> 8; \
  1006. } while (0)
  1007. #endif
  1008. #define SMC_SET_MAC_ADDR(lp, addr) \
  1009. do { \
  1010. SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
  1011. SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
  1012. SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
  1013. } while (0)
  1014. #define SMC_SET_MCAST(lp, x) \
  1015. do { \
  1016. const unsigned char *mt = (x); \
  1017. SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
  1018. SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
  1019. SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
  1020. SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
  1021. } while (0)
  1022. #define SMC_PUT_PKT_HDR(lp, status, length) \
  1023. do { \
  1024. if (SMC_32BIT(lp)) \
  1025. SMC_outl((status) | (length)<<16, ioaddr, \
  1026. DATA_REG(lp)); \
  1027. else { \
  1028. SMC_outw(status, ioaddr, DATA_REG(lp)); \
  1029. SMC_outw(length, ioaddr, DATA_REG(lp)); \
  1030. } \
  1031. } while (0)
  1032. #define SMC_GET_PKT_HDR(lp, status, length) \
  1033. do { \
  1034. if (SMC_32BIT(lp)) { \
  1035. unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
  1036. (status) = __val & 0xffff; \
  1037. (length) = __val >> 16; \
  1038. } else { \
  1039. (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
  1040. (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
  1041. } \
  1042. } while (0)
  1043. #define SMC_PUSH_DATA(lp, p, l) \
  1044. do { \
  1045. if (SMC_32BIT(lp)) { \
  1046. void *__ptr = (p); \
  1047. int __len = (l); \
  1048. void __iomem *__ioaddr = ioaddr; \
  1049. if (__len >= 2 && (unsigned long)__ptr & 2) { \
  1050. __len -= 2; \
  1051. SMC_outw(*(u16 *)__ptr, ioaddr, \
  1052. DATA_REG(lp)); \
  1053. __ptr += 2; \
  1054. } \
  1055. if (SMC_CAN_USE_DATACS && lp->datacs) \
  1056. __ioaddr = lp->datacs; \
  1057. SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
  1058. if (__len & 2) { \
  1059. __ptr += (__len & ~3); \
  1060. SMC_outw(*((u16 *)__ptr), ioaddr, \
  1061. DATA_REG(lp)); \
  1062. } \
  1063. } else if (SMC_16BIT(lp)) \
  1064. SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
  1065. else if (SMC_8BIT(lp)) \
  1066. SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
  1067. } while (0)
  1068. #define SMC_PULL_DATA(lp, p, l) \
  1069. do { \
  1070. if (SMC_32BIT(lp)) { \
  1071. void *__ptr = (p); \
  1072. int __len = (l); \
  1073. void __iomem *__ioaddr = ioaddr; \
  1074. if ((unsigned long)__ptr & 2) { \
  1075. /* \
  1076. * We want 32bit alignment here. \
  1077. * Since some buses perform a full \
  1078. * 32bit fetch even for 16bit data \
  1079. * we can't use SMC_inw() here. \
  1080. * Back both source (on-chip) and \
  1081. * destination pointers of 2 bytes. \
  1082. * This is possible since the call to \
  1083. * SMC_GET_PKT_HDR() already advanced \
  1084. * the source pointer of 4 bytes, and \
  1085. * the skb_reserve(skb, 2) advanced \
  1086. * the destination pointer of 2 bytes. \
  1087. */ \
  1088. __ptr -= 2; \
  1089. __len += 2; \
  1090. SMC_SET_PTR(lp, \
  1091. 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
  1092. } \
  1093. if (SMC_CAN_USE_DATACS && lp->datacs) \
  1094. __ioaddr = lp->datacs; \
  1095. __len += 2; \
  1096. SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
  1097. } else if (SMC_16BIT(lp)) \
  1098. SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
  1099. else if (SMC_8BIT(lp)) \
  1100. SMC_insb(ioaddr, DATA_REG(lp), p, l); \
  1101. } while (0)
  1102. #endif /* _SMC91X_H_ */