skge.c 106 KB

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  1. /*
  2. * New driver for Marvell Yukon chipset and SysKonnect Gigabit
  3. * Ethernet adapters. Based on earlier sk98lin, e100 and
  4. * FreeBSD if_sk drivers.
  5. *
  6. * This driver intentionally does not support all the features
  7. * of the original driver such as link fail-over and link management because
  8. * those should be done at higher levels.
  9. *
  10. * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #include <linux/in.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/pci.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/ip.h>
  35. #include <linux/delay.h>
  36. #include <linux/crc32.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/debugfs.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/mii.h>
  41. #include <asm/irq.h>
  42. #include "skge.h"
  43. #define DRV_NAME "skge"
  44. #define DRV_VERSION "1.13"
  45. #define PFX DRV_NAME " "
  46. #define DEFAULT_TX_RING_SIZE 128
  47. #define DEFAULT_RX_RING_SIZE 512
  48. #define MAX_TX_RING_SIZE 1024
  49. #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
  50. #define MAX_RX_RING_SIZE 4096
  51. #define RX_COPY_THRESHOLD 128
  52. #define RX_BUF_SIZE 1536
  53. #define PHY_RETRIES 1000
  54. #define ETH_JUMBO_MTU 9000
  55. #define TX_WATCHDOG (5 * HZ)
  56. #define NAPI_WEIGHT 64
  57. #define BLINK_MS 250
  58. #define LINK_HZ HZ
  59. #define SKGE_EEPROM_MAGIC 0x9933aabb
  60. MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
  61. MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
  62. MODULE_LICENSE("GPL");
  63. MODULE_VERSION(DRV_VERSION);
  64. static const u32 default_msg
  65. = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
  66. | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
  67. static int debug = -1; /* defaults above */
  68. module_param(debug, int, 0);
  69. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  70. static const struct pci_device_id skge_id_table[] = {
  71. { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
  76. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
  77. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
  78. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
  79. { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
  81. { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
  82. { 0 }
  83. };
  84. MODULE_DEVICE_TABLE(pci, skge_id_table);
  85. static int skge_up(struct net_device *dev);
  86. static int skge_down(struct net_device *dev);
  87. static void skge_phy_reset(struct skge_port *skge);
  88. static void skge_tx_clean(struct net_device *dev);
  89. static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  90. static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  91. static void genesis_get_stats(struct skge_port *skge, u64 *data);
  92. static void yukon_get_stats(struct skge_port *skge, u64 *data);
  93. static void yukon_init(struct skge_hw *hw, int port);
  94. static void genesis_mac_init(struct skge_hw *hw, int port);
  95. static void genesis_link_up(struct skge_port *skge);
  96. /* Avoid conditionals by using array */
  97. static const int txqaddr[] = { Q_XA1, Q_XA2 };
  98. static const int rxqaddr[] = { Q_R1, Q_R2 };
  99. static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
  100. static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
  101. static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
  102. static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
  103. static int skge_get_regs_len(struct net_device *dev)
  104. {
  105. return 0x4000;
  106. }
  107. /*
  108. * Returns copy of whole control register region
  109. * Note: skip RAM address register because accessing it will
  110. * cause bus hangs!
  111. */
  112. static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  113. void *p)
  114. {
  115. const struct skge_port *skge = netdev_priv(dev);
  116. const void __iomem *io = skge->hw->regs;
  117. regs->version = 1;
  118. memset(p, 0, regs->len);
  119. memcpy_fromio(p, io, B3_RAM_ADDR);
  120. memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
  121. regs->len - B3_RI_WTO_R1);
  122. }
  123. /* Wake on Lan only supported on Yukon chips with rev 1 or above */
  124. static u32 wol_supported(const struct skge_hw *hw)
  125. {
  126. if (hw->chip_id == CHIP_ID_GENESIS)
  127. return 0;
  128. if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
  129. return 0;
  130. return WAKE_MAGIC | WAKE_PHY;
  131. }
  132. static u32 pci_wake_enabled(struct pci_dev *dev)
  133. {
  134. int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  135. u16 value;
  136. /* If device doesn't support PM Capabilities, but request is to disable
  137. * wake events, it's a nop; otherwise fail */
  138. if (!pm)
  139. return 0;
  140. pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
  141. value &= PCI_PM_CAP_PME_MASK;
  142. value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
  143. return value != 0;
  144. }
  145. static void skge_wol_init(struct skge_port *skge)
  146. {
  147. struct skge_hw *hw = skge->hw;
  148. int port = skge->port;
  149. u16 ctrl;
  150. skge_write16(hw, B0_CTST, CS_RST_CLR);
  151. skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
  152. /* Turn on Vaux */
  153. skge_write8(hw, B0_POWER_CTRL,
  154. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
  155. /* WA code for COMA mode -- clear PHY reset */
  156. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  157. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  158. u32 reg = skge_read32(hw, B2_GP_IO);
  159. reg |= GP_DIR_9;
  160. reg &= ~GP_IO_9;
  161. skge_write32(hw, B2_GP_IO, reg);
  162. }
  163. skge_write32(hw, SK_REG(port, GPHY_CTRL),
  164. GPC_DIS_SLEEP |
  165. GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
  166. GPC_ANEG_1 | GPC_RST_SET);
  167. skge_write32(hw, SK_REG(port, GPHY_CTRL),
  168. GPC_DIS_SLEEP |
  169. GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
  170. GPC_ANEG_1 | GPC_RST_CLR);
  171. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  172. /* Force to 10/100 skge_reset will re-enable on resume */
  173. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
  174. PHY_AN_100FULL | PHY_AN_100HALF |
  175. PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
  176. /* no 1000 HD/FD */
  177. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
  178. gm_phy_write(hw, port, PHY_MARV_CTRL,
  179. PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
  180. PHY_CT_RE_CFG | PHY_CT_DUP_MD);
  181. /* Set GMAC to no flow control and auto update for speed/duplex */
  182. gma_write16(hw, port, GM_GP_CTRL,
  183. GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
  184. GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
  185. /* Set WOL address */
  186. memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
  187. skge->netdev->dev_addr, ETH_ALEN);
  188. /* Turn on appropriate WOL control bits */
  189. skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
  190. ctrl = 0;
  191. if (skge->wol & WAKE_PHY)
  192. ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
  193. else
  194. ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
  195. if (skge->wol & WAKE_MAGIC)
  196. ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
  197. else
  198. ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
  199. ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
  200. skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
  201. /* block receiver */
  202. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  203. }
  204. static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  205. {
  206. struct skge_port *skge = netdev_priv(dev);
  207. wol->supported = wol_supported(skge->hw);
  208. wol->wolopts = skge->wol;
  209. }
  210. static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  211. {
  212. struct skge_port *skge = netdev_priv(dev);
  213. struct skge_hw *hw = skge->hw;
  214. if (wol->wolopts & ~wol_supported(hw))
  215. return -EOPNOTSUPP;
  216. skge->wol = wol->wolopts;
  217. return 0;
  218. }
  219. /* Determine supported/advertised modes based on hardware.
  220. * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
  221. */
  222. static u32 skge_supported_modes(const struct skge_hw *hw)
  223. {
  224. u32 supported;
  225. if (hw->copper) {
  226. supported = SUPPORTED_10baseT_Half
  227. | SUPPORTED_10baseT_Full
  228. | SUPPORTED_100baseT_Half
  229. | SUPPORTED_100baseT_Full
  230. | SUPPORTED_1000baseT_Half
  231. | SUPPORTED_1000baseT_Full
  232. | SUPPORTED_Autoneg| SUPPORTED_TP;
  233. if (hw->chip_id == CHIP_ID_GENESIS)
  234. supported &= ~(SUPPORTED_10baseT_Half
  235. | SUPPORTED_10baseT_Full
  236. | SUPPORTED_100baseT_Half
  237. | SUPPORTED_100baseT_Full);
  238. else if (hw->chip_id == CHIP_ID_YUKON)
  239. supported &= ~SUPPORTED_1000baseT_Half;
  240. } else
  241. supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
  242. | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
  243. return supported;
  244. }
  245. static int skge_get_settings(struct net_device *dev,
  246. struct ethtool_cmd *ecmd)
  247. {
  248. struct skge_port *skge = netdev_priv(dev);
  249. struct skge_hw *hw = skge->hw;
  250. ecmd->transceiver = XCVR_INTERNAL;
  251. ecmd->supported = skge_supported_modes(hw);
  252. if (hw->copper) {
  253. ecmd->port = PORT_TP;
  254. ecmd->phy_address = hw->phy_addr;
  255. } else
  256. ecmd->port = PORT_FIBRE;
  257. ecmd->advertising = skge->advertising;
  258. ecmd->autoneg = skge->autoneg;
  259. ecmd->speed = skge->speed;
  260. ecmd->duplex = skge->duplex;
  261. return 0;
  262. }
  263. static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  264. {
  265. struct skge_port *skge = netdev_priv(dev);
  266. const struct skge_hw *hw = skge->hw;
  267. u32 supported = skge_supported_modes(hw);
  268. if (ecmd->autoneg == AUTONEG_ENABLE) {
  269. ecmd->advertising = supported;
  270. skge->duplex = -1;
  271. skge->speed = -1;
  272. } else {
  273. u32 setting;
  274. switch (ecmd->speed) {
  275. case SPEED_1000:
  276. if (ecmd->duplex == DUPLEX_FULL)
  277. setting = SUPPORTED_1000baseT_Full;
  278. else if (ecmd->duplex == DUPLEX_HALF)
  279. setting = SUPPORTED_1000baseT_Half;
  280. else
  281. return -EINVAL;
  282. break;
  283. case SPEED_100:
  284. if (ecmd->duplex == DUPLEX_FULL)
  285. setting = SUPPORTED_100baseT_Full;
  286. else if (ecmd->duplex == DUPLEX_HALF)
  287. setting = SUPPORTED_100baseT_Half;
  288. else
  289. return -EINVAL;
  290. break;
  291. case SPEED_10:
  292. if (ecmd->duplex == DUPLEX_FULL)
  293. setting = SUPPORTED_10baseT_Full;
  294. else if (ecmd->duplex == DUPLEX_HALF)
  295. setting = SUPPORTED_10baseT_Half;
  296. else
  297. return -EINVAL;
  298. break;
  299. default:
  300. return -EINVAL;
  301. }
  302. if ((setting & supported) == 0)
  303. return -EINVAL;
  304. skge->speed = ecmd->speed;
  305. skge->duplex = ecmd->duplex;
  306. }
  307. skge->autoneg = ecmd->autoneg;
  308. skge->advertising = ecmd->advertising;
  309. if (netif_running(dev))
  310. skge_phy_reset(skge);
  311. return (0);
  312. }
  313. static void skge_get_drvinfo(struct net_device *dev,
  314. struct ethtool_drvinfo *info)
  315. {
  316. struct skge_port *skge = netdev_priv(dev);
  317. strcpy(info->driver, DRV_NAME);
  318. strcpy(info->version, DRV_VERSION);
  319. strcpy(info->fw_version, "N/A");
  320. strcpy(info->bus_info, pci_name(skge->hw->pdev));
  321. }
  322. static const struct skge_stat {
  323. char name[ETH_GSTRING_LEN];
  324. u16 xmac_offset;
  325. u16 gma_offset;
  326. } skge_stats[] = {
  327. { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
  328. { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
  329. { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
  330. { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
  331. { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
  332. { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
  333. { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
  334. { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
  335. { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
  336. { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
  337. { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
  338. { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
  339. { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
  340. { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
  341. { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
  342. { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
  343. { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
  344. { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
  345. { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
  346. { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
  347. { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
  348. };
  349. static int skge_get_sset_count(struct net_device *dev, int sset)
  350. {
  351. switch (sset) {
  352. case ETH_SS_STATS:
  353. return ARRAY_SIZE(skge_stats);
  354. default:
  355. return -EOPNOTSUPP;
  356. }
  357. }
  358. static void skge_get_ethtool_stats(struct net_device *dev,
  359. struct ethtool_stats *stats, u64 *data)
  360. {
  361. struct skge_port *skge = netdev_priv(dev);
  362. if (skge->hw->chip_id == CHIP_ID_GENESIS)
  363. genesis_get_stats(skge, data);
  364. else
  365. yukon_get_stats(skge, data);
  366. }
  367. /* Use hardware MIB variables for critical path statistics and
  368. * transmit feedback not reported at interrupt.
  369. * Other errors are accounted for in interrupt handler.
  370. */
  371. static struct net_device_stats *skge_get_stats(struct net_device *dev)
  372. {
  373. struct skge_port *skge = netdev_priv(dev);
  374. u64 data[ARRAY_SIZE(skge_stats)];
  375. if (skge->hw->chip_id == CHIP_ID_GENESIS)
  376. genesis_get_stats(skge, data);
  377. else
  378. yukon_get_stats(skge, data);
  379. dev->stats.tx_bytes = data[0];
  380. dev->stats.rx_bytes = data[1];
  381. dev->stats.tx_packets = data[2] + data[4] + data[6];
  382. dev->stats.rx_packets = data[3] + data[5] + data[7];
  383. dev->stats.multicast = data[3] + data[5];
  384. dev->stats.collisions = data[10];
  385. dev->stats.tx_aborted_errors = data[12];
  386. return &dev->stats;
  387. }
  388. static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  389. {
  390. int i;
  391. switch (stringset) {
  392. case ETH_SS_STATS:
  393. for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
  394. memcpy(data + i * ETH_GSTRING_LEN,
  395. skge_stats[i].name, ETH_GSTRING_LEN);
  396. break;
  397. }
  398. }
  399. static void skge_get_ring_param(struct net_device *dev,
  400. struct ethtool_ringparam *p)
  401. {
  402. struct skge_port *skge = netdev_priv(dev);
  403. p->rx_max_pending = MAX_RX_RING_SIZE;
  404. p->tx_max_pending = MAX_TX_RING_SIZE;
  405. p->rx_mini_max_pending = 0;
  406. p->rx_jumbo_max_pending = 0;
  407. p->rx_pending = skge->rx_ring.count;
  408. p->tx_pending = skge->tx_ring.count;
  409. p->rx_mini_pending = 0;
  410. p->rx_jumbo_pending = 0;
  411. }
  412. static int skge_set_ring_param(struct net_device *dev,
  413. struct ethtool_ringparam *p)
  414. {
  415. struct skge_port *skge = netdev_priv(dev);
  416. int err;
  417. if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
  418. p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
  419. return -EINVAL;
  420. skge->rx_ring.count = p->rx_pending;
  421. skge->tx_ring.count = p->tx_pending;
  422. if (netif_running(dev)) {
  423. skge_down(dev);
  424. err = skge_up(dev);
  425. if (err)
  426. dev_close(dev);
  427. }
  428. return 0;
  429. }
  430. static u32 skge_get_msglevel(struct net_device *netdev)
  431. {
  432. struct skge_port *skge = netdev_priv(netdev);
  433. return skge->msg_enable;
  434. }
  435. static void skge_set_msglevel(struct net_device *netdev, u32 value)
  436. {
  437. struct skge_port *skge = netdev_priv(netdev);
  438. skge->msg_enable = value;
  439. }
  440. static int skge_nway_reset(struct net_device *dev)
  441. {
  442. struct skge_port *skge = netdev_priv(dev);
  443. if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
  444. return -EINVAL;
  445. skge_phy_reset(skge);
  446. return 0;
  447. }
  448. static int skge_set_sg(struct net_device *dev, u32 data)
  449. {
  450. struct skge_port *skge = netdev_priv(dev);
  451. struct skge_hw *hw = skge->hw;
  452. if (hw->chip_id == CHIP_ID_GENESIS && data)
  453. return -EOPNOTSUPP;
  454. return ethtool_op_set_sg(dev, data);
  455. }
  456. static int skge_set_tx_csum(struct net_device *dev, u32 data)
  457. {
  458. struct skge_port *skge = netdev_priv(dev);
  459. struct skge_hw *hw = skge->hw;
  460. if (hw->chip_id == CHIP_ID_GENESIS && data)
  461. return -EOPNOTSUPP;
  462. return ethtool_op_set_tx_csum(dev, data);
  463. }
  464. static u32 skge_get_rx_csum(struct net_device *dev)
  465. {
  466. struct skge_port *skge = netdev_priv(dev);
  467. return skge->rx_csum;
  468. }
  469. /* Only Yukon supports checksum offload. */
  470. static int skge_set_rx_csum(struct net_device *dev, u32 data)
  471. {
  472. struct skge_port *skge = netdev_priv(dev);
  473. if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
  474. return -EOPNOTSUPP;
  475. skge->rx_csum = data;
  476. return 0;
  477. }
  478. static void skge_get_pauseparam(struct net_device *dev,
  479. struct ethtool_pauseparam *ecmd)
  480. {
  481. struct skge_port *skge = netdev_priv(dev);
  482. ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
  483. || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
  484. ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
  485. ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
  486. }
  487. static int skge_set_pauseparam(struct net_device *dev,
  488. struct ethtool_pauseparam *ecmd)
  489. {
  490. struct skge_port *skge = netdev_priv(dev);
  491. struct ethtool_pauseparam old;
  492. skge_get_pauseparam(dev, &old);
  493. if (ecmd->autoneg != old.autoneg)
  494. skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
  495. else {
  496. if (ecmd->rx_pause && ecmd->tx_pause)
  497. skge->flow_control = FLOW_MODE_SYMMETRIC;
  498. else if (ecmd->rx_pause && !ecmd->tx_pause)
  499. skge->flow_control = FLOW_MODE_SYM_OR_REM;
  500. else if (!ecmd->rx_pause && ecmd->tx_pause)
  501. skge->flow_control = FLOW_MODE_LOC_SEND;
  502. else
  503. skge->flow_control = FLOW_MODE_NONE;
  504. }
  505. if (netif_running(dev))
  506. skge_phy_reset(skge);
  507. return 0;
  508. }
  509. /* Chip internal frequency for clock calculations */
  510. static inline u32 hwkhz(const struct skge_hw *hw)
  511. {
  512. return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
  513. }
  514. /* Chip HZ to microseconds */
  515. static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
  516. {
  517. return (ticks * 1000) / hwkhz(hw);
  518. }
  519. /* Microseconds to chip HZ */
  520. static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
  521. {
  522. return hwkhz(hw) * usec / 1000;
  523. }
  524. static int skge_get_coalesce(struct net_device *dev,
  525. struct ethtool_coalesce *ecmd)
  526. {
  527. struct skge_port *skge = netdev_priv(dev);
  528. struct skge_hw *hw = skge->hw;
  529. int port = skge->port;
  530. ecmd->rx_coalesce_usecs = 0;
  531. ecmd->tx_coalesce_usecs = 0;
  532. if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
  533. u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
  534. u32 msk = skge_read32(hw, B2_IRQM_MSK);
  535. if (msk & rxirqmask[port])
  536. ecmd->rx_coalesce_usecs = delay;
  537. if (msk & txirqmask[port])
  538. ecmd->tx_coalesce_usecs = delay;
  539. }
  540. return 0;
  541. }
  542. /* Note: interrupt timer is per board, but can turn on/off per port */
  543. static int skge_set_coalesce(struct net_device *dev,
  544. struct ethtool_coalesce *ecmd)
  545. {
  546. struct skge_port *skge = netdev_priv(dev);
  547. struct skge_hw *hw = skge->hw;
  548. int port = skge->port;
  549. u32 msk = skge_read32(hw, B2_IRQM_MSK);
  550. u32 delay = 25;
  551. if (ecmd->rx_coalesce_usecs == 0)
  552. msk &= ~rxirqmask[port];
  553. else if (ecmd->rx_coalesce_usecs < 25 ||
  554. ecmd->rx_coalesce_usecs > 33333)
  555. return -EINVAL;
  556. else {
  557. msk |= rxirqmask[port];
  558. delay = ecmd->rx_coalesce_usecs;
  559. }
  560. if (ecmd->tx_coalesce_usecs == 0)
  561. msk &= ~txirqmask[port];
  562. else if (ecmd->tx_coalesce_usecs < 25 ||
  563. ecmd->tx_coalesce_usecs > 33333)
  564. return -EINVAL;
  565. else {
  566. msk |= txirqmask[port];
  567. delay = min(delay, ecmd->rx_coalesce_usecs);
  568. }
  569. skge_write32(hw, B2_IRQM_MSK, msk);
  570. if (msk == 0)
  571. skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
  572. else {
  573. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
  574. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  575. }
  576. return 0;
  577. }
  578. enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
  579. static void skge_led(struct skge_port *skge, enum led_mode mode)
  580. {
  581. struct skge_hw *hw = skge->hw;
  582. int port = skge->port;
  583. spin_lock_bh(&hw->phy_lock);
  584. if (hw->chip_id == CHIP_ID_GENESIS) {
  585. switch (mode) {
  586. case LED_MODE_OFF:
  587. if (hw->phy_type == SK_PHY_BCOM)
  588. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
  589. else {
  590. skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
  591. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
  592. }
  593. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  594. skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
  595. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
  596. break;
  597. case LED_MODE_ON:
  598. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
  599. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
  600. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  601. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  602. break;
  603. case LED_MODE_TST:
  604. skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
  605. skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
  606. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  607. if (hw->phy_type == SK_PHY_BCOM)
  608. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
  609. else {
  610. skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
  611. skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
  612. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  613. }
  614. }
  615. } else {
  616. switch (mode) {
  617. case LED_MODE_OFF:
  618. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  619. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  620. PHY_M_LED_MO_DUP(MO_LED_OFF) |
  621. PHY_M_LED_MO_10(MO_LED_OFF) |
  622. PHY_M_LED_MO_100(MO_LED_OFF) |
  623. PHY_M_LED_MO_1000(MO_LED_OFF) |
  624. PHY_M_LED_MO_RX(MO_LED_OFF));
  625. break;
  626. case LED_MODE_ON:
  627. gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
  628. PHY_M_LED_PULS_DUR(PULS_170MS) |
  629. PHY_M_LED_BLINK_RT(BLINK_84MS) |
  630. PHY_M_LEDC_TX_CTRL |
  631. PHY_M_LEDC_DP_CTRL);
  632. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  633. PHY_M_LED_MO_RX(MO_LED_OFF) |
  634. (skge->speed == SPEED_100 ?
  635. PHY_M_LED_MO_100(MO_LED_ON) : 0));
  636. break;
  637. case LED_MODE_TST:
  638. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  639. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  640. PHY_M_LED_MO_DUP(MO_LED_ON) |
  641. PHY_M_LED_MO_10(MO_LED_ON) |
  642. PHY_M_LED_MO_100(MO_LED_ON) |
  643. PHY_M_LED_MO_1000(MO_LED_ON) |
  644. PHY_M_LED_MO_RX(MO_LED_ON));
  645. }
  646. }
  647. spin_unlock_bh(&hw->phy_lock);
  648. }
  649. /* blink LED's for finding board */
  650. static int skge_phys_id(struct net_device *dev, u32 data)
  651. {
  652. struct skge_port *skge = netdev_priv(dev);
  653. unsigned long ms;
  654. enum led_mode mode = LED_MODE_TST;
  655. if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
  656. ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
  657. else
  658. ms = data * 1000;
  659. while (ms > 0) {
  660. skge_led(skge, mode);
  661. mode ^= LED_MODE_TST;
  662. if (msleep_interruptible(BLINK_MS))
  663. break;
  664. ms -= BLINK_MS;
  665. }
  666. /* back to regular LED state */
  667. skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
  668. return 0;
  669. }
  670. static int skge_get_eeprom_len(struct net_device *dev)
  671. {
  672. struct skge_port *skge = netdev_priv(dev);
  673. u32 reg2;
  674. pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
  675. return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
  676. }
  677. static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
  678. {
  679. u32 val;
  680. pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
  681. do {
  682. pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
  683. } while (!(offset & PCI_VPD_ADDR_F));
  684. pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
  685. return val;
  686. }
  687. static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
  688. {
  689. pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
  690. pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
  691. offset | PCI_VPD_ADDR_F);
  692. do {
  693. pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
  694. } while (offset & PCI_VPD_ADDR_F);
  695. }
  696. static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  697. u8 *data)
  698. {
  699. struct skge_port *skge = netdev_priv(dev);
  700. struct pci_dev *pdev = skge->hw->pdev;
  701. int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
  702. int length = eeprom->len;
  703. u16 offset = eeprom->offset;
  704. if (!cap)
  705. return -EINVAL;
  706. eeprom->magic = SKGE_EEPROM_MAGIC;
  707. while (length > 0) {
  708. u32 val = skge_vpd_read(pdev, cap, offset);
  709. int n = min_t(int, length, sizeof(val));
  710. memcpy(data, &val, n);
  711. length -= n;
  712. data += n;
  713. offset += n;
  714. }
  715. return 0;
  716. }
  717. static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  718. u8 *data)
  719. {
  720. struct skge_port *skge = netdev_priv(dev);
  721. struct pci_dev *pdev = skge->hw->pdev;
  722. int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
  723. int length = eeprom->len;
  724. u16 offset = eeprom->offset;
  725. if (!cap)
  726. return -EINVAL;
  727. if (eeprom->magic != SKGE_EEPROM_MAGIC)
  728. return -EINVAL;
  729. while (length > 0) {
  730. u32 val;
  731. int n = min_t(int, length, sizeof(val));
  732. if (n < sizeof(val))
  733. val = skge_vpd_read(pdev, cap, offset);
  734. memcpy(&val, data, n);
  735. skge_vpd_write(pdev, cap, offset, val);
  736. length -= n;
  737. data += n;
  738. offset += n;
  739. }
  740. return 0;
  741. }
  742. static const struct ethtool_ops skge_ethtool_ops = {
  743. .get_settings = skge_get_settings,
  744. .set_settings = skge_set_settings,
  745. .get_drvinfo = skge_get_drvinfo,
  746. .get_regs_len = skge_get_regs_len,
  747. .get_regs = skge_get_regs,
  748. .get_wol = skge_get_wol,
  749. .set_wol = skge_set_wol,
  750. .get_msglevel = skge_get_msglevel,
  751. .set_msglevel = skge_set_msglevel,
  752. .nway_reset = skge_nway_reset,
  753. .get_link = ethtool_op_get_link,
  754. .get_eeprom_len = skge_get_eeprom_len,
  755. .get_eeprom = skge_get_eeprom,
  756. .set_eeprom = skge_set_eeprom,
  757. .get_ringparam = skge_get_ring_param,
  758. .set_ringparam = skge_set_ring_param,
  759. .get_pauseparam = skge_get_pauseparam,
  760. .set_pauseparam = skge_set_pauseparam,
  761. .get_coalesce = skge_get_coalesce,
  762. .set_coalesce = skge_set_coalesce,
  763. .set_sg = skge_set_sg,
  764. .set_tx_csum = skge_set_tx_csum,
  765. .get_rx_csum = skge_get_rx_csum,
  766. .set_rx_csum = skge_set_rx_csum,
  767. .get_strings = skge_get_strings,
  768. .phys_id = skge_phys_id,
  769. .get_sset_count = skge_get_sset_count,
  770. .get_ethtool_stats = skge_get_ethtool_stats,
  771. };
  772. /*
  773. * Allocate ring elements and chain them together
  774. * One-to-one association of board descriptors with ring elements
  775. */
  776. static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
  777. {
  778. struct skge_tx_desc *d;
  779. struct skge_element *e;
  780. int i;
  781. ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
  782. if (!ring->start)
  783. return -ENOMEM;
  784. for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
  785. e->desc = d;
  786. if (i == ring->count - 1) {
  787. e->next = ring->start;
  788. d->next_offset = base;
  789. } else {
  790. e->next = e + 1;
  791. d->next_offset = base + (i+1) * sizeof(*d);
  792. }
  793. }
  794. ring->to_use = ring->to_clean = ring->start;
  795. return 0;
  796. }
  797. /* Allocate and setup a new buffer for receiving */
  798. static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
  799. struct sk_buff *skb, unsigned int bufsize)
  800. {
  801. struct skge_rx_desc *rd = e->desc;
  802. u64 map;
  803. map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
  804. PCI_DMA_FROMDEVICE);
  805. rd->dma_lo = map;
  806. rd->dma_hi = map >> 32;
  807. e->skb = skb;
  808. rd->csum1_start = ETH_HLEN;
  809. rd->csum2_start = ETH_HLEN;
  810. rd->csum1 = 0;
  811. rd->csum2 = 0;
  812. wmb();
  813. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
  814. pci_unmap_addr_set(e, mapaddr, map);
  815. pci_unmap_len_set(e, maplen, bufsize);
  816. }
  817. /* Resume receiving using existing skb,
  818. * Note: DMA address is not changed by chip.
  819. * MTU not changed while receiver active.
  820. */
  821. static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
  822. {
  823. struct skge_rx_desc *rd = e->desc;
  824. rd->csum2 = 0;
  825. rd->csum2_start = ETH_HLEN;
  826. wmb();
  827. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
  828. }
  829. /* Free all buffers in receive ring, assumes receiver stopped */
  830. static void skge_rx_clean(struct skge_port *skge)
  831. {
  832. struct skge_hw *hw = skge->hw;
  833. struct skge_ring *ring = &skge->rx_ring;
  834. struct skge_element *e;
  835. e = ring->start;
  836. do {
  837. struct skge_rx_desc *rd = e->desc;
  838. rd->control = 0;
  839. if (e->skb) {
  840. pci_unmap_single(hw->pdev,
  841. pci_unmap_addr(e, mapaddr),
  842. pci_unmap_len(e, maplen),
  843. PCI_DMA_FROMDEVICE);
  844. dev_kfree_skb(e->skb);
  845. e->skb = NULL;
  846. }
  847. } while ((e = e->next) != ring->start);
  848. }
  849. /* Allocate buffers for receive ring
  850. * For receive: to_clean is next received frame.
  851. */
  852. static int skge_rx_fill(struct net_device *dev)
  853. {
  854. struct skge_port *skge = netdev_priv(dev);
  855. struct skge_ring *ring = &skge->rx_ring;
  856. struct skge_element *e;
  857. e = ring->start;
  858. do {
  859. struct sk_buff *skb;
  860. skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
  861. GFP_KERNEL);
  862. if (!skb)
  863. return -ENOMEM;
  864. skb_reserve(skb, NET_IP_ALIGN);
  865. skge_rx_setup(skge, e, skb, skge->rx_buf_size);
  866. } while ( (e = e->next) != ring->start);
  867. ring->to_clean = ring->start;
  868. return 0;
  869. }
  870. static const char *skge_pause(enum pause_status status)
  871. {
  872. switch(status) {
  873. case FLOW_STAT_NONE:
  874. return "none";
  875. case FLOW_STAT_REM_SEND:
  876. return "rx only";
  877. case FLOW_STAT_LOC_SEND:
  878. return "tx_only";
  879. case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
  880. return "both";
  881. default:
  882. return "indeterminated";
  883. }
  884. }
  885. static void skge_link_up(struct skge_port *skge)
  886. {
  887. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
  888. LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
  889. netif_carrier_on(skge->netdev);
  890. netif_wake_queue(skge->netdev);
  891. if (netif_msg_link(skge)) {
  892. printk(KERN_INFO PFX
  893. "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  894. skge->netdev->name, skge->speed,
  895. skge->duplex == DUPLEX_FULL ? "full" : "half",
  896. skge_pause(skge->flow_status));
  897. }
  898. }
  899. static void skge_link_down(struct skge_port *skge)
  900. {
  901. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
  902. netif_carrier_off(skge->netdev);
  903. netif_stop_queue(skge->netdev);
  904. if (netif_msg_link(skge))
  905. printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
  906. }
  907. static void xm_link_down(struct skge_hw *hw, int port)
  908. {
  909. struct net_device *dev = hw->dev[port];
  910. struct skge_port *skge = netdev_priv(dev);
  911. xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
  912. if (netif_carrier_ok(dev))
  913. skge_link_down(skge);
  914. }
  915. static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
  916. {
  917. int i;
  918. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  919. *val = xm_read16(hw, port, XM_PHY_DATA);
  920. if (hw->phy_type == SK_PHY_XMAC)
  921. goto ready;
  922. for (i = 0; i < PHY_RETRIES; i++) {
  923. if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
  924. goto ready;
  925. udelay(1);
  926. }
  927. return -ETIMEDOUT;
  928. ready:
  929. *val = xm_read16(hw, port, XM_PHY_DATA);
  930. return 0;
  931. }
  932. static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
  933. {
  934. u16 v = 0;
  935. if (__xm_phy_read(hw, port, reg, &v))
  936. printk(KERN_WARNING PFX "%s: phy read timed out\n",
  937. hw->dev[port]->name);
  938. return v;
  939. }
  940. static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  941. {
  942. int i;
  943. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  944. for (i = 0; i < PHY_RETRIES; i++) {
  945. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  946. goto ready;
  947. udelay(1);
  948. }
  949. return -EIO;
  950. ready:
  951. xm_write16(hw, port, XM_PHY_DATA, val);
  952. for (i = 0; i < PHY_RETRIES; i++) {
  953. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  954. return 0;
  955. udelay(1);
  956. }
  957. return -ETIMEDOUT;
  958. }
  959. static void genesis_init(struct skge_hw *hw)
  960. {
  961. /* set blink source counter */
  962. skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
  963. skge_write8(hw, B2_BSC_CTRL, BSC_START);
  964. /* configure mac arbiter */
  965. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  966. /* configure mac arbiter timeout values */
  967. skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
  968. skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
  969. skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
  970. skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
  971. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  972. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  973. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  974. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  975. /* configure packet arbiter timeout */
  976. skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
  977. skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
  978. skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
  979. skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
  980. skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
  981. }
  982. static void genesis_reset(struct skge_hw *hw, int port)
  983. {
  984. const u8 zero[8] = { 0 };
  985. u32 reg;
  986. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  987. /* reset the statistics module */
  988. xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
  989. xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
  990. xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
  991. xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
  992. xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
  993. /* disable Broadcom PHY IRQ */
  994. if (hw->phy_type == SK_PHY_BCOM)
  995. xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
  996. xm_outhash(hw, port, XM_HSM, zero);
  997. /* Flush TX and RX fifo */
  998. reg = xm_read32(hw, port, XM_MODE);
  999. xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
  1000. xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
  1001. }
  1002. /* Convert mode to MII values */
  1003. static const u16 phy_pause_map[] = {
  1004. [FLOW_MODE_NONE] = 0,
  1005. [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
  1006. [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
  1007. [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
  1008. };
  1009. /* special defines for FIBER (88E1011S only) */
  1010. static const u16 fiber_pause_map[] = {
  1011. [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
  1012. [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
  1013. [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
  1014. [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
  1015. };
  1016. /* Check status of Broadcom phy link */
  1017. static void bcom_check_link(struct skge_hw *hw, int port)
  1018. {
  1019. struct net_device *dev = hw->dev[port];
  1020. struct skge_port *skge = netdev_priv(dev);
  1021. u16 status;
  1022. /* read twice because of latch */
  1023. xm_phy_read(hw, port, PHY_BCOM_STAT);
  1024. status = xm_phy_read(hw, port, PHY_BCOM_STAT);
  1025. if ((status & PHY_ST_LSYNC) == 0) {
  1026. xm_link_down(hw, port);
  1027. return;
  1028. }
  1029. if (skge->autoneg == AUTONEG_ENABLE) {
  1030. u16 lpa, aux;
  1031. if (!(status & PHY_ST_AN_OVER))
  1032. return;
  1033. lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
  1034. if (lpa & PHY_B_AN_RF) {
  1035. printk(KERN_NOTICE PFX "%s: remote fault\n",
  1036. dev->name);
  1037. return;
  1038. }
  1039. aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
  1040. /* Check Duplex mismatch */
  1041. switch (aux & PHY_B_AS_AN_RES_MSK) {
  1042. case PHY_B_RES_1000FD:
  1043. skge->duplex = DUPLEX_FULL;
  1044. break;
  1045. case PHY_B_RES_1000HD:
  1046. skge->duplex = DUPLEX_HALF;
  1047. break;
  1048. default:
  1049. printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
  1050. dev->name);
  1051. return;
  1052. }
  1053. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1054. switch (aux & PHY_B_AS_PAUSE_MSK) {
  1055. case PHY_B_AS_PAUSE_MSK:
  1056. skge->flow_status = FLOW_STAT_SYMMETRIC;
  1057. break;
  1058. case PHY_B_AS_PRR:
  1059. skge->flow_status = FLOW_STAT_REM_SEND;
  1060. break;
  1061. case PHY_B_AS_PRT:
  1062. skge->flow_status = FLOW_STAT_LOC_SEND;
  1063. break;
  1064. default:
  1065. skge->flow_status = FLOW_STAT_NONE;
  1066. }
  1067. skge->speed = SPEED_1000;
  1068. }
  1069. if (!netif_carrier_ok(dev))
  1070. genesis_link_up(skge);
  1071. }
  1072. /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
  1073. * Phy on for 100 or 10Mbit operation
  1074. */
  1075. static void bcom_phy_init(struct skge_port *skge)
  1076. {
  1077. struct skge_hw *hw = skge->hw;
  1078. int port = skge->port;
  1079. int i;
  1080. u16 id1, r, ext, ctl;
  1081. /* magic workaround patterns for Broadcom */
  1082. static const struct {
  1083. u16 reg;
  1084. u16 val;
  1085. } A1hack[] = {
  1086. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
  1087. { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
  1088. { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
  1089. { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
  1090. }, C0hack[] = {
  1091. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
  1092. { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
  1093. };
  1094. /* read Id from external PHY (all have the same address) */
  1095. id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
  1096. /* Optimize MDIO transfer by suppressing preamble. */
  1097. r = xm_read16(hw, port, XM_MMU_CMD);
  1098. r |= XM_MMU_NO_PRE;
  1099. xm_write16(hw, port, XM_MMU_CMD,r);
  1100. switch (id1) {
  1101. case PHY_BCOM_ID1_C0:
  1102. /*
  1103. * Workaround BCOM Errata for the C0 type.
  1104. * Write magic patterns to reserved registers.
  1105. */
  1106. for (i = 0; i < ARRAY_SIZE(C0hack); i++)
  1107. xm_phy_write(hw, port,
  1108. C0hack[i].reg, C0hack[i].val);
  1109. break;
  1110. case PHY_BCOM_ID1_A1:
  1111. /*
  1112. * Workaround BCOM Errata for the A1 type.
  1113. * Write magic patterns to reserved registers.
  1114. */
  1115. for (i = 0; i < ARRAY_SIZE(A1hack); i++)
  1116. xm_phy_write(hw, port,
  1117. A1hack[i].reg, A1hack[i].val);
  1118. break;
  1119. }
  1120. /*
  1121. * Workaround BCOM Errata (#10523) for all BCom PHYs.
  1122. * Disable Power Management after reset.
  1123. */
  1124. r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
  1125. r |= PHY_B_AC_DIS_PM;
  1126. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
  1127. /* Dummy read */
  1128. xm_read16(hw, port, XM_ISRC);
  1129. ext = PHY_B_PEC_EN_LTR; /* enable tx led */
  1130. ctl = PHY_CT_SP1000; /* always 1000mbit */
  1131. if (skge->autoneg == AUTONEG_ENABLE) {
  1132. /*
  1133. * Workaround BCOM Errata #1 for the C5 type.
  1134. * 1000Base-T Link Acquisition Failure in Slave Mode
  1135. * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
  1136. */
  1137. u16 adv = PHY_B_1000C_RD;
  1138. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1139. adv |= PHY_B_1000C_AHD;
  1140. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1141. adv |= PHY_B_1000C_AFD;
  1142. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
  1143. ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1144. } else {
  1145. if (skge->duplex == DUPLEX_FULL)
  1146. ctl |= PHY_CT_DUP_MD;
  1147. /* Force to slave */
  1148. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
  1149. }
  1150. /* Set autonegotiation pause parameters */
  1151. xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
  1152. phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
  1153. /* Handle Jumbo frames */
  1154. if (hw->dev[port]->mtu > ETH_DATA_LEN) {
  1155. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  1156. PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
  1157. ext |= PHY_B_PEC_HIGH_LA;
  1158. }
  1159. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
  1160. xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
  1161. /* Use link status change interrupt */
  1162. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  1163. }
  1164. static void xm_phy_init(struct skge_port *skge)
  1165. {
  1166. struct skge_hw *hw = skge->hw;
  1167. int port = skge->port;
  1168. u16 ctrl = 0;
  1169. if (skge->autoneg == AUTONEG_ENABLE) {
  1170. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1171. ctrl |= PHY_X_AN_HD;
  1172. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1173. ctrl |= PHY_X_AN_FD;
  1174. ctrl |= fiber_pause_map[skge->flow_control];
  1175. xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
  1176. /* Restart Auto-negotiation */
  1177. ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
  1178. } else {
  1179. /* Set DuplexMode in Config register */
  1180. if (skge->duplex == DUPLEX_FULL)
  1181. ctrl |= PHY_CT_DUP_MD;
  1182. /*
  1183. * Do NOT enable Auto-negotiation here. This would hold
  1184. * the link down because no IDLEs are transmitted
  1185. */
  1186. }
  1187. xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
  1188. /* Poll PHY for status changes */
  1189. mod_timer(&skge->link_timer, jiffies + LINK_HZ);
  1190. }
  1191. static int xm_check_link(struct net_device *dev)
  1192. {
  1193. struct skge_port *skge = netdev_priv(dev);
  1194. struct skge_hw *hw = skge->hw;
  1195. int port = skge->port;
  1196. u16 status;
  1197. /* read twice because of latch */
  1198. xm_phy_read(hw, port, PHY_XMAC_STAT);
  1199. status = xm_phy_read(hw, port, PHY_XMAC_STAT);
  1200. if ((status & PHY_ST_LSYNC) == 0) {
  1201. xm_link_down(hw, port);
  1202. return 0;
  1203. }
  1204. if (skge->autoneg == AUTONEG_ENABLE) {
  1205. u16 lpa, res;
  1206. if (!(status & PHY_ST_AN_OVER))
  1207. return 0;
  1208. lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
  1209. if (lpa & PHY_B_AN_RF) {
  1210. printk(KERN_NOTICE PFX "%s: remote fault\n",
  1211. dev->name);
  1212. return 0;
  1213. }
  1214. res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
  1215. /* Check Duplex mismatch */
  1216. switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
  1217. case PHY_X_RS_FD:
  1218. skge->duplex = DUPLEX_FULL;
  1219. break;
  1220. case PHY_X_RS_HD:
  1221. skge->duplex = DUPLEX_HALF;
  1222. break;
  1223. default:
  1224. printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
  1225. dev->name);
  1226. return 0;
  1227. }
  1228. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1229. if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
  1230. skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
  1231. (lpa & PHY_X_P_SYM_MD))
  1232. skge->flow_status = FLOW_STAT_SYMMETRIC;
  1233. else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
  1234. (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
  1235. /* Enable PAUSE receive, disable PAUSE transmit */
  1236. skge->flow_status = FLOW_STAT_REM_SEND;
  1237. else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
  1238. (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
  1239. /* Disable PAUSE receive, enable PAUSE transmit */
  1240. skge->flow_status = FLOW_STAT_LOC_SEND;
  1241. else
  1242. skge->flow_status = FLOW_STAT_NONE;
  1243. skge->speed = SPEED_1000;
  1244. }
  1245. if (!netif_carrier_ok(dev))
  1246. genesis_link_up(skge);
  1247. return 1;
  1248. }
  1249. /* Poll to check for link coming up.
  1250. *
  1251. * Since internal PHY is wired to a level triggered pin, can't
  1252. * get an interrupt when carrier is detected, need to poll for
  1253. * link coming up.
  1254. */
  1255. static void xm_link_timer(unsigned long arg)
  1256. {
  1257. struct skge_port *skge = (struct skge_port *) arg;
  1258. struct net_device *dev = skge->netdev;
  1259. struct skge_hw *hw = skge->hw;
  1260. int port = skge->port;
  1261. int i;
  1262. unsigned long flags;
  1263. if (!netif_running(dev))
  1264. return;
  1265. spin_lock_irqsave(&hw->phy_lock, flags);
  1266. /*
  1267. * Verify that the link by checking GPIO register three times.
  1268. * This pin has the signal from the link_sync pin connected to it.
  1269. */
  1270. for (i = 0; i < 3; i++) {
  1271. if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
  1272. goto link_down;
  1273. }
  1274. /* Re-enable interrupt to detect link down */
  1275. if (xm_check_link(dev)) {
  1276. u16 msk = xm_read16(hw, port, XM_IMSK);
  1277. msk &= ~XM_IS_INP_ASS;
  1278. xm_write16(hw, port, XM_IMSK, msk);
  1279. xm_read16(hw, port, XM_ISRC);
  1280. } else {
  1281. link_down:
  1282. mod_timer(&skge->link_timer,
  1283. round_jiffies(jiffies + LINK_HZ));
  1284. }
  1285. spin_unlock_irqrestore(&hw->phy_lock, flags);
  1286. }
  1287. static void genesis_mac_init(struct skge_hw *hw, int port)
  1288. {
  1289. struct net_device *dev = hw->dev[port];
  1290. struct skge_port *skge = netdev_priv(dev);
  1291. int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
  1292. int i;
  1293. u32 r;
  1294. const u8 zero[6] = { 0 };
  1295. for (i = 0; i < 10; i++) {
  1296. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
  1297. MFF_SET_MAC_RST);
  1298. if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
  1299. goto reset_ok;
  1300. udelay(1);
  1301. }
  1302. printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
  1303. reset_ok:
  1304. /* Unreset the XMAC. */
  1305. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  1306. /*
  1307. * Perform additional initialization for external PHYs,
  1308. * namely for the 1000baseTX cards that use the XMAC's
  1309. * GMII mode.
  1310. */
  1311. if (hw->phy_type != SK_PHY_XMAC) {
  1312. /* Take external Phy out of reset */
  1313. r = skge_read32(hw, B2_GP_IO);
  1314. if (port == 0)
  1315. r |= GP_DIR_0|GP_IO_0;
  1316. else
  1317. r |= GP_DIR_2|GP_IO_2;
  1318. skge_write32(hw, B2_GP_IO, r);
  1319. /* Enable GMII interface */
  1320. xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
  1321. }
  1322. switch(hw->phy_type) {
  1323. case SK_PHY_XMAC:
  1324. xm_phy_init(skge);
  1325. break;
  1326. case SK_PHY_BCOM:
  1327. bcom_phy_init(skge);
  1328. bcom_check_link(hw, port);
  1329. }
  1330. /* Set Station Address */
  1331. xm_outaddr(hw, port, XM_SA, dev->dev_addr);
  1332. /* We don't use match addresses so clear */
  1333. for (i = 1; i < 16; i++)
  1334. xm_outaddr(hw, port, XM_EXM(i), zero);
  1335. /* Clear MIB counters */
  1336. xm_write16(hw, port, XM_STAT_CMD,
  1337. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  1338. /* Clear two times according to Errata #3 */
  1339. xm_write16(hw, port, XM_STAT_CMD,
  1340. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  1341. /* configure Rx High Water Mark (XM_RX_HI_WM) */
  1342. xm_write16(hw, port, XM_RX_HI_WM, 1450);
  1343. /* We don't need the FCS appended to the packet. */
  1344. r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
  1345. if (jumbo)
  1346. r |= XM_RX_BIG_PK_OK;
  1347. if (skge->duplex == DUPLEX_HALF) {
  1348. /*
  1349. * If in manual half duplex mode the other side might be in
  1350. * full duplex mode, so ignore if a carrier extension is not seen
  1351. * on frames received
  1352. */
  1353. r |= XM_RX_DIS_CEXT;
  1354. }
  1355. xm_write16(hw, port, XM_RX_CMD, r);
  1356. /* We want short frames padded to 60 bytes. */
  1357. xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
  1358. /* Increase threshold for jumbo frames on dual port */
  1359. if (hw->ports > 1 && jumbo)
  1360. xm_write16(hw, port, XM_TX_THR, 1020);
  1361. else
  1362. xm_write16(hw, port, XM_TX_THR, 512);
  1363. /*
  1364. * Enable the reception of all error frames. This is is
  1365. * a necessary evil due to the design of the XMAC. The
  1366. * XMAC's receive FIFO is only 8K in size, however jumbo
  1367. * frames can be up to 9000 bytes in length. When bad
  1368. * frame filtering is enabled, the XMAC's RX FIFO operates
  1369. * in 'store and forward' mode. For this to work, the
  1370. * entire frame has to fit into the FIFO, but that means
  1371. * that jumbo frames larger than 8192 bytes will be
  1372. * truncated. Disabling all bad frame filtering causes
  1373. * the RX FIFO to operate in streaming mode, in which
  1374. * case the XMAC will start transferring frames out of the
  1375. * RX FIFO as soon as the FIFO threshold is reached.
  1376. */
  1377. xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
  1378. /*
  1379. * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
  1380. * - Enable all bits excepting 'Octets Rx OK Low CntOv'
  1381. * and 'Octets Rx OK Hi Cnt Ov'.
  1382. */
  1383. xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
  1384. /*
  1385. * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
  1386. * - Enable all bits excepting 'Octets Tx OK Low CntOv'
  1387. * and 'Octets Tx OK Hi Cnt Ov'.
  1388. */
  1389. xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
  1390. /* Configure MAC arbiter */
  1391. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  1392. /* configure timeout values */
  1393. skge_write8(hw, B3_MA_TOINI_RX1, 72);
  1394. skge_write8(hw, B3_MA_TOINI_RX2, 72);
  1395. skge_write8(hw, B3_MA_TOINI_TX1, 72);
  1396. skge_write8(hw, B3_MA_TOINI_TX2, 72);
  1397. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  1398. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  1399. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  1400. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  1401. /* Configure Rx MAC FIFO */
  1402. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
  1403. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
  1404. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
  1405. /* Configure Tx MAC FIFO */
  1406. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
  1407. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
  1408. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
  1409. if (jumbo) {
  1410. /* Enable frame flushing if jumbo frames used */
  1411. skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
  1412. } else {
  1413. /* enable timeout timers if normal frames */
  1414. skge_write16(hw, B3_PA_CTRL,
  1415. (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
  1416. }
  1417. }
  1418. static void genesis_stop(struct skge_port *skge)
  1419. {
  1420. struct skge_hw *hw = skge->hw;
  1421. int port = skge->port;
  1422. unsigned retries = 1000;
  1423. u16 cmd;
  1424. /* Disable Tx and Rx */
  1425. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1426. cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  1427. xm_write16(hw, port, XM_MMU_CMD, cmd);
  1428. genesis_reset(hw, port);
  1429. /* Clear Tx packet arbiter timeout IRQ */
  1430. skge_write16(hw, B3_PA_CTRL,
  1431. port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
  1432. /* Reset the MAC */
  1433. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  1434. do {
  1435. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
  1436. if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
  1437. break;
  1438. } while (--retries > 0);
  1439. /* For external PHYs there must be special handling */
  1440. if (hw->phy_type != SK_PHY_XMAC) {
  1441. u32 reg = skge_read32(hw, B2_GP_IO);
  1442. if (port == 0) {
  1443. reg |= GP_DIR_0;
  1444. reg &= ~GP_IO_0;
  1445. } else {
  1446. reg |= GP_DIR_2;
  1447. reg &= ~GP_IO_2;
  1448. }
  1449. skge_write32(hw, B2_GP_IO, reg);
  1450. skge_read32(hw, B2_GP_IO);
  1451. }
  1452. xm_write16(hw, port, XM_MMU_CMD,
  1453. xm_read16(hw, port, XM_MMU_CMD)
  1454. & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
  1455. xm_read16(hw, port, XM_MMU_CMD);
  1456. }
  1457. static void genesis_get_stats(struct skge_port *skge, u64 *data)
  1458. {
  1459. struct skge_hw *hw = skge->hw;
  1460. int port = skge->port;
  1461. int i;
  1462. unsigned long timeout = jiffies + HZ;
  1463. xm_write16(hw, port,
  1464. XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
  1465. /* wait for update to complete */
  1466. while (xm_read16(hw, port, XM_STAT_CMD)
  1467. & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
  1468. if (time_after(jiffies, timeout))
  1469. break;
  1470. udelay(10);
  1471. }
  1472. /* special case for 64 bit octet counter */
  1473. data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
  1474. | xm_read32(hw, port, XM_TXO_OK_LO);
  1475. data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
  1476. | xm_read32(hw, port, XM_RXO_OK_LO);
  1477. for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
  1478. data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
  1479. }
  1480. static void genesis_mac_intr(struct skge_hw *hw, int port)
  1481. {
  1482. struct net_device *dev = hw->dev[port];
  1483. struct skge_port *skge = netdev_priv(dev);
  1484. u16 status = xm_read16(hw, port, XM_ISRC);
  1485. if (netif_msg_intr(skge))
  1486. printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
  1487. dev->name, status);
  1488. if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
  1489. xm_link_down(hw, port);
  1490. mod_timer(&skge->link_timer, jiffies + 1);
  1491. }
  1492. if (status & XM_IS_TXF_UR) {
  1493. xm_write32(hw, port, XM_MODE, XM_MD_FTF);
  1494. ++dev->stats.tx_fifo_errors;
  1495. }
  1496. }
  1497. static void genesis_link_up(struct skge_port *skge)
  1498. {
  1499. struct skge_hw *hw = skge->hw;
  1500. int port = skge->port;
  1501. u16 cmd, msk;
  1502. u32 mode;
  1503. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1504. /*
  1505. * enabling pause frame reception is required for 1000BT
  1506. * because the XMAC is not reset if the link is going down
  1507. */
  1508. if (skge->flow_status == FLOW_STAT_NONE ||
  1509. skge->flow_status == FLOW_STAT_LOC_SEND)
  1510. /* Disable Pause Frame Reception */
  1511. cmd |= XM_MMU_IGN_PF;
  1512. else
  1513. /* Enable Pause Frame Reception */
  1514. cmd &= ~XM_MMU_IGN_PF;
  1515. xm_write16(hw, port, XM_MMU_CMD, cmd);
  1516. mode = xm_read32(hw, port, XM_MODE);
  1517. if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
  1518. skge->flow_status == FLOW_STAT_LOC_SEND) {
  1519. /*
  1520. * Configure Pause Frame Generation
  1521. * Use internal and external Pause Frame Generation.
  1522. * Sending pause frames is edge triggered.
  1523. * Send a Pause frame with the maximum pause time if
  1524. * internal oder external FIFO full condition occurs.
  1525. * Send a zero pause time frame to re-start transmission.
  1526. */
  1527. /* XM_PAUSE_DA = '010000C28001' (default) */
  1528. /* XM_MAC_PTIME = 0xffff (maximum) */
  1529. /* remember this value is defined in big endian (!) */
  1530. xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
  1531. mode |= XM_PAUSE_MODE;
  1532. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
  1533. } else {
  1534. /*
  1535. * disable pause frame generation is required for 1000BT
  1536. * because the XMAC is not reset if the link is going down
  1537. */
  1538. /* Disable Pause Mode in Mode Register */
  1539. mode &= ~XM_PAUSE_MODE;
  1540. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
  1541. }
  1542. xm_write32(hw, port, XM_MODE, mode);
  1543. /* Turn on detection of Tx underrun */
  1544. msk = xm_read16(hw, port, XM_IMSK);
  1545. msk &= ~XM_IS_TXF_UR;
  1546. xm_write16(hw, port, XM_IMSK, msk);
  1547. xm_read16(hw, port, XM_ISRC);
  1548. /* get MMU Command Reg. */
  1549. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1550. if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
  1551. cmd |= XM_MMU_GMII_FD;
  1552. /*
  1553. * Workaround BCOM Errata (#10523) for all BCom Phys
  1554. * Enable Power Management after link up
  1555. */
  1556. if (hw->phy_type == SK_PHY_BCOM) {
  1557. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  1558. xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
  1559. & ~PHY_B_AC_DIS_PM);
  1560. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  1561. }
  1562. /* enable Rx/Tx */
  1563. xm_write16(hw, port, XM_MMU_CMD,
  1564. cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  1565. skge_link_up(skge);
  1566. }
  1567. static inline void bcom_phy_intr(struct skge_port *skge)
  1568. {
  1569. struct skge_hw *hw = skge->hw;
  1570. int port = skge->port;
  1571. u16 isrc;
  1572. isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
  1573. if (netif_msg_intr(skge))
  1574. printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
  1575. skge->netdev->name, isrc);
  1576. if (isrc & PHY_B_IS_PSE)
  1577. printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
  1578. hw->dev[port]->name);
  1579. /* Workaround BCom Errata:
  1580. * enable and disable loopback mode if "NO HCD" occurs.
  1581. */
  1582. if (isrc & PHY_B_IS_NO_HDCL) {
  1583. u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
  1584. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  1585. ctrl | PHY_CT_LOOP);
  1586. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  1587. ctrl & ~PHY_CT_LOOP);
  1588. }
  1589. if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
  1590. bcom_check_link(hw, port);
  1591. }
  1592. static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  1593. {
  1594. int i;
  1595. gma_write16(hw, port, GM_SMI_DATA, val);
  1596. gma_write16(hw, port, GM_SMI_CTRL,
  1597. GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
  1598. for (i = 0; i < PHY_RETRIES; i++) {
  1599. udelay(1);
  1600. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  1601. return 0;
  1602. }
  1603. printk(KERN_WARNING PFX "%s: phy write timeout\n",
  1604. hw->dev[port]->name);
  1605. return -EIO;
  1606. }
  1607. static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
  1608. {
  1609. int i;
  1610. gma_write16(hw, port, GM_SMI_CTRL,
  1611. GM_SMI_CT_PHY_AD(hw->phy_addr)
  1612. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  1613. for (i = 0; i < PHY_RETRIES; i++) {
  1614. udelay(1);
  1615. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
  1616. goto ready;
  1617. }
  1618. return -ETIMEDOUT;
  1619. ready:
  1620. *val = gma_read16(hw, port, GM_SMI_DATA);
  1621. return 0;
  1622. }
  1623. static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
  1624. {
  1625. u16 v = 0;
  1626. if (__gm_phy_read(hw, port, reg, &v))
  1627. printk(KERN_WARNING PFX "%s: phy read timeout\n",
  1628. hw->dev[port]->name);
  1629. return v;
  1630. }
  1631. /* Marvell Phy Initialization */
  1632. static void yukon_init(struct skge_hw *hw, int port)
  1633. {
  1634. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1635. u16 ctrl, ct1000, adv;
  1636. if (skge->autoneg == AUTONEG_ENABLE) {
  1637. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  1638. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  1639. PHY_M_EC_MAC_S_MSK);
  1640. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  1641. ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
  1642. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  1643. }
  1644. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1645. if (skge->autoneg == AUTONEG_DISABLE)
  1646. ctrl &= ~PHY_CT_ANE;
  1647. ctrl |= PHY_CT_RESET;
  1648. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1649. ctrl = 0;
  1650. ct1000 = 0;
  1651. adv = PHY_AN_CSMA;
  1652. if (skge->autoneg == AUTONEG_ENABLE) {
  1653. if (hw->copper) {
  1654. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1655. ct1000 |= PHY_M_1000C_AFD;
  1656. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1657. ct1000 |= PHY_M_1000C_AHD;
  1658. if (skge->advertising & ADVERTISED_100baseT_Full)
  1659. adv |= PHY_M_AN_100_FD;
  1660. if (skge->advertising & ADVERTISED_100baseT_Half)
  1661. adv |= PHY_M_AN_100_HD;
  1662. if (skge->advertising & ADVERTISED_10baseT_Full)
  1663. adv |= PHY_M_AN_10_FD;
  1664. if (skge->advertising & ADVERTISED_10baseT_Half)
  1665. adv |= PHY_M_AN_10_HD;
  1666. /* Set Flow-control capabilities */
  1667. adv |= phy_pause_map[skge->flow_control];
  1668. } else {
  1669. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1670. adv |= PHY_M_AN_1000X_AFD;
  1671. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1672. adv |= PHY_M_AN_1000X_AHD;
  1673. adv |= fiber_pause_map[skge->flow_control];
  1674. }
  1675. /* Restart Auto-negotiation */
  1676. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1677. } else {
  1678. /* forced speed/duplex settings */
  1679. ct1000 = PHY_M_1000C_MSE;
  1680. if (skge->duplex == DUPLEX_FULL)
  1681. ctrl |= PHY_CT_DUP_MD;
  1682. switch (skge->speed) {
  1683. case SPEED_1000:
  1684. ctrl |= PHY_CT_SP1000;
  1685. break;
  1686. case SPEED_100:
  1687. ctrl |= PHY_CT_SP100;
  1688. break;
  1689. }
  1690. ctrl |= PHY_CT_RESET;
  1691. }
  1692. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  1693. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  1694. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1695. /* Enable phy interrupt on autonegotiation complete (or link up) */
  1696. if (skge->autoneg == AUTONEG_ENABLE)
  1697. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
  1698. else
  1699. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1700. }
  1701. static void yukon_reset(struct skge_hw *hw, int port)
  1702. {
  1703. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
  1704. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  1705. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  1706. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  1707. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  1708. gma_write16(hw, port, GM_RX_CTRL,
  1709. gma_read16(hw, port, GM_RX_CTRL)
  1710. | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  1711. }
  1712. /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
  1713. static int is_yukon_lite_a0(struct skge_hw *hw)
  1714. {
  1715. u32 reg;
  1716. int ret;
  1717. if (hw->chip_id != CHIP_ID_YUKON)
  1718. return 0;
  1719. reg = skge_read32(hw, B2_FAR);
  1720. skge_write8(hw, B2_FAR + 3, 0xff);
  1721. ret = (skge_read8(hw, B2_FAR + 3) != 0);
  1722. skge_write32(hw, B2_FAR, reg);
  1723. return ret;
  1724. }
  1725. static void yukon_mac_init(struct skge_hw *hw, int port)
  1726. {
  1727. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1728. int i;
  1729. u32 reg;
  1730. const u8 *addr = hw->dev[port]->dev_addr;
  1731. /* WA code for COMA mode -- set PHY reset */
  1732. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1733. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1734. reg = skge_read32(hw, B2_GP_IO);
  1735. reg |= GP_DIR_9 | GP_IO_9;
  1736. skge_write32(hw, B2_GP_IO, reg);
  1737. }
  1738. /* hard reset */
  1739. skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1740. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1741. /* WA code for COMA mode -- clear PHY reset */
  1742. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1743. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1744. reg = skge_read32(hw, B2_GP_IO);
  1745. reg |= GP_DIR_9;
  1746. reg &= ~GP_IO_9;
  1747. skge_write32(hw, B2_GP_IO, reg);
  1748. }
  1749. /* Set hardware config mode */
  1750. reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
  1751. GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
  1752. reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
  1753. /* Clear GMC reset */
  1754. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
  1755. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
  1756. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
  1757. if (skge->autoneg == AUTONEG_DISABLE) {
  1758. reg = GM_GPCR_AU_ALL_DIS;
  1759. gma_write16(hw, port, GM_GP_CTRL,
  1760. gma_read16(hw, port, GM_GP_CTRL) | reg);
  1761. switch (skge->speed) {
  1762. case SPEED_1000:
  1763. reg &= ~GM_GPCR_SPEED_100;
  1764. reg |= GM_GPCR_SPEED_1000;
  1765. break;
  1766. case SPEED_100:
  1767. reg &= ~GM_GPCR_SPEED_1000;
  1768. reg |= GM_GPCR_SPEED_100;
  1769. break;
  1770. case SPEED_10:
  1771. reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
  1772. break;
  1773. }
  1774. if (skge->duplex == DUPLEX_FULL)
  1775. reg |= GM_GPCR_DUP_FULL;
  1776. } else
  1777. reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
  1778. switch (skge->flow_control) {
  1779. case FLOW_MODE_NONE:
  1780. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1781. reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1782. break;
  1783. case FLOW_MODE_LOC_SEND:
  1784. /* disable Rx flow-control */
  1785. reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1786. break;
  1787. case FLOW_MODE_SYMMETRIC:
  1788. case FLOW_MODE_SYM_OR_REM:
  1789. /* enable Tx & Rx flow-control */
  1790. break;
  1791. }
  1792. gma_write16(hw, port, GM_GP_CTRL, reg);
  1793. skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  1794. yukon_init(hw, port);
  1795. /* MIB clear */
  1796. reg = gma_read16(hw, port, GM_PHY_ADDR);
  1797. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  1798. for (i = 0; i < GM_MIB_CNT_SIZE; i++)
  1799. gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
  1800. gma_write16(hw, port, GM_PHY_ADDR, reg);
  1801. /* transmit control */
  1802. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  1803. /* receive control reg: unicast + multicast + no FCS */
  1804. gma_write16(hw, port, GM_RX_CTRL,
  1805. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  1806. /* transmit flow control */
  1807. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  1808. /* transmit parameter */
  1809. gma_write16(hw, port, GM_TX_PARAM,
  1810. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  1811. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  1812. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
  1813. /* configure the Serial Mode Register */
  1814. reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
  1815. | GM_SMOD_VLAN_ENA
  1816. | IPG_DATA_VAL(IPG_DATA_DEF);
  1817. if (hw->dev[port]->mtu > ETH_DATA_LEN)
  1818. reg |= GM_SMOD_JUMBO_ENA;
  1819. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  1820. /* physical address: used for pause frames */
  1821. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  1822. /* virtual address for data */
  1823. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  1824. /* enable interrupt mask for counter overflows */
  1825. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  1826. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  1827. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  1828. /* Initialize Mac Fifo */
  1829. /* Configure Rx MAC FIFO */
  1830. skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
  1831. reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
  1832. /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
  1833. if (is_yukon_lite_a0(hw))
  1834. reg &= ~GMF_RX_F_FL_ON;
  1835. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  1836. skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
  1837. /*
  1838. * because Pause Packet Truncation in GMAC is not working
  1839. * we have to increase the Flush Threshold to 64 bytes
  1840. * in order to flush pause packets in Rx FIFO on Yukon-1
  1841. */
  1842. skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
  1843. /* Configure Tx MAC FIFO */
  1844. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  1845. skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  1846. }
  1847. /* Go into power down mode */
  1848. static void yukon_suspend(struct skge_hw *hw, int port)
  1849. {
  1850. u16 ctrl;
  1851. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  1852. ctrl |= PHY_M_PC_POL_R_DIS;
  1853. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  1854. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1855. ctrl |= PHY_CT_RESET;
  1856. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1857. /* switch IEEE compatible power down mode on */
  1858. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1859. ctrl |= PHY_CT_PDOWN;
  1860. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1861. }
  1862. static void yukon_stop(struct skge_port *skge)
  1863. {
  1864. struct skge_hw *hw = skge->hw;
  1865. int port = skge->port;
  1866. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  1867. yukon_reset(hw, port);
  1868. gma_write16(hw, port, GM_GP_CTRL,
  1869. gma_read16(hw, port, GM_GP_CTRL)
  1870. & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
  1871. gma_read16(hw, port, GM_GP_CTRL);
  1872. yukon_suspend(hw, port);
  1873. /* set GPHY Control reset */
  1874. skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1875. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1876. }
  1877. static void yukon_get_stats(struct skge_port *skge, u64 *data)
  1878. {
  1879. struct skge_hw *hw = skge->hw;
  1880. int port = skge->port;
  1881. int i;
  1882. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  1883. | gma_read32(hw, port, GM_TXO_OK_LO);
  1884. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  1885. | gma_read32(hw, port, GM_RXO_OK_LO);
  1886. for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
  1887. data[i] = gma_read32(hw, port,
  1888. skge_stats[i].gma_offset);
  1889. }
  1890. static void yukon_mac_intr(struct skge_hw *hw, int port)
  1891. {
  1892. struct net_device *dev = hw->dev[port];
  1893. struct skge_port *skge = netdev_priv(dev);
  1894. u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1895. if (netif_msg_intr(skge))
  1896. printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
  1897. dev->name, status);
  1898. if (status & GM_IS_RX_FF_OR) {
  1899. ++dev->stats.rx_fifo_errors;
  1900. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1901. }
  1902. if (status & GM_IS_TX_FF_UR) {
  1903. ++dev->stats.tx_fifo_errors;
  1904. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1905. }
  1906. }
  1907. static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
  1908. {
  1909. switch (aux & PHY_M_PS_SPEED_MSK) {
  1910. case PHY_M_PS_SPEED_1000:
  1911. return SPEED_1000;
  1912. case PHY_M_PS_SPEED_100:
  1913. return SPEED_100;
  1914. default:
  1915. return SPEED_10;
  1916. }
  1917. }
  1918. static void yukon_link_up(struct skge_port *skge)
  1919. {
  1920. struct skge_hw *hw = skge->hw;
  1921. int port = skge->port;
  1922. u16 reg;
  1923. /* Enable Transmit FIFO Underrun */
  1924. skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  1925. reg = gma_read16(hw, port, GM_GP_CTRL);
  1926. if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
  1927. reg |= GM_GPCR_DUP_FULL;
  1928. /* enable Rx/Tx */
  1929. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1930. gma_write16(hw, port, GM_GP_CTRL, reg);
  1931. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1932. skge_link_up(skge);
  1933. }
  1934. static void yukon_link_down(struct skge_port *skge)
  1935. {
  1936. struct skge_hw *hw = skge->hw;
  1937. int port = skge->port;
  1938. u16 ctrl;
  1939. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1940. ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1941. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1942. if (skge->flow_status == FLOW_STAT_REM_SEND) {
  1943. ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1944. ctrl |= PHY_M_AN_ASP;
  1945. /* restore Asymmetric Pause bit */
  1946. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
  1947. }
  1948. skge_link_down(skge);
  1949. yukon_init(hw, port);
  1950. }
  1951. static void yukon_phy_intr(struct skge_port *skge)
  1952. {
  1953. struct skge_hw *hw = skge->hw;
  1954. int port = skge->port;
  1955. const char *reason = NULL;
  1956. u16 istatus, phystat;
  1957. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1958. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1959. if (netif_msg_intr(skge))
  1960. printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1961. skge->netdev->name, istatus, phystat);
  1962. if (istatus & PHY_M_IS_AN_COMPL) {
  1963. if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
  1964. & PHY_M_AN_RF) {
  1965. reason = "remote fault";
  1966. goto failed;
  1967. }
  1968. if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
  1969. reason = "master/slave fault";
  1970. goto failed;
  1971. }
  1972. if (!(phystat & PHY_M_PS_SPDUP_RES)) {
  1973. reason = "speed/duplex";
  1974. goto failed;
  1975. }
  1976. skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
  1977. ? DUPLEX_FULL : DUPLEX_HALF;
  1978. skge->speed = yukon_speed(hw, phystat);
  1979. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1980. switch (phystat & PHY_M_PS_PAUSE_MSK) {
  1981. case PHY_M_PS_PAUSE_MSK:
  1982. skge->flow_status = FLOW_STAT_SYMMETRIC;
  1983. break;
  1984. case PHY_M_PS_RX_P_EN:
  1985. skge->flow_status = FLOW_STAT_REM_SEND;
  1986. break;
  1987. case PHY_M_PS_TX_P_EN:
  1988. skge->flow_status = FLOW_STAT_LOC_SEND;
  1989. break;
  1990. default:
  1991. skge->flow_status = FLOW_STAT_NONE;
  1992. }
  1993. if (skge->flow_status == FLOW_STAT_NONE ||
  1994. (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
  1995. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1996. else
  1997. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1998. yukon_link_up(skge);
  1999. return;
  2000. }
  2001. if (istatus & PHY_M_IS_LSP_CHANGE)
  2002. skge->speed = yukon_speed(hw, phystat);
  2003. if (istatus & PHY_M_IS_DUP_CHANGE)
  2004. skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  2005. if (istatus & PHY_M_IS_LST_CHANGE) {
  2006. if (phystat & PHY_M_PS_LINK_UP)
  2007. yukon_link_up(skge);
  2008. else
  2009. yukon_link_down(skge);
  2010. }
  2011. return;
  2012. failed:
  2013. printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
  2014. skge->netdev->name, reason);
  2015. /* XXX restart autonegotiation? */
  2016. }
  2017. static void skge_phy_reset(struct skge_port *skge)
  2018. {
  2019. struct skge_hw *hw = skge->hw;
  2020. int port = skge->port;
  2021. struct net_device *dev = hw->dev[port];
  2022. netif_stop_queue(skge->netdev);
  2023. netif_carrier_off(skge->netdev);
  2024. spin_lock_bh(&hw->phy_lock);
  2025. if (hw->chip_id == CHIP_ID_GENESIS) {
  2026. genesis_reset(hw, port);
  2027. genesis_mac_init(hw, port);
  2028. } else {
  2029. yukon_reset(hw, port);
  2030. yukon_init(hw, port);
  2031. }
  2032. spin_unlock_bh(&hw->phy_lock);
  2033. dev->set_multicast_list(dev);
  2034. }
  2035. /* Basic MII support */
  2036. static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2037. {
  2038. struct mii_ioctl_data *data = if_mii(ifr);
  2039. struct skge_port *skge = netdev_priv(dev);
  2040. struct skge_hw *hw = skge->hw;
  2041. int err = -EOPNOTSUPP;
  2042. if (!netif_running(dev))
  2043. return -ENODEV; /* Phy still in reset */
  2044. switch(cmd) {
  2045. case SIOCGMIIPHY:
  2046. data->phy_id = hw->phy_addr;
  2047. /* fallthru */
  2048. case SIOCGMIIREG: {
  2049. u16 val = 0;
  2050. spin_lock_bh(&hw->phy_lock);
  2051. if (hw->chip_id == CHIP_ID_GENESIS)
  2052. err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
  2053. else
  2054. err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
  2055. spin_unlock_bh(&hw->phy_lock);
  2056. data->val_out = val;
  2057. break;
  2058. }
  2059. case SIOCSMIIREG:
  2060. if (!capable(CAP_NET_ADMIN))
  2061. return -EPERM;
  2062. spin_lock_bh(&hw->phy_lock);
  2063. if (hw->chip_id == CHIP_ID_GENESIS)
  2064. err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
  2065. data->val_in);
  2066. else
  2067. err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
  2068. data->val_in);
  2069. spin_unlock_bh(&hw->phy_lock);
  2070. break;
  2071. }
  2072. return err;
  2073. }
  2074. static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
  2075. {
  2076. u32 end;
  2077. start /= 8;
  2078. len /= 8;
  2079. end = start + len - 1;
  2080. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  2081. skge_write32(hw, RB_ADDR(q, RB_START), start);
  2082. skge_write32(hw, RB_ADDR(q, RB_WP), start);
  2083. skge_write32(hw, RB_ADDR(q, RB_RP), start);
  2084. skge_write32(hw, RB_ADDR(q, RB_END), end);
  2085. if (q == Q_R1 || q == Q_R2) {
  2086. /* Set thresholds on receive queue's */
  2087. skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
  2088. start + (2*len)/3);
  2089. skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
  2090. start + (len/3));
  2091. } else {
  2092. /* Enable store & forward on Tx queue's because
  2093. * Tx FIFO is only 4K on Genesis and 1K on Yukon
  2094. */
  2095. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  2096. }
  2097. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  2098. }
  2099. /* Setup Bus Memory Interface */
  2100. static void skge_qset(struct skge_port *skge, u16 q,
  2101. const struct skge_element *e)
  2102. {
  2103. struct skge_hw *hw = skge->hw;
  2104. u32 watermark = 0x600;
  2105. u64 base = skge->dma + (e->desc - skge->mem);
  2106. /* optimization to reduce window on 32bit/33mhz */
  2107. if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
  2108. watermark /= 2;
  2109. skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
  2110. skge_write32(hw, Q_ADDR(q, Q_F), watermark);
  2111. skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
  2112. skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
  2113. }
  2114. static int skge_up(struct net_device *dev)
  2115. {
  2116. struct skge_port *skge = netdev_priv(dev);
  2117. struct skge_hw *hw = skge->hw;
  2118. int port = skge->port;
  2119. u32 chunk, ram_addr;
  2120. size_t rx_size, tx_size;
  2121. int err;
  2122. if (!is_valid_ether_addr(dev->dev_addr))
  2123. return -EINVAL;
  2124. if (netif_msg_ifup(skge))
  2125. printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
  2126. if (dev->mtu > RX_BUF_SIZE)
  2127. skge->rx_buf_size = dev->mtu + ETH_HLEN;
  2128. else
  2129. skge->rx_buf_size = RX_BUF_SIZE;
  2130. rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
  2131. tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
  2132. skge->mem_size = tx_size + rx_size;
  2133. skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
  2134. if (!skge->mem)
  2135. return -ENOMEM;
  2136. BUG_ON(skge->dma & 7);
  2137. if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
  2138. dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
  2139. err = -EINVAL;
  2140. goto free_pci_mem;
  2141. }
  2142. memset(skge->mem, 0, skge->mem_size);
  2143. err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
  2144. if (err)
  2145. goto free_pci_mem;
  2146. err = skge_rx_fill(dev);
  2147. if (err)
  2148. goto free_rx_ring;
  2149. err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
  2150. skge->dma + rx_size);
  2151. if (err)
  2152. goto free_rx_ring;
  2153. /* Initialize MAC */
  2154. spin_lock_bh(&hw->phy_lock);
  2155. if (hw->chip_id == CHIP_ID_GENESIS)
  2156. genesis_mac_init(hw, port);
  2157. else
  2158. yukon_mac_init(hw, port);
  2159. spin_unlock_bh(&hw->phy_lock);
  2160. /* Configure RAMbuffers - equally between ports and tx/rx */
  2161. chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
  2162. ram_addr = hw->ram_offset + 2 * chunk * port;
  2163. skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
  2164. skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
  2165. BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
  2166. skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
  2167. skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
  2168. /* Start receiver BMU */
  2169. wmb();
  2170. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
  2171. skge_led(skge, LED_MODE_ON);
  2172. spin_lock_irq(&hw->hw_lock);
  2173. hw->intr_mask |= portmask[port];
  2174. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2175. spin_unlock_irq(&hw->hw_lock);
  2176. napi_enable(&skge->napi);
  2177. return 0;
  2178. free_rx_ring:
  2179. skge_rx_clean(skge);
  2180. kfree(skge->rx_ring.start);
  2181. free_pci_mem:
  2182. pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
  2183. skge->mem = NULL;
  2184. return err;
  2185. }
  2186. /* stop receiver */
  2187. static void skge_rx_stop(struct skge_hw *hw, int port)
  2188. {
  2189. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
  2190. skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
  2191. RB_RST_SET|RB_DIS_OP_MD);
  2192. skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
  2193. }
  2194. static int skge_down(struct net_device *dev)
  2195. {
  2196. struct skge_port *skge = netdev_priv(dev);
  2197. struct skge_hw *hw = skge->hw;
  2198. int port = skge->port;
  2199. if (skge->mem == NULL)
  2200. return 0;
  2201. if (netif_msg_ifdown(skge))
  2202. printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
  2203. netif_stop_queue(dev);
  2204. if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
  2205. del_timer_sync(&skge->link_timer);
  2206. napi_disable(&skge->napi);
  2207. netif_carrier_off(dev);
  2208. spin_lock_irq(&hw->hw_lock);
  2209. hw->intr_mask &= ~portmask[port];
  2210. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2211. spin_unlock_irq(&hw->hw_lock);
  2212. skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
  2213. if (hw->chip_id == CHIP_ID_GENESIS)
  2214. genesis_stop(skge);
  2215. else
  2216. yukon_stop(skge);
  2217. /* Stop transmitter */
  2218. skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
  2219. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  2220. RB_RST_SET|RB_DIS_OP_MD);
  2221. /* Disable Force Sync bit and Enable Alloc bit */
  2222. skge_write8(hw, SK_REG(port, TXA_CTRL),
  2223. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  2224. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  2225. skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  2226. skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  2227. /* Reset PCI FIFO */
  2228. skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
  2229. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  2230. /* Reset the RAM Buffer async Tx queue */
  2231. skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
  2232. skge_rx_stop(hw, port);
  2233. if (hw->chip_id == CHIP_ID_GENESIS) {
  2234. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
  2235. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
  2236. } else {
  2237. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  2238. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  2239. }
  2240. skge_led(skge, LED_MODE_OFF);
  2241. netif_tx_lock_bh(dev);
  2242. skge_tx_clean(dev);
  2243. netif_tx_unlock_bh(dev);
  2244. skge_rx_clean(skge);
  2245. kfree(skge->rx_ring.start);
  2246. kfree(skge->tx_ring.start);
  2247. pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
  2248. skge->mem = NULL;
  2249. return 0;
  2250. }
  2251. static inline int skge_avail(const struct skge_ring *ring)
  2252. {
  2253. smp_mb();
  2254. return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
  2255. + (ring->to_clean - ring->to_use) - 1;
  2256. }
  2257. static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
  2258. {
  2259. struct skge_port *skge = netdev_priv(dev);
  2260. struct skge_hw *hw = skge->hw;
  2261. struct skge_element *e;
  2262. struct skge_tx_desc *td;
  2263. int i;
  2264. u32 control, len;
  2265. u64 map;
  2266. if (skb_padto(skb, ETH_ZLEN))
  2267. return NETDEV_TX_OK;
  2268. if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
  2269. return NETDEV_TX_BUSY;
  2270. e = skge->tx_ring.to_use;
  2271. td = e->desc;
  2272. BUG_ON(td->control & BMU_OWN);
  2273. e->skb = skb;
  2274. len = skb_headlen(skb);
  2275. map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  2276. pci_unmap_addr_set(e, mapaddr, map);
  2277. pci_unmap_len_set(e, maplen, len);
  2278. td->dma_lo = map;
  2279. td->dma_hi = map >> 32;
  2280. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2281. const int offset = skb_transport_offset(skb);
  2282. /* This seems backwards, but it is what the sk98lin
  2283. * does. Looks like hardware is wrong?
  2284. */
  2285. if (ipip_hdr(skb)->protocol == IPPROTO_UDP
  2286. && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
  2287. control = BMU_TCP_CHECK;
  2288. else
  2289. control = BMU_UDP_CHECK;
  2290. td->csum_offs = 0;
  2291. td->csum_start = offset;
  2292. td->csum_write = offset + skb->csum_offset;
  2293. } else
  2294. control = BMU_CHECK;
  2295. if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
  2296. control |= BMU_EOF| BMU_IRQ_EOF;
  2297. else {
  2298. struct skge_tx_desc *tf = td;
  2299. control |= BMU_STFWD;
  2300. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2301. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2302. map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  2303. frag->size, PCI_DMA_TODEVICE);
  2304. e = e->next;
  2305. e->skb = skb;
  2306. tf = e->desc;
  2307. BUG_ON(tf->control & BMU_OWN);
  2308. tf->dma_lo = map;
  2309. tf->dma_hi = (u64) map >> 32;
  2310. pci_unmap_addr_set(e, mapaddr, map);
  2311. pci_unmap_len_set(e, maplen, frag->size);
  2312. tf->control = BMU_OWN | BMU_SW | control | frag->size;
  2313. }
  2314. tf->control |= BMU_EOF | BMU_IRQ_EOF;
  2315. }
  2316. /* Make sure all the descriptors written */
  2317. wmb();
  2318. td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
  2319. wmb();
  2320. skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
  2321. if (unlikely(netif_msg_tx_queued(skge)))
  2322. printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
  2323. dev->name, e - skge->tx_ring.start, skb->len);
  2324. skge->tx_ring.to_use = e->next;
  2325. smp_wmb();
  2326. if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
  2327. pr_debug("%s: transmit queue full\n", dev->name);
  2328. netif_stop_queue(dev);
  2329. }
  2330. dev->trans_start = jiffies;
  2331. return NETDEV_TX_OK;
  2332. }
  2333. /* Free resources associated with this reing element */
  2334. static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
  2335. u32 control)
  2336. {
  2337. struct pci_dev *pdev = skge->hw->pdev;
  2338. /* skb header vs. fragment */
  2339. if (control & BMU_STF)
  2340. pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
  2341. pci_unmap_len(e, maplen),
  2342. PCI_DMA_TODEVICE);
  2343. else
  2344. pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
  2345. pci_unmap_len(e, maplen),
  2346. PCI_DMA_TODEVICE);
  2347. if (control & BMU_EOF) {
  2348. if (unlikely(netif_msg_tx_done(skge)))
  2349. printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
  2350. skge->netdev->name, e - skge->tx_ring.start);
  2351. dev_kfree_skb(e->skb);
  2352. }
  2353. }
  2354. /* Free all buffers in transmit ring */
  2355. static void skge_tx_clean(struct net_device *dev)
  2356. {
  2357. struct skge_port *skge = netdev_priv(dev);
  2358. struct skge_element *e;
  2359. for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
  2360. struct skge_tx_desc *td = e->desc;
  2361. skge_tx_free(skge, e, td->control);
  2362. td->control = 0;
  2363. }
  2364. skge->tx_ring.to_clean = e;
  2365. netif_wake_queue(dev);
  2366. }
  2367. static void skge_tx_timeout(struct net_device *dev)
  2368. {
  2369. struct skge_port *skge = netdev_priv(dev);
  2370. if (netif_msg_timer(skge))
  2371. printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
  2372. skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
  2373. skge_tx_clean(dev);
  2374. }
  2375. static int skge_change_mtu(struct net_device *dev, int new_mtu)
  2376. {
  2377. int err;
  2378. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  2379. return -EINVAL;
  2380. if (!netif_running(dev)) {
  2381. dev->mtu = new_mtu;
  2382. return 0;
  2383. }
  2384. skge_down(dev);
  2385. dev->mtu = new_mtu;
  2386. err = skge_up(dev);
  2387. if (err)
  2388. dev_close(dev);
  2389. return err;
  2390. }
  2391. static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
  2392. static void genesis_add_filter(u8 filter[8], const u8 *addr)
  2393. {
  2394. u32 crc, bit;
  2395. crc = ether_crc_le(ETH_ALEN, addr);
  2396. bit = ~crc & 0x3f;
  2397. filter[bit/8] |= 1 << (bit%8);
  2398. }
  2399. static void genesis_set_multicast(struct net_device *dev)
  2400. {
  2401. struct skge_port *skge = netdev_priv(dev);
  2402. struct skge_hw *hw = skge->hw;
  2403. int port = skge->port;
  2404. int i, count = dev->mc_count;
  2405. struct dev_mc_list *list = dev->mc_list;
  2406. u32 mode;
  2407. u8 filter[8];
  2408. mode = xm_read32(hw, port, XM_MODE);
  2409. mode |= XM_MD_ENA_HASH;
  2410. if (dev->flags & IFF_PROMISC)
  2411. mode |= XM_MD_ENA_PROM;
  2412. else
  2413. mode &= ~XM_MD_ENA_PROM;
  2414. if (dev->flags & IFF_ALLMULTI)
  2415. memset(filter, 0xff, sizeof(filter));
  2416. else {
  2417. memset(filter, 0, sizeof(filter));
  2418. if (skge->flow_status == FLOW_STAT_REM_SEND
  2419. || skge->flow_status == FLOW_STAT_SYMMETRIC)
  2420. genesis_add_filter(filter, pause_mc_addr);
  2421. for (i = 0; list && i < count; i++, list = list->next)
  2422. genesis_add_filter(filter, list->dmi_addr);
  2423. }
  2424. xm_write32(hw, port, XM_MODE, mode);
  2425. xm_outhash(hw, port, XM_HSM, filter);
  2426. }
  2427. static void yukon_add_filter(u8 filter[8], const u8 *addr)
  2428. {
  2429. u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
  2430. filter[bit/8] |= 1 << (bit%8);
  2431. }
  2432. static void yukon_set_multicast(struct net_device *dev)
  2433. {
  2434. struct skge_port *skge = netdev_priv(dev);
  2435. struct skge_hw *hw = skge->hw;
  2436. int port = skge->port;
  2437. struct dev_mc_list *list = dev->mc_list;
  2438. int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
  2439. || skge->flow_status == FLOW_STAT_SYMMETRIC);
  2440. u16 reg;
  2441. u8 filter[8];
  2442. memset(filter, 0, sizeof(filter));
  2443. reg = gma_read16(hw, port, GM_RX_CTRL);
  2444. reg |= GM_RXCR_UCF_ENA;
  2445. if (dev->flags & IFF_PROMISC) /* promiscuous */
  2446. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  2447. else if (dev->flags & IFF_ALLMULTI) /* all multicast */
  2448. memset(filter, 0xff, sizeof(filter));
  2449. else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
  2450. reg &= ~GM_RXCR_MCF_ENA;
  2451. else {
  2452. int i;
  2453. reg |= GM_RXCR_MCF_ENA;
  2454. if (rx_pause)
  2455. yukon_add_filter(filter, pause_mc_addr);
  2456. for (i = 0; list && i < dev->mc_count; i++, list = list->next)
  2457. yukon_add_filter(filter, list->dmi_addr);
  2458. }
  2459. gma_write16(hw, port, GM_MC_ADDR_H1,
  2460. (u16)filter[0] | ((u16)filter[1] << 8));
  2461. gma_write16(hw, port, GM_MC_ADDR_H2,
  2462. (u16)filter[2] | ((u16)filter[3] << 8));
  2463. gma_write16(hw, port, GM_MC_ADDR_H3,
  2464. (u16)filter[4] | ((u16)filter[5] << 8));
  2465. gma_write16(hw, port, GM_MC_ADDR_H4,
  2466. (u16)filter[6] | ((u16)filter[7] << 8));
  2467. gma_write16(hw, port, GM_RX_CTRL, reg);
  2468. }
  2469. static inline u16 phy_length(const struct skge_hw *hw, u32 status)
  2470. {
  2471. if (hw->chip_id == CHIP_ID_GENESIS)
  2472. return status >> XMR_FS_LEN_SHIFT;
  2473. else
  2474. return status >> GMR_FS_LEN_SHIFT;
  2475. }
  2476. static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
  2477. {
  2478. if (hw->chip_id == CHIP_ID_GENESIS)
  2479. return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
  2480. else
  2481. return (status & GMR_FS_ANY_ERR) ||
  2482. (status & GMR_FS_RX_OK) == 0;
  2483. }
  2484. /* Get receive buffer from descriptor.
  2485. * Handles copy of small buffers and reallocation failures
  2486. */
  2487. static struct sk_buff *skge_rx_get(struct net_device *dev,
  2488. struct skge_element *e,
  2489. u32 control, u32 status, u16 csum)
  2490. {
  2491. struct skge_port *skge = netdev_priv(dev);
  2492. struct sk_buff *skb;
  2493. u16 len = control & BMU_BBC;
  2494. if (unlikely(netif_msg_rx_status(skge)))
  2495. printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
  2496. dev->name, e - skge->rx_ring.start,
  2497. status, len);
  2498. if (len > skge->rx_buf_size)
  2499. goto error;
  2500. if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
  2501. goto error;
  2502. if (bad_phy_status(skge->hw, status))
  2503. goto error;
  2504. if (phy_length(skge->hw, status) != len)
  2505. goto error;
  2506. if (len < RX_COPY_THRESHOLD) {
  2507. skb = netdev_alloc_skb(dev, len + 2);
  2508. if (!skb)
  2509. goto resubmit;
  2510. skb_reserve(skb, 2);
  2511. pci_dma_sync_single_for_cpu(skge->hw->pdev,
  2512. pci_unmap_addr(e, mapaddr),
  2513. len, PCI_DMA_FROMDEVICE);
  2514. skb_copy_from_linear_data(e->skb, skb->data, len);
  2515. pci_dma_sync_single_for_device(skge->hw->pdev,
  2516. pci_unmap_addr(e, mapaddr),
  2517. len, PCI_DMA_FROMDEVICE);
  2518. skge_rx_reuse(e, skge->rx_buf_size);
  2519. } else {
  2520. struct sk_buff *nskb;
  2521. nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
  2522. if (!nskb)
  2523. goto resubmit;
  2524. skb_reserve(nskb, NET_IP_ALIGN);
  2525. pci_unmap_single(skge->hw->pdev,
  2526. pci_unmap_addr(e, mapaddr),
  2527. pci_unmap_len(e, maplen),
  2528. PCI_DMA_FROMDEVICE);
  2529. skb = e->skb;
  2530. prefetch(skb->data);
  2531. skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
  2532. }
  2533. skb_put(skb, len);
  2534. if (skge->rx_csum) {
  2535. skb->csum = csum;
  2536. skb->ip_summed = CHECKSUM_COMPLETE;
  2537. }
  2538. skb->protocol = eth_type_trans(skb, dev);
  2539. return skb;
  2540. error:
  2541. if (netif_msg_rx_err(skge))
  2542. printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
  2543. dev->name, e - skge->rx_ring.start,
  2544. control, status);
  2545. if (skge->hw->chip_id == CHIP_ID_GENESIS) {
  2546. if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
  2547. dev->stats.rx_length_errors++;
  2548. if (status & XMR_FS_FRA_ERR)
  2549. dev->stats.rx_frame_errors++;
  2550. if (status & XMR_FS_FCS_ERR)
  2551. dev->stats.rx_crc_errors++;
  2552. } else {
  2553. if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
  2554. dev->stats.rx_length_errors++;
  2555. if (status & GMR_FS_FRAGMENT)
  2556. dev->stats.rx_frame_errors++;
  2557. if (status & GMR_FS_CRC_ERR)
  2558. dev->stats.rx_crc_errors++;
  2559. }
  2560. resubmit:
  2561. skge_rx_reuse(e, skge->rx_buf_size);
  2562. return NULL;
  2563. }
  2564. /* Free all buffers in Tx ring which are no longer owned by device */
  2565. static void skge_tx_done(struct net_device *dev)
  2566. {
  2567. struct skge_port *skge = netdev_priv(dev);
  2568. struct skge_ring *ring = &skge->tx_ring;
  2569. struct skge_element *e;
  2570. skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  2571. for (e = ring->to_clean; e != ring->to_use; e = e->next) {
  2572. u32 control = ((const struct skge_tx_desc *) e->desc)->control;
  2573. if (control & BMU_OWN)
  2574. break;
  2575. skge_tx_free(skge, e, control);
  2576. }
  2577. skge->tx_ring.to_clean = e;
  2578. /* Can run lockless until we need to synchronize to restart queue. */
  2579. smp_mb();
  2580. if (unlikely(netif_queue_stopped(dev) &&
  2581. skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
  2582. netif_tx_lock(dev);
  2583. if (unlikely(netif_queue_stopped(dev) &&
  2584. skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
  2585. netif_wake_queue(dev);
  2586. }
  2587. netif_tx_unlock(dev);
  2588. }
  2589. }
  2590. static int skge_poll(struct napi_struct *napi, int to_do)
  2591. {
  2592. struct skge_port *skge = container_of(napi, struct skge_port, napi);
  2593. struct net_device *dev = skge->netdev;
  2594. struct skge_hw *hw = skge->hw;
  2595. struct skge_ring *ring = &skge->rx_ring;
  2596. struct skge_element *e;
  2597. int work_done = 0;
  2598. skge_tx_done(dev);
  2599. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  2600. for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
  2601. struct skge_rx_desc *rd = e->desc;
  2602. struct sk_buff *skb;
  2603. u32 control;
  2604. rmb();
  2605. control = rd->control;
  2606. if (control & BMU_OWN)
  2607. break;
  2608. skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
  2609. if (likely(skb)) {
  2610. dev->last_rx = jiffies;
  2611. netif_receive_skb(skb);
  2612. ++work_done;
  2613. }
  2614. }
  2615. ring->to_clean = e;
  2616. /* restart receiver */
  2617. wmb();
  2618. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
  2619. if (work_done < to_do) {
  2620. unsigned long flags;
  2621. spin_lock_irqsave(&hw->hw_lock, flags);
  2622. __netif_rx_complete(dev, napi);
  2623. hw->intr_mask |= napimask[skge->port];
  2624. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2625. skge_read32(hw, B0_IMSK);
  2626. spin_unlock_irqrestore(&hw->hw_lock, flags);
  2627. }
  2628. return work_done;
  2629. }
  2630. /* Parity errors seem to happen when Genesis is connected to a switch
  2631. * with no other ports present. Heartbeat error??
  2632. */
  2633. static void skge_mac_parity(struct skge_hw *hw, int port)
  2634. {
  2635. struct net_device *dev = hw->dev[port];
  2636. ++dev->stats.tx_heartbeat_errors;
  2637. if (hw->chip_id == CHIP_ID_GENESIS)
  2638. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
  2639. MFF_CLR_PERR);
  2640. else
  2641. /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
  2642. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
  2643. (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
  2644. ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
  2645. }
  2646. static void skge_mac_intr(struct skge_hw *hw, int port)
  2647. {
  2648. if (hw->chip_id == CHIP_ID_GENESIS)
  2649. genesis_mac_intr(hw, port);
  2650. else
  2651. yukon_mac_intr(hw, port);
  2652. }
  2653. /* Handle device specific framing and timeout interrupts */
  2654. static void skge_error_irq(struct skge_hw *hw)
  2655. {
  2656. struct pci_dev *pdev = hw->pdev;
  2657. u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
  2658. if (hw->chip_id == CHIP_ID_GENESIS) {
  2659. /* clear xmac errors */
  2660. if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
  2661. skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
  2662. if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
  2663. skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
  2664. } else {
  2665. /* Timestamp (unused) overflow */
  2666. if (hwstatus & IS_IRQ_TIST_OV)
  2667. skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  2668. }
  2669. if (hwstatus & IS_RAM_RD_PAR) {
  2670. dev_err(&pdev->dev, "Ram read data parity error\n");
  2671. skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
  2672. }
  2673. if (hwstatus & IS_RAM_WR_PAR) {
  2674. dev_err(&pdev->dev, "Ram write data parity error\n");
  2675. skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
  2676. }
  2677. if (hwstatus & IS_M1_PAR_ERR)
  2678. skge_mac_parity(hw, 0);
  2679. if (hwstatus & IS_M2_PAR_ERR)
  2680. skge_mac_parity(hw, 1);
  2681. if (hwstatus & IS_R1_PAR_ERR) {
  2682. dev_err(&pdev->dev, "%s: receive queue parity error\n",
  2683. hw->dev[0]->name);
  2684. skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
  2685. }
  2686. if (hwstatus & IS_R2_PAR_ERR) {
  2687. dev_err(&pdev->dev, "%s: receive queue parity error\n",
  2688. hw->dev[1]->name);
  2689. skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
  2690. }
  2691. if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
  2692. u16 pci_status, pci_cmd;
  2693. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  2694. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  2695. dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
  2696. pci_cmd, pci_status);
  2697. /* Write the error bits back to clear them. */
  2698. pci_status &= PCI_STATUS_ERROR_BITS;
  2699. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2700. pci_write_config_word(pdev, PCI_COMMAND,
  2701. pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  2702. pci_write_config_word(pdev, PCI_STATUS, pci_status);
  2703. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2704. /* if error still set then just ignore it */
  2705. hwstatus = skge_read32(hw, B0_HWE_ISRC);
  2706. if (hwstatus & IS_IRQ_STAT) {
  2707. dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
  2708. hw->intr_mask &= ~IS_HW_ERR;
  2709. }
  2710. }
  2711. }
  2712. /*
  2713. * Interrupt from PHY are handled in tasklet (softirq)
  2714. * because accessing phy registers requires spin wait which might
  2715. * cause excess interrupt latency.
  2716. */
  2717. static void skge_extirq(unsigned long arg)
  2718. {
  2719. struct skge_hw *hw = (struct skge_hw *) arg;
  2720. int port;
  2721. for (port = 0; port < hw->ports; port++) {
  2722. struct net_device *dev = hw->dev[port];
  2723. if (netif_running(dev)) {
  2724. struct skge_port *skge = netdev_priv(dev);
  2725. spin_lock(&hw->phy_lock);
  2726. if (hw->chip_id != CHIP_ID_GENESIS)
  2727. yukon_phy_intr(skge);
  2728. else if (hw->phy_type == SK_PHY_BCOM)
  2729. bcom_phy_intr(skge);
  2730. spin_unlock(&hw->phy_lock);
  2731. }
  2732. }
  2733. spin_lock_irq(&hw->hw_lock);
  2734. hw->intr_mask |= IS_EXT_REG;
  2735. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2736. skge_read32(hw, B0_IMSK);
  2737. spin_unlock_irq(&hw->hw_lock);
  2738. }
  2739. static irqreturn_t skge_intr(int irq, void *dev_id)
  2740. {
  2741. struct skge_hw *hw = dev_id;
  2742. u32 status;
  2743. int handled = 0;
  2744. spin_lock(&hw->hw_lock);
  2745. /* Reading this register masks IRQ */
  2746. status = skge_read32(hw, B0_SP_ISRC);
  2747. if (status == 0 || status == ~0)
  2748. goto out;
  2749. handled = 1;
  2750. status &= hw->intr_mask;
  2751. if (status & IS_EXT_REG) {
  2752. hw->intr_mask &= ~IS_EXT_REG;
  2753. tasklet_schedule(&hw->phy_task);
  2754. }
  2755. if (status & (IS_XA1_F|IS_R1_F)) {
  2756. struct skge_port *skge = netdev_priv(hw->dev[0]);
  2757. hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
  2758. netif_rx_schedule(hw->dev[0], &skge->napi);
  2759. }
  2760. if (status & IS_PA_TO_TX1)
  2761. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
  2762. if (status & IS_PA_TO_RX1) {
  2763. ++hw->dev[0]->stats.rx_over_errors;
  2764. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
  2765. }
  2766. if (status & IS_MAC1)
  2767. skge_mac_intr(hw, 0);
  2768. if (hw->dev[1]) {
  2769. struct skge_port *skge = netdev_priv(hw->dev[1]);
  2770. if (status & (IS_XA2_F|IS_R2_F)) {
  2771. hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
  2772. netif_rx_schedule(hw->dev[1], &skge->napi);
  2773. }
  2774. if (status & IS_PA_TO_RX2) {
  2775. ++hw->dev[1]->stats.rx_over_errors;
  2776. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
  2777. }
  2778. if (status & IS_PA_TO_TX2)
  2779. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
  2780. if (status & IS_MAC2)
  2781. skge_mac_intr(hw, 1);
  2782. }
  2783. if (status & IS_HW_ERR)
  2784. skge_error_irq(hw);
  2785. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2786. skge_read32(hw, B0_IMSK);
  2787. out:
  2788. spin_unlock(&hw->hw_lock);
  2789. return IRQ_RETVAL(handled);
  2790. }
  2791. #ifdef CONFIG_NET_POLL_CONTROLLER
  2792. static void skge_netpoll(struct net_device *dev)
  2793. {
  2794. struct skge_port *skge = netdev_priv(dev);
  2795. disable_irq(dev->irq);
  2796. skge_intr(dev->irq, skge->hw);
  2797. enable_irq(dev->irq);
  2798. }
  2799. #endif
  2800. static int skge_set_mac_address(struct net_device *dev, void *p)
  2801. {
  2802. struct skge_port *skge = netdev_priv(dev);
  2803. struct skge_hw *hw = skge->hw;
  2804. unsigned port = skge->port;
  2805. const struct sockaddr *addr = p;
  2806. u16 ctrl;
  2807. if (!is_valid_ether_addr(addr->sa_data))
  2808. return -EADDRNOTAVAIL;
  2809. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2810. if (!netif_running(dev)) {
  2811. memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
  2812. memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
  2813. } else {
  2814. /* disable Rx */
  2815. spin_lock_bh(&hw->phy_lock);
  2816. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  2817. gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
  2818. memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
  2819. memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
  2820. if (hw->chip_id == CHIP_ID_GENESIS)
  2821. xm_outaddr(hw, port, XM_SA, dev->dev_addr);
  2822. else {
  2823. gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
  2824. gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
  2825. }
  2826. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  2827. spin_unlock_bh(&hw->phy_lock);
  2828. }
  2829. return 0;
  2830. }
  2831. static const struct {
  2832. u8 id;
  2833. const char *name;
  2834. } skge_chips[] = {
  2835. { CHIP_ID_GENESIS, "Genesis" },
  2836. { CHIP_ID_YUKON, "Yukon" },
  2837. { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
  2838. { CHIP_ID_YUKON_LP, "Yukon-LP"},
  2839. };
  2840. static const char *skge_board_name(const struct skge_hw *hw)
  2841. {
  2842. int i;
  2843. static char buf[16];
  2844. for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
  2845. if (skge_chips[i].id == hw->chip_id)
  2846. return skge_chips[i].name;
  2847. snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
  2848. return buf;
  2849. }
  2850. /*
  2851. * Setup the board data structure, but don't bring up
  2852. * the port(s)
  2853. */
  2854. static int skge_reset(struct skge_hw *hw)
  2855. {
  2856. u32 reg;
  2857. u16 ctst, pci_status;
  2858. u8 t8, mac_cfg, pmd_type;
  2859. int i;
  2860. ctst = skge_read16(hw, B0_CTST);
  2861. /* do a SW reset */
  2862. skge_write8(hw, B0_CTST, CS_RST_SET);
  2863. skge_write8(hw, B0_CTST, CS_RST_CLR);
  2864. /* clear PCI errors, if any */
  2865. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2866. skge_write8(hw, B2_TST_CTRL2, 0);
  2867. pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
  2868. pci_write_config_word(hw->pdev, PCI_STATUS,
  2869. pci_status | PCI_STATUS_ERROR_BITS);
  2870. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2871. skge_write8(hw, B0_CTST, CS_MRST_CLR);
  2872. /* restore CLK_RUN bits (for Yukon-Lite) */
  2873. skge_write16(hw, B0_CTST,
  2874. ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
  2875. hw->chip_id = skge_read8(hw, B2_CHIP_ID);
  2876. hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
  2877. pmd_type = skge_read8(hw, B2_PMD_TYP);
  2878. hw->copper = (pmd_type == 'T' || pmd_type == '1');
  2879. switch (hw->chip_id) {
  2880. case CHIP_ID_GENESIS:
  2881. switch (hw->phy_type) {
  2882. case SK_PHY_XMAC:
  2883. hw->phy_addr = PHY_ADDR_XMAC;
  2884. break;
  2885. case SK_PHY_BCOM:
  2886. hw->phy_addr = PHY_ADDR_BCOM;
  2887. break;
  2888. default:
  2889. dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
  2890. hw->phy_type);
  2891. return -EOPNOTSUPP;
  2892. }
  2893. break;
  2894. case CHIP_ID_YUKON:
  2895. case CHIP_ID_YUKON_LITE:
  2896. case CHIP_ID_YUKON_LP:
  2897. if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
  2898. hw->copper = 1;
  2899. hw->phy_addr = PHY_ADDR_MARV;
  2900. break;
  2901. default:
  2902. dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
  2903. hw->chip_id);
  2904. return -EOPNOTSUPP;
  2905. }
  2906. mac_cfg = skge_read8(hw, B2_MAC_CFG);
  2907. hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
  2908. hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
  2909. /* read the adapters RAM size */
  2910. t8 = skge_read8(hw, B2_E_0);
  2911. if (hw->chip_id == CHIP_ID_GENESIS) {
  2912. if (t8 == 3) {
  2913. /* special case: 4 x 64k x 36, offset = 0x80000 */
  2914. hw->ram_size = 0x100000;
  2915. hw->ram_offset = 0x80000;
  2916. } else
  2917. hw->ram_size = t8 * 512;
  2918. }
  2919. else if (t8 == 0)
  2920. hw->ram_size = 0x20000;
  2921. else
  2922. hw->ram_size = t8 * 4096;
  2923. hw->intr_mask = IS_HW_ERR;
  2924. /* Use PHY IRQ for all but fiber based Genesis board */
  2925. if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
  2926. hw->intr_mask |= IS_EXT_REG;
  2927. if (hw->chip_id == CHIP_ID_GENESIS)
  2928. genesis_init(hw);
  2929. else {
  2930. /* switch power to VCC (WA for VAUX problem) */
  2931. skge_write8(hw, B0_POWER_CTRL,
  2932. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  2933. /* avoid boards with stuck Hardware error bits */
  2934. if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
  2935. (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
  2936. dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
  2937. hw->intr_mask &= ~IS_HW_ERR;
  2938. }
  2939. /* Clear PHY COMA */
  2940. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2941. pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
  2942. reg &= ~PCI_PHY_COMA;
  2943. pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
  2944. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2945. for (i = 0; i < hw->ports; i++) {
  2946. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  2947. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  2948. }
  2949. }
  2950. /* turn off hardware timer (unused) */
  2951. skge_write8(hw, B2_TI_CTRL, TIM_STOP);
  2952. skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  2953. skge_write8(hw, B0_LED, LED_STAT_ON);
  2954. /* enable the Tx Arbiters */
  2955. for (i = 0; i < hw->ports; i++)
  2956. skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  2957. /* Initialize ram interface */
  2958. skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
  2959. skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
  2960. skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
  2961. skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
  2962. skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
  2963. skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
  2964. skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
  2965. skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
  2966. skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
  2967. skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
  2968. skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
  2969. skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
  2970. skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
  2971. skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
  2972. /* Set interrupt moderation for Transmit only
  2973. * Receive interrupts avoided by NAPI
  2974. */
  2975. skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
  2976. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
  2977. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  2978. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2979. for (i = 0; i < hw->ports; i++) {
  2980. if (hw->chip_id == CHIP_ID_GENESIS)
  2981. genesis_reset(hw, i);
  2982. else
  2983. yukon_reset(hw, i);
  2984. }
  2985. return 0;
  2986. }
  2987. #ifdef CONFIG_SKGE_DEBUG
  2988. static struct dentry *skge_debug;
  2989. static int skge_debug_show(struct seq_file *seq, void *v)
  2990. {
  2991. struct net_device *dev = seq->private;
  2992. const struct skge_port *skge = netdev_priv(dev);
  2993. const struct skge_hw *hw = skge->hw;
  2994. const struct skge_element *e;
  2995. if (!netif_running(dev))
  2996. return -ENETDOWN;
  2997. seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
  2998. skge_read32(hw, B0_IMSK));
  2999. seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
  3000. for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
  3001. const struct skge_tx_desc *t = e->desc;
  3002. seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
  3003. t->control, t->dma_hi, t->dma_lo, t->status,
  3004. t->csum_offs, t->csum_write, t->csum_start);
  3005. }
  3006. seq_printf(seq, "\nRx Ring: \n");
  3007. for (e = skge->rx_ring.to_clean; ; e = e->next) {
  3008. const struct skge_rx_desc *r = e->desc;
  3009. if (r->control & BMU_OWN)
  3010. break;
  3011. seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
  3012. r->control, r->dma_hi, r->dma_lo, r->status,
  3013. r->timestamp, r->csum1, r->csum1_start);
  3014. }
  3015. return 0;
  3016. }
  3017. static int skge_debug_open(struct inode *inode, struct file *file)
  3018. {
  3019. return single_open(file, skge_debug_show, inode->i_private);
  3020. }
  3021. static const struct file_operations skge_debug_fops = {
  3022. .owner = THIS_MODULE,
  3023. .open = skge_debug_open,
  3024. .read = seq_read,
  3025. .llseek = seq_lseek,
  3026. .release = single_release,
  3027. };
  3028. /*
  3029. * Use network device events to create/remove/rename
  3030. * debugfs file entries
  3031. */
  3032. static int skge_device_event(struct notifier_block *unused,
  3033. unsigned long event, void *ptr)
  3034. {
  3035. struct net_device *dev = ptr;
  3036. struct skge_port *skge;
  3037. struct dentry *d;
  3038. if (dev->open != &skge_up || !skge_debug)
  3039. goto done;
  3040. skge = netdev_priv(dev);
  3041. switch(event) {
  3042. case NETDEV_CHANGENAME:
  3043. if (skge->debugfs) {
  3044. d = debugfs_rename(skge_debug, skge->debugfs,
  3045. skge_debug, dev->name);
  3046. if (d)
  3047. skge->debugfs = d;
  3048. else {
  3049. pr_info(PFX "%s: rename failed\n", dev->name);
  3050. debugfs_remove(skge->debugfs);
  3051. }
  3052. }
  3053. break;
  3054. case NETDEV_GOING_DOWN:
  3055. if (skge->debugfs) {
  3056. debugfs_remove(skge->debugfs);
  3057. skge->debugfs = NULL;
  3058. }
  3059. break;
  3060. case NETDEV_UP:
  3061. d = debugfs_create_file(dev->name, S_IRUGO,
  3062. skge_debug, dev,
  3063. &skge_debug_fops);
  3064. if (!d || IS_ERR(d))
  3065. pr_info(PFX "%s: debugfs create failed\n",
  3066. dev->name);
  3067. else
  3068. skge->debugfs = d;
  3069. break;
  3070. }
  3071. done:
  3072. return NOTIFY_DONE;
  3073. }
  3074. static struct notifier_block skge_notifier = {
  3075. .notifier_call = skge_device_event,
  3076. };
  3077. static __init void skge_debug_init(void)
  3078. {
  3079. struct dentry *ent;
  3080. ent = debugfs_create_dir("skge", NULL);
  3081. if (!ent || IS_ERR(ent)) {
  3082. pr_info(PFX "debugfs create directory failed\n");
  3083. return;
  3084. }
  3085. skge_debug = ent;
  3086. register_netdevice_notifier(&skge_notifier);
  3087. }
  3088. static __exit void skge_debug_cleanup(void)
  3089. {
  3090. if (skge_debug) {
  3091. unregister_netdevice_notifier(&skge_notifier);
  3092. debugfs_remove(skge_debug);
  3093. skge_debug = NULL;
  3094. }
  3095. }
  3096. #else
  3097. #define skge_debug_init()
  3098. #define skge_debug_cleanup()
  3099. #endif
  3100. /* Initialize network device */
  3101. static struct net_device *skge_devinit(struct skge_hw *hw, int port,
  3102. int highmem)
  3103. {
  3104. struct skge_port *skge;
  3105. struct net_device *dev = alloc_etherdev(sizeof(*skge));
  3106. if (!dev) {
  3107. dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
  3108. return NULL;
  3109. }
  3110. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  3111. dev->open = skge_up;
  3112. dev->stop = skge_down;
  3113. dev->do_ioctl = skge_ioctl;
  3114. dev->hard_start_xmit = skge_xmit_frame;
  3115. dev->get_stats = skge_get_stats;
  3116. if (hw->chip_id == CHIP_ID_GENESIS)
  3117. dev->set_multicast_list = genesis_set_multicast;
  3118. else
  3119. dev->set_multicast_list = yukon_set_multicast;
  3120. dev->set_mac_address = skge_set_mac_address;
  3121. dev->change_mtu = skge_change_mtu;
  3122. SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
  3123. dev->tx_timeout = skge_tx_timeout;
  3124. dev->watchdog_timeo = TX_WATCHDOG;
  3125. #ifdef CONFIG_NET_POLL_CONTROLLER
  3126. dev->poll_controller = skge_netpoll;
  3127. #endif
  3128. dev->irq = hw->pdev->irq;
  3129. if (highmem)
  3130. dev->features |= NETIF_F_HIGHDMA;
  3131. skge = netdev_priv(dev);
  3132. netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
  3133. skge->netdev = dev;
  3134. skge->hw = hw;
  3135. skge->msg_enable = netif_msg_init(debug, default_msg);
  3136. skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
  3137. skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
  3138. /* Auto speed and flow control */
  3139. skge->autoneg = AUTONEG_ENABLE;
  3140. skge->flow_control = FLOW_MODE_SYM_OR_REM;
  3141. skge->duplex = -1;
  3142. skge->speed = -1;
  3143. skge->advertising = skge_supported_modes(hw);
  3144. if (pci_wake_enabled(hw->pdev))
  3145. skge->wol = wol_supported(hw) & WAKE_MAGIC;
  3146. hw->dev[port] = dev;
  3147. skge->port = port;
  3148. /* Only used for Genesis XMAC */
  3149. setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
  3150. if (hw->chip_id != CHIP_ID_GENESIS) {
  3151. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  3152. skge->rx_csum = 1;
  3153. }
  3154. /* read the mac address */
  3155. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
  3156. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  3157. /* device is off until link detection */
  3158. netif_carrier_off(dev);
  3159. netif_stop_queue(dev);
  3160. return dev;
  3161. }
  3162. static void __devinit skge_show_addr(struct net_device *dev)
  3163. {
  3164. const struct skge_port *skge = netdev_priv(dev);
  3165. DECLARE_MAC_BUF(mac);
  3166. if (netif_msg_probe(skge))
  3167. printk(KERN_INFO PFX "%s: addr %s\n",
  3168. dev->name, print_mac(mac, dev->dev_addr));
  3169. }
  3170. static int __devinit skge_probe(struct pci_dev *pdev,
  3171. const struct pci_device_id *ent)
  3172. {
  3173. struct net_device *dev, *dev1;
  3174. struct skge_hw *hw;
  3175. int err, using_dac = 0;
  3176. err = pci_enable_device(pdev);
  3177. if (err) {
  3178. dev_err(&pdev->dev, "cannot enable PCI device\n");
  3179. goto err_out;
  3180. }
  3181. err = pci_request_regions(pdev, DRV_NAME);
  3182. if (err) {
  3183. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  3184. goto err_out_disable_pdev;
  3185. }
  3186. pci_set_master(pdev);
  3187. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  3188. using_dac = 1;
  3189. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  3190. } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
  3191. using_dac = 0;
  3192. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  3193. }
  3194. if (err) {
  3195. dev_err(&pdev->dev, "no usable DMA configuration\n");
  3196. goto err_out_free_regions;
  3197. }
  3198. #ifdef __BIG_ENDIAN
  3199. /* byte swap descriptors in hardware */
  3200. {
  3201. u32 reg;
  3202. pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
  3203. reg |= PCI_REV_DESC;
  3204. pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
  3205. }
  3206. #endif
  3207. err = -ENOMEM;
  3208. hw = kzalloc(sizeof(*hw), GFP_KERNEL);
  3209. if (!hw) {
  3210. dev_err(&pdev->dev, "cannot allocate hardware struct\n");
  3211. goto err_out_free_regions;
  3212. }
  3213. hw->pdev = pdev;
  3214. spin_lock_init(&hw->hw_lock);
  3215. spin_lock_init(&hw->phy_lock);
  3216. tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
  3217. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  3218. if (!hw->regs) {
  3219. dev_err(&pdev->dev, "cannot map device registers\n");
  3220. goto err_out_free_hw;
  3221. }
  3222. err = skge_reset(hw);
  3223. if (err)
  3224. goto err_out_iounmap;
  3225. printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
  3226. (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
  3227. skge_board_name(hw), hw->chip_rev);
  3228. dev = skge_devinit(hw, 0, using_dac);
  3229. if (!dev)
  3230. goto err_out_led_off;
  3231. /* Some motherboards are broken and has zero in ROM. */
  3232. if (!is_valid_ether_addr(dev->dev_addr))
  3233. dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
  3234. err = register_netdev(dev);
  3235. if (err) {
  3236. dev_err(&pdev->dev, "cannot register net device\n");
  3237. goto err_out_free_netdev;
  3238. }
  3239. err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
  3240. if (err) {
  3241. dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
  3242. dev->name, pdev->irq);
  3243. goto err_out_unregister;
  3244. }
  3245. skge_show_addr(dev);
  3246. if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
  3247. if (register_netdev(dev1) == 0)
  3248. skge_show_addr(dev1);
  3249. else {
  3250. /* Failure to register second port need not be fatal */
  3251. dev_warn(&pdev->dev, "register of second port failed\n");
  3252. hw->dev[1] = NULL;
  3253. free_netdev(dev1);
  3254. }
  3255. }
  3256. pci_set_drvdata(pdev, hw);
  3257. return 0;
  3258. err_out_unregister:
  3259. unregister_netdev(dev);
  3260. err_out_free_netdev:
  3261. free_netdev(dev);
  3262. err_out_led_off:
  3263. skge_write16(hw, B0_LED, LED_STAT_OFF);
  3264. err_out_iounmap:
  3265. iounmap(hw->regs);
  3266. err_out_free_hw:
  3267. kfree(hw);
  3268. err_out_free_regions:
  3269. pci_release_regions(pdev);
  3270. err_out_disable_pdev:
  3271. pci_disable_device(pdev);
  3272. pci_set_drvdata(pdev, NULL);
  3273. err_out:
  3274. return err;
  3275. }
  3276. static void __devexit skge_remove(struct pci_dev *pdev)
  3277. {
  3278. struct skge_hw *hw = pci_get_drvdata(pdev);
  3279. struct net_device *dev0, *dev1;
  3280. if (!hw)
  3281. return;
  3282. flush_scheduled_work();
  3283. if ((dev1 = hw->dev[1]))
  3284. unregister_netdev(dev1);
  3285. dev0 = hw->dev[0];
  3286. unregister_netdev(dev0);
  3287. tasklet_disable(&hw->phy_task);
  3288. spin_lock_irq(&hw->hw_lock);
  3289. hw->intr_mask = 0;
  3290. skge_write32(hw, B0_IMSK, 0);
  3291. skge_read32(hw, B0_IMSK);
  3292. spin_unlock_irq(&hw->hw_lock);
  3293. skge_write16(hw, B0_LED, LED_STAT_OFF);
  3294. skge_write8(hw, B0_CTST, CS_RST_SET);
  3295. free_irq(pdev->irq, hw);
  3296. pci_release_regions(pdev);
  3297. pci_disable_device(pdev);
  3298. if (dev1)
  3299. free_netdev(dev1);
  3300. free_netdev(dev0);
  3301. iounmap(hw->regs);
  3302. kfree(hw);
  3303. pci_set_drvdata(pdev, NULL);
  3304. }
  3305. #ifdef CONFIG_PM
  3306. static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
  3307. {
  3308. struct skge_hw *hw = pci_get_drvdata(pdev);
  3309. int i, err, wol = 0;
  3310. if (!hw)
  3311. return 0;
  3312. err = pci_save_state(pdev);
  3313. if (err)
  3314. return err;
  3315. for (i = 0; i < hw->ports; i++) {
  3316. struct net_device *dev = hw->dev[i];
  3317. struct skge_port *skge = netdev_priv(dev);
  3318. if (netif_running(dev))
  3319. skge_down(dev);
  3320. if (skge->wol)
  3321. skge_wol_init(skge);
  3322. wol |= skge->wol;
  3323. }
  3324. skge_write32(hw, B0_IMSK, 0);
  3325. pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
  3326. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  3327. return 0;
  3328. }
  3329. static int skge_resume(struct pci_dev *pdev)
  3330. {
  3331. struct skge_hw *hw = pci_get_drvdata(pdev);
  3332. int i, err;
  3333. if (!hw)
  3334. return 0;
  3335. err = pci_set_power_state(pdev, PCI_D0);
  3336. if (err)
  3337. goto out;
  3338. err = pci_restore_state(pdev);
  3339. if (err)
  3340. goto out;
  3341. pci_enable_wake(pdev, PCI_D0, 0);
  3342. err = skge_reset(hw);
  3343. if (err)
  3344. goto out;
  3345. for (i = 0; i < hw->ports; i++) {
  3346. struct net_device *dev = hw->dev[i];
  3347. if (netif_running(dev)) {
  3348. err = skge_up(dev);
  3349. if (err) {
  3350. printk(KERN_ERR PFX "%s: could not up: %d\n",
  3351. dev->name, err);
  3352. dev_close(dev);
  3353. goto out;
  3354. }
  3355. }
  3356. }
  3357. out:
  3358. return err;
  3359. }
  3360. #endif
  3361. static void skge_shutdown(struct pci_dev *pdev)
  3362. {
  3363. struct skge_hw *hw = pci_get_drvdata(pdev);
  3364. int i, wol = 0;
  3365. if (!hw)
  3366. return;
  3367. for (i = 0; i < hw->ports; i++) {
  3368. struct net_device *dev = hw->dev[i];
  3369. struct skge_port *skge = netdev_priv(dev);
  3370. if (skge->wol)
  3371. skge_wol_init(skge);
  3372. wol |= skge->wol;
  3373. }
  3374. pci_enable_wake(pdev, PCI_D3hot, wol);
  3375. pci_enable_wake(pdev, PCI_D3cold, wol);
  3376. pci_disable_device(pdev);
  3377. pci_set_power_state(pdev, PCI_D3hot);
  3378. }
  3379. static struct pci_driver skge_driver = {
  3380. .name = DRV_NAME,
  3381. .id_table = skge_id_table,
  3382. .probe = skge_probe,
  3383. .remove = __devexit_p(skge_remove),
  3384. #ifdef CONFIG_PM
  3385. .suspend = skge_suspend,
  3386. .resume = skge_resume,
  3387. #endif
  3388. .shutdown = skge_shutdown,
  3389. };
  3390. static int __init skge_init_module(void)
  3391. {
  3392. skge_debug_init();
  3393. return pci_register_driver(&skge_driver);
  3394. }
  3395. static void __exit skge_cleanup_module(void)
  3396. {
  3397. pci_unregister_driver(&skge_driver);
  3398. skge_debug_cleanup();
  3399. }
  3400. module_init(skge_init_module);
  3401. module_exit(skge_cleanup_module);