spi.h 1.6 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005 Fen Systems Ltd.
  4. * Copyright 2006 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #ifndef EFX_SPI_H
  11. #define EFX_SPI_H
  12. #include "net_driver.h"
  13. /**************************************************************************
  14. *
  15. * Basic SPI command set and bit definitions
  16. *
  17. *************************************************************************/
  18. /*
  19. * Commands common to all known devices.
  20. *
  21. */
  22. /* Write status register */
  23. #define SPI_WRSR 0x01
  24. /* Write data to memory array */
  25. #define SPI_WRITE 0x02
  26. /* Read data from memory array */
  27. #define SPI_READ 0x03
  28. /* Reset write enable latch */
  29. #define SPI_WRDI 0x04
  30. /* Read status register */
  31. #define SPI_RDSR 0x05
  32. /* Set write enable latch */
  33. #define SPI_WREN 0x06
  34. /* SST: Enable write to status register */
  35. #define SPI_SST_EWSR 0x50
  36. /*
  37. * Status register bits. Not all bits are supported on all devices.
  38. *
  39. */
  40. /* Write-protect pin enabled */
  41. #define SPI_STATUS_WPEN 0x80
  42. /* Block protection bit 2 */
  43. #define SPI_STATUS_BP2 0x10
  44. /* Block protection bit 1 */
  45. #define SPI_STATUS_BP1 0x08
  46. /* Block protection bit 0 */
  47. #define SPI_STATUS_BP0 0x04
  48. /* State of the write enable latch */
  49. #define SPI_STATUS_WEN 0x02
  50. /* Device busy flag */
  51. #define SPI_STATUS_NRDY 0x01
  52. #endif /* EFX_SPI_H */