net_driver.h 28 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. /* Common definitions for all Efx net driver code */
  11. #ifndef EFX_NET_DRIVER_H
  12. #define EFX_NET_DRIVER_H
  13. #include <linux/version.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/if_vlan.h>
  18. #include <linux/timer.h>
  19. #include <linux/mii.h>
  20. #include <linux/list.h>
  21. #include <linux/pci.h>
  22. #include <linux/device.h>
  23. #include <linux/highmem.h>
  24. #include <linux/workqueue.h>
  25. #include <linux/inet_lro.h>
  26. #include "enum.h"
  27. #include "bitfield.h"
  28. #include "i2c-direct.h"
  29. #define EFX_MAX_LRO_DESCRIPTORS 8
  30. #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
  31. /**************************************************************************
  32. *
  33. * Build definitions
  34. *
  35. **************************************************************************/
  36. #ifndef EFX_DRIVER_NAME
  37. #define EFX_DRIVER_NAME "sfc"
  38. #endif
  39. #define EFX_DRIVER_VERSION "2.2.0136"
  40. #ifdef EFX_ENABLE_DEBUG
  41. #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  42. #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  43. #else
  44. #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  45. #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  46. #endif
  47. #define NET_DEV_REGISTERED(efx) \
  48. ((efx)->net_dev->reg_state == NETREG_REGISTERED)
  49. /* Include net device name in log messages if it has been registered.
  50. * Use efx->name not efx->net_dev->name so that races with (un)registration
  51. * are harmless.
  52. */
  53. #define NET_DEV_NAME(efx) (NET_DEV_REGISTERED(efx) ? (efx)->name : "")
  54. /* Un-rate-limited logging */
  55. #define EFX_ERR(efx, fmt, args...) \
  56. dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, NET_DEV_NAME(efx), ##args)
  57. #define EFX_INFO(efx, fmt, args...) \
  58. dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, NET_DEV_NAME(efx), ##args)
  59. #ifdef EFX_ENABLE_DEBUG
  60. #define EFX_LOG(efx, fmt, args...) \
  61. dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
  62. #else
  63. #define EFX_LOG(efx, fmt, args...) \
  64. dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, NET_DEV_NAME(efx), ##args)
  65. #endif
  66. #define EFX_TRACE(efx, fmt, args...) do {} while (0)
  67. #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
  68. /* Rate-limited logging */
  69. #define EFX_ERR_RL(efx, fmt, args...) \
  70. do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
  71. #define EFX_INFO_RL(efx, fmt, args...) \
  72. do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
  73. #define EFX_LOG_RL(efx, fmt, args...) \
  74. do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
  75. /* Kernel headers may redefine inline anyway */
  76. #ifndef inline
  77. #define inline inline __attribute__ ((always_inline))
  78. #endif
  79. /**************************************************************************
  80. *
  81. * Efx data structures
  82. *
  83. **************************************************************************/
  84. #define EFX_MAX_CHANNELS 32
  85. #define EFX_MAX_TX_QUEUES 1
  86. #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
  87. /**
  88. * struct efx_special_buffer - An Efx special buffer
  89. * @addr: CPU base address of the buffer
  90. * @dma_addr: DMA base address of the buffer
  91. * @len: Buffer length, in bytes
  92. * @index: Buffer index within controller;s buffer table
  93. * @entries: Number of buffer table entries
  94. *
  95. * Special buffers are used for the event queues and the TX and RX
  96. * descriptor queues for each channel. They are *not* used for the
  97. * actual transmit and receive buffers.
  98. *
  99. * Note that for Falcon, TX and RX descriptor queues live in host memory.
  100. * Allocation and freeing procedures must take this into account.
  101. */
  102. struct efx_special_buffer {
  103. void *addr;
  104. dma_addr_t dma_addr;
  105. unsigned int len;
  106. int index;
  107. int entries;
  108. };
  109. /**
  110. * struct efx_tx_buffer - An Efx TX buffer
  111. * @skb: The associated socket buffer.
  112. * Set only on the final fragment of a packet; %NULL for all other
  113. * fragments. When this fragment completes, then we can free this
  114. * skb.
  115. * @tsoh: The associated TSO header structure, or %NULL if this
  116. * buffer is not a TSO header.
  117. * @dma_addr: DMA address of the fragment.
  118. * @len: Length of this fragment.
  119. * This field is zero when the queue slot is empty.
  120. * @continuation: True if this fragment is not the end of a packet.
  121. * @unmap_single: True if pci_unmap_single should be used.
  122. * @unmap_addr: DMA address to unmap
  123. * @unmap_len: Length of this fragment to unmap
  124. */
  125. struct efx_tx_buffer {
  126. const struct sk_buff *skb;
  127. struct efx_tso_header *tsoh;
  128. dma_addr_t dma_addr;
  129. unsigned short len;
  130. unsigned char continuation;
  131. unsigned char unmap_single;
  132. dma_addr_t unmap_addr;
  133. unsigned short unmap_len;
  134. };
  135. /**
  136. * struct efx_tx_queue - An Efx TX queue
  137. *
  138. * This is a ring buffer of TX fragments.
  139. * Since the TX completion path always executes on the same
  140. * CPU and the xmit path can operate on different CPUs,
  141. * performance is increased by ensuring that the completion
  142. * path and the xmit path operate on different cache lines.
  143. * This is particularly important if the xmit path is always
  144. * executing on one CPU which is different from the completion
  145. * path. There is also a cache line for members which are
  146. * read but not written on the fast path.
  147. *
  148. * @efx: The associated Efx NIC
  149. * @queue: DMA queue number
  150. * @used: Queue is used by net driver
  151. * @channel: The associated channel
  152. * @buffer: The software buffer ring
  153. * @txd: The hardware descriptor ring
  154. * @read_count: Current read pointer.
  155. * This is the number of buffers that have been removed from both rings.
  156. * @stopped: Stopped flag.
  157. * Set if this TX queue is currently stopping its port.
  158. * @insert_count: Current insert pointer
  159. * This is the number of buffers that have been added to the
  160. * software ring.
  161. * @write_count: Current write pointer
  162. * This is the number of buffers that have been added to the
  163. * hardware ring.
  164. * @old_read_count: The value of read_count when last checked.
  165. * This is here for performance reasons. The xmit path will
  166. * only get the up-to-date value of read_count if this
  167. * variable indicates that the queue is full. This is to
  168. * avoid cache-line ping-pong between the xmit path and the
  169. * completion path.
  170. * @tso_headers_free: A list of TSO headers allocated for this TX queue
  171. * that are not in use, and so available for new TSO sends. The list
  172. * is protected by the TX queue lock.
  173. * @tso_bursts: Number of times TSO xmit invoked by kernel
  174. * @tso_long_headers: Number of packets with headers too long for standard
  175. * blocks
  176. * @tso_packets: Number of packets via the TSO xmit path
  177. */
  178. struct efx_tx_queue {
  179. /* Members which don't change on the fast path */
  180. struct efx_nic *efx ____cacheline_aligned_in_smp;
  181. int queue;
  182. int used;
  183. struct efx_channel *channel;
  184. struct efx_nic *nic;
  185. struct efx_tx_buffer *buffer;
  186. struct efx_special_buffer txd;
  187. /* Members used mainly on the completion path */
  188. unsigned int read_count ____cacheline_aligned_in_smp;
  189. int stopped;
  190. /* Members used only on the xmit path */
  191. unsigned int insert_count ____cacheline_aligned_in_smp;
  192. unsigned int write_count;
  193. unsigned int old_read_count;
  194. struct efx_tso_header *tso_headers_free;
  195. unsigned int tso_bursts;
  196. unsigned int tso_long_headers;
  197. unsigned int tso_packets;
  198. };
  199. /**
  200. * struct efx_rx_buffer - An Efx RX data buffer
  201. * @dma_addr: DMA base address of the buffer
  202. * @skb: The associated socket buffer, if any.
  203. * If both this and page are %NULL, the buffer slot is currently free.
  204. * @page: The associated page buffer, if any.
  205. * If both this and skb are %NULL, the buffer slot is currently free.
  206. * @data: Pointer to ethernet header
  207. * @len: Buffer length, in bytes.
  208. * @unmap_addr: DMA address to unmap
  209. */
  210. struct efx_rx_buffer {
  211. dma_addr_t dma_addr;
  212. struct sk_buff *skb;
  213. struct page *page;
  214. char *data;
  215. unsigned int len;
  216. dma_addr_t unmap_addr;
  217. };
  218. /**
  219. * struct efx_rx_queue - An Efx RX queue
  220. * @efx: The associated Efx NIC
  221. * @queue: DMA queue number
  222. * @used: Queue is used by net driver
  223. * @channel: The associated channel
  224. * @buffer: The software buffer ring
  225. * @rxd: The hardware descriptor ring
  226. * @added_count: Number of buffers added to the receive queue.
  227. * @notified_count: Number of buffers given to NIC (<= @added_count).
  228. * @removed_count: Number of buffers removed from the receive queue.
  229. * @add_lock: Receive queue descriptor add spin lock.
  230. * This lock must be held in order to add buffers to the RX
  231. * descriptor ring (rxd and buffer) and to update added_count (but
  232. * not removed_count).
  233. * @max_fill: RX descriptor maximum fill level (<= ring size)
  234. * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
  235. * (<= @max_fill)
  236. * @fast_fill_limit: The level to which a fast fill will fill
  237. * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
  238. * @min_fill: RX descriptor minimum non-zero fill level.
  239. * This records the minimum fill level observed when a ring
  240. * refill was triggered.
  241. * @min_overfill: RX descriptor minimum overflow fill level.
  242. * This records the minimum fill level at which RX queue
  243. * overflow was observed. It should never be set.
  244. * @alloc_page_count: RX allocation strategy counter.
  245. * @alloc_skb_count: RX allocation strategy counter.
  246. * @work: Descriptor push work thread
  247. * @buf_page: Page for next RX buffer.
  248. * We can use a single page for multiple RX buffers. This tracks
  249. * the remaining space in the allocation.
  250. * @buf_dma_addr: Page's DMA address.
  251. * @buf_data: Page's host address.
  252. */
  253. struct efx_rx_queue {
  254. struct efx_nic *efx;
  255. int queue;
  256. int used;
  257. struct efx_channel *channel;
  258. struct efx_rx_buffer *buffer;
  259. struct efx_special_buffer rxd;
  260. int added_count;
  261. int notified_count;
  262. int removed_count;
  263. spinlock_t add_lock;
  264. unsigned int max_fill;
  265. unsigned int fast_fill_trigger;
  266. unsigned int fast_fill_limit;
  267. unsigned int min_fill;
  268. unsigned int min_overfill;
  269. unsigned int alloc_page_count;
  270. unsigned int alloc_skb_count;
  271. struct delayed_work work;
  272. unsigned int slow_fill_count;
  273. struct page *buf_page;
  274. dma_addr_t buf_dma_addr;
  275. char *buf_data;
  276. };
  277. /**
  278. * struct efx_buffer - An Efx general-purpose buffer
  279. * @addr: host base address of the buffer
  280. * @dma_addr: DMA base address of the buffer
  281. * @len: Buffer length, in bytes
  282. *
  283. * Falcon uses these buffers for its interrupt status registers and
  284. * MAC stats dumps.
  285. */
  286. struct efx_buffer {
  287. void *addr;
  288. dma_addr_t dma_addr;
  289. unsigned int len;
  290. };
  291. /* Flags for channel->used_flags */
  292. #define EFX_USED_BY_RX 1
  293. #define EFX_USED_BY_TX 2
  294. #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
  295. enum efx_rx_alloc_method {
  296. RX_ALLOC_METHOD_AUTO = 0,
  297. RX_ALLOC_METHOD_SKB = 1,
  298. RX_ALLOC_METHOD_PAGE = 2,
  299. };
  300. /**
  301. * struct efx_channel - An Efx channel
  302. *
  303. * A channel comprises an event queue, at least one TX queue, at least
  304. * one RX queue, and an associated tasklet for processing the event
  305. * queue.
  306. *
  307. * @efx: Associated Efx NIC
  308. * @evqnum: Event queue number
  309. * @channel: Channel instance number
  310. * @used_flags: Channel is used by net driver
  311. * @enabled: Channel enabled indicator
  312. * @irq: IRQ number (MSI and MSI-X only)
  313. * @has_interrupt: Channel has an interrupt
  314. * @irq_moderation: IRQ moderation value (in us)
  315. * @napi_dev: Net device used with NAPI
  316. * @napi_str: NAPI control structure
  317. * @reset_work: Scheduled reset work thread
  318. * @work_pending: Is work pending via NAPI?
  319. * @eventq: Event queue buffer
  320. * @eventq_read_ptr: Event queue read pointer
  321. * @last_eventq_read_ptr: Last event queue read pointer value.
  322. * @eventq_magic: Event queue magic value for driver-generated test events
  323. * @lro_mgr: LRO state
  324. * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
  325. * and diagnostic counters
  326. * @rx_alloc_push_pages: RX allocation method currently in use for pushing
  327. * descriptors
  328. * @rx_alloc_pop_pages: RX allocation method currently in use for popping
  329. * descriptors
  330. * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
  331. * @n_rx_ip_frag_err: Count of RX IP fragment errors
  332. * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
  333. * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
  334. * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
  335. * @n_rx_overlength: Count of RX_OVERLENGTH errors
  336. * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
  337. */
  338. struct efx_channel {
  339. struct efx_nic *efx;
  340. int evqnum;
  341. int channel;
  342. int used_flags;
  343. int enabled;
  344. int irq;
  345. unsigned int has_interrupt;
  346. unsigned int irq_moderation;
  347. struct net_device *napi_dev;
  348. struct napi_struct napi_str;
  349. struct work_struct reset_work;
  350. int work_pending;
  351. struct efx_special_buffer eventq;
  352. unsigned int eventq_read_ptr;
  353. unsigned int last_eventq_read_ptr;
  354. unsigned int eventq_magic;
  355. struct net_lro_mgr lro_mgr;
  356. int rx_alloc_level;
  357. int rx_alloc_push_pages;
  358. int rx_alloc_pop_pages;
  359. unsigned n_rx_tobe_disc;
  360. unsigned n_rx_ip_frag_err;
  361. unsigned n_rx_ip_hdr_chksum_err;
  362. unsigned n_rx_tcp_udp_chksum_err;
  363. unsigned n_rx_frm_trunc;
  364. unsigned n_rx_overlength;
  365. unsigned n_skbuff_leaks;
  366. /* Used to pipeline received packets in order to optimise memory
  367. * access with prefetches.
  368. */
  369. struct efx_rx_buffer *rx_pkt;
  370. int rx_pkt_csummed;
  371. };
  372. /**
  373. * struct efx_blinker - S/W LED blinking context
  374. * @led_num: LED ID (board-specific meaning)
  375. * @state: Current state - on or off
  376. * @resubmit: Timer resubmission flag
  377. * @timer: Control timer for blinking
  378. */
  379. struct efx_blinker {
  380. int led_num;
  381. int state;
  382. int resubmit;
  383. struct timer_list timer;
  384. };
  385. /**
  386. * struct efx_board - board information
  387. * @type: Board model type
  388. * @major: Major rev. ('A', 'B' ...)
  389. * @minor: Minor rev. (0, 1, ...)
  390. * @init: Initialisation function
  391. * @init_leds: Sets up board LEDs
  392. * @set_fault_led: Turns the fault LED on or off
  393. * @blink: Starts/stops blinking
  394. * @blinker: used to blink LEDs in software
  395. */
  396. struct efx_board {
  397. int type;
  398. int major;
  399. int minor;
  400. int (*init) (struct efx_nic *nic);
  401. /* As the LEDs are typically attached to the PHY, LEDs
  402. * have a separate init callback that happens later than
  403. * board init. */
  404. int (*init_leds)(struct efx_nic *efx);
  405. void (*set_fault_led) (struct efx_nic *efx, int state);
  406. void (*blink) (struct efx_nic *efx, int start);
  407. struct efx_blinker blinker;
  408. };
  409. #define STRING_TABLE_LOOKUP(val, member) \
  410. member ## _names[val]
  411. enum efx_int_mode {
  412. /* Be careful if altering to correct macro below */
  413. EFX_INT_MODE_MSIX = 0,
  414. EFX_INT_MODE_MSI = 1,
  415. EFX_INT_MODE_LEGACY = 2,
  416. EFX_INT_MODE_MAX /* Insert any new items before this */
  417. };
  418. #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
  419. enum phy_type {
  420. PHY_TYPE_NONE = 0,
  421. PHY_TYPE_CX4_RTMR = 1,
  422. PHY_TYPE_1G_ALASKA = 2,
  423. PHY_TYPE_10XPRESS = 3,
  424. PHY_TYPE_XFP = 4,
  425. PHY_TYPE_PM8358 = 6,
  426. PHY_TYPE_MAX /* Insert any new items before this */
  427. };
  428. #define PHY_ADDR_INVALID 0xff
  429. enum nic_state {
  430. STATE_INIT = 0,
  431. STATE_RUNNING = 1,
  432. STATE_FINI = 2,
  433. STATE_RESETTING = 3, /* rtnl_lock always held */
  434. STATE_DISABLED = 4,
  435. STATE_MAX,
  436. };
  437. /*
  438. * Alignment of page-allocated RX buffers
  439. *
  440. * Controls the number of bytes inserted at the start of an RX buffer.
  441. * This is the equivalent of NET_IP_ALIGN [which controls the alignment
  442. * of the skb->head for hardware DMA].
  443. */
  444. #if defined(__i386__) || defined(__x86_64__)
  445. #define EFX_PAGE_IP_ALIGN 0
  446. #else
  447. #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
  448. #endif
  449. /*
  450. * Alignment of the skb->head which wraps a page-allocated RX buffer
  451. *
  452. * The skb allocated to wrap an rx_buffer can have this alignment. Since
  453. * the data is memcpy'd from the rx_buf, it does not need to be equal to
  454. * EFX_PAGE_IP_ALIGN.
  455. */
  456. #define EFX_PAGE_SKB_ALIGN 2
  457. /* Forward declaration */
  458. struct efx_nic;
  459. /* Pseudo bit-mask flow control field */
  460. enum efx_fc_type {
  461. EFX_FC_RX = 1,
  462. EFX_FC_TX = 2,
  463. EFX_FC_AUTO = 4,
  464. };
  465. /**
  466. * struct efx_phy_operations - Efx PHY operations table
  467. * @init: Initialise PHY
  468. * @fini: Shut down PHY
  469. * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
  470. * @clear_interrupt: Clear down interrupt
  471. * @blink: Blink LEDs
  472. * @check_hw: Check hardware
  473. * @reset_xaui: Reset XAUI side of PHY for (software sequenced reset)
  474. * @mmds: MMD presence mask
  475. * @loopbacks: Supported loopback modes mask
  476. */
  477. struct efx_phy_operations {
  478. int (*init) (struct efx_nic *efx);
  479. void (*fini) (struct efx_nic *efx);
  480. void (*reconfigure) (struct efx_nic *efx);
  481. void (*clear_interrupt) (struct efx_nic *efx);
  482. int (*check_hw) (struct efx_nic *efx);
  483. void (*reset_xaui) (struct efx_nic *efx);
  484. int mmds;
  485. unsigned loopbacks;
  486. };
  487. /*
  488. * Efx extended statistics
  489. *
  490. * Not all statistics are provided by all supported MACs. The purpose
  491. * is this structure is to contain the raw statistics provided by each
  492. * MAC.
  493. */
  494. struct efx_mac_stats {
  495. u64 tx_bytes;
  496. u64 tx_good_bytes;
  497. u64 tx_bad_bytes;
  498. unsigned long tx_packets;
  499. unsigned long tx_bad;
  500. unsigned long tx_pause;
  501. unsigned long tx_control;
  502. unsigned long tx_unicast;
  503. unsigned long tx_multicast;
  504. unsigned long tx_broadcast;
  505. unsigned long tx_lt64;
  506. unsigned long tx_64;
  507. unsigned long tx_65_to_127;
  508. unsigned long tx_128_to_255;
  509. unsigned long tx_256_to_511;
  510. unsigned long tx_512_to_1023;
  511. unsigned long tx_1024_to_15xx;
  512. unsigned long tx_15xx_to_jumbo;
  513. unsigned long tx_gtjumbo;
  514. unsigned long tx_collision;
  515. unsigned long tx_single_collision;
  516. unsigned long tx_multiple_collision;
  517. unsigned long tx_excessive_collision;
  518. unsigned long tx_deferred;
  519. unsigned long tx_late_collision;
  520. unsigned long tx_excessive_deferred;
  521. unsigned long tx_non_tcpudp;
  522. unsigned long tx_mac_src_error;
  523. unsigned long tx_ip_src_error;
  524. u64 rx_bytes;
  525. u64 rx_good_bytes;
  526. u64 rx_bad_bytes;
  527. unsigned long rx_packets;
  528. unsigned long rx_good;
  529. unsigned long rx_bad;
  530. unsigned long rx_pause;
  531. unsigned long rx_control;
  532. unsigned long rx_unicast;
  533. unsigned long rx_multicast;
  534. unsigned long rx_broadcast;
  535. unsigned long rx_lt64;
  536. unsigned long rx_64;
  537. unsigned long rx_65_to_127;
  538. unsigned long rx_128_to_255;
  539. unsigned long rx_256_to_511;
  540. unsigned long rx_512_to_1023;
  541. unsigned long rx_1024_to_15xx;
  542. unsigned long rx_15xx_to_jumbo;
  543. unsigned long rx_gtjumbo;
  544. unsigned long rx_bad_lt64;
  545. unsigned long rx_bad_64_to_15xx;
  546. unsigned long rx_bad_15xx_to_jumbo;
  547. unsigned long rx_bad_gtjumbo;
  548. unsigned long rx_overflow;
  549. unsigned long rx_missed;
  550. unsigned long rx_false_carrier;
  551. unsigned long rx_symbol_error;
  552. unsigned long rx_align_error;
  553. unsigned long rx_length_error;
  554. unsigned long rx_internal_error;
  555. unsigned long rx_good_lt64;
  556. };
  557. /* Number of bits used in a multicast filter hash address */
  558. #define EFX_MCAST_HASH_BITS 8
  559. /* Number of (single-bit) entries in a multicast filter hash */
  560. #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
  561. /* An Efx multicast filter hash */
  562. union efx_multicast_hash {
  563. u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
  564. efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
  565. };
  566. /**
  567. * struct efx_nic - an Efx NIC
  568. * @name: Device name (net device name or bus id before net device registered)
  569. * @pci_dev: The PCI device
  570. * @type: Controller type attributes
  571. * @legacy_irq: IRQ number
  572. * @workqueue: Workqueue for resets, port reconfigures and the HW monitor
  573. * @reset_work: Scheduled reset workitem
  574. * @monitor_work: Hardware monitor workitem
  575. * @membase_phys: Memory BAR value as physical address
  576. * @membase: Memory BAR value
  577. * @biu_lock: BIU (bus interface unit) lock
  578. * @interrupt_mode: Interrupt mode
  579. * @i2c: I2C interface
  580. * @board_info: Board-level information
  581. * @state: Device state flag. Serialised by the rtnl_lock.
  582. * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
  583. * @tx_queue: TX DMA queues
  584. * @rx_queue: RX DMA queues
  585. * @channel: Channels
  586. * @rss_queues: Number of RSS queues
  587. * @rx_buffer_len: RX buffer length
  588. * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
  589. * @irq_status: Interrupt status buffer
  590. * @last_irq_cpu: Last CPU to handle interrupt.
  591. * This register is written with the SMP processor ID whenever an
  592. * interrupt is handled. It is used by falcon_test_interrupt()
  593. * to verify that an interrupt has occurred.
  594. * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
  595. * @nic_data: Hardware dependant state
  596. * @mac_lock: MAC access lock. Protects @port_enabled, efx_monitor() and
  597. * efx_reconfigure_port()
  598. * @port_enabled: Port enabled indicator.
  599. * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
  600. * efx_reconfigure_work with kernel interfaces. Safe to read under any
  601. * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
  602. * be held to modify it.
  603. * @port_initialized: Port initialized?
  604. * @net_dev: Operating system network device. Consider holding the rtnl lock
  605. * @rx_checksum_enabled: RX checksumming enabled
  606. * @netif_stop_count: Port stop count
  607. * @netif_stop_lock: Port stop lock
  608. * @mac_stats: MAC statistics. These include all statistics the MACs
  609. * can provide. Generic code converts these into a standard
  610. * &struct net_device_stats.
  611. * @stats_buffer: DMA buffer for statistics
  612. * @stats_lock: Statistics update lock
  613. * @mac_address: Permanent MAC address
  614. * @phy_type: PHY type
  615. * @phy_lock: PHY access lock
  616. * @phy_op: PHY interface
  617. * @phy_data: PHY private data (including PHY-specific stats)
  618. * @mii: PHY interface
  619. * @tx_disabled: PHY transmitter turned off
  620. * @link_up: Link status
  621. * @link_options: Link options (MII/GMII format)
  622. * @n_link_state_changes: Number of times the link has changed state
  623. * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
  624. * @multicast_hash: Multicast hash table
  625. * @flow_control: Flow control flags - separate RX/TX so can't use link_options
  626. * @reconfigure_work: work item for dealing with PHY events
  627. * @loopback_mode: Loopback status
  628. * @loopback_modes: Supported loopback mode bitmask
  629. * @loopback_selftest: Offline self-test private state
  630. *
  631. * The @priv field of the corresponding &struct net_device points to
  632. * this.
  633. */
  634. struct efx_nic {
  635. char name[IFNAMSIZ];
  636. struct pci_dev *pci_dev;
  637. const struct efx_nic_type *type;
  638. int legacy_irq;
  639. struct workqueue_struct *workqueue;
  640. struct work_struct reset_work;
  641. struct delayed_work monitor_work;
  642. unsigned long membase_phys;
  643. void __iomem *membase;
  644. spinlock_t biu_lock;
  645. enum efx_int_mode interrupt_mode;
  646. struct efx_i2c_interface i2c;
  647. struct efx_board board_info;
  648. enum nic_state state;
  649. enum reset_type reset_pending;
  650. struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES];
  651. struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
  652. struct efx_channel channel[EFX_MAX_CHANNELS];
  653. int rss_queues;
  654. unsigned int rx_buffer_len;
  655. unsigned int rx_buffer_order;
  656. struct efx_buffer irq_status;
  657. volatile signed int last_irq_cpu;
  658. unsigned n_rx_nodesc_drop_cnt;
  659. void *nic_data;
  660. struct mutex mac_lock;
  661. int port_enabled;
  662. int port_initialized;
  663. struct net_device *net_dev;
  664. int rx_checksum_enabled;
  665. atomic_t netif_stop_count;
  666. spinlock_t netif_stop_lock;
  667. struct efx_mac_stats mac_stats;
  668. struct efx_buffer stats_buffer;
  669. spinlock_t stats_lock;
  670. unsigned char mac_address[ETH_ALEN];
  671. enum phy_type phy_type;
  672. spinlock_t phy_lock;
  673. struct efx_phy_operations *phy_op;
  674. void *phy_data;
  675. struct mii_if_info mii;
  676. unsigned tx_disabled;
  677. int link_up;
  678. unsigned int link_options;
  679. unsigned int n_link_state_changes;
  680. int promiscuous;
  681. union efx_multicast_hash multicast_hash;
  682. enum efx_fc_type flow_control;
  683. struct work_struct reconfigure_work;
  684. atomic_t rx_reset;
  685. enum efx_loopback_mode loopback_mode;
  686. unsigned int loopback_modes;
  687. void *loopback_selftest;
  688. };
  689. /**
  690. * struct efx_nic_type - Efx device type definition
  691. * @mem_bar: Memory BAR number
  692. * @mem_map_size: Memory BAR mapped size
  693. * @txd_ptr_tbl_base: TX descriptor ring base address
  694. * @rxd_ptr_tbl_base: RX descriptor ring base address
  695. * @buf_tbl_base: Buffer table base address
  696. * @evq_ptr_tbl_base: Event queue pointer table base address
  697. * @evq_rptr_tbl_base: Event queue read-pointer table base address
  698. * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
  699. * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
  700. * @evq_size: Event queue size (must be a power of two)
  701. * @max_dma_mask: Maximum possible DMA mask
  702. * @tx_dma_mask: TX DMA mask
  703. * @bug5391_mask: Address mask for bug 5391 workaround
  704. * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
  705. * @rx_xon_thresh: RX FIFO XON watermark (bytes)
  706. * @rx_buffer_padding: Padding added to each RX buffer
  707. * @max_interrupt_mode: Highest capability interrupt mode supported
  708. * from &enum efx_init_mode.
  709. * @phys_addr_channels: Number of channels with physically addressed
  710. * descriptors
  711. */
  712. struct efx_nic_type {
  713. unsigned int mem_bar;
  714. unsigned int mem_map_size;
  715. unsigned int txd_ptr_tbl_base;
  716. unsigned int rxd_ptr_tbl_base;
  717. unsigned int buf_tbl_base;
  718. unsigned int evq_ptr_tbl_base;
  719. unsigned int evq_rptr_tbl_base;
  720. unsigned int txd_ring_mask;
  721. unsigned int rxd_ring_mask;
  722. unsigned int evq_size;
  723. dma_addr_t max_dma_mask;
  724. unsigned int tx_dma_mask;
  725. unsigned bug5391_mask;
  726. int rx_xoff_thresh;
  727. int rx_xon_thresh;
  728. unsigned int rx_buffer_padding;
  729. unsigned int max_interrupt_mode;
  730. unsigned int phys_addr_channels;
  731. };
  732. /**************************************************************************
  733. *
  734. * Prototypes and inline functions
  735. *
  736. *************************************************************************/
  737. /* Iterate over all used channels */
  738. #define efx_for_each_channel(_channel, _efx) \
  739. for (_channel = &_efx->channel[0]; \
  740. _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
  741. _channel++) \
  742. if (!_channel->used_flags) \
  743. continue; \
  744. else
  745. /* Iterate over all used channels with interrupts */
  746. #define efx_for_each_channel_with_interrupt(_channel, _efx) \
  747. for (_channel = &_efx->channel[0]; \
  748. _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
  749. _channel++) \
  750. if (!(_channel->used_flags && _channel->has_interrupt)) \
  751. continue; \
  752. else
  753. /* Iterate over all used TX queues */
  754. #define efx_for_each_tx_queue(_tx_queue, _efx) \
  755. for (_tx_queue = &_efx->tx_queue[0]; \
  756. _tx_queue < &_efx->tx_queue[EFX_MAX_TX_QUEUES]; \
  757. _tx_queue++) \
  758. if (!_tx_queue->used) \
  759. continue; \
  760. else
  761. /* Iterate over all TX queues belonging to a channel */
  762. #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
  763. for (_tx_queue = &_channel->efx->tx_queue[0]; \
  764. _tx_queue < &_channel->efx->tx_queue[EFX_MAX_TX_QUEUES]; \
  765. _tx_queue++) \
  766. if ((!_tx_queue->used) || \
  767. (_tx_queue->channel != _channel)) \
  768. continue; \
  769. else
  770. /* Iterate over all used RX queues */
  771. #define efx_for_each_rx_queue(_rx_queue, _efx) \
  772. for (_rx_queue = &_efx->rx_queue[0]; \
  773. _rx_queue < &_efx->rx_queue[EFX_MAX_RX_QUEUES]; \
  774. _rx_queue++) \
  775. if (!_rx_queue->used) \
  776. continue; \
  777. else
  778. /* Iterate over all RX queues belonging to a channel */
  779. #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
  780. for (_rx_queue = &_channel->efx->rx_queue[0]; \
  781. _rx_queue < &_channel->efx->rx_queue[EFX_MAX_RX_QUEUES]; \
  782. _rx_queue++) \
  783. if ((!_rx_queue->used) || \
  784. (_rx_queue->channel != _channel)) \
  785. continue; \
  786. else
  787. /* Returns a pointer to the specified receive buffer in the RX
  788. * descriptor queue.
  789. */
  790. static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
  791. unsigned int index)
  792. {
  793. return (&rx_queue->buffer[index]);
  794. }
  795. /* Set bit in a little-endian bitfield */
  796. static inline void set_bit_le(int nr, unsigned char *addr)
  797. {
  798. addr[nr / 8] |= (1 << (nr % 8));
  799. }
  800. /* Clear bit in a little-endian bitfield */
  801. static inline void clear_bit_le(int nr, unsigned char *addr)
  802. {
  803. addr[nr / 8] &= ~(1 << (nr % 8));
  804. }
  805. /**
  806. * EFX_MAX_FRAME_LEN - calculate maximum frame length
  807. *
  808. * This calculates the maximum frame length that will be used for a
  809. * given MTU. The frame length will be equal to the MTU plus a
  810. * constant amount of header space and padding. This is the quantity
  811. * that the net driver will program into the MAC as the maximum frame
  812. * length.
  813. *
  814. * The 10G MAC used in Falcon requires 8-byte alignment on the frame
  815. * length, so we round up to the nearest 8.
  816. */
  817. #define EFX_MAX_FRAME_LEN(mtu) \
  818. ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
  819. #endif /* EFX_NET_DRIVER_H */