falcon_io.h 8.0 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #ifndef EFX_FALCON_IO_H
  11. #define EFX_FALCON_IO_H
  12. #include <linux/io.h>
  13. #include <linux/spinlock.h>
  14. #include "net_driver.h"
  15. /**************************************************************************
  16. *
  17. * Falcon hardware access
  18. *
  19. **************************************************************************
  20. *
  21. * Notes on locking strategy:
  22. *
  23. * Most Falcon registers require 16-byte (or 8-byte, for SRAM
  24. * registers) atomic writes which necessitates locking.
  25. * Under normal operation few writes to the Falcon BAR are made and these
  26. * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
  27. * cased to allow 4-byte (hence lockless) accesses.
  28. *
  29. * It *is* safe to write to these 4-byte registers in the middle of an
  30. * access to an 8-byte or 16-byte register. We therefore use a
  31. * spinlock to protect accesses to the larger registers, but no locks
  32. * for the 4-byte registers.
  33. *
  34. * A write barrier is needed to ensure that DW3 is written after DW0/1/2
  35. * due to the way the 16byte registers are "collected" in the Falcon BIU
  36. *
  37. * We also lock when carrying out reads, to ensure consistency of the
  38. * data (made possible since the BIU reads all 128 bits into a cache).
  39. * Reads are very rare, so this isn't a significant performance
  40. * impact. (Most data transferred from NIC to host is DMAed directly
  41. * into host memory).
  42. *
  43. * I/O BAR access uses locks for both reads and writes (but is only provided
  44. * for testing purposes).
  45. */
  46. /* Special buffer descriptors (Falcon SRAM) */
  47. #define BUF_TBL_KER_A1 0x18000
  48. #define BUF_TBL_KER_B0 0x800000
  49. #if BITS_PER_LONG == 64
  50. #define FALCON_USE_QWORD_IO 1
  51. #endif
  52. #define _falcon_writeq(efx, value, reg) \
  53. __raw_writeq((__force u64) (value), (efx)->membase + (reg))
  54. #define _falcon_writel(efx, value, reg) \
  55. __raw_writel((__force u32) (value), (efx)->membase + (reg))
  56. #define _falcon_readq(efx, reg) \
  57. ((__force __le64) __raw_readq((efx)->membase + (reg)))
  58. #define _falcon_readl(efx, reg) \
  59. ((__force __le32) __raw_readl((efx)->membase + (reg)))
  60. /* Writes to a normal 16-byte Falcon register, locking as appropriate. */
  61. static inline void falcon_write(struct efx_nic *efx, efx_oword_t *value,
  62. unsigned int reg)
  63. {
  64. unsigned long flags;
  65. EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
  66. EFX_OWORD_VAL(*value));
  67. spin_lock_irqsave(&efx->biu_lock, flags);
  68. #ifdef FALCON_USE_QWORD_IO
  69. _falcon_writeq(efx, value->u64[0], reg + 0);
  70. wmb();
  71. _falcon_writeq(efx, value->u64[1], reg + 8);
  72. #else
  73. _falcon_writel(efx, value->u32[0], reg + 0);
  74. _falcon_writel(efx, value->u32[1], reg + 4);
  75. _falcon_writel(efx, value->u32[2], reg + 8);
  76. wmb();
  77. _falcon_writel(efx, value->u32[3], reg + 12);
  78. #endif
  79. mmiowb();
  80. spin_unlock_irqrestore(&efx->biu_lock, flags);
  81. }
  82. /* Writes to an 8-byte Falcon SRAM register, locking as appropriate. */
  83. static inline void falcon_write_sram(struct efx_nic *efx, efx_qword_t *value,
  84. unsigned int index)
  85. {
  86. unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
  87. unsigned long flags;
  88. EFX_REGDUMP(efx, "writing SRAM register %x with " EFX_QWORD_FMT "\n",
  89. reg, EFX_QWORD_VAL(*value));
  90. spin_lock_irqsave(&efx->biu_lock, flags);
  91. #ifdef FALCON_USE_QWORD_IO
  92. _falcon_writeq(efx, value->u64[0], reg + 0);
  93. #else
  94. _falcon_writel(efx, value->u32[0], reg + 0);
  95. wmb();
  96. _falcon_writel(efx, value->u32[1], reg + 4);
  97. #endif
  98. mmiowb();
  99. spin_unlock_irqrestore(&efx->biu_lock, flags);
  100. }
  101. /* Write dword to Falcon register that allows partial writes
  102. *
  103. * Some Falcon registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
  104. * TX_DESC_UPD_REG) can be written to as a single dword. This allows
  105. * for lockless writes.
  106. */
  107. static inline void falcon_writel(struct efx_nic *efx, efx_dword_t *value,
  108. unsigned int reg)
  109. {
  110. EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
  111. reg, EFX_DWORD_VAL(*value));
  112. /* No lock required */
  113. _falcon_writel(efx, value->u32[0], reg);
  114. }
  115. /* Read from a Falcon register
  116. *
  117. * This reads an entire 16-byte Falcon register in one go, locking as
  118. * appropriate. It is essential to read the first dword first, as this
  119. * prompts Falcon to load the current value into the shadow register.
  120. */
  121. static inline void falcon_read(struct efx_nic *efx, efx_oword_t *value,
  122. unsigned int reg)
  123. {
  124. unsigned long flags;
  125. spin_lock_irqsave(&efx->biu_lock, flags);
  126. value->u32[0] = _falcon_readl(efx, reg + 0);
  127. rmb();
  128. value->u32[1] = _falcon_readl(efx, reg + 4);
  129. value->u32[2] = _falcon_readl(efx, reg + 8);
  130. value->u32[3] = _falcon_readl(efx, reg + 12);
  131. spin_unlock_irqrestore(&efx->biu_lock, flags);
  132. EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
  133. EFX_OWORD_VAL(*value));
  134. }
  135. /* This reads an 8-byte Falcon SRAM entry in one go. */
  136. static inline void falcon_read_sram(struct efx_nic *efx, efx_qword_t *value,
  137. unsigned int index)
  138. {
  139. unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
  140. unsigned long flags;
  141. spin_lock_irqsave(&efx->biu_lock, flags);
  142. #ifdef FALCON_USE_QWORD_IO
  143. value->u64[0] = _falcon_readq(efx, reg + 0);
  144. #else
  145. value->u32[0] = _falcon_readl(efx, reg + 0);
  146. rmb();
  147. value->u32[1] = _falcon_readl(efx, reg + 4);
  148. #endif
  149. spin_unlock_irqrestore(&efx->biu_lock, flags);
  150. EFX_REGDUMP(efx, "read from SRAM register %x, got "EFX_QWORD_FMT"\n",
  151. reg, EFX_QWORD_VAL(*value));
  152. }
  153. /* Read dword from Falcon register that allows partial writes (sic) */
  154. static inline void falcon_readl(struct efx_nic *efx, efx_dword_t *value,
  155. unsigned int reg)
  156. {
  157. value->u32[0] = _falcon_readl(efx, reg);
  158. EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
  159. reg, EFX_DWORD_VAL(*value));
  160. }
  161. /* Write to a register forming part of a table */
  162. static inline void falcon_write_table(struct efx_nic *efx, efx_oword_t *value,
  163. unsigned int reg, unsigned int index)
  164. {
  165. falcon_write(efx, value, reg + index * sizeof(efx_oword_t));
  166. }
  167. /* Read to a register forming part of a table */
  168. static inline void falcon_read_table(struct efx_nic *efx, efx_oword_t *value,
  169. unsigned int reg, unsigned int index)
  170. {
  171. falcon_read(efx, value, reg + index * sizeof(efx_oword_t));
  172. }
  173. /* Write to a dword register forming part of a table */
  174. static inline void falcon_writel_table(struct efx_nic *efx, efx_dword_t *value,
  175. unsigned int reg, unsigned int index)
  176. {
  177. falcon_writel(efx, value, reg + index * sizeof(efx_oword_t));
  178. }
  179. /* Page-mapped register block size */
  180. #define FALCON_PAGE_BLOCK_SIZE 0x2000
  181. /* Calculate offset to page-mapped register block */
  182. #define FALCON_PAGED_REG(page, reg) \
  183. ((page) * FALCON_PAGE_BLOCK_SIZE + (reg))
  184. /* As for falcon_write(), but for a page-mapped register. */
  185. static inline void falcon_write_page(struct efx_nic *efx, efx_oword_t *value,
  186. unsigned int reg, unsigned int page)
  187. {
  188. falcon_write(efx, value, FALCON_PAGED_REG(page, reg));
  189. }
  190. /* As for falcon_writel(), but for a page-mapped register. */
  191. static inline void falcon_writel_page(struct efx_nic *efx, efx_dword_t *value,
  192. unsigned int reg, unsigned int page)
  193. {
  194. falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
  195. }
  196. /* Write dword to Falcon page-mapped register with an extra lock.
  197. *
  198. * As for falcon_writel_page(), but for a register that suffers from
  199. * SFC bug 3181. Take out a lock so the BIU collector cannot be
  200. * confused. */
  201. static inline void falcon_writel_page_locked(struct efx_nic *efx,
  202. efx_dword_t *value,
  203. unsigned int reg,
  204. unsigned int page)
  205. {
  206. unsigned long flags;
  207. spin_lock_irqsave(&efx->biu_lock, flags);
  208. falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
  209. spin_unlock_irqrestore(&efx->biu_lock, flags);
  210. }
  211. #endif /* EFX_FALCON_IO_H */